AM62Ax MCU+ SDK  09.01.00
sdl_ecc_soc.h
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1 /*
2  * SDL ECC
3  *
4  * Software Diagnostics Library module for ECC
5  *
6  * Copyright (c) Texas Instruments Incorporated 2023
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  *
12  * Redistributions of source code must retain the above copyright
13  * notice, this list of conditions and the following disclaimer.
14  *
15  * Redistributions in binary form must reproduce the above copyright
16  * notice, this list of conditions and the following disclaimer in the
17  * documentation and/or other materials provided with the
18  * distribution.
19  *
20  * Neither the name of Texas Instruments Incorporated nor the names of
21  * its contributors may be used to endorse or promote products derived
22  * from this software without specific prior written permission.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35  *
36  */
46 #ifndef INCLUDE_SDL_ECC_SOC_H_
47 #define INCLUDE_SDL_ECC_SOC_H_
48 
49 #include <stdint.h>
50 #include <sdl/sdl_ecc.h>
51 #include <sdl/ecc/sdl_ip_ecc.h>
52 #include <sdl/include/sdl_types.h>
53 #include <sdl/esm/soc/am62ax/sdl_esm_core.h>
54 #include <sdl/esm/soc/am62ax/sdl_esm_soc.h>
55 #include <sdl/ecc/sdl_ecc_priv.h>
56 #include <sdl/include/am62ax/sdlr_soc_ecc_aggr.h>
57 #include <sdl/include/am62ax/sdlr_intr_esm0.h>
58 #include <sdl/include/am62ax/sdlr_intr_wkup_esm0.h>
59 #include <sdl/include/am62ax/sdlr_soc_baseaddress.h>
60 
61 
62 
63 /* define Max memEntries for each aggregator (i.e. the number of RAM ID's with * Wrapper type) */
64 #define SDL_PSCSS0_SAM62A_MAIN_PSC_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
65 #define SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
66 #define SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
67 #define SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
68 #define SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (0U)
69 #define SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_RAM_IDS_TOTAL_ENTRIES (9U)
70 #define SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
71 #define SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_RAM_IDS_TOTAL_ENTRIES (0U)
72 #define SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
73 #define SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (29U)
74 #define SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (8U)
75 #define SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
76 #define SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (3U)
77 #define SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (0U)
78 #define SDL_DMASS0_DMSS_AM62A_ECCAGGR_RAM_IDS_TOTAL_ENTRIES (28U)
79 #define SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (7U)
80 #define SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES (1U)
81 #define SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES (1U)
82 #define SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES (1U)
83 #define SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES (1U)
84 #define SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES (1U)
85 #define SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES (1U)
86 #define SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (2U)
87 #define SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_RAM_IDS_TOTAL_ENTRIES (16U)
88 #define SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (12U)
89 #define SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (0U)
90 #define SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (29U)
91 #define SDL_SMS0_SMS_HSM_ECC_RAM_IDS_TOTAL_ENTRIES (2U)
92 #define SDL_SMS0_SMS_TIFS_ECC_RAM_IDS_TOTAL_ENTRIES (2U)
93 #define SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (6U)
94 #define SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (12U)
95 #define SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (62U)
96 #define SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (0U)
97 #define SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
98 #define SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (2U)
99 #define SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (2U)
100 #define SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
101 #define SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_RAM_IDS_TOTAL_ENTRIES (4U)
102 #define SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (0U)
103 #define SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RAM_IDS_TOTAL_ENTRIES (4U)
104 #define SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
105 #define SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RAM_IDS_TOTAL_ENTRIES (27U)
106 #define SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RAM_IDS_TOTAL_ENTRIES (27U)
107 #define SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_RAM_IDS_TOTAL_ENTRIES (27U)
108 #define SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_RAM_IDS_TOTAL_ENTRIES (27U)
109 #define SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RAM_IDS_TOTAL_ENTRIES (24U)
110 #define SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
111 #define SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
112 #define SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
113 #define SDL_ECC_Base_Address_TOTAL_ENTRIES (49U)
114 
119 static const SDL_MemConfig_t SDL_PSCSS0_SAM62A_MAIN_PSC_WRAP_ECC_AGGR_MemEntries[SDL_PSCSS0_SAM62A_MAIN_PSC_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
120 {
121  { SDL_PSCSS0_SAM62A_MAIN_PSC_WRAP_ECC_AGGR_AM62A_PSC_CHFW_CBASS_DST_FW_CH_VBUSP_TABLE_RAM_ID, 0u,
122  SDL_PSCSS0_SAM62A_MAIN_PSC_WRAP_ECC_AGGR_AM62A_PSC_CHFW_CBASS_DST_FW_CH_VBUSP_TABLE_RAM_SIZE, 10u,
123  SDL_PSCSS0_SAM62A_MAIN_PSC_WRAP_ECC_AGGR_AM62A_PSC_CHFW_CBASS_DST_FW_CH_VBUSP_TABLE_ROW_WIDTH, ((bool)false) },
124 };
125 
130 static const SDL_MemConfig_t SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_MemEntries[SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
131 {
132  { SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_RAM_ID, 0x0000000000u,
133  SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_RAM_SIZE, 4u,
134  SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_ROW_WIDTH, ((bool)true) },
135 };
136 
141 static const SDL_MemConfig_t SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_MemEntries[SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
142 {
143  { SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_RAM_ID, 0x0000900000u,
144  SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_RAM_SIZE, 4u,
145  SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_ROW_WIDTH, ((bool)true) },
146 };
147 
152 static const SDL_MemConfig_t SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_MemEntries[SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
153 {
154  { SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_MSRAM2KX256E_MSRAM0_ECC0_RAM_ID, 0x0043C40000u,
155  SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_MSRAM2KX256E_MSRAM0_ECC0_RAM_SIZE, 32u,
156  SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_MSRAM2KX256E_MSRAM0_ECC0_ROW_WIDTH, ((bool)true) },
157 };
158 
164 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
165 {
166  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
167  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
168  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
169  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
170  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
171  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
172  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
173  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
174  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_4_CHECKER_TYPE,
175  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_4_WIDTH },
176  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_5_CHECKER_TYPE,
177  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_5_WIDTH },
178  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_6_CHECKER_TYPE,
179  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_GROUP_6_WIDTH },
180 };
181 
187 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
188 {
189  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
190  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
191  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
192  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
193  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
194  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
195  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
196  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
197  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
198  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
199  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
200  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
201  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
202  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
203  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
204  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
205  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
206  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
207  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
208  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
209  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
210  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
211  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
212  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
213  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
214  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
215  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
216  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
217  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
218  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
219  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
220  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
221  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
222  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
223  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
224  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
225  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
226  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
227  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
228  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
229  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
230  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
231  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
232  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
233  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
234  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
235  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
236  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
237  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
238  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
239  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
240  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
241  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
242  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
243  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
244  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
245  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
246  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
247  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
248  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
249  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
250  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
251  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
252  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
253  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
254  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
255  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
256  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
257  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
258  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
259  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
260  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
261  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
262  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
263  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
264  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
265  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
266  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
267  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
268  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
269  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
270  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
271  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
272  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
273  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
274  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
275  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
276  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
277  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
278  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
279  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
280  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
281  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
282  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
283  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
284  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
285  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
286  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
287  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
288  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
289  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
290  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
291  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
292  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
293  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
294  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
295  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
296  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
297  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
298  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
299  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
300  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
301  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
302  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
303  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
304  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
305  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
306  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
307  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
308  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
309  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
310  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
311  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
312  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
313  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
314  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
315  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
316  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
317  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
318  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
319  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
320  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
321  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
322  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
323  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
324  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
325  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
326  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
327  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_69_CHECKER_TYPE,
328  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
329 };
330 
336 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
337 {
338  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
339  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
340  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
341  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
342  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
343  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
344  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
345  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
346  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
347  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
348  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
349  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
350  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
351  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
352  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
353  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
354  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
355  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
356  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
357  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
358  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
359  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
360  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
361  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
362  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
363  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
364  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
365  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
366  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
367  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
368  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
369  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
370  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
371  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
372  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
373  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
374  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
375  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
376  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
377  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
378  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
379  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
380  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
381  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
382  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
383  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
384  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
385  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
386  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
387  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
388  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
389  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
390  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
391  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
392  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
393  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
394  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
395  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
396  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
397  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
398  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
399  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
400  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
401  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
402  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
403  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
404  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
405  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
406  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
407  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
408  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
409  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
410  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
411  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
412  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
413  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
414  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
415  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
416  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
417  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
418  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
419  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
420  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
421  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
422  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
423  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
424  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
425  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
426  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
427  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
428  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
429  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
430  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
431  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
432  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
433  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
434  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
435  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
436  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
437  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
438  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
439  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
440  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
441  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
442  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
443  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
444  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
445  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
446  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
447  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
448  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
449  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
450  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
451  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
452  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
453  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
454  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
455  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
456  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
457  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
458  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
459  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
460  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
461  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
462  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
463  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
464  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
465  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
466  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
467  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
468  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
469  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
470  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
471  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
472  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
473  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
474  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
475  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
476  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_69_CHECKER_TYPE,
477  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
478  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_70_CHECKER_TYPE,
479  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_70_WIDTH },
480  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_71_CHECKER_TYPE,
481  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_71_WIDTH },
482  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_72_CHECKER_TYPE,
483  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_72_WIDTH },
484 };
485 
491 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_SAM62A_DM_MCU_ECC_AGGR_EDC_CTRL_groupEntries[SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_SAM62A_DM_MCU_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
492 {
493  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_SAM62A_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
494  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_SAM62A_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
495  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_SAM62A_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
496  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_SAM62A_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
497  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_SAM62A_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
498  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_SAM62A_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
499  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_SAM62A_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
500  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_SAM62A_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
501  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_SAM62A_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
502  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_SAM62A_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
503  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_SAM62A_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
504  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_SAM62A_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
505 };
506 
511 static const SDL_MemConfig_t SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_MemEntries[SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_RAM_IDS_TOTAL_ENTRIES] =
512 {
513  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_CFG_CONFIG_RAM_ID, 0u,
514  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_CFG_CONFIG_RAM_SIZE, 11u,
515  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_CFG_CONFIG_ROW_WIDTH, ((bool)false) },
516  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_CFG_STATE_RAM_ID, 0u,
517  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_CFG_STATE_RAM_SIZE, 50u,
518  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_CFG_STATE_ROW_WIDTH, ((bool)false) },
519  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_F0_RAM_ID, 0u,
520  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_F0_RAM_SIZE, 16u,
521  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_F0_ROW_WIDTH, ((bool)false) },
522  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_F1_RAM_ID, 0u,
523  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_F1_RAM_SIZE, 16u,
524  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_F1_ROW_WIDTH, ((bool)false) },
525  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_WC_RAM_ID, 0u,
526  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_WC_RAM_SIZE, 4u,
527  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_WC_ROW_WIDTH, ((bool)false) },
528  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_STATS_STSR0_RAM_ID, 0u,
529  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_STATS_STSR0_RAM_SIZE, 12u,
530  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_STATS_STSR0_ROW_WIDTH, ((bool)false) },
531  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RINGOCC_CNTR_RAM_ID, 0u,
532  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RINGOCC_CNTR_RAM_SIZE, 4u,
533  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RINGOCC_CNTR_ROW_WIDTH, ((bool)false) },
534  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_RAM_ID, 0u,
535  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_RAM_SIZE, 16u,
536  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_ROW_WIDTH, ((bool)false) },
537  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_INTAGGR_COMMON_IM_TPRAM_153X34_SWW_SR_RAM_ID, 0u,
538  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_INTAGGR_COMMON_IM_TPRAM_153X34_SWW_SR_RAM_SIZE, 5u,
539  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_INTAGGR_COMMON_IM_TPRAM_153X34_SWW_SR_ROW_WIDTH, ((bool)false) },
540 };
541 
546 static const SDL_MemConfig_t SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MemEntries[SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
547 {
548  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_ID, 0x79140000u,
549  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_SIZE, 4u,
550  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_ROW_WIDTH, ((bool)true) },
551 };
552 
558 static const SDL_GrpChkConfig_t SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_groupEntries[SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS] =
559 {
560  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
561  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_0_WIDTH },
562  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
563  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_1_WIDTH },
564  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
565  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_2_WIDTH },
566  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
567  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_3_WIDTH },
568  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
569  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_4_WIDTH },
570  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
571  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_5_WIDTH },
572  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
573  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_6_WIDTH },
574  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
575  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_7_WIDTH },
576  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
577  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_8_WIDTH },
578  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
579  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_9_WIDTH },
580  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
581  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_10_WIDTH },
582  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
583  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_11_WIDTH },
584  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
585  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_12_WIDTH },
586  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
587  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_13_WIDTH },
588  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
589  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_14_WIDTH },
590  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
591  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_15_WIDTH },
592  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
593  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_16_WIDTH },
594  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
595  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_17_WIDTH },
596  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
597  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_18_WIDTH },
598  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
599  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_19_WIDTH },
600  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
601  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_20_WIDTH },
602  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
603  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_21_WIDTH },
604  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
605  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_22_WIDTH },
606  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
607  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_23_WIDTH },
608  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
609  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_24_WIDTH },
610  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
611  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_25_WIDTH },
612  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
613  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_26_WIDTH },
614  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
615  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_27_WIDTH },
616  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
617  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_28_WIDTH },
618  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
619  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_29_WIDTH },
620  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
621  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_30_WIDTH },
622  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
623  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_31_WIDTH },
624  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
625  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_32_WIDTH },
626  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
627  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_33_WIDTH },
628  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
629  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_34_WIDTH },
630  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
631  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_35_WIDTH },
632  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
633  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_36_WIDTH },
634  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
635  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_37_WIDTH },
636  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
637  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_38_WIDTH },
638  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
639  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_39_WIDTH },
640  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
641  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_40_WIDTH },
642  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
643  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_41_WIDTH },
644  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
645  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_42_WIDTH },
646  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
647  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_43_WIDTH },
648  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
649  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_44_WIDTH },
650  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
651  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_45_WIDTH },
652  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
653  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_46_WIDTH },
654  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
655  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_47_WIDTH },
656  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
657  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_48_WIDTH },
658  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
659  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_49_WIDTH },
660  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
661  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_50_WIDTH },
662  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
663  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_51_WIDTH },
664  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
665  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_52_WIDTH },
666  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
667  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_53_WIDTH },
668  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
669  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_54_WIDTH },
670  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
671  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_55_WIDTH },
672  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
673  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_56_WIDTH },
674  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
675  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_57_WIDTH },
676  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
677  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_58_WIDTH },
678  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
679  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_59_WIDTH },
680  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
681  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_60_WIDTH },
682  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
683  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_61_WIDTH },
684  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
685  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_62_WIDTH },
686  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
687  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_63_WIDTH },
688  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
689  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_64_WIDTH },
690 };
691 
697 static const SDL_GrpChkConfig_t SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
698 {
699  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
700  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
701  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
702  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
703  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
704  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
705  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
706  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
707  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
708  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
709  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
710  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
711 };
712 
718 static const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_groupEntries[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
719 {
720  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
721  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_0_WIDTH },
722  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
723  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_1_WIDTH },
724  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
725  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_2_WIDTH },
726  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
727  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_3_WIDTH },
728  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
729  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_4_WIDTH },
730  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
731  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_5_WIDTH },
732 };
733 
739 static const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_groupEntries[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
740 {
741  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
742  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_0_WIDTH },
743  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
744  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_1_WIDTH },
745  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
746  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_2_WIDTH },
747  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
748  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_3_WIDTH },
749  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
750  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_4_WIDTH },
751  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
752  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_5_WIDTH },
753  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
754  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_6_WIDTH },
755  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
756  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_7_WIDTH },
757  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
758  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_8_WIDTH },
759  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
760  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_9_WIDTH },
761  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
762  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_10_WIDTH },
763  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
764  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_11_WIDTH },
765  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
766  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_12_WIDTH },
767  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
768  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_13_WIDTH },
769  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
770  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_14_WIDTH },
771  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
772  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_15_WIDTH },
773  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
774  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_16_WIDTH },
775  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
776  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_17_WIDTH },
777  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
778  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_18_WIDTH },
779  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
780  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_19_WIDTH },
781  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
782  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_20_WIDTH },
783  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
784  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_21_WIDTH },
785  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
786  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_22_WIDTH },
787  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
788  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_23_WIDTH },
789  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
790  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_24_WIDTH },
791  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
792  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_25_WIDTH },
793  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
794  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_26_WIDTH },
795  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
796  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_27_WIDTH },
797  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
798  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_28_WIDTH },
799  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
800  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_29_WIDTH },
801  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
802  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_30_WIDTH },
803  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
804  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_31_WIDTH },
805  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
806  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_32_WIDTH },
807  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
808  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_33_WIDTH },
809  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
810  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_34_WIDTH },
811  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
812  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_35_WIDTH },
813  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
814  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_36_WIDTH },
815  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
816  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_37_WIDTH },
817  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
818  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_38_WIDTH },
819  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
820  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_39_WIDTH },
821  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
822  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_40_WIDTH },
823  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
824  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_41_WIDTH },
825  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
826  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_42_WIDTH },
827  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
828  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_43_WIDTH },
829  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
830  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_44_WIDTH },
831  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
832  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_45_WIDTH },
833  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
834  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_46_WIDTH },
835  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
836  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_47_WIDTH },
837  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
838  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_48_WIDTH },
839  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
840  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_49_WIDTH },
841  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
842  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_50_WIDTH },
843  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
844  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_51_WIDTH },
845  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
846  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_52_WIDTH },
847  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
848  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_53_WIDTH },
849  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
850  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_54_WIDTH },
851  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
852  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_55_WIDTH },
853  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
854  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_56_WIDTH },
855  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
856  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_57_WIDTH },
857  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
858  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_58_WIDTH },
859  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
860  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_59_WIDTH },
861  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
862  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_60_WIDTH },
863  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
864  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_61_WIDTH },
865  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
866  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_62_WIDTH },
867  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
868  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_63_WIDTH },
869  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
870  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_64_WIDTH },
871  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
872  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_65_WIDTH },
873  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
874  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_66_WIDTH },
875  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
876  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_67_WIDTH },
877  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
878  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_68_WIDTH },
879  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
880  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_69_WIDTH },
881  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
882  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_70_WIDTH },
883  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
884  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_71_WIDTH },
885  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
886  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_72_WIDTH },
887  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
888  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_73_WIDTH },
889  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
890  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_74_WIDTH },
891  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
892  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_75_WIDTH },
893  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
894  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_76_WIDTH },
895  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
896  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_77_WIDTH },
897  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
898  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_78_WIDTH },
899  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
900  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_79_WIDTH },
901  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
902  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_80_WIDTH },
903  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
904  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_81_WIDTH },
905  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
906  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_82_WIDTH },
907  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
908  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_83_WIDTH },
909  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
910  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_84_WIDTH },
911  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
912  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_85_WIDTH },
913  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
914  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_86_WIDTH },
915  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
916  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_87_WIDTH },
917  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
918  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_88_WIDTH },
919  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
920  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_89_WIDTH },
921  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
922  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_90_WIDTH },
923  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
924  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_91_WIDTH },
925  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
926  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_92_WIDTH },
927  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
928  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_93_WIDTH },
929  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
930  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_94_WIDTH },
931  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
932  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_95_WIDTH },
933  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
934  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_96_WIDTH },
935  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
936  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_97_WIDTH },
937  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
938  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_98_WIDTH },
939  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
940  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_99_WIDTH },
941  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
942  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_100_WIDTH },
943  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
944  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_101_WIDTH },
945  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
946  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_102_WIDTH },
947  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
948  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_103_WIDTH },
949  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
950  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_104_WIDTH },
951  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
952  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_105_WIDTH },
953  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
954  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_106_WIDTH },
955  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
956  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_107_WIDTH },
957  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
958  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_108_WIDTH },
959  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
960  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_109_WIDTH },
961  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
962  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_110_WIDTH },
963  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
964  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_111_WIDTH },
965  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
966  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_112_WIDTH },
967  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
968  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_113_WIDTH },
969  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
970  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_114_WIDTH },
971  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
972  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_115_WIDTH },
973  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
974  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_116_WIDTH },
975  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
976  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_117_WIDTH },
977  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
978  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_118_WIDTH },
979  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
980  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_119_WIDTH },
981  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
982  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_120_WIDTH },
983  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
984  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_121_WIDTH },
985  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
986  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_122_WIDTH },
987  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
988  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_123_WIDTH },
989  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
990  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_124_WIDTH },
991  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
992  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_125_WIDTH },
993  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
994  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_126_WIDTH },
995  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
996  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_127_WIDTH },
997  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
998  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_128_WIDTH },
999  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
1000  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_129_WIDTH },
1001  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
1002  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_130_WIDTH },
1003  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
1004  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_131_WIDTH },
1005  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
1006  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_132_WIDTH },
1007  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_133_CHECKER_TYPE,
1008  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_133_WIDTH },
1009  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_134_CHECKER_TYPE,
1010  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_134_WIDTH },
1011  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_135_CHECKER_TYPE,
1012  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_135_WIDTH },
1013  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_136_CHECKER_TYPE,
1014  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_136_WIDTH },
1015  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_137_CHECKER_TYPE,
1016  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_137_WIDTH },
1017  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_138_CHECKER_TYPE,
1018  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_138_WIDTH },
1019  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_139_CHECKER_TYPE,
1020  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_139_WIDTH },
1021  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_140_CHECKER_TYPE,
1022  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_140_WIDTH },
1023  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_141_CHECKER_TYPE,
1024  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_141_WIDTH },
1025  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_142_CHECKER_TYPE,
1026  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_142_WIDTH },
1027  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_143_CHECKER_TYPE,
1028  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_143_WIDTH },
1029  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_144_CHECKER_TYPE,
1030  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_144_WIDTH },
1031  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_145_CHECKER_TYPE,
1032  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_145_WIDTH },
1033  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_146_CHECKER_TYPE,
1034  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_146_WIDTH },
1035  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_147_CHECKER_TYPE,
1036  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_147_WIDTH },
1037  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_148_CHECKER_TYPE,
1038  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_148_WIDTH },
1039  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_149_CHECKER_TYPE,
1040  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_149_WIDTH },
1041  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_150_CHECKER_TYPE,
1042  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_150_WIDTH },
1043  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_151_CHECKER_TYPE,
1044  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_151_WIDTH },
1045  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_152_CHECKER_TYPE,
1046  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_152_WIDTH },
1047  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_153_CHECKER_TYPE,
1048  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_153_WIDTH },
1049  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_154_CHECKER_TYPE,
1050  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_154_WIDTH },
1051  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_155_CHECKER_TYPE,
1052  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_155_WIDTH },
1053  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_156_CHECKER_TYPE,
1054  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_156_WIDTH },
1055  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_157_CHECKER_TYPE,
1056  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_157_WIDTH },
1057  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_158_CHECKER_TYPE,
1058  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_158_WIDTH },
1059  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_159_CHECKER_TYPE,
1060  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_159_WIDTH },
1061  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_160_CHECKER_TYPE,
1062  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_160_WIDTH },
1063  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_161_CHECKER_TYPE,
1064  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_161_WIDTH },
1065  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_162_CHECKER_TYPE,
1066  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_162_WIDTH },
1067  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_163_CHECKER_TYPE,
1068  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_163_WIDTH },
1069  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_164_CHECKER_TYPE,
1070  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_164_WIDTH },
1071  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_165_CHECKER_TYPE,
1072  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_165_WIDTH },
1073  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_166_CHECKER_TYPE,
1074  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_166_WIDTH },
1075  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_167_CHECKER_TYPE,
1076  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_167_WIDTH },
1077  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_168_CHECKER_TYPE,
1078  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_168_WIDTH },
1079  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_169_CHECKER_TYPE,
1080  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_169_WIDTH },
1081  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_170_CHECKER_TYPE,
1082  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_170_WIDTH },
1083 };
1084 
1090 static const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
1091 {
1092  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
1093  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
1094  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
1095  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
1096  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
1097  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
1098 };
1099 
1105 static const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
1106 {
1107  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
1108  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
1109  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
1110  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
1111  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
1112  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
1113  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
1114  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
1115  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
1116  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
1117  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
1118  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
1119  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
1120  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
1121  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
1122  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
1123  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
1124  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
1125  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
1126  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
1127  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
1128  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
1129  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
1130  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
1131  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
1132  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
1133  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
1134  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
1135  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
1136  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
1137  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
1138  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
1139  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
1140  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
1141  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
1142  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
1143  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
1144  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
1145  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
1146  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
1147  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
1148  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
1149  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
1150  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
1151  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
1152  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
1153  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
1154  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
1155  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
1156  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
1157  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
1158  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
1159  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
1160  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
1161  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
1162  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
1163  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
1164  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
1165  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
1166  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
1167  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
1168  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
1169  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
1170  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
1171  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
1172  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
1173  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
1174  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
1175  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
1176  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
1177  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
1178  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
1179  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
1180  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
1181  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
1182  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
1183  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
1184  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
1185  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
1186  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
1187  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
1188  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
1189  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
1190  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
1191  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
1192  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
1193  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
1194  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
1195  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
1196  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
1197  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
1198  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
1199  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
1200  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
1201  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
1202  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
1203  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
1204  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
1205  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
1206  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
1207 };
1208 
1213 static const SDL_MemConfig_t SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_MemEntries[SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
1214 {
1215  { SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_RAM_ID, 0u,
1216  SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_RAM_SIZE, 4u,
1217  SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_ROW_WIDTH, ((bool)false) },
1218 };
1219 
1224 static const SDL_MemConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_MemEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
1225 {
1226  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID, 0u,
1227  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_SIZE, 4u,
1228  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_ROW_WIDTH, ((bool)false) },
1229  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID, 0u,
1230  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_SIZE, 4u,
1231  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_ROW_WIDTH, ((bool)false) },
1232  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID, 0u,
1233  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_SIZE, 4u,
1234  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_ROW_WIDTH, ((bool)false) },
1235  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID, 0u,
1236  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_SIZE, 4u,
1237  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_ROW_WIDTH, ((bool)false) },
1238  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID, 0u,
1239  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_SIZE, 8u,
1240  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_ROW_WIDTH, ((bool)true) },
1241  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID, 0u,
1242  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_SIZE, 8u,
1243  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_ROW_WIDTH, ((bool)true) },
1244  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID, 0u,
1245  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_SIZE, 8u,
1246  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_ROW_WIDTH, ((bool)true) },
1247  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID, 0u,
1248  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_SIZE, 8u,
1249  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_ROW_WIDTH, ((bool)true) },
1250  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID, 0u,
1251  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_SIZE, 4u,
1252  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_ROW_WIDTH, ((bool)false) },
1253  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID, 0u,
1254  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_SIZE, 4u,
1255  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_ROW_WIDTH, ((bool)false) },
1256  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID, 0u,
1257  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_SIZE, 4u,
1258  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_ROW_WIDTH, ((bool)false) },
1259  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID, 0u,
1260  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_SIZE, 4u,
1261  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_ROW_WIDTH, ((bool)false) },
1262  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID, 0u,
1263  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_SIZE, 4u,
1264  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_ROW_WIDTH, ((bool)false) },
1265  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID, 0u,
1266  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_SIZE, 4u,
1267  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_ROW_WIDTH, ((bool)true) },
1268  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID, 0u,
1269  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_SIZE, 4u,
1270  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_ROW_WIDTH, ((bool)true) },
1271  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID, 0u,
1272  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_SIZE, 4u,
1273  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_ROW_WIDTH, ((bool)true) },
1274  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID, 0u,
1275  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_SIZE, 4u,
1276  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_ROW_WIDTH, ((bool)true) },
1277  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID, 0u,
1278  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_SIZE, 4u,
1279  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_ROW_WIDTH, ((bool)true) },
1280  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID, 0u,
1281  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_SIZE, 4u,
1282  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_ROW_WIDTH, ((bool)true) },
1283  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID, 0u,
1284  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_SIZE, 4u,
1285  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_ROW_WIDTH, ((bool)true) },
1286  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID, 0u,
1287  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_SIZE, 4u,
1288  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_ROW_WIDTH, ((bool)true) },
1289  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_ATCM0_BANK0_RAM_ID, 0x00u,
1290  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_ATCM0_BANK0_RAM_SIZE, 4u,
1291  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_ATCM0_BANK0_ROW_WIDTH, ((bool)true) },
1292  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_ATCM0_BANK1_RAM_ID, 0x00u,
1293  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_ATCM0_BANK1_RAM_SIZE, 4u,
1294  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_ATCM0_BANK1_ROW_WIDTH, ((bool)true) },
1295  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B0TCM0_BANK0_RAM_ID, 0x41010000u,
1296  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B0TCM0_BANK0_RAM_SIZE, 4u,
1297  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B0TCM0_BANK0_ROW_WIDTH, ((bool)true) },
1298  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B0TCM0_BANK1_RAM_ID, 0x41010000u,
1299  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B0TCM0_BANK1_RAM_SIZE, 4u,
1300  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B0TCM0_BANK1_ROW_WIDTH, ((bool)true) },
1301  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B1TCM0_BANK0_RAM_ID, 0x41010000u,
1302  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B1TCM0_BANK0_RAM_SIZE, 4u,
1303  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B1TCM0_BANK0_ROW_WIDTH, ((bool)true) },
1304  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B1TCM0_BANK1_RAM_ID, 0x41010000u,
1305  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B1TCM0_BANK1_RAM_SIZE, 4u,
1306  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B1TCM0_BANK1_ROW_WIDTH, ((bool)true) },
1307  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID, 0u,
1308  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_SIZE, 4u,
1309  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ROW_WIDTH, ((bool)false) },
1310  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_MEM_MST_RAMECC_RAM_ID, 0u,
1311  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_MEM_MST_RAMECC_RAM_SIZE, 8u,
1312  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_MEM_MST_RAMECC_ROW_WIDTH, ((bool)false) },
1313 };
1314 
1320 static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_groupEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_MAX_NUM_CHECKERS] =
1321 {
1322  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_0_CHECKER_TYPE,
1323  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_0_WIDTH },
1324  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_1_CHECKER_TYPE,
1325  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_1_WIDTH },
1326  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_2_CHECKER_TYPE,
1327  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_2_WIDTH },
1328  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_3_CHECKER_TYPE,
1329  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_3_WIDTH },
1330  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_4_CHECKER_TYPE,
1331  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_4_WIDTH },
1332  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_5_CHECKER_TYPE,
1333  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_5_WIDTH },
1334  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_6_CHECKER_TYPE,
1335  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_6_WIDTH },
1336  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_7_CHECKER_TYPE,
1337  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_7_WIDTH },
1338  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_8_CHECKER_TYPE,
1339  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_8_WIDTH },
1340  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_9_CHECKER_TYPE,
1341  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_9_WIDTH },
1342  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_10_CHECKER_TYPE,
1343  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_10_WIDTH },
1344  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_11_CHECKER_TYPE,
1345  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_11_WIDTH },
1346  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_12_CHECKER_TYPE,
1347  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_12_WIDTH },
1348  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_13_CHECKER_TYPE,
1349  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_13_WIDTH },
1350  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_14_CHECKER_TYPE,
1351  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_14_WIDTH },
1352  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_15_CHECKER_TYPE,
1353  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_15_WIDTH },
1354  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_16_CHECKER_TYPE,
1355  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_16_WIDTH },
1356  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_17_CHECKER_TYPE,
1357  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_17_WIDTH },
1358  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_18_CHECKER_TYPE,
1359  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_18_WIDTH },
1360  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_19_CHECKER_TYPE,
1361  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_19_WIDTH },
1362  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_20_CHECKER_TYPE,
1363  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_20_WIDTH },
1364  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_21_CHECKER_TYPE,
1365  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_21_WIDTH },
1366  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_22_CHECKER_TYPE,
1367  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_22_WIDTH },
1368  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_23_CHECKER_TYPE,
1369  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_23_WIDTH },
1370  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_24_CHECKER_TYPE,
1371  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_24_WIDTH },
1372  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_25_CHECKER_TYPE,
1373  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_25_WIDTH },
1374  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_26_CHECKER_TYPE,
1375  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_26_WIDTH },
1376  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_27_CHECKER_TYPE,
1377  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_27_WIDTH },
1378  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_28_CHECKER_TYPE,
1379  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_28_WIDTH },
1380  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_29_CHECKER_TYPE,
1381  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_29_WIDTH },
1382  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_30_CHECKER_TYPE,
1383  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_30_WIDTH },
1384  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_31_CHECKER_TYPE,
1385  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_31_WIDTH },
1386  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_32_CHECKER_TYPE,
1387  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_32_WIDTH },
1388  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_33_CHECKER_TYPE,
1389  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_33_WIDTH },
1390  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_34_CHECKER_TYPE,
1391  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_34_WIDTH },
1392  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_35_CHECKER_TYPE,
1393  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_GROUP_35_WIDTH },
1394 };
1395 
1401 static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_groupEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_MAX_NUM_CHECKERS] =
1402 {
1403  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
1404  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_0_WIDTH },
1405  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
1406  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_1_WIDTH },
1407  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
1408  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_2_WIDTH },
1409  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
1410  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_3_WIDTH },
1411  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
1412  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_4_WIDTH },
1413  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
1414  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_5_WIDTH },
1415  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
1416  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_6_WIDTH },
1417  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
1418  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_7_WIDTH },
1419  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
1420  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_8_WIDTH },
1421  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
1422  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_9_WIDTH },
1423  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
1424  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_10_WIDTH },
1425  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
1426  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_11_WIDTH },
1427  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
1428  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_12_WIDTH },
1429  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
1430  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_13_WIDTH },
1431  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
1432  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_14_WIDTH },
1433  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
1434  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_15_WIDTH },
1435  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
1436  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_16_WIDTH },
1437  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
1438  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_17_WIDTH },
1439  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
1440  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_18_WIDTH },
1441  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
1442  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_19_WIDTH },
1443  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
1444  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_20_WIDTH },
1445  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
1446  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_21_WIDTH },
1447  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
1448  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_22_WIDTH },
1449  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
1450  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_23_WIDTH },
1451  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
1452  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_24_WIDTH },
1453  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
1454  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_25_WIDTH },
1455  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
1456  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_26_WIDTH },
1457  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
1458  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_27_WIDTH },
1459  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
1460  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_28_WIDTH },
1461  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
1462  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_29_WIDTH },
1463  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
1464  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_30_WIDTH },
1465  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
1466  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_31_WIDTH },
1467  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
1468  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_32_WIDTH },
1469  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
1470  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_33_WIDTH },
1471  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
1472  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_34_WIDTH },
1473  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
1474  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_35_WIDTH },
1475  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
1476  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_GROUP_36_WIDTH },
1477 };
1478 
1484 static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_groupEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_MAX_NUM_CHECKERS] =
1485 {
1486  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
1487  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_0_WIDTH },
1488  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
1489  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_1_WIDTH },
1490  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
1491  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_2_WIDTH },
1492  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
1493  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_3_WIDTH },
1494  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
1495  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_4_WIDTH },
1496  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
1497  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_5_WIDTH },
1498  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
1499  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_6_WIDTH },
1500  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
1501  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_7_WIDTH },
1502  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
1503  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_8_WIDTH },
1504  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
1505  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_9_WIDTH },
1506  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
1507  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_10_WIDTH },
1508  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
1509  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_11_WIDTH },
1510  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
1511  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_12_WIDTH },
1512  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
1513  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_13_WIDTH },
1514  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
1515  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_GROUP_14_WIDTH },
1516 };
1517 
1523 static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_groupEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_MAX_NUM_CHECKERS] =
1524 {
1525  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_0_CHECKER_TYPE,
1526  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_0_WIDTH },
1527  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_1_CHECKER_TYPE,
1528  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_1_WIDTH },
1529  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_2_CHECKER_TYPE,
1530  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_2_WIDTH },
1531  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_3_CHECKER_TYPE,
1532  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_3_WIDTH },
1533  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_4_CHECKER_TYPE,
1534  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_4_WIDTH },
1535  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_5_CHECKER_TYPE,
1536  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_5_WIDTH },
1537  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_6_CHECKER_TYPE,
1538  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_6_WIDTH },
1539  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_7_CHECKER_TYPE,
1540  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_7_WIDTH },
1541  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_8_CHECKER_TYPE,
1542  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_8_WIDTH },
1543  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_9_CHECKER_TYPE,
1544  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_9_WIDTH },
1545  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_10_CHECKER_TYPE,
1546  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_10_WIDTH },
1547  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_11_CHECKER_TYPE,
1548  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_11_WIDTH },
1549  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_12_CHECKER_TYPE,
1550  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_12_WIDTH },
1551  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_13_CHECKER_TYPE,
1552  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_13_WIDTH },
1553  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_14_CHECKER_TYPE,
1554  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_14_WIDTH },
1555  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_15_CHECKER_TYPE,
1556  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_15_WIDTH },
1557  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_16_CHECKER_TYPE,
1558  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_16_WIDTH },
1559  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_17_CHECKER_TYPE,
1560  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_17_WIDTH },
1561  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_18_CHECKER_TYPE,
1562  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_18_WIDTH },
1563  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_19_CHECKER_TYPE,
1564  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_19_WIDTH },
1565  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_20_CHECKER_TYPE,
1566  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_20_WIDTH },
1567  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_21_CHECKER_TYPE,
1568  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_21_WIDTH },
1569  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_22_CHECKER_TYPE,
1570  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_22_WIDTH },
1571  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_23_CHECKER_TYPE,
1572  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_23_WIDTH },
1573  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_24_CHECKER_TYPE,
1574  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_24_WIDTH },
1575  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_25_CHECKER_TYPE,
1576  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_GROUP_25_WIDTH },
1577 };
1578 
1584 static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
1585 {
1586  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
1587  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
1588  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
1589  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
1590  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
1591  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
1592  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
1593  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
1594  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
1595  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
1596  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
1597  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
1598  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
1599  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
1600  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
1601  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
1602  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
1603  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
1604  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
1605  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
1606  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
1607  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
1608  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
1609  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
1610  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
1611  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
1612  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
1613  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
1614  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
1615  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
1616  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
1617  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
1618  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
1619  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
1620  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
1621  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
1622  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
1623  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
1624  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
1625  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
1626  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
1627  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
1628  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
1629  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
1630  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
1631  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
1632  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
1633  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
1634  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
1635  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
1636  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
1637  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
1638  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
1639  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
1640  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
1641  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
1642  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
1643  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
1644  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
1645  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
1646  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
1647  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
1648  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
1649  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
1650  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
1651  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
1652  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
1653  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
1654  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
1655  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
1656  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
1657  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
1658  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
1659  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
1660  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
1661  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
1662  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
1663  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
1664  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
1665  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
1666  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
1667  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
1668  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
1669  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
1670  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
1671  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
1672  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
1673  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
1674  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
1675  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
1676  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
1677  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
1678  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
1679  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
1680  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
1681  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
1682  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
1683  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
1684  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
1685  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
1686  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
1687  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
1688  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
1689  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
1690  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
1691  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
1692  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
1693  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
1694  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
1695  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
1696  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
1697  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
1698  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
1699  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
1700  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
1701  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
1702  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
1703  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
1704  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
1705  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
1706  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
1707  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
1708  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
1709  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
1710  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
1711  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
1712  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
1713  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
1714  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
1715  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
1716  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
1717  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
1718  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
1719  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
1720  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
1721  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
1722  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
1723  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
1724  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_69_CHECKER_TYPE,
1725  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
1726  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_70_CHECKER_TYPE,
1727  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_70_WIDTH },
1728  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_71_CHECKER_TYPE,
1729  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_71_WIDTH },
1730  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_72_CHECKER_TYPE,
1731  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_72_WIDTH },
1732  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_73_CHECKER_TYPE,
1733  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_73_WIDTH },
1734  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_74_CHECKER_TYPE,
1735  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_74_WIDTH },
1736  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_75_CHECKER_TYPE,
1737  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_75_WIDTH },
1738  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_76_CHECKER_TYPE,
1739  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_76_WIDTH },
1740 };
1741 
1747 static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
1748 {
1749  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
1750  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
1751  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
1752  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
1753  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
1754  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
1755  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
1756  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
1757  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
1758  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
1759  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
1760  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
1761 };
1762 
1767 static const SDL_MemConfig_t SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_MemEntries[SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
1768 {
1769  { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_ALE_RAM_RAM_ID, 0u,
1770  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_ALE_RAM_RAM_SIZE, 71u,
1771  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_ALE_RAM_ROW_WIDTH, ((bool)false) },
1772  { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL1_RAM_ID, 0u,
1773  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL1_RAM_SIZE, 32u,
1774  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL1_ROW_WIDTH, ((bool)false) },
1775  { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL2_RAM_ID, 0u,
1776  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL2_RAM_SIZE, 32u,
1777  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL2_ROW_WIDTH, ((bool)false) },
1778  { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL3_RAM_ID, 0u,
1779  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL3_RAM_SIZE, 32u,
1780  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL3_ROW_WIDTH, ((bool)false) },
1781  { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL4_RAM_ID, 0u,
1782  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL4_RAM_SIZE, 32u,
1783  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL4_ROW_WIDTH, ((bool)false) },
1784  { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL5_RAM_ID, 0u,
1785  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL5_RAM_SIZE, 32u,
1786  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL5_ROW_WIDTH, ((bool)false) },
1787  { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL6_RAM_ID, 0u,
1788  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL6_RAM_SIZE, 32u,
1789  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL6_ROW_WIDTH, ((bool)false) },
1790  { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_EST_RAM_RAM_ID, 0u,
1791  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_EST_RAM_RAM_SIZE, 4u,
1792  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_EST_RAM_ROW_WIDTH, ((bool)false) },
1793 };
1794 
1799 static const SDL_MemConfig_t SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MemEntries[SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
1800 {
1801  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_ID, 0x79100000u,
1802  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_SIZE, 4u,
1803  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_ROW_WIDTH, ((bool)true) },
1804 };
1805 
1811 static const SDL_GrpChkConfig_t SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_groupEntries[SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS] =
1812 {
1813  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
1814  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_0_WIDTH },
1815  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
1816  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_1_WIDTH },
1817  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
1818  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_2_WIDTH },
1819  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
1820  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_3_WIDTH },
1821  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
1822  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_4_WIDTH },
1823  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
1824  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_5_WIDTH },
1825  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
1826  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_6_WIDTH },
1827  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
1828  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_7_WIDTH },
1829  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
1830  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_8_WIDTH },
1831  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
1832  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_9_WIDTH },
1833  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
1834  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_10_WIDTH },
1835  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
1836  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_11_WIDTH },
1837  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
1838  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_12_WIDTH },
1839  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
1840  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_13_WIDTH },
1841  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
1842  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_14_WIDTH },
1843  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
1844  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_15_WIDTH },
1845  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
1846  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_16_WIDTH },
1847  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
1848  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_17_WIDTH },
1849  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
1850  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_18_WIDTH },
1851  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
1852  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_19_WIDTH },
1853  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
1854  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_20_WIDTH },
1855  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
1856  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_21_WIDTH },
1857  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
1858  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_22_WIDTH },
1859  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
1860  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_23_WIDTH },
1861  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
1862  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_24_WIDTH },
1863  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
1864  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_25_WIDTH },
1865  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
1866  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_26_WIDTH },
1867  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
1868  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_27_WIDTH },
1869  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
1870  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_28_WIDTH },
1871  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
1872  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_29_WIDTH },
1873  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
1874  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_30_WIDTH },
1875  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
1876  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_31_WIDTH },
1877  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
1878  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_32_WIDTH },
1879  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
1880  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_33_WIDTH },
1881  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
1882  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_34_WIDTH },
1883  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
1884  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_35_WIDTH },
1885  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
1886  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_36_WIDTH },
1887  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
1888  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_37_WIDTH },
1889  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
1890  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_38_WIDTH },
1891  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
1892  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_39_WIDTH },
1893  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
1894  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_40_WIDTH },
1895  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
1896  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_41_WIDTH },
1897  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
1898  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_42_WIDTH },
1899  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
1900  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_43_WIDTH },
1901  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
1902  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_44_WIDTH },
1903  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
1904  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_45_WIDTH },
1905  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
1906  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_46_WIDTH },
1907  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
1908  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_47_WIDTH },
1909  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
1910  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_48_WIDTH },
1911  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
1912  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_49_WIDTH },
1913  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
1914  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_50_WIDTH },
1915  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
1916  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_51_WIDTH },
1917  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
1918  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_52_WIDTH },
1919  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
1920  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_53_WIDTH },
1921  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
1922  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_54_WIDTH },
1923  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
1924  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_55_WIDTH },
1925  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
1926  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_56_WIDTH },
1927  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
1928  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_57_WIDTH },
1929  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
1930  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_58_WIDTH },
1931  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
1932  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_59_WIDTH },
1933  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
1934  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_60_WIDTH },
1935  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
1936  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_61_WIDTH },
1937  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
1938  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_62_WIDTH },
1939  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
1940  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_63_WIDTH },
1941  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
1942  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_GROUP_64_WIDTH },
1943 };
1944 
1950 static const SDL_GrpChkConfig_t SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
1951 {
1952  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
1953  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
1954  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
1955  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
1956  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
1957  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
1958  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
1959  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
1960  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
1961  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
1962  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
1963  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
1964 };
1965 
1970 static const SDL_MemConfig_t SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_MemEntries[SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
1971 {
1972  { SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ICB_RAMECC_RAM_ID, 0u,
1973  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ICB_RAMECC_RAM_SIZE, 4u,
1974  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ICB_RAMECC_ROW_WIDTH, ((bool)true) },
1975  { SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ITE_RAMECC_RAM_ID, 0u,
1976  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ITE_RAMECC_RAM_SIZE, 8u,
1977  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ITE_RAMECC_ROW_WIDTH, ((bool)true) },
1978  { SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_LPI_RAMECC_RAM_ID, 0u,
1979  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_LPI_RAMECC_RAM_SIZE, 4u,
1980  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_LPI_RAMECC_ROW_WIDTH, ((bool)true) },
1981 };
1982 
1988 static const SDL_GrpChkConfig_t SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
1989 {
1990  { SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
1991  SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
1992  { SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
1993  SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
1994  { SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
1995  SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
1996  { SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
1997  SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
1998 };
1999 
2004 static const SDL_MemConfig_t SDL_DMASS0_DMSS_AM62A_ECCAGGR_MemEntries[SDL_DMASS0_DMSS_AM62A_ECCAGGR_RAM_IDS_TOTAL_ENTRIES] =
2005 {
2006  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_CFG_CONFIG_RAM_ID, 0u,
2007  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_CFG_CONFIG_RAM_SIZE, 12u,
2008  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_CFG_CONFIG_ROW_WIDTH, ((bool)false) },
2009  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_CFG_STATE_RAM_ID, 0u,
2010  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_CFG_STATE_RAM_SIZE, 28u,
2011  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_CFG_STATE_ROW_WIDTH, ((bool)false) },
2012  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_TPCFIFO_F0_RAM_ID, 0u,
2013  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_TPCFIFO_F0_RAM_SIZE, 18u,
2014  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_TPCFIFO_F0_ROW_WIDTH, ((bool)false) },
2015  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_TPCFIFO_F1_RAM_ID, 0u,
2016  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_TPCFIFO_F1_RAM_SIZE, 18u,
2017  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_TPCFIFO_F1_ROW_WIDTH, ((bool)false) },
2018  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_RPCFIFO_F0_RAM_ID, 0u,
2019  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_RPCFIFO_F0_RAM_SIZE, 16u,
2020  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_RPCFIFO_F0_ROW_WIDTH, ((bool)false) },
2021  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_RPCFIFO_F1_RAM_ID, 0u,
2022  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_RPCFIFO_F1_RAM_SIZE, 16u,
2023  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_RPCFIFO_F1_ROW_WIDTH, ((bool)false) },
2024  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_RPCFIFO_WC_RAM_ID, 0u,
2025  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_RPCFIFO_WC_RAM_SIZE, 4u,
2026  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_RPCFIFO_WC_ROW_WIDTH, ((bool)false) },
2027  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_STATS_STST0_RAM_ID, 0u,
2028  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_STATS_STST0_RAM_SIZE, 12u,
2029  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_STATS_STST0_ROW_WIDTH, ((bool)false) },
2030  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_STATS_STSR0_RAM_ID, 0u,
2031  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_STATS_STSR0_RAM_SIZE, 16u,
2032  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_STATS_STSR0_ROW_WIDTH, ((bool)false) },
2033  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_RINGOCC_CNTR_RAM_ID, 0u,
2034  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_RINGOCC_CNTR_RAM_SIZE, 4u,
2035  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_RINGOCC_CNTR_ROW_WIDTH, ((bool)false) },
2036  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_CFG_CONFIG_RAM_ID, 0u,
2037  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_CFG_CONFIG_RAM_SIZE, 11u,
2038  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_CFG_CONFIG_ROW_WIDTH, ((bool)false) },
2039  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_CFG_STATE_RAM_ID, 0u,
2040  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_CFG_STATE_RAM_SIZE, 50u,
2041  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_CFG_STATE_ROW_WIDTH, ((bool)false) },
2042  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_PCFIFO_DFIFO_F0_RAM_ID, 0u,
2043  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_PCFIFO_DFIFO_F0_RAM_SIZE, 16u,
2044  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_PCFIFO_DFIFO_F0_ROW_WIDTH, ((bool)false) },
2045  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_PCFIFO_DFIFO_F1_RAM_ID, 0u,
2046  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_PCFIFO_DFIFO_F1_RAM_SIZE, 16u,
2047  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_PCFIFO_DFIFO_F1_ROW_WIDTH, ((bool)false) },
2048  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_TPCFIFO_F0_RAM_ID, 0u,
2049  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_TPCFIFO_F0_RAM_SIZE, 18u,
2050  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_TPCFIFO_F0_ROW_WIDTH, ((bool)false) },
2051  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_TPCFIFO_F1_RAM_ID, 0u,
2052  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_TPCFIFO_F1_RAM_SIZE, 18u,
2053  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_TPCFIFO_F1_ROW_WIDTH, ((bool)false) },
2054  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_RPCFIFO_F0_RAM_ID, 0u,
2055  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_RPCFIFO_F0_RAM_SIZE, 16u,
2056  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_RPCFIFO_F0_ROW_WIDTH, ((bool)false) },
2057  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_RPCFIFO_F1_RAM_ID, 0u,
2058  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_RPCFIFO_F1_RAM_SIZE, 16u,
2059  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_RPCFIFO_F1_ROW_WIDTH, ((bool)false) },
2060  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_RPCFIFO_WC_RAM_ID, 0u,
2061  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_RPCFIFO_WC_RAM_SIZE, 4u,
2062  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_RPCFIFO_WC_ROW_WIDTH, ((bool)false) },
2063  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_STATS_STST0_RAM_ID, 0u,
2064  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_STATS_STST0_RAM_SIZE, 12u,
2065  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_STATS_STST0_ROW_WIDTH, ((bool)false) },
2066  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_STATS_STSR0_RAM_ID, 0u,
2067  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_STATS_STSR0_RAM_SIZE, 12u,
2068  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_STATS_STSR0_ROW_WIDTH, ((bool)false) },
2069  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_RINGOCC_CNTR_RAM_ID, 0u,
2070  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_RINGOCC_CNTR_RAM_SIZE, 4u,
2071  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_RINGOCC_CNTR_ROW_WIDTH, ((bool)false) },
2072  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_INTAGGR_STATREG_SR_SPRAM_184X128_SWW_SR_RAM_ID, 0u,
2073  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_INTAGGR_STATREG_SR_SPRAM_184X128_SWW_SR_RAM_SIZE, 16u,
2074  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_INTAGGR_STATREG_SR_SPRAM_184X128_SWW_SR_ROW_WIDTH, ((bool)false) },
2075  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_INTAGGR_COMMON_IM_TPRAM_1531X34_SWW_SR_RAM_ID, 0u,
2076  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_INTAGGR_COMMON_IM_TPRAM_1531X34_SWW_SR_RAM_SIZE, 5u,
2077  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_INTAGGR_COMMON_IM_TPRAM_1531X34_SWW_SR_ROW_WIDTH, ((bool)false) },
2078  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_IPCSS_RINGACC_STRAM_RAM_ID, 0u,
2079  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_IPCSS_RINGACC_STRAM_RAM_SIZE, 27u,
2080  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_IPCSS_RINGACC_STRAM_ROW_WIDTH, ((bool)false) },
2081  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_IPCSS_SEC_PROXY_BUF_STRAM_RAM_ID, 0u,
2082  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_IPCSS_SEC_PROXY_BUF_STRAM_RAM_SIZE, 12u,
2083  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_IPCSS_SEC_PROXY_BUF_STRAM_ROW_WIDTH, ((bool)false) },
2084  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_IPCSS_SEC_PROXY_BUF_BUFRAM_RAM_ID, 0u,
2085  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_IPCSS_SEC_PROXY_BUF_BUFRAM_RAM_SIZE, 8u,
2086  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_IPCSS_SEC_PROXY_BUF_BUFRAM_ROW_WIDTH, ((bool)false) },
2087  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_IPCSS_MSRAM_ECC0_RAM_ID, 0u,
2088  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_IPCSS_MSRAM_ECC0_RAM_SIZE, 8u,
2089  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_IPCSS_MSRAM_ECC0_ROW_WIDTH, ((bool)false) },
2090 };
2091 
2096 static const SDL_MemConfig_t SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_MemEntries[SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
2097 {
2098  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_RAM_ID, 0u,
2099  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_RAM_SIZE, 18u,
2100  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_ROW_WIDTH, ((bool)false) },
2101  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_RAM_ID, 0u,
2102  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_RAM_SIZE, 6u,
2103  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_ROW_WIDTH, ((bool)false) },
2104  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_RAM_ID, 0u,
2105  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_RAM_SIZE, 6u,
2106  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_ROW_WIDTH, ((bool)false) },
2107  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_RAM_ID, 0u,
2108  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_RAM_SIZE, 6u,
2109  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_ROW_WIDTH, ((bool)false) },
2110  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_RAM_ID, 0u,
2111  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_RAM_SIZE, 6u,
2112  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_ROW_WIDTH, ((bool)false) },
2113  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_RAM_ID, 0u,
2114  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_RAM_SIZE, 5u,
2115  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_ROW_WIDTH, ((bool)false) },
2116  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_RAM_ID, 0u,
2117  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_RAM_SIZE, 5u,
2118  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_ROW_WIDTH, ((bool)false) },
2119 };
2120 
2126 static const SDL_GrpChkConfig_t SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_groupEntries[SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_MAX_NUM_CHECKERS] =
2127 {
2128  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
2129  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_GROUP_0_WIDTH },
2130  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
2131  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_GROUP_1_WIDTH },
2132 };
2133 
2138 static const SDL_MemConfig_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES] =
2139 {
2140  { SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_ID, 0u,
2141  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_SIZE, 8u,
2142  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_ROW_WIDTH, ((bool)false) },
2143 };
2144 
2149 static const SDL_MemConfig_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES] =
2150 {
2151  { SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_ID, 0u,
2152  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_SIZE, 8u,
2153  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_ROW_WIDTH, ((bool)false) },
2154 };
2155 
2160 static const SDL_MemConfig_t SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries[SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES] =
2161 {
2162  { SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_ID, 0u,
2163  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_SIZE, 8u,
2164  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_ROW_WIDTH, ((bool)false) },
2165 };
2166 
2171 static const SDL_MemConfig_t SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries[SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES] =
2172 {
2173  { SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_ID, 0u,
2174  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_SIZE, 8u,
2175  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_ROW_WIDTH, ((bool)false) },
2176 };
2177 
2182 static const SDL_MemConfig_t SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_MemEntries[SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES] =
2183 {
2184  { SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_EMMCSD8SS_SDHC_WRAP_TXMEM_RAM_ID, 0u,
2185  SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_EMMCSD8SS_SDHC_WRAP_TXMEM_RAM_SIZE, 8u,
2186  SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_EMMCSD8SS_SDHC_WRAP_TXMEM_ROW_WIDTH, ((bool)false) },
2187 };
2188 
2193 static const SDL_MemConfig_t SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_MemEntries[SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES] =
2194 {
2195  { SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_EMMCSD8SS_SDHC_WRAP_RXMEM_RAM_ID, 0u,
2196  SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_EMMCSD8SS_SDHC_WRAP_RXMEM_RAM_SIZE, 8u,
2197  SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_EMMCSD8SS_SDHC_WRAP_RXMEM_ROW_WIDTH, ((bool)false) },
2198 };
2199 
2204 static const SDL_MemConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_MemEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
2205 {
2206  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_RD_RAMECC_RAM_ID, 0u,
2207  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_RD_RAMECC_RAM_SIZE, 10u,
2208  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_RD_RAMECC_ROW_WIDTH, ((bool)false) },
2209  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_WR_RAMECC_RAM_ID, 0u,
2210  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_WR_RAMECC_RAM_SIZE, 10u,
2211  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_WR_RAMECC_ROW_WIDTH, ((bool)false) },
2212 };
2213 
2219 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_MAX_NUM_CHECKERS] =
2220 {
2221  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_0_CHECKER_TYPE,
2222  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_0_WIDTH },
2223  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_1_CHECKER_TYPE,
2224  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_1_WIDTH },
2225  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_2_CHECKER_TYPE,
2226  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_2_WIDTH },
2227  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_3_CHECKER_TYPE,
2228  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_3_WIDTH },
2229  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_4_CHECKER_TYPE,
2230  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_4_WIDTH },
2231  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_5_CHECKER_TYPE,
2232  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_5_WIDTH },
2233  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_6_CHECKER_TYPE,
2234  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_6_WIDTH },
2235  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_7_CHECKER_TYPE,
2236  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_7_WIDTH },
2237  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_8_CHECKER_TYPE,
2238  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_8_WIDTH },
2239  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_9_CHECKER_TYPE,
2240  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_9_WIDTH },
2241  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_10_CHECKER_TYPE,
2242  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_10_WIDTH },
2243  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_11_CHECKER_TYPE,
2244  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_11_WIDTH },
2245  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_12_CHECKER_TYPE,
2246  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_12_WIDTH },
2247  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_13_CHECKER_TYPE,
2248  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_13_WIDTH },
2249  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_14_CHECKER_TYPE,
2250  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_14_WIDTH },
2251  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_15_CHECKER_TYPE,
2252  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_15_WIDTH },
2253  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_16_CHECKER_TYPE,
2254  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_16_WIDTH },
2255  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_17_CHECKER_TYPE,
2256  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_17_WIDTH },
2257  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_18_CHECKER_TYPE,
2258  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_18_WIDTH },
2259  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_19_CHECKER_TYPE,
2260  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_19_WIDTH },
2261  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_20_CHECKER_TYPE,
2262  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_20_WIDTH },
2263  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_21_CHECKER_TYPE,
2264  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_21_WIDTH },
2265  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_22_CHECKER_TYPE,
2266  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_22_WIDTH },
2267  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_23_CHECKER_TYPE,
2268  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_23_WIDTH },
2269  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_24_CHECKER_TYPE,
2270  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_24_WIDTH },
2271  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_25_CHECKER_TYPE,
2272  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_25_WIDTH },
2273  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_26_CHECKER_TYPE,
2274  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_26_WIDTH },
2275  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_27_CHECKER_TYPE,
2276  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_27_WIDTH },
2277  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_28_CHECKER_TYPE,
2278  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_28_WIDTH },
2279  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_29_CHECKER_TYPE,
2280  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_29_WIDTH },
2281  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_30_CHECKER_TYPE,
2282  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_30_WIDTH },
2283  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_31_CHECKER_TYPE,
2284  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_31_WIDTH },
2285  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_32_CHECKER_TYPE,
2286  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_32_WIDTH },
2287  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_33_CHECKER_TYPE,
2288  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_33_WIDTH },
2289  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_34_CHECKER_TYPE,
2290  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_34_WIDTH },
2291  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_35_CHECKER_TYPE,
2292  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_35_WIDTH },
2293  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_36_CHECKER_TYPE,
2294  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_36_WIDTH },
2295  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_37_CHECKER_TYPE,
2296  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_37_WIDTH },
2297  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_38_CHECKER_TYPE,
2298  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_38_WIDTH },
2299  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_39_CHECKER_TYPE,
2300  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_39_WIDTH },
2301  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_40_CHECKER_TYPE,
2302  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_40_WIDTH },
2303  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_41_CHECKER_TYPE,
2304  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_41_WIDTH },
2305  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_42_CHECKER_TYPE,
2306  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_42_WIDTH },
2307  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_43_CHECKER_TYPE,
2308  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_43_WIDTH },
2309  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_44_CHECKER_TYPE,
2310  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_44_WIDTH },
2311  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_45_CHECKER_TYPE,
2312  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_45_WIDTH },
2313  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_46_CHECKER_TYPE,
2314  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_46_WIDTH },
2315  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_47_CHECKER_TYPE,
2316  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_47_WIDTH },
2317  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_48_CHECKER_TYPE,
2318  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_48_WIDTH },
2319  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_49_CHECKER_TYPE,
2320  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_49_WIDTH },
2321  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_50_CHECKER_TYPE,
2322  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_50_WIDTH },
2323  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_51_CHECKER_TYPE,
2324  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_51_WIDTH },
2325  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_52_CHECKER_TYPE,
2326  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_52_WIDTH },
2327  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_53_CHECKER_TYPE,
2328  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_53_WIDTH },
2329  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_54_CHECKER_TYPE,
2330  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_54_WIDTH },
2331  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_55_CHECKER_TYPE,
2332  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_55_WIDTH },
2333  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_56_CHECKER_TYPE,
2334  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_56_WIDTH },
2335  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_57_CHECKER_TYPE,
2336  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_57_WIDTH },
2337  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_58_CHECKER_TYPE,
2338  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_58_WIDTH },
2339  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_59_CHECKER_TYPE,
2340  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_59_WIDTH },
2341  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_60_CHECKER_TYPE,
2342  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_60_WIDTH },
2343  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_61_CHECKER_TYPE,
2344  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_61_WIDTH },
2345  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_62_CHECKER_TYPE,
2346  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_62_WIDTH },
2347  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_63_CHECKER_TYPE,
2348  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_63_WIDTH },
2349  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_64_CHECKER_TYPE,
2350  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_64_WIDTH },
2351  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_65_CHECKER_TYPE,
2352  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_65_WIDTH },
2353  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_66_CHECKER_TYPE,
2354  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_66_WIDTH },
2355  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_67_CHECKER_TYPE,
2356  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_67_WIDTH },
2357  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_68_CHECKER_TYPE,
2358  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_GROUP_68_WIDTH },
2359 };
2360 
2366 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_MAX_NUM_CHECKERS] =
2367 {
2368  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
2369  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_0_WIDTH },
2370  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
2371  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_1_WIDTH },
2372  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
2373  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_2_WIDTH },
2374  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
2375  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_3_WIDTH },
2376  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
2377  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_4_WIDTH },
2378  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
2379  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_5_WIDTH },
2380  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
2381  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_6_WIDTH },
2382  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
2383  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_7_WIDTH },
2384  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
2385  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_8_WIDTH },
2386  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
2387  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_9_WIDTH },
2388  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
2389  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_10_WIDTH },
2390  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
2391  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_11_WIDTH },
2392  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
2393  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_12_WIDTH },
2394  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
2395  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_13_WIDTH },
2396  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
2397  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_14_WIDTH },
2398  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_15_CHECKER_TYPE,
2399  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_15_WIDTH },
2400  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_16_CHECKER_TYPE,
2401  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_16_WIDTH },
2402  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_17_CHECKER_TYPE,
2403  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_17_WIDTH },
2404  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_18_CHECKER_TYPE,
2405  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_18_WIDTH },
2406  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_19_CHECKER_TYPE,
2407  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_19_WIDTH },
2408  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_20_CHECKER_TYPE,
2409  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_20_WIDTH },
2410  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_21_CHECKER_TYPE,
2411  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_21_WIDTH },
2412  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_22_CHECKER_TYPE,
2413  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_22_WIDTH },
2414  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_23_CHECKER_TYPE,
2415  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_23_WIDTH },
2416  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_24_CHECKER_TYPE,
2417  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_24_WIDTH },
2418  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_25_CHECKER_TYPE,
2419  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_25_WIDTH },
2420  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_26_CHECKER_TYPE,
2421  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_26_WIDTH },
2422  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_27_CHECKER_TYPE,
2423  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_27_WIDTH },
2424  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_28_CHECKER_TYPE,
2425  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_28_WIDTH },
2426  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_29_CHECKER_TYPE,
2427  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_29_WIDTH },
2428  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_30_CHECKER_TYPE,
2429  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_30_WIDTH },
2430  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_31_CHECKER_TYPE,
2431  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_31_WIDTH },
2432  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_32_CHECKER_TYPE,
2433  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_32_WIDTH },
2434  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_33_CHECKER_TYPE,
2435  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_33_WIDTH },
2436  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_34_CHECKER_TYPE,
2437  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_34_WIDTH },
2438  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_35_CHECKER_TYPE,
2439  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_35_WIDTH },
2440  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_36_CHECKER_TYPE,
2441  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_36_WIDTH },
2442  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_37_CHECKER_TYPE,
2443  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_37_WIDTH },
2444  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_38_CHECKER_TYPE,
2445  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_38_WIDTH },
2446  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_39_CHECKER_TYPE,
2447  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_39_WIDTH },
2448  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_40_CHECKER_TYPE,
2449  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_40_WIDTH },
2450  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_41_CHECKER_TYPE,
2451  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_41_WIDTH },
2452  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_42_CHECKER_TYPE,
2453  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_42_WIDTH },
2454  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_43_CHECKER_TYPE,
2455  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_43_WIDTH },
2456  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_44_CHECKER_TYPE,
2457  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_44_WIDTH },
2458  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_45_CHECKER_TYPE,
2459  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_45_WIDTH },
2460  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_46_CHECKER_TYPE,
2461  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_46_WIDTH },
2462  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_47_CHECKER_TYPE,
2463  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_47_WIDTH },
2464  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_48_CHECKER_TYPE,
2465  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_48_WIDTH },
2466  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_49_CHECKER_TYPE,
2467  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_49_WIDTH },
2468  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_50_CHECKER_TYPE,
2469  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_50_WIDTH },
2470  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_51_CHECKER_TYPE,
2471  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_51_WIDTH },
2472  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_52_CHECKER_TYPE,
2473  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_52_WIDTH },
2474  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_53_CHECKER_TYPE,
2475  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_53_WIDTH },
2476  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_54_CHECKER_TYPE,
2477  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_54_WIDTH },
2478  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_55_CHECKER_TYPE,
2479  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_55_WIDTH },
2480  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_56_CHECKER_TYPE,
2481  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_56_WIDTH },
2482  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_57_CHECKER_TYPE,
2483  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_57_WIDTH },
2484  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_58_CHECKER_TYPE,
2485  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_58_WIDTH },
2486  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_59_CHECKER_TYPE,
2487  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_59_WIDTH },
2488  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_60_CHECKER_TYPE,
2489  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_60_WIDTH },
2490  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_61_CHECKER_TYPE,
2491  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_61_WIDTH },
2492  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_62_CHECKER_TYPE,
2493  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_62_WIDTH },
2494  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_63_CHECKER_TYPE,
2495  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_63_WIDTH },
2496  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_64_CHECKER_TYPE,
2497  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_GROUP_64_WIDTH },
2498 };
2499 
2505 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_MAX_NUM_CHECKERS] =
2506 {
2507  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_0_CHECKER_TYPE,
2508  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_0_WIDTH },
2509  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_1_CHECKER_TYPE,
2510  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_1_WIDTH },
2511  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_2_CHECKER_TYPE,
2512  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_2_WIDTH },
2513  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_3_CHECKER_TYPE,
2514  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_3_WIDTH },
2515  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_4_CHECKER_TYPE,
2516  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_4_WIDTH },
2517  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_5_CHECKER_TYPE,
2518  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_5_WIDTH },
2519  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_6_CHECKER_TYPE,
2520  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_6_WIDTH },
2521  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_7_CHECKER_TYPE,
2522  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_7_WIDTH },
2523  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_8_CHECKER_TYPE,
2524  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_8_WIDTH },
2525  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_9_CHECKER_TYPE,
2526  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_9_WIDTH },
2527  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_10_CHECKER_TYPE,
2528  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_10_WIDTH },
2529  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_11_CHECKER_TYPE,
2530  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_11_WIDTH },
2531  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_12_CHECKER_TYPE,
2532  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_12_WIDTH },
2533  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_13_CHECKER_TYPE,
2534  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_13_WIDTH },
2535  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_14_CHECKER_TYPE,
2536  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_14_WIDTH },
2537  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_15_CHECKER_TYPE,
2538  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_15_WIDTH },
2539  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_16_CHECKER_TYPE,
2540  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_16_WIDTH },
2541  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_17_CHECKER_TYPE,
2542  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_17_WIDTH },
2543  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_18_CHECKER_TYPE,
2544  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_18_WIDTH },
2545  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_19_CHECKER_TYPE,
2546  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_19_WIDTH },
2547  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_20_CHECKER_TYPE,
2548  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_20_WIDTH },
2549  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_21_CHECKER_TYPE,
2550  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_21_WIDTH },
2551  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_22_CHECKER_TYPE,
2552  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_22_WIDTH },
2553  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_23_CHECKER_TYPE,
2554  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_23_WIDTH },
2555  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_24_CHECKER_TYPE,
2556  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_24_WIDTH },
2557  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_25_CHECKER_TYPE,
2558  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_25_WIDTH },
2559  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_26_CHECKER_TYPE,
2560  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_26_WIDTH },
2561  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_27_CHECKER_TYPE,
2562  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_27_WIDTH },
2563  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_28_CHECKER_TYPE,
2564  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_28_WIDTH },
2565  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_29_CHECKER_TYPE,
2566  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_29_WIDTH },
2567  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_30_CHECKER_TYPE,
2568  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_30_WIDTH },
2569  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_31_CHECKER_TYPE,
2570  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_31_WIDTH },
2571  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_32_CHECKER_TYPE,
2572  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_32_WIDTH },
2573  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_33_CHECKER_TYPE,
2574  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_33_WIDTH },
2575  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_34_CHECKER_TYPE,
2576  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_34_WIDTH },
2577  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_35_CHECKER_TYPE,
2578  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_35_WIDTH },
2579  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_36_CHECKER_TYPE,
2580  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_36_WIDTH },
2581  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_37_CHECKER_TYPE,
2582  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_37_WIDTH },
2583  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_38_CHECKER_TYPE,
2584  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_38_WIDTH },
2585  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_39_CHECKER_TYPE,
2586  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_39_WIDTH },
2587  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_40_CHECKER_TYPE,
2588  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_40_WIDTH },
2589  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_41_CHECKER_TYPE,
2590  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_41_WIDTH },
2591  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_42_CHECKER_TYPE,
2592  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_42_WIDTH },
2593  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_43_CHECKER_TYPE,
2594  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_43_WIDTH },
2595  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_44_CHECKER_TYPE,
2596  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_44_WIDTH },
2597  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_45_CHECKER_TYPE,
2598  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_45_WIDTH },
2599  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_46_CHECKER_TYPE,
2600  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_46_WIDTH },
2601  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_47_CHECKER_TYPE,
2602  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_47_WIDTH },
2603  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_48_CHECKER_TYPE,
2604  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_48_WIDTH },
2605  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_49_CHECKER_TYPE,
2606  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_49_WIDTH },
2607  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_50_CHECKER_TYPE,
2608  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_50_WIDTH },
2609  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_51_CHECKER_TYPE,
2610  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_51_WIDTH },
2611  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_52_CHECKER_TYPE,
2612  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_52_WIDTH },
2613  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_53_CHECKER_TYPE,
2614  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_53_WIDTH },
2615  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_54_CHECKER_TYPE,
2616  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_54_WIDTH },
2617  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_55_CHECKER_TYPE,
2618  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_55_WIDTH },
2619  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_56_CHECKER_TYPE,
2620  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_56_WIDTH },
2621  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_57_CHECKER_TYPE,
2622  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_57_WIDTH },
2623  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_58_CHECKER_TYPE,
2624  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_58_WIDTH },
2625  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_59_CHECKER_TYPE,
2626  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_59_WIDTH },
2627  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_60_CHECKER_TYPE,
2628  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_60_WIDTH },
2629  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_61_CHECKER_TYPE,
2630  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_61_WIDTH },
2631  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_62_CHECKER_TYPE,
2632  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_62_WIDTH },
2633  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_63_CHECKER_TYPE,
2634  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_63_WIDTH },
2635  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_64_CHECKER_TYPE,
2636  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_64_WIDTH },
2637  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_65_CHECKER_TYPE,
2638  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_65_WIDTH },
2639  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_66_CHECKER_TYPE,
2640  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_66_WIDTH },
2641  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_67_CHECKER_TYPE,
2642  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_67_WIDTH },
2643  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_68_CHECKER_TYPE,
2644  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_GROUP_68_WIDTH },
2645 };
2646 
2652 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_MAX_NUM_CHECKERS] =
2653 {
2654  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
2655  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_0_WIDTH },
2656  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
2657  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_1_WIDTH },
2658  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
2659  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_2_WIDTH },
2660  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
2661  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_3_WIDTH },
2662  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
2663  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_4_WIDTH },
2664  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
2665  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_5_WIDTH },
2666  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
2667  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_6_WIDTH },
2668  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
2669  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_7_WIDTH },
2670  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
2671  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_8_WIDTH },
2672  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
2673  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_9_WIDTH },
2674  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
2675  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_10_WIDTH },
2676  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
2677  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_11_WIDTH },
2678  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
2679  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_12_WIDTH },
2680  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
2681  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_13_WIDTH },
2682  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
2683  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_GROUP_14_WIDTH },
2684 };
2685 
2691 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_MAX_NUM_CHECKERS] =
2692 {
2693  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_GROUP_0_CHECKER_TYPE,
2694  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_GROUP_0_WIDTH },
2695  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_GROUP_1_CHECKER_TYPE,
2696  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_GROUP_1_WIDTH },
2697  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_GROUP_2_CHECKER_TYPE,
2698  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_GROUP_2_WIDTH },
2699  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_GROUP_3_CHECKER_TYPE,
2700  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_GROUP_3_WIDTH },
2701 };
2702 
2708 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_MAX_NUM_CHECKERS] =
2709 {
2710  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
2711  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_0_WIDTH },
2712  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
2713  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_1_WIDTH },
2714  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
2715  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_2_WIDTH },
2716  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
2717  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_3_WIDTH },
2718  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
2719  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_4_WIDTH },
2720  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
2721  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_5_WIDTH },
2722  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
2723  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_6_WIDTH },
2724  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
2725  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_7_WIDTH },
2726  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
2727  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_8_WIDTH },
2728  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
2729  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_9_WIDTH },
2730  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
2731  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_10_WIDTH },
2732  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
2733  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_11_WIDTH },
2734  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
2735  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_12_WIDTH },
2736  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
2737  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_13_WIDTH },
2738  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
2739  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_GROUP_14_WIDTH },
2740 };
2741 
2747 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_DM2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_DM2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_MAX_NUM_CHECKERS] =
2748 {
2749  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_DM2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_0_CHECKER_TYPE,
2750  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_DM2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_0_WIDTH },
2751 };
2752 
2758 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_MAX_NUM_CHECKERS] =
2759 {
2760  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_0_CHECKER_TYPE,
2761  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_0_WIDTH },
2762  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_1_CHECKER_TYPE,
2763  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_1_WIDTH },
2764  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_2_CHECKER_TYPE,
2765  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_2_WIDTH },
2766  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_3_CHECKER_TYPE,
2767  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_3_WIDTH },
2768  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_4_CHECKER_TYPE,
2769  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_4_WIDTH },
2770  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_5_CHECKER_TYPE,
2771  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_5_WIDTH },
2772  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_6_CHECKER_TYPE,
2773  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_6_WIDTH },
2774  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_7_CHECKER_TYPE,
2775  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_7_WIDTH },
2776  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_8_CHECKER_TYPE,
2777  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_8_WIDTH },
2778  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_9_CHECKER_TYPE,
2779  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_9_WIDTH },
2780  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_10_CHECKER_TYPE,
2781  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_10_WIDTH },
2782  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_11_CHECKER_TYPE,
2783  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_11_WIDTH },
2784  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_12_CHECKER_TYPE,
2785  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_12_WIDTH },
2786  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_13_CHECKER_TYPE,
2787  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_13_WIDTH },
2788  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_14_CHECKER_TYPE,
2789  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_14_WIDTH },
2790  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_15_CHECKER_TYPE,
2791  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_15_WIDTH },
2792  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_16_CHECKER_TYPE,
2793  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_16_WIDTH },
2794  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_17_CHECKER_TYPE,
2795  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_17_WIDTH },
2796  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_18_CHECKER_TYPE,
2797  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_18_WIDTH },
2798  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_19_CHECKER_TYPE,
2799  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_19_WIDTH },
2800  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_20_CHECKER_TYPE,
2801  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_20_WIDTH },
2802  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_21_CHECKER_TYPE,
2803  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_21_WIDTH },
2804  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_22_CHECKER_TYPE,
2805  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_22_WIDTH },
2806  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_23_CHECKER_TYPE,
2807  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_23_WIDTH },
2808  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_24_CHECKER_TYPE,
2809  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_24_WIDTH },
2810  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_25_CHECKER_TYPE,
2811  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_25_WIDTH },
2812  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_26_CHECKER_TYPE,
2813  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_26_WIDTH },
2814  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_27_CHECKER_TYPE,
2815  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_27_WIDTH },
2816  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_28_CHECKER_TYPE,
2817  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_28_WIDTH },
2818  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_29_CHECKER_TYPE,
2819  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_29_WIDTH },
2820  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_30_CHECKER_TYPE,
2821  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_30_WIDTH },
2822  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_31_CHECKER_TYPE,
2823  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_31_WIDTH },
2824  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_32_CHECKER_TYPE,
2825  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_32_WIDTH },
2826  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_33_CHECKER_TYPE,
2827  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_33_WIDTH },
2828  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_34_CHECKER_TYPE,
2829  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_34_WIDTH },
2830  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_35_CHECKER_TYPE,
2831  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_35_WIDTH },
2832  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_36_CHECKER_TYPE,
2833  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_36_WIDTH },
2834  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_37_CHECKER_TYPE,
2835  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_37_WIDTH },
2836  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_38_CHECKER_TYPE,
2837  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_38_WIDTH },
2838  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_39_CHECKER_TYPE,
2839  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_39_WIDTH },
2840  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_40_CHECKER_TYPE,
2841  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_40_WIDTH },
2842  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_41_CHECKER_TYPE,
2843  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_41_WIDTH },
2844  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_42_CHECKER_TYPE,
2845  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_42_WIDTH },
2846  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_43_CHECKER_TYPE,
2847  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_43_WIDTH },
2848  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_44_CHECKER_TYPE,
2849  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_44_WIDTH },
2850  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_45_CHECKER_TYPE,
2851  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_45_WIDTH },
2852  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_46_CHECKER_TYPE,
2853  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_46_WIDTH },
2854  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_47_CHECKER_TYPE,
2855  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_47_WIDTH },
2856  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_48_CHECKER_TYPE,
2857  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_48_WIDTH },
2858  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_49_CHECKER_TYPE,
2859  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_49_WIDTH },
2860  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_50_CHECKER_TYPE,
2861  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_50_WIDTH },
2862  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_51_CHECKER_TYPE,
2863  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_51_WIDTH },
2864  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_52_CHECKER_TYPE,
2865  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_52_WIDTH },
2866  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_53_CHECKER_TYPE,
2867  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_53_WIDTH },
2868  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_54_CHECKER_TYPE,
2869  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_54_WIDTH },
2870  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_55_CHECKER_TYPE,
2871  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_55_WIDTH },
2872  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_56_CHECKER_TYPE,
2873  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_56_WIDTH },
2874  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_57_CHECKER_TYPE,
2875  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_57_WIDTH },
2876  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_58_CHECKER_TYPE,
2877  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_58_WIDTH },
2878  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_59_CHECKER_TYPE,
2879  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_59_WIDTH },
2880  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_60_CHECKER_TYPE,
2881  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_60_WIDTH },
2882  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_61_CHECKER_TYPE,
2883  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_61_WIDTH },
2884  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_62_CHECKER_TYPE,
2885  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_62_WIDTH },
2886  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_63_CHECKER_TYPE,
2887  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_63_WIDTH },
2888  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_64_CHECKER_TYPE,
2889  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_64_WIDTH },
2890  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_65_CHECKER_TYPE,
2891  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_65_WIDTH },
2892  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_66_CHECKER_TYPE,
2893  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_66_WIDTH },
2894  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_67_CHECKER_TYPE,
2895  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_67_WIDTH },
2896  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_68_CHECKER_TYPE,
2897  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_GROUP_68_WIDTH },
2898 };
2899 
2905 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
2906 {
2907  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
2908  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
2909  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
2910  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
2911  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
2912  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
2913  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
2914  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
2915  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_4_CHECKER_TYPE,
2916  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_4_WIDTH },
2917  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_5_CHECKER_TYPE,
2918  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_5_WIDTH },
2919  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_6_CHECKER_TYPE,
2920  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_6_WIDTH },
2921 };
2922 
2928 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
2929 {
2930  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
2931  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
2932  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
2933  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
2934  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
2935  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
2936  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
2937  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
2938  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
2939  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
2940  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
2941  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
2942  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
2943  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
2944  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
2945  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
2946  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
2947  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
2948  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
2949  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
2950  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
2951  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
2952  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
2953  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
2954  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
2955  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
2956  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
2957  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
2958  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
2959  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
2960  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_15_CHECKER_TYPE,
2961  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_15_WIDTH },
2962  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_16_CHECKER_TYPE,
2963  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_16_WIDTH },
2964 };
2965 
2971 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
2972 {
2973  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
2974  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
2975  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
2976  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
2977  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
2978  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
2979  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
2980  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_3_WIDTH },
2981  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
2982  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_4_WIDTH },
2983  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
2984  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_5_WIDTH },
2985  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
2986  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_6_WIDTH },
2987  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
2988  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_7_WIDTH },
2989  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
2990  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_8_WIDTH },
2991  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
2992  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_9_WIDTH },
2993  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
2994  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_10_WIDTH },
2995  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
2996  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_11_WIDTH },
2997  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
2998  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_12_WIDTH },
2999 };
3000 
3006 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
3007 {
3008  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
3009  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
3010  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
3011  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
3012  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
3013  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
3014  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
3015  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_3_WIDTH },
3016  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
3017  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_4_WIDTH },
3018  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
3019  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_5_WIDTH },
3020  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
3021  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_6_WIDTH },
3022  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
3023  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_7_WIDTH },
3024  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
3025  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_8_WIDTH },
3026  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
3027  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_9_WIDTH },
3028  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
3029  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_10_WIDTH },
3030  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
3031  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_11_WIDTH },
3032  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
3033  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_GROUP_12_WIDTH },
3034 };
3035 
3041 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
3042 {
3043  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
3044  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
3045  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
3046  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
3047  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
3048  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
3049  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
3050  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_3_WIDTH },
3051  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
3052  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_4_WIDTH },
3053  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
3054  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_5_WIDTH },
3055  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
3056  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_6_WIDTH },
3057  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
3058  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_7_WIDTH },
3059  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
3060  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_8_WIDTH },
3061  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
3062  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_9_WIDTH },
3063  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
3064  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_10_WIDTH },
3065  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
3066  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_11_WIDTH },
3067  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
3068  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_GROUP_12_WIDTH },
3069 };
3070 
3076 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
3077 {
3078  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
3079  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
3080  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
3081  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
3082  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
3083  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
3084  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
3085  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
3086  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_4_CHECKER_TYPE,
3087  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_4_WIDTH },
3088  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_5_CHECKER_TYPE,
3089  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_5_WIDTH },
3090  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_6_CHECKER_TYPE,
3091  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_GROUP_6_WIDTH },
3092 };
3093 
3099 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
3100 {
3101  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
3102  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
3103  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
3104  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
3105  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
3106  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
3107  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
3108  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
3109  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
3110  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
3111  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
3112  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
3113  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
3114  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
3115  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
3116  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
3117  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
3118  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
3119  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
3120  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
3121  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
3122  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
3123  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
3124  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
3125  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
3126  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
3127  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
3128  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
3129  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
3130  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
3131  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_15_CHECKER_TYPE,
3132  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_15_WIDTH },
3133  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_16_CHECKER_TYPE,
3134  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_GROUP_16_WIDTH },
3135 };
3136 
3142 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
3143 {
3144  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
3145  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
3146  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
3147  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
3148  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
3149  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
3150  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
3151  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_3_WIDTH },
3152  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
3153  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_4_WIDTH },
3154  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
3155  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_5_WIDTH },
3156  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
3157  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_6_WIDTH },
3158  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
3159  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_7_WIDTH },
3160  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
3161  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_8_WIDTH },
3162  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
3163  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_9_WIDTH },
3164  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
3165  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_10_WIDTH },
3166  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
3167  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_11_WIDTH },
3168  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
3169  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_12_WIDTH },
3170 };
3171 
3177 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
3178 {
3179  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
3180  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
3181  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
3182  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
3183  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
3184  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
3185  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
3186  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_3_WIDTH },
3187  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
3188  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_4_WIDTH },
3189  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
3190  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_5_WIDTH },
3191  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
3192  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_6_WIDTH },
3193  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
3194  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_7_WIDTH },
3195  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
3196  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_8_WIDTH },
3197  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
3198  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_9_WIDTH },
3199  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
3200  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_10_WIDTH },
3201  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
3202  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_11_WIDTH },
3203  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
3204  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_12_WIDTH },
3205 };
3206 
3212 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_MAX_NUM_CHECKERS] =
3213 {
3214  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_0_CHECKER_TYPE,
3215  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_0_WIDTH },
3216  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_1_CHECKER_TYPE,
3217  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_1_WIDTH },
3218  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_2_CHECKER_TYPE,
3219  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_2_WIDTH },
3220  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_3_CHECKER_TYPE,
3221  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_3_WIDTH },
3222  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_4_CHECKER_TYPE,
3223  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_4_WIDTH },
3224  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_5_CHECKER_TYPE,
3225  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_5_WIDTH },
3226  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_6_CHECKER_TYPE,
3227  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_6_WIDTH },
3228  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_7_CHECKER_TYPE,
3229  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_7_WIDTH },
3230  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_8_CHECKER_TYPE,
3231  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_8_WIDTH },
3232  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_9_CHECKER_TYPE,
3233  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_9_WIDTH },
3234  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_10_CHECKER_TYPE,
3235  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_10_WIDTH },
3236  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_11_CHECKER_TYPE,
3237  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_11_WIDTH },
3238  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_12_CHECKER_TYPE,
3239  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_12_WIDTH },
3240  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_13_CHECKER_TYPE,
3241  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_13_WIDTH },
3242  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_14_CHECKER_TYPE,
3243  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_14_WIDTH },
3244  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_15_CHECKER_TYPE,
3245  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_15_WIDTH },
3246  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_16_CHECKER_TYPE,
3247  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_16_WIDTH },
3248  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_17_CHECKER_TYPE,
3249  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_17_WIDTH },
3250  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_18_CHECKER_TYPE,
3251  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_18_WIDTH },
3252  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_19_CHECKER_TYPE,
3253  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_19_WIDTH },
3254  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_20_CHECKER_TYPE,
3255  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_20_WIDTH },
3256  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_21_CHECKER_TYPE,
3257  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_21_WIDTH },
3258  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_22_CHECKER_TYPE,
3259  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_22_WIDTH },
3260  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_23_CHECKER_TYPE,
3261  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_23_WIDTH },
3262  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_24_CHECKER_TYPE,
3263  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_24_WIDTH },
3264  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_25_CHECKER_TYPE,
3265  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_25_WIDTH },
3266  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_26_CHECKER_TYPE,
3267  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_26_WIDTH },
3268  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_27_CHECKER_TYPE,
3269  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_27_WIDTH },
3270  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_28_CHECKER_TYPE,
3271  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_28_WIDTH },
3272  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_29_CHECKER_TYPE,
3273  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_29_WIDTH },
3274  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_30_CHECKER_TYPE,
3275  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_30_WIDTH },
3276  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_31_CHECKER_TYPE,
3277  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_31_WIDTH },
3278  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_32_CHECKER_TYPE,
3279  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_32_WIDTH },
3280  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_33_CHECKER_TYPE,
3281  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_33_WIDTH },
3282  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_34_CHECKER_TYPE,
3283  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_34_WIDTH },
3284  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_35_CHECKER_TYPE,
3285  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_35_WIDTH },
3286  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_36_CHECKER_TYPE,
3287  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_36_WIDTH },
3288  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_37_CHECKER_TYPE,
3289  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_37_WIDTH },
3290  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_38_CHECKER_TYPE,
3291  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_38_WIDTH },
3292  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_39_CHECKER_TYPE,
3293  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_39_WIDTH },
3294  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_40_CHECKER_TYPE,
3295  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_40_WIDTH },
3296  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_41_CHECKER_TYPE,
3297  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_41_WIDTH },
3298  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_42_CHECKER_TYPE,
3299  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_42_WIDTH },
3300  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_43_CHECKER_TYPE,
3301  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_43_WIDTH },
3302  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_44_CHECKER_TYPE,
3303  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_44_WIDTH },
3304  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_45_CHECKER_TYPE,
3305  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_45_WIDTH },
3306  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_46_CHECKER_TYPE,
3307  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_46_WIDTH },
3308  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_47_CHECKER_TYPE,
3309  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_47_WIDTH },
3310  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_48_CHECKER_TYPE,
3311  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_48_WIDTH },
3312  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_49_CHECKER_TYPE,
3313  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_49_WIDTH },
3314  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_50_CHECKER_TYPE,
3315  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_50_WIDTH },
3316  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_51_CHECKER_TYPE,
3317  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_51_WIDTH },
3318  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_52_CHECKER_TYPE,
3319  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_52_WIDTH },
3320  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_53_CHECKER_TYPE,
3321  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_53_WIDTH },
3322  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_54_CHECKER_TYPE,
3323  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_54_WIDTH },
3324  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_55_CHECKER_TYPE,
3325  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_55_WIDTH },
3326  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_56_CHECKER_TYPE,
3327  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_56_WIDTH },
3328  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_57_CHECKER_TYPE,
3329  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_57_WIDTH },
3330  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_58_CHECKER_TYPE,
3331  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_58_WIDTH },
3332  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_59_CHECKER_TYPE,
3333  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_59_WIDTH },
3334  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_60_CHECKER_TYPE,
3335  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_60_WIDTH },
3336  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_61_CHECKER_TYPE,
3337  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_61_WIDTH },
3338  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_62_CHECKER_TYPE,
3339  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_62_WIDTH },
3340  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_63_CHECKER_TYPE,
3341  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_63_WIDTH },
3342  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_64_CHECKER_TYPE,
3343  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_64_WIDTH },
3344  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_65_CHECKER_TYPE,
3345  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_65_WIDTH },
3346  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_66_CHECKER_TYPE,
3347  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_66_WIDTH },
3348  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_67_CHECKER_TYPE,
3349  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_67_WIDTH },
3350  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_68_CHECKER_TYPE,
3351  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_68_WIDTH },
3352  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_69_CHECKER_TYPE,
3353  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_69_WIDTH },
3354  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_70_CHECKER_TYPE,
3355  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_70_WIDTH },
3356  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_71_CHECKER_TYPE,
3357  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_71_WIDTH },
3358  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_72_CHECKER_TYPE,
3359  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_72_WIDTH },
3360  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_73_CHECKER_TYPE,
3361  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_73_WIDTH },
3362  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_74_CHECKER_TYPE,
3363  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_74_WIDTH },
3364  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_75_CHECKER_TYPE,
3365  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_75_WIDTH },
3366  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_76_CHECKER_TYPE,
3367  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_76_WIDTH },
3368  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_77_CHECKER_TYPE,
3369  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_77_WIDTH },
3370  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_78_CHECKER_TYPE,
3371  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_78_WIDTH },
3372  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_79_CHECKER_TYPE,
3373  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_79_WIDTH },
3374  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_80_CHECKER_TYPE,
3375  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_80_WIDTH },
3376  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_81_CHECKER_TYPE,
3377  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_81_WIDTH },
3378  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_82_CHECKER_TYPE,
3379  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_82_WIDTH },
3380  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_83_CHECKER_TYPE,
3381  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_83_WIDTH },
3382  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_84_CHECKER_TYPE,
3383  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_84_WIDTH },
3384  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_85_CHECKER_TYPE,
3385  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_85_WIDTH },
3386  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_86_CHECKER_TYPE,
3387  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_86_WIDTH },
3388  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_87_CHECKER_TYPE,
3389  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_87_WIDTH },
3390  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_88_CHECKER_TYPE,
3391  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_88_WIDTH },
3392  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_89_CHECKER_TYPE,
3393  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_89_WIDTH },
3394  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_90_CHECKER_TYPE,
3395  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_90_WIDTH },
3396  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_91_CHECKER_TYPE,
3397  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_91_WIDTH },
3398  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_92_CHECKER_TYPE,
3399  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_92_WIDTH },
3400  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_93_CHECKER_TYPE,
3401  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_93_WIDTH },
3402  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_94_CHECKER_TYPE,
3403  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_94_WIDTH },
3404  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_95_CHECKER_TYPE,
3405  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_95_WIDTH },
3406  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_96_CHECKER_TYPE,
3407  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_96_WIDTH },
3408  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_97_CHECKER_TYPE,
3409  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_97_WIDTH },
3410  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_98_CHECKER_TYPE,
3411  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_98_WIDTH },
3412  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_99_CHECKER_TYPE,
3413  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_99_WIDTH },
3414  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_100_CHECKER_TYPE,
3415  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_100_WIDTH },
3416  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_101_CHECKER_TYPE,
3417  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_101_WIDTH },
3418  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_102_CHECKER_TYPE,
3419  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_102_WIDTH },
3420  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_103_CHECKER_TYPE,
3421  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_103_WIDTH },
3422  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_104_CHECKER_TYPE,
3423  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_104_WIDTH },
3424  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_105_CHECKER_TYPE,
3425  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_105_WIDTH },
3426  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_106_CHECKER_TYPE,
3427  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_106_WIDTH },
3428  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_107_CHECKER_TYPE,
3429  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_107_WIDTH },
3430  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_108_CHECKER_TYPE,
3431  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_108_WIDTH },
3432  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_109_CHECKER_TYPE,
3433  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_109_WIDTH },
3434  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_110_CHECKER_TYPE,
3435  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_110_WIDTH },
3436  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_111_CHECKER_TYPE,
3437  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_111_WIDTH },
3438  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_112_CHECKER_TYPE,
3439  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_112_WIDTH },
3440  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_113_CHECKER_TYPE,
3441  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_113_WIDTH },
3442  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_114_CHECKER_TYPE,
3443  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_114_WIDTH },
3444  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_115_CHECKER_TYPE,
3445  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_115_WIDTH },
3446  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_116_CHECKER_TYPE,
3447  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_116_WIDTH },
3448  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_117_CHECKER_TYPE,
3449  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_117_WIDTH },
3450  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_118_CHECKER_TYPE,
3451  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_118_WIDTH },
3452  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_119_CHECKER_TYPE,
3453  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_119_WIDTH },
3454  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_120_CHECKER_TYPE,
3455  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_120_WIDTH },
3456  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_121_CHECKER_TYPE,
3457  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_121_WIDTH },
3458  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_122_CHECKER_TYPE,
3459  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_122_WIDTH },
3460  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_123_CHECKER_TYPE,
3461  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_123_WIDTH },
3462  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_124_CHECKER_TYPE,
3463  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_124_WIDTH },
3464  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_125_CHECKER_TYPE,
3465  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_125_WIDTH },
3466  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_126_CHECKER_TYPE,
3467  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_126_WIDTH },
3468  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_127_CHECKER_TYPE,
3469  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_127_WIDTH },
3470  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_128_CHECKER_TYPE,
3471  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_128_WIDTH },
3472  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_129_CHECKER_TYPE,
3473  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_129_WIDTH },
3474  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_130_CHECKER_TYPE,
3475  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_130_WIDTH },
3476  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_131_CHECKER_TYPE,
3477  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_131_WIDTH },
3478  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_132_CHECKER_TYPE,
3479  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_132_WIDTH },
3480  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_133_CHECKER_TYPE,
3481  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_133_WIDTH },
3482  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_134_CHECKER_TYPE,
3483  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_134_WIDTH },
3484  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_135_CHECKER_TYPE,
3485  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_135_WIDTH },
3486  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_136_CHECKER_TYPE,
3487  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_136_WIDTH },
3488  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_137_CHECKER_TYPE,
3489  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_137_WIDTH },
3490  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_138_CHECKER_TYPE,
3491  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_138_WIDTH },
3492  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_139_CHECKER_TYPE,
3493  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_139_WIDTH },
3494  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_140_CHECKER_TYPE,
3495  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_140_WIDTH },
3496  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_141_CHECKER_TYPE,
3497  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_141_WIDTH },
3498  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_142_CHECKER_TYPE,
3499  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_142_WIDTH },
3500  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_143_CHECKER_TYPE,
3501  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_143_WIDTH },
3502  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_144_CHECKER_TYPE,
3503  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_144_WIDTH },
3504  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_145_CHECKER_TYPE,
3505  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_145_WIDTH },
3506  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_146_CHECKER_TYPE,
3507  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_146_WIDTH },
3508  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_147_CHECKER_TYPE,
3509  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_147_WIDTH },
3510  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_148_CHECKER_TYPE,
3511  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_148_WIDTH },
3512  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_149_CHECKER_TYPE,
3513  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_149_WIDTH },
3514  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_150_CHECKER_TYPE,
3515  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_150_WIDTH },
3516  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_151_CHECKER_TYPE,
3517  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_151_WIDTH },
3518  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_152_CHECKER_TYPE,
3519  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_152_WIDTH },
3520  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_153_CHECKER_TYPE,
3521  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_153_WIDTH },
3522  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_154_CHECKER_TYPE,
3523  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_154_WIDTH },
3524  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_155_CHECKER_TYPE,
3525  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_155_WIDTH },
3526  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_156_CHECKER_TYPE,
3527  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_156_WIDTH },
3528  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_157_CHECKER_TYPE,
3529  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_157_WIDTH },
3530  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_158_CHECKER_TYPE,
3531  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_158_WIDTH },
3532  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_159_CHECKER_TYPE,
3533  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_159_WIDTH },
3534  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_160_CHECKER_TYPE,
3535  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_160_WIDTH },
3536  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_161_CHECKER_TYPE,
3537  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_161_WIDTH },
3538  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_162_CHECKER_TYPE,
3539  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_162_WIDTH },
3540  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_163_CHECKER_TYPE,
3541  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_163_WIDTH },
3542  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_164_CHECKER_TYPE,
3543  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_164_WIDTH },
3544  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_165_CHECKER_TYPE,
3545  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_165_WIDTH },
3546  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_166_CHECKER_TYPE,
3547  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_166_WIDTH },
3548  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_167_CHECKER_TYPE,
3549  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_167_WIDTH },
3550  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_168_CHECKER_TYPE,
3551  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_168_WIDTH },
3552  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_169_CHECKER_TYPE,
3553  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_169_WIDTH },
3554  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_170_CHECKER_TYPE,
3555  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_170_WIDTH },
3556  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_171_CHECKER_TYPE,
3557  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_171_WIDTH },
3558  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_172_CHECKER_TYPE,
3559  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_172_WIDTH },
3560  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_173_CHECKER_TYPE,
3561  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_173_WIDTH },
3562  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_174_CHECKER_TYPE,
3563  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_174_WIDTH },
3564  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_175_CHECKER_TYPE,
3565  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_175_WIDTH },
3566  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_176_CHECKER_TYPE,
3567  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_176_WIDTH },
3568  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_177_CHECKER_TYPE,
3569  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_177_WIDTH },
3570  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_178_CHECKER_TYPE,
3571  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_178_WIDTH },
3572  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_179_CHECKER_TYPE,
3573  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_179_WIDTH },
3574  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_180_CHECKER_TYPE,
3575  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_180_WIDTH },
3576  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_181_CHECKER_TYPE,
3577  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_181_WIDTH },
3578  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_182_CHECKER_TYPE,
3579  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_182_WIDTH },
3580  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_183_CHECKER_TYPE,
3581  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_183_WIDTH },
3582  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_184_CHECKER_TYPE,
3583  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_184_WIDTH },
3584  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_185_CHECKER_TYPE,
3585  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_185_WIDTH },
3586  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_186_CHECKER_TYPE,
3587  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_186_WIDTH },
3588  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_187_CHECKER_TYPE,
3589  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_187_WIDTH },
3590  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_188_CHECKER_TYPE,
3591  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_188_WIDTH },
3592  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_189_CHECKER_TYPE,
3593  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_189_WIDTH },
3594  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_190_CHECKER_TYPE,
3595  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_190_WIDTH },
3596  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_191_CHECKER_TYPE,
3597  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_191_WIDTH },
3598  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_192_CHECKER_TYPE,
3599  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_192_WIDTH },
3600  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_193_CHECKER_TYPE,
3601  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_193_WIDTH },
3602  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_194_CHECKER_TYPE,
3603  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_194_WIDTH },
3604  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_195_CHECKER_TYPE,
3605  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_195_WIDTH },
3606  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_196_CHECKER_TYPE,
3607  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_196_WIDTH },
3608  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_197_CHECKER_TYPE,
3609  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_197_WIDTH },
3610  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_198_CHECKER_TYPE,
3611  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_198_WIDTH },
3612  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_199_CHECKER_TYPE,
3613  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_199_WIDTH },
3614  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_200_CHECKER_TYPE,
3615  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_200_WIDTH },
3616  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_201_CHECKER_TYPE,
3617  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_201_WIDTH },
3618  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_202_CHECKER_TYPE,
3619  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_202_WIDTH },
3620  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_203_CHECKER_TYPE,
3621  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_203_WIDTH },
3622  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_204_CHECKER_TYPE,
3623  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_204_WIDTH },
3624  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_205_CHECKER_TYPE,
3625  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_205_WIDTH },
3626  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_206_CHECKER_TYPE,
3627  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_206_WIDTH },
3628  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_207_CHECKER_TYPE,
3629  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_207_WIDTH },
3630  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_208_CHECKER_TYPE,
3631  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_208_WIDTH },
3632  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_209_CHECKER_TYPE,
3633  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_209_WIDTH },
3634  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_210_CHECKER_TYPE,
3635  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_210_WIDTH },
3636  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_211_CHECKER_TYPE,
3637  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_211_WIDTH },
3638  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_212_CHECKER_TYPE,
3639  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_212_WIDTH },
3640  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_213_CHECKER_TYPE,
3641  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_213_WIDTH },
3642  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_214_CHECKER_TYPE,
3643  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_214_WIDTH },
3644  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_215_CHECKER_TYPE,
3645  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_GROUP_215_WIDTH },
3646 };
3647 
3653 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_MAX_NUM_CHECKERS] =
3654 {
3655  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_0_CHECKER_TYPE,
3656  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_0_WIDTH },
3657  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_1_CHECKER_TYPE,
3658  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_1_WIDTH },
3659  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_2_CHECKER_TYPE,
3660  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_2_WIDTH },
3661  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_3_CHECKER_TYPE,
3662  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_3_WIDTH },
3663  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_4_CHECKER_TYPE,
3664  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_4_WIDTH },
3665  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_5_CHECKER_TYPE,
3666  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_5_WIDTH },
3667  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_6_CHECKER_TYPE,
3668  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_6_WIDTH },
3669  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_7_CHECKER_TYPE,
3670  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_7_WIDTH },
3671  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_8_CHECKER_TYPE,
3672  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_8_WIDTH },
3673  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_9_CHECKER_TYPE,
3674  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_9_WIDTH },
3675  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_10_CHECKER_TYPE,
3676  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_10_WIDTH },
3677  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_11_CHECKER_TYPE,
3678  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_11_WIDTH },
3679  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_12_CHECKER_TYPE,
3680  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_12_WIDTH },
3681  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_13_CHECKER_TYPE,
3682  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_13_WIDTH },
3683  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_14_CHECKER_TYPE,
3684  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_14_WIDTH },
3685  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_15_CHECKER_TYPE,
3686  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_15_WIDTH },
3687  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_16_CHECKER_TYPE,
3688  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_16_WIDTH },
3689  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_17_CHECKER_TYPE,
3690  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_17_WIDTH },
3691  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_18_CHECKER_TYPE,
3692  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_18_WIDTH },
3693  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_19_CHECKER_TYPE,
3694  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_19_WIDTH },
3695  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_20_CHECKER_TYPE,
3696  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_20_WIDTH },
3697  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_21_CHECKER_TYPE,
3698  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_21_WIDTH },
3699  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_22_CHECKER_TYPE,
3700  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_22_WIDTH },
3701  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_23_CHECKER_TYPE,
3702  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_23_WIDTH },
3703  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_24_CHECKER_TYPE,
3704  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_24_WIDTH },
3705  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_25_CHECKER_TYPE,
3706  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_25_WIDTH },
3707  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_26_CHECKER_TYPE,
3708  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_26_WIDTH },
3709  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_27_CHECKER_TYPE,
3710  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_27_WIDTH },
3711  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_28_CHECKER_TYPE,
3712  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_28_WIDTH },
3713  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_29_CHECKER_TYPE,
3714  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_29_WIDTH },
3715  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_30_CHECKER_TYPE,
3716  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_30_WIDTH },
3717  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_31_CHECKER_TYPE,
3718  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_31_WIDTH },
3719  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_32_CHECKER_TYPE,
3720  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_32_WIDTH },
3721  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_33_CHECKER_TYPE,
3722  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_33_WIDTH },
3723  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_34_CHECKER_TYPE,
3724  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_34_WIDTH },
3725  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_35_CHECKER_TYPE,
3726  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_35_WIDTH },
3727  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_36_CHECKER_TYPE,
3728  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_36_WIDTH },
3729  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_37_CHECKER_TYPE,
3730  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_37_WIDTH },
3731  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_38_CHECKER_TYPE,
3732  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_38_WIDTH },
3733  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_39_CHECKER_TYPE,
3734  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_39_WIDTH },
3735  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_40_CHECKER_TYPE,
3736  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_40_WIDTH },
3737  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_41_CHECKER_TYPE,
3738  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_41_WIDTH },
3739  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_42_CHECKER_TYPE,
3740  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_42_WIDTH },
3741  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_43_CHECKER_TYPE,
3742  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_43_WIDTH },
3743  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_44_CHECKER_TYPE,
3744  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_44_WIDTH },
3745  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_45_CHECKER_TYPE,
3746  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_45_WIDTH },
3747  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_46_CHECKER_TYPE,
3748  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_46_WIDTH },
3749  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_47_CHECKER_TYPE,
3750  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_47_WIDTH },
3751  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_48_CHECKER_TYPE,
3752  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_48_WIDTH },
3753  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_49_CHECKER_TYPE,
3754  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_49_WIDTH },
3755  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_50_CHECKER_TYPE,
3756  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_50_WIDTH },
3757  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_51_CHECKER_TYPE,
3758  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_51_WIDTH },
3759  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_52_CHECKER_TYPE,
3760  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_52_WIDTH },
3761  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_53_CHECKER_TYPE,
3762  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_53_WIDTH },
3763  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_54_CHECKER_TYPE,
3764  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_54_WIDTH },
3765  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_55_CHECKER_TYPE,
3766  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_55_WIDTH },
3767  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_56_CHECKER_TYPE,
3768  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_56_WIDTH },
3769  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_57_CHECKER_TYPE,
3770  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_57_WIDTH },
3771  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_58_CHECKER_TYPE,
3772  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_58_WIDTH },
3773  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_59_CHECKER_TYPE,
3774  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_59_WIDTH },
3775  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_60_CHECKER_TYPE,
3776  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_60_WIDTH },
3777  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_61_CHECKER_TYPE,
3778  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_61_WIDTH },
3779  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_62_CHECKER_TYPE,
3780  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_62_WIDTH },
3781  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_63_CHECKER_TYPE,
3782  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_63_WIDTH },
3783  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_64_CHECKER_TYPE,
3784  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_64_WIDTH },
3785  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_65_CHECKER_TYPE,
3786  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_65_WIDTH },
3787  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_66_CHECKER_TYPE,
3788  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_66_WIDTH },
3789  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_67_CHECKER_TYPE,
3790  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_67_WIDTH },
3791  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_68_CHECKER_TYPE,
3792  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_68_WIDTH },
3793  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_69_CHECKER_TYPE,
3794  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_69_WIDTH },
3795  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_70_CHECKER_TYPE,
3796  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_70_WIDTH },
3797  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_71_CHECKER_TYPE,
3798  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_71_WIDTH },
3799  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_72_CHECKER_TYPE,
3800  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_72_WIDTH },
3801  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_73_CHECKER_TYPE,
3802  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_73_WIDTH },
3803  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_74_CHECKER_TYPE,
3804  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_74_WIDTH },
3805  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_75_CHECKER_TYPE,
3806  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_75_WIDTH },
3807  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_76_CHECKER_TYPE,
3808  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_76_WIDTH },
3809  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_77_CHECKER_TYPE,
3810  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_77_WIDTH },
3811  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_78_CHECKER_TYPE,
3812  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_78_WIDTH },
3813  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_79_CHECKER_TYPE,
3814  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_79_WIDTH },
3815  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_80_CHECKER_TYPE,
3816  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_80_WIDTH },
3817  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_81_CHECKER_TYPE,
3818  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_81_WIDTH },
3819  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_82_CHECKER_TYPE,
3820  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_82_WIDTH },
3821  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_83_CHECKER_TYPE,
3822  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_83_WIDTH },
3823  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_84_CHECKER_TYPE,
3824  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_84_WIDTH },
3825  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_85_CHECKER_TYPE,
3826  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_85_WIDTH },
3827  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_86_CHECKER_TYPE,
3828  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_86_WIDTH },
3829  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_87_CHECKER_TYPE,
3830  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_87_WIDTH },
3831  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_88_CHECKER_TYPE,
3832  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_88_WIDTH },
3833  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_89_CHECKER_TYPE,
3834  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_89_WIDTH },
3835  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_90_CHECKER_TYPE,
3836  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_90_WIDTH },
3837  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_91_CHECKER_TYPE,
3838  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_91_WIDTH },
3839  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_92_CHECKER_TYPE,
3840  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_92_WIDTH },
3841  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_93_CHECKER_TYPE,
3842  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_93_WIDTH },
3843  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_94_CHECKER_TYPE,
3844  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_94_WIDTH },
3845  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_95_CHECKER_TYPE,
3846  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_95_WIDTH },
3847  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_96_CHECKER_TYPE,
3848  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_96_WIDTH },
3849  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_97_CHECKER_TYPE,
3850  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_97_WIDTH },
3851  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_98_CHECKER_TYPE,
3852  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_98_WIDTH },
3853  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_99_CHECKER_TYPE,
3854  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_99_WIDTH },
3855  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_100_CHECKER_TYPE,
3856  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_100_WIDTH },
3857  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_101_CHECKER_TYPE,
3858  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_101_WIDTH },
3859  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_102_CHECKER_TYPE,
3860  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_102_WIDTH },
3861  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_103_CHECKER_TYPE,
3862  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_103_WIDTH },
3863  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_104_CHECKER_TYPE,
3864  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_GROUP_104_WIDTH },
3865 };
3866 
3872 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS] =
3873 {
3874  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_0_CHECKER_TYPE,
3875  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_0_WIDTH },
3876  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_1_CHECKER_TYPE,
3877  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_1_WIDTH },
3878  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_2_CHECKER_TYPE,
3879  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_2_WIDTH },
3880  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_3_CHECKER_TYPE,
3881  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_3_WIDTH },
3882  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_4_CHECKER_TYPE,
3883  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_4_WIDTH },
3884  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_5_CHECKER_TYPE,
3885  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_5_WIDTH },
3886  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_6_CHECKER_TYPE,
3887  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_6_WIDTH },
3888  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_7_CHECKER_TYPE,
3889  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_7_WIDTH },
3890  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_8_CHECKER_TYPE,
3891  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_8_WIDTH },
3892  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_9_CHECKER_TYPE,
3893  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_9_WIDTH },
3894  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_10_CHECKER_TYPE,
3895  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_10_WIDTH },
3896  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_11_CHECKER_TYPE,
3897  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_11_WIDTH },
3898  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_12_CHECKER_TYPE,
3899  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_12_WIDTH },
3900  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_13_CHECKER_TYPE,
3901  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_13_WIDTH },
3902  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_14_CHECKER_TYPE,
3903  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_14_WIDTH },
3904  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_15_CHECKER_TYPE,
3905  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_15_WIDTH },
3906  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_16_CHECKER_TYPE,
3907  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_16_WIDTH },
3908  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_17_CHECKER_TYPE,
3909  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_17_WIDTH },
3910  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_18_CHECKER_TYPE,
3911  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_18_WIDTH },
3912  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_19_CHECKER_TYPE,
3913  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_19_WIDTH },
3914  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_20_CHECKER_TYPE,
3915  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_20_WIDTH },
3916  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_21_CHECKER_TYPE,
3917  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_21_WIDTH },
3918  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_22_CHECKER_TYPE,
3919  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_22_WIDTH },
3920  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_23_CHECKER_TYPE,
3921  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_23_WIDTH },
3922  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_24_CHECKER_TYPE,
3923  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_24_WIDTH },
3924  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_25_CHECKER_TYPE,
3925  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_25_WIDTH },
3926  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_26_CHECKER_TYPE,
3927  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_26_WIDTH },
3928  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_27_CHECKER_TYPE,
3929  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_27_WIDTH },
3930  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_28_CHECKER_TYPE,
3931  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_28_WIDTH },
3932  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_29_CHECKER_TYPE,
3933  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_29_WIDTH },
3934  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_30_CHECKER_TYPE,
3935  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_30_WIDTH },
3936  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_31_CHECKER_TYPE,
3937  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_31_WIDTH },
3938  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_32_CHECKER_TYPE,
3939  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_32_WIDTH },
3940  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_33_CHECKER_TYPE,
3941  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_33_WIDTH },
3942  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_34_CHECKER_TYPE,
3943  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_34_WIDTH },
3944  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_35_CHECKER_TYPE,
3945  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_35_WIDTH },
3946  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_36_CHECKER_TYPE,
3947  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_36_WIDTH },
3948  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_37_CHECKER_TYPE,
3949  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_37_WIDTH },
3950  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_38_CHECKER_TYPE,
3951  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_38_WIDTH },
3952  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_39_CHECKER_TYPE,
3953  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_39_WIDTH },
3954  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_40_CHECKER_TYPE,
3955  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_40_WIDTH },
3956  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_41_CHECKER_TYPE,
3957  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_41_WIDTH },
3958  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_42_CHECKER_TYPE,
3959  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_42_WIDTH },
3960  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_43_CHECKER_TYPE,
3961  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_43_WIDTH },
3962  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_44_CHECKER_TYPE,
3963  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_44_WIDTH },
3964  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_45_CHECKER_TYPE,
3965  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_45_WIDTH },
3966  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_46_CHECKER_TYPE,
3967  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_46_WIDTH },
3968  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_47_CHECKER_TYPE,
3969  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_47_WIDTH },
3970  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_48_CHECKER_TYPE,
3971  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_48_WIDTH },
3972  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_49_CHECKER_TYPE,
3973  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_49_WIDTH },
3974  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_50_CHECKER_TYPE,
3975  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_50_WIDTH },
3976  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_51_CHECKER_TYPE,
3977  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_51_WIDTH },
3978  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_52_CHECKER_TYPE,
3979  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_52_WIDTH },
3980  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_53_CHECKER_TYPE,
3981  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_53_WIDTH },
3982  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_54_CHECKER_TYPE,
3983  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_54_WIDTH },
3984  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_55_CHECKER_TYPE,
3985  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_55_WIDTH },
3986  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_56_CHECKER_TYPE,
3987  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_56_WIDTH },
3988  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_57_CHECKER_TYPE,
3989  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_57_WIDTH },
3990  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_58_CHECKER_TYPE,
3991  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_58_WIDTH },
3992  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_59_CHECKER_TYPE,
3993  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_59_WIDTH },
3994  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_60_CHECKER_TYPE,
3995  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_60_WIDTH },
3996  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_61_CHECKER_TYPE,
3997  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_61_WIDTH },
3998  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_62_CHECKER_TYPE,
3999  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_62_WIDTH },
4000  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_63_CHECKER_TYPE,
4001  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_63_WIDTH },
4002  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_64_CHECKER_TYPE,
4003  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_64_WIDTH },
4004  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_65_CHECKER_TYPE,
4005  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_65_WIDTH },
4006  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_66_CHECKER_TYPE,
4007  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_66_WIDTH },
4008  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_67_CHECKER_TYPE,
4009  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_67_WIDTH },
4010  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_68_CHECKER_TYPE,
4011  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_68_WIDTH },
4012  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_69_CHECKER_TYPE,
4013  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_69_WIDTH },
4014  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_70_CHECKER_TYPE,
4015  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_70_WIDTH },
4016  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_71_CHECKER_TYPE,
4017  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_71_WIDTH },
4018  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_72_CHECKER_TYPE,
4019  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_72_WIDTH },
4020  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_73_CHECKER_TYPE,
4021  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_73_WIDTH },
4022  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_74_CHECKER_TYPE,
4023  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_74_WIDTH },
4024  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_75_CHECKER_TYPE,
4025  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_75_WIDTH },
4026  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_76_CHECKER_TYPE,
4027  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_76_WIDTH },
4028  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_77_CHECKER_TYPE,
4029  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_77_WIDTH },
4030  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_78_CHECKER_TYPE,
4031  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_78_WIDTH },
4032  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_79_CHECKER_TYPE,
4033  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_79_WIDTH },
4034  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_80_CHECKER_TYPE,
4035  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_80_WIDTH },
4036  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_81_CHECKER_TYPE,
4037  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_81_WIDTH },
4038  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_82_CHECKER_TYPE,
4039  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_82_WIDTH },
4040  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_83_CHECKER_TYPE,
4041  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_83_WIDTH },
4042  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_84_CHECKER_TYPE,
4043  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_84_WIDTH },
4044  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_85_CHECKER_TYPE,
4045  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_85_WIDTH },
4046  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_86_CHECKER_TYPE,
4047  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_86_WIDTH },
4048  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_87_CHECKER_TYPE,
4049  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_87_WIDTH },
4050  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_88_CHECKER_TYPE,
4051  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_88_WIDTH },
4052  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_89_CHECKER_TYPE,
4053  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_89_WIDTH },
4054  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_90_CHECKER_TYPE,
4055  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_90_WIDTH },
4056  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_91_CHECKER_TYPE,
4057  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_91_WIDTH },
4058  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_92_CHECKER_TYPE,
4059  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_92_WIDTH },
4060  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_93_CHECKER_TYPE,
4061  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_93_WIDTH },
4062  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_94_CHECKER_TYPE,
4063  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_94_WIDTH },
4064  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_95_CHECKER_TYPE,
4065  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_95_WIDTH },
4066  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_96_CHECKER_TYPE,
4067  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_96_WIDTH },
4068  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_97_CHECKER_TYPE,
4069  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_97_WIDTH },
4070  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_98_CHECKER_TYPE,
4071  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_98_WIDTH },
4072  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_99_CHECKER_TYPE,
4073  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_99_WIDTH },
4074  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_100_CHECKER_TYPE,
4075  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_100_WIDTH },
4076  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_101_CHECKER_TYPE,
4077  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_101_WIDTH },
4078  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_102_CHECKER_TYPE,
4079  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_102_WIDTH },
4080  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_103_CHECKER_TYPE,
4081  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_103_WIDTH },
4082  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_104_CHECKER_TYPE,
4083  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_104_WIDTH },
4084  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_105_CHECKER_TYPE,
4085  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_105_WIDTH },
4086  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_106_CHECKER_TYPE,
4087  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_106_WIDTH },
4088  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_107_CHECKER_TYPE,
4089  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_107_WIDTH },
4090  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_108_CHECKER_TYPE,
4091  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_108_WIDTH },
4092  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_109_CHECKER_TYPE,
4093  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_109_WIDTH },
4094  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_110_CHECKER_TYPE,
4095  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_110_WIDTH },
4096  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_111_CHECKER_TYPE,
4097  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_111_WIDTH },
4098  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_112_CHECKER_TYPE,
4099  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_112_WIDTH },
4100  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_113_CHECKER_TYPE,
4101  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_113_WIDTH },
4102  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_114_CHECKER_TYPE,
4103  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_114_WIDTH },
4104  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_115_CHECKER_TYPE,
4105  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_115_WIDTH },
4106  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_116_CHECKER_TYPE,
4107  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_116_WIDTH },
4108  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_117_CHECKER_TYPE,
4109  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_117_WIDTH },
4110  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_118_CHECKER_TYPE,
4111  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_118_WIDTH },
4112  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_119_CHECKER_TYPE,
4113  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_119_WIDTH },
4114  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_120_CHECKER_TYPE,
4115  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_120_WIDTH },
4116  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_121_CHECKER_TYPE,
4117  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_121_WIDTH },
4118  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_122_CHECKER_TYPE,
4119  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_122_WIDTH },
4120  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_123_CHECKER_TYPE,
4121  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_123_WIDTH },
4122  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_124_CHECKER_TYPE,
4123  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_124_WIDTH },
4124  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_125_CHECKER_TYPE,
4125  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_125_WIDTH },
4126  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_126_CHECKER_TYPE,
4127  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_126_WIDTH },
4128  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_127_CHECKER_TYPE,
4129  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_127_WIDTH },
4130  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_128_CHECKER_TYPE,
4131  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_128_WIDTH },
4132  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_129_CHECKER_TYPE,
4133  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_129_WIDTH },
4134  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_130_CHECKER_TYPE,
4135  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_130_WIDTH },
4136  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_131_CHECKER_TYPE,
4137  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_131_WIDTH },
4138  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_132_CHECKER_TYPE,
4139  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_132_WIDTH },
4140  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_133_CHECKER_TYPE,
4141  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_133_WIDTH },
4142  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_134_CHECKER_TYPE,
4143  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_134_WIDTH },
4144  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_135_CHECKER_TYPE,
4145  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_135_WIDTH },
4146  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_136_CHECKER_TYPE,
4147  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_136_WIDTH },
4148  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_137_CHECKER_TYPE,
4149  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_137_WIDTH },
4150  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_138_CHECKER_TYPE,
4151  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_138_WIDTH },
4152  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_139_CHECKER_TYPE,
4153  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_139_WIDTH },
4154  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_140_CHECKER_TYPE,
4155  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_140_WIDTH },
4156  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_141_CHECKER_TYPE,
4157  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_141_WIDTH },
4158  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_142_CHECKER_TYPE,
4159  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_142_WIDTH },
4160  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_143_CHECKER_TYPE,
4161  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_143_WIDTH },
4162  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_144_CHECKER_TYPE,
4163  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_144_WIDTH },
4164  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_145_CHECKER_TYPE,
4165  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_145_WIDTH },
4166  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_146_CHECKER_TYPE,
4167  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_146_WIDTH },
4168  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_147_CHECKER_TYPE,
4169  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_147_WIDTH },
4170  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_148_CHECKER_TYPE,
4171  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_148_WIDTH },
4172  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_149_CHECKER_TYPE,
4173  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_149_WIDTH },
4174  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_150_CHECKER_TYPE,
4175  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_150_WIDTH },
4176  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_151_CHECKER_TYPE,
4177  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_151_WIDTH },
4178  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_152_CHECKER_TYPE,
4179  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_152_WIDTH },
4180  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_153_CHECKER_TYPE,
4181  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_153_WIDTH },
4182  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_154_CHECKER_TYPE,
4183  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_154_WIDTH },
4184  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_155_CHECKER_TYPE,
4185  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_155_WIDTH },
4186  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_156_CHECKER_TYPE,
4187  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_156_WIDTH },
4188  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_157_CHECKER_TYPE,
4189  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_157_WIDTH },
4190  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_158_CHECKER_TYPE,
4191  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_158_WIDTH },
4192  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_159_CHECKER_TYPE,
4193  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_159_WIDTH },
4194  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_160_CHECKER_TYPE,
4195  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_160_WIDTH },
4196  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_161_CHECKER_TYPE,
4197  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_161_WIDTH },
4198  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_162_CHECKER_TYPE,
4199  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_162_WIDTH },
4200  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_163_CHECKER_TYPE,
4201  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_163_WIDTH },
4202  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_164_CHECKER_TYPE,
4203  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_164_WIDTH },
4204  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_165_CHECKER_TYPE,
4205  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_165_WIDTH },
4206  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_166_CHECKER_TYPE,
4207  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_166_WIDTH },
4208  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_167_CHECKER_TYPE,
4209  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_167_WIDTH },
4210  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_168_CHECKER_TYPE,
4211  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_168_WIDTH },
4212  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_169_CHECKER_TYPE,
4213  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_169_WIDTH },
4214  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_170_CHECKER_TYPE,
4215  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_170_WIDTH },
4216  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_171_CHECKER_TYPE,
4217  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_171_WIDTH },
4218  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_172_CHECKER_TYPE,
4219  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_172_WIDTH },
4220  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_173_CHECKER_TYPE,
4221  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_173_WIDTH },
4222  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_174_CHECKER_TYPE,
4223  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_174_WIDTH },
4224  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_175_CHECKER_TYPE,
4225  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_175_WIDTH },
4226 };
4227 
4233 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] =
4234 {
4235  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_0_CHECKER_TYPE,
4236  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
4237  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_1_CHECKER_TYPE,
4238  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
4239  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_2_CHECKER_TYPE,
4240  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
4241  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_3_CHECKER_TYPE,
4242  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
4243  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_4_CHECKER_TYPE,
4244  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
4245  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_5_CHECKER_TYPE,
4246  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
4247  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_6_CHECKER_TYPE,
4248  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
4249  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_7_CHECKER_TYPE,
4250  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
4251  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_8_CHECKER_TYPE,
4252  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
4253  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_9_CHECKER_TYPE,
4254  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
4255  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_10_CHECKER_TYPE,
4256  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
4257  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_11_CHECKER_TYPE,
4258  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
4259  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_12_CHECKER_TYPE,
4260  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
4261  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_13_CHECKER_TYPE,
4262  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
4263  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_14_CHECKER_TYPE,
4264  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
4265  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_15_CHECKER_TYPE,
4266  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
4267  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_16_CHECKER_TYPE,
4268  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
4269  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_17_CHECKER_TYPE,
4270  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
4271  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_18_CHECKER_TYPE,
4272  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
4273  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_19_CHECKER_TYPE,
4274  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
4275  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_20_CHECKER_TYPE,
4276  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
4277  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_21_CHECKER_TYPE,
4278  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
4279  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_22_CHECKER_TYPE,
4280  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
4281  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_23_CHECKER_TYPE,
4282  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
4283  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_24_CHECKER_TYPE,
4284  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
4285  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_25_CHECKER_TYPE,
4286  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
4287  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_26_CHECKER_TYPE,
4288  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
4289  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_27_CHECKER_TYPE,
4290  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
4291  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_28_CHECKER_TYPE,
4292  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
4293  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_29_CHECKER_TYPE,
4294  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
4295  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_30_CHECKER_TYPE,
4296  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
4297  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_31_CHECKER_TYPE,
4298  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
4299  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_32_CHECKER_TYPE,
4300  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
4301  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_33_CHECKER_TYPE,
4302  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
4303  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_34_CHECKER_TYPE,
4304  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
4305  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_35_CHECKER_TYPE,
4306  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
4307  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_36_CHECKER_TYPE,
4308  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
4309  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_37_CHECKER_TYPE,
4310  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
4311  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_38_CHECKER_TYPE,
4312  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
4313  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_39_CHECKER_TYPE,
4314  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
4315  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_40_CHECKER_TYPE,
4316  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
4317  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_41_CHECKER_TYPE,
4318  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
4319  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_42_CHECKER_TYPE,
4320  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
4321  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_43_CHECKER_TYPE,
4322  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
4323  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_44_CHECKER_TYPE,
4324  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
4325  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_45_CHECKER_TYPE,
4326  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
4327  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_46_CHECKER_TYPE,
4328  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
4329  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_47_CHECKER_TYPE,
4330  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
4331  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_48_CHECKER_TYPE,
4332  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
4333  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_49_CHECKER_TYPE,
4334  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
4335  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_50_CHECKER_TYPE,
4336  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
4337  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_51_CHECKER_TYPE,
4338  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
4339  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_52_CHECKER_TYPE,
4340  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
4341  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_53_CHECKER_TYPE,
4342  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
4343  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_54_CHECKER_TYPE,
4344  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
4345  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_55_CHECKER_TYPE,
4346  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
4347  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_56_CHECKER_TYPE,
4348  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
4349  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_57_CHECKER_TYPE,
4350  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
4351  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_58_CHECKER_TYPE,
4352  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
4353  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_59_CHECKER_TYPE,
4354  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
4355  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_60_CHECKER_TYPE,
4356  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
4357  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_61_CHECKER_TYPE,
4358  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
4359  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_62_CHECKER_TYPE,
4360  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
4361  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_63_CHECKER_TYPE,
4362  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
4363  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_64_CHECKER_TYPE,
4364  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
4365  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_65_CHECKER_TYPE,
4366  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
4367  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_66_CHECKER_TYPE,
4368  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
4369  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_67_CHECKER_TYPE,
4370  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
4371  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_68_CHECKER_TYPE,
4372  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
4373  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_69_CHECKER_TYPE,
4374  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
4375  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_70_CHECKER_TYPE,
4376  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
4377  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_71_CHECKER_TYPE,
4378  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
4379  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_72_CHECKER_TYPE,
4380  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
4381  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_73_CHECKER_TYPE,
4382  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
4383  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_74_CHECKER_TYPE,
4384  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
4385  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_75_CHECKER_TYPE,
4386  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
4387  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_76_CHECKER_TYPE,
4388  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
4389  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_77_CHECKER_TYPE,
4390  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
4391  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_78_CHECKER_TYPE,
4392  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
4393  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_79_CHECKER_TYPE,
4394  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
4395  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_80_CHECKER_TYPE,
4396  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
4397  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_81_CHECKER_TYPE,
4398  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
4399  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_82_CHECKER_TYPE,
4400  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
4401  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_83_CHECKER_TYPE,
4402  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
4403  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_84_CHECKER_TYPE,
4404  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
4405  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_85_CHECKER_TYPE,
4406  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
4407  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_86_CHECKER_TYPE,
4408  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
4409  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_87_CHECKER_TYPE,
4410  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
4411  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_88_CHECKER_TYPE,
4412  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
4413  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_89_CHECKER_TYPE,
4414  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
4415  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_90_CHECKER_TYPE,
4416  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
4417  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_91_CHECKER_TYPE,
4418  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
4419  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_92_CHECKER_TYPE,
4420  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
4421  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_93_CHECKER_TYPE,
4422  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
4423  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_94_CHECKER_TYPE,
4424  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
4425  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_95_CHECKER_TYPE,
4426  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
4427  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_96_CHECKER_TYPE,
4428  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
4429  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_97_CHECKER_TYPE,
4430  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
4431  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_98_CHECKER_TYPE,
4432  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
4433  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_99_CHECKER_TYPE,
4434  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
4435  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_100_CHECKER_TYPE,
4436  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
4437  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_101_CHECKER_TYPE,
4438  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
4439  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_102_CHECKER_TYPE,
4440  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
4441  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_103_CHECKER_TYPE,
4442  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
4443  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_104_CHECKER_TYPE,
4444  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
4445  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_105_CHECKER_TYPE,
4446  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
4447  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_106_CHECKER_TYPE,
4448  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
4449  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_107_CHECKER_TYPE,
4450  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
4451  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_108_CHECKER_TYPE,
4452  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
4453  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_109_CHECKER_TYPE,
4454  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
4455  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_110_CHECKER_TYPE,
4456  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
4457  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_111_CHECKER_TYPE,
4458  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
4459  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_112_CHECKER_TYPE,
4460  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
4461  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_113_CHECKER_TYPE,
4462  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
4463  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_114_CHECKER_TYPE,
4464  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
4465  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_115_CHECKER_TYPE,
4466  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
4467  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_116_CHECKER_TYPE,
4468  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
4469  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_117_CHECKER_TYPE,
4470  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
4471  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_118_CHECKER_TYPE,
4472  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
4473  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_119_CHECKER_TYPE,
4474  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
4475  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_120_CHECKER_TYPE,
4476  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
4477  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_121_CHECKER_TYPE,
4478  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
4479  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_122_CHECKER_TYPE,
4480  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
4481  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_123_CHECKER_TYPE,
4482  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
4483  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_124_CHECKER_TYPE,
4484  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
4485  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_125_CHECKER_TYPE,
4486  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
4487  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_126_CHECKER_TYPE,
4488  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
4489  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_127_CHECKER_TYPE,
4490  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
4491  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_128_CHECKER_TYPE,
4492  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
4493  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_129_CHECKER_TYPE,
4494  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
4495  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_130_CHECKER_TYPE,
4496  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
4497  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_131_CHECKER_TYPE,
4498  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
4499  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_132_CHECKER_TYPE,
4500  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
4501  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_133_CHECKER_TYPE,
4502  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
4503  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_134_CHECKER_TYPE,
4504  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
4505  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_135_CHECKER_TYPE,
4506  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
4507  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_136_CHECKER_TYPE,
4508  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
4509  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_137_CHECKER_TYPE,
4510  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
4511  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_138_CHECKER_TYPE,
4512  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
4513  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_139_CHECKER_TYPE,
4514  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
4515  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_140_CHECKER_TYPE,
4516  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
4517  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_141_CHECKER_TYPE,
4518  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
4519  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_142_CHECKER_TYPE,
4520  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
4521  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_143_CHECKER_TYPE,
4522  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
4523  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_144_CHECKER_TYPE,
4524  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
4525  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_145_CHECKER_TYPE,
4526  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
4527  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_146_CHECKER_TYPE,
4528  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
4529  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_147_CHECKER_TYPE,
4530  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
4531  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_148_CHECKER_TYPE,
4532  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
4533  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_149_CHECKER_TYPE,
4534  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
4535  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_150_CHECKER_TYPE,
4536  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
4537  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_151_CHECKER_TYPE,
4538  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
4539  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_152_CHECKER_TYPE,
4540  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
4541  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_153_CHECKER_TYPE,
4542  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
4543  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_154_CHECKER_TYPE,
4544  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
4545  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_155_CHECKER_TYPE,
4546  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
4547  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_156_CHECKER_TYPE,
4548  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
4549  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_157_CHECKER_TYPE,
4550  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
4551  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_158_CHECKER_TYPE,
4552  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
4553  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_159_CHECKER_TYPE,
4554  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
4555  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_160_CHECKER_TYPE,
4556  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
4557  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_161_CHECKER_TYPE,
4558  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
4559  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_162_CHECKER_TYPE,
4560  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
4561  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_163_CHECKER_TYPE,
4562  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
4563  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_164_CHECKER_TYPE,
4564  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
4565  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_165_CHECKER_TYPE,
4566  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
4567  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_166_CHECKER_TYPE,
4568  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
4569  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_167_CHECKER_TYPE,
4570  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
4571  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_168_CHECKER_TYPE,
4572  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
4573  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_169_CHECKER_TYPE,
4574  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
4575  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_170_CHECKER_TYPE,
4576  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
4577  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_171_CHECKER_TYPE,
4578  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
4579  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_172_CHECKER_TYPE,
4580  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
4581  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_173_CHECKER_TYPE,
4582  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
4583  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_174_CHECKER_TYPE,
4584  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
4585  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_175_CHECKER_TYPE,
4586  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
4587  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_176_CHECKER_TYPE,
4588  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
4589  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_177_CHECKER_TYPE,
4590  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
4591  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_178_CHECKER_TYPE,
4592  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
4593  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_179_CHECKER_TYPE,
4594  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
4595  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_180_CHECKER_TYPE,
4596  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
4597  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_181_CHECKER_TYPE,
4598  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
4599  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_182_CHECKER_TYPE,
4600  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
4601  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_183_CHECKER_TYPE,
4602  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
4603  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_184_CHECKER_TYPE,
4604  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
4605  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_185_CHECKER_TYPE,
4606  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
4607  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_186_CHECKER_TYPE,
4608  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
4609  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_187_CHECKER_TYPE,
4610  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
4611  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_188_CHECKER_TYPE,
4612  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
4613  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_189_CHECKER_TYPE,
4614  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
4615  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_190_CHECKER_TYPE,
4616  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
4617  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_191_CHECKER_TYPE,
4618  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
4619  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_192_CHECKER_TYPE,
4620  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
4621  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_193_CHECKER_TYPE,
4622  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
4623  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_194_CHECKER_TYPE,
4624  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
4625  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_195_CHECKER_TYPE,
4626  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
4627  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_196_CHECKER_TYPE,
4628  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
4629  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_197_CHECKER_TYPE,
4630  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
4631  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_198_CHECKER_TYPE,
4632  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
4633  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_199_CHECKER_TYPE,
4634  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
4635  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_200_CHECKER_TYPE,
4636  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
4637  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_201_CHECKER_TYPE,
4638  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
4639  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_202_CHECKER_TYPE,
4640  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
4641  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_203_CHECKER_TYPE,
4642  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
4643  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_204_CHECKER_TYPE,
4644  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
4645  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_205_CHECKER_TYPE,
4646  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
4647  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_206_CHECKER_TYPE,
4648  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
4649  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_207_CHECKER_TYPE,
4650  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
4651  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_208_CHECKER_TYPE,
4652  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
4653  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_209_CHECKER_TYPE,
4654  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
4655  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_210_CHECKER_TYPE,
4656  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
4657  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_211_CHECKER_TYPE,
4658  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
4659  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_212_CHECKER_TYPE,
4660  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
4661  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_213_CHECKER_TYPE,
4662  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
4663  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_214_CHECKER_TYPE,
4664  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
4665  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_215_CHECKER_TYPE,
4666  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
4667  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_216_CHECKER_TYPE,
4668  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
4669  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_217_CHECKER_TYPE,
4670  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
4671  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_218_CHECKER_TYPE,
4672  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
4673  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_219_CHECKER_TYPE,
4674  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
4675  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_220_CHECKER_TYPE,
4676  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
4677  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_221_CHECKER_TYPE,
4678  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
4679  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_222_CHECKER_TYPE,
4680  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
4681  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_223_CHECKER_TYPE,
4682  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
4683  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_224_CHECKER_TYPE,
4684  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
4685  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_225_CHECKER_TYPE,
4686  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
4687  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_226_CHECKER_TYPE,
4688  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
4689  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_227_CHECKER_TYPE,
4690  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
4691  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_228_CHECKER_TYPE,
4692  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
4693  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_229_CHECKER_TYPE,
4694  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
4695  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_230_CHECKER_TYPE,
4696  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
4697  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_231_CHECKER_TYPE,
4698  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
4699  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_232_CHECKER_TYPE,
4700  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
4701  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_233_CHECKER_TYPE,
4702  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
4703  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_234_CHECKER_TYPE,
4704  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
4705  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_235_CHECKER_TYPE,
4706  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
4707  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_236_CHECKER_TYPE,
4708  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
4709  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_237_CHECKER_TYPE,
4710  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
4711  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_238_CHECKER_TYPE,
4712  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
4713  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_239_CHECKER_TYPE,
4714  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
4715  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_240_CHECKER_TYPE,
4716  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
4717  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_241_CHECKER_TYPE,
4718  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
4719  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_242_CHECKER_TYPE,
4720  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
4721  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_243_CHECKER_TYPE,
4722  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
4723  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_244_CHECKER_TYPE,
4724  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
4725  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_245_CHECKER_TYPE,
4726  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
4727  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_246_CHECKER_TYPE,
4728  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
4729  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_247_CHECKER_TYPE,
4730  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
4731  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_248_CHECKER_TYPE,
4732  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
4733  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_249_CHECKER_TYPE,
4734  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
4735  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_250_CHECKER_TYPE,
4736  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
4737  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_251_CHECKER_TYPE,
4738  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
4739  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_252_CHECKER_TYPE,
4740  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
4741  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_253_CHECKER_TYPE,
4742  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
4743  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_254_CHECKER_TYPE,
4744  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
4745  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_255_CHECKER_TYPE,
4746  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
4747 };
4748 
4754 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] =
4755 {
4756  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_0_CHECKER_TYPE,
4757  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
4758  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_1_CHECKER_TYPE,
4759  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
4760  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_2_CHECKER_TYPE,
4761  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
4762  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_3_CHECKER_TYPE,
4763  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
4764  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_4_CHECKER_TYPE,
4765  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
4766  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_5_CHECKER_TYPE,
4767  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
4768  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_6_CHECKER_TYPE,
4769  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
4770  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_7_CHECKER_TYPE,
4771  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
4772  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_8_CHECKER_TYPE,
4773  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
4774  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_9_CHECKER_TYPE,
4775  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
4776  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_10_CHECKER_TYPE,
4777  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
4778  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_11_CHECKER_TYPE,
4779  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
4780  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_12_CHECKER_TYPE,
4781  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
4782  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_13_CHECKER_TYPE,
4783  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
4784  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_14_CHECKER_TYPE,
4785  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
4786  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_15_CHECKER_TYPE,
4787  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
4788  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_16_CHECKER_TYPE,
4789  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
4790  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_17_CHECKER_TYPE,
4791  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
4792  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_18_CHECKER_TYPE,
4793  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
4794  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_19_CHECKER_TYPE,
4795  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
4796  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_20_CHECKER_TYPE,
4797  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
4798  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_21_CHECKER_TYPE,
4799  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
4800  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_22_CHECKER_TYPE,
4801  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
4802  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_23_CHECKER_TYPE,
4803  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
4804  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_24_CHECKER_TYPE,
4805  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH },
4806  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_25_CHECKER_TYPE,
4807  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH },
4808  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_26_CHECKER_TYPE,
4809  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH },
4810  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_27_CHECKER_TYPE,
4811  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH },
4812  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_28_CHECKER_TYPE,
4813  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH },
4814  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_29_CHECKER_TYPE,
4815  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH },
4816  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_30_CHECKER_TYPE,
4817  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH },
4818  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_31_CHECKER_TYPE,
4819  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH },
4820  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_32_CHECKER_TYPE,
4821  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH },
4822  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_33_CHECKER_TYPE,
4823  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH },
4824  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_34_CHECKER_TYPE,
4825  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH },
4826  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_35_CHECKER_TYPE,
4827  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH },
4828  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_36_CHECKER_TYPE,
4829  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH },
4830  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_37_CHECKER_TYPE,
4831  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH },
4832  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_38_CHECKER_TYPE,
4833  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH },
4834  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_39_CHECKER_TYPE,
4835  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH },
4836  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_40_CHECKER_TYPE,
4837  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH },
4838  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_41_CHECKER_TYPE,
4839  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH },
4840  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_42_CHECKER_TYPE,
4841  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH },
4842  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_43_CHECKER_TYPE,
4843  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_43_WIDTH },
4844  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_44_CHECKER_TYPE,
4845  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_44_WIDTH },
4846  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_45_CHECKER_TYPE,
4847  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_45_WIDTH },
4848  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_46_CHECKER_TYPE,
4849  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_46_WIDTH },
4850  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_47_CHECKER_TYPE,
4851  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_47_WIDTH },
4852  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_48_CHECKER_TYPE,
4853  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_48_WIDTH },
4854  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_49_CHECKER_TYPE,
4855  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_49_WIDTH },
4856  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_50_CHECKER_TYPE,
4857  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_50_WIDTH },
4858  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_51_CHECKER_TYPE,
4859  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_51_WIDTH },
4860  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_52_CHECKER_TYPE,
4861  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_52_WIDTH },
4862  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_53_CHECKER_TYPE,
4863  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_53_WIDTH },
4864  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_54_CHECKER_TYPE,
4865  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_54_WIDTH },
4866  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_55_CHECKER_TYPE,
4867  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_55_WIDTH },
4868  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_56_CHECKER_TYPE,
4869  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_56_WIDTH },
4870  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_57_CHECKER_TYPE,
4871  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_57_WIDTH },
4872  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_58_CHECKER_TYPE,
4873  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_58_WIDTH },
4874  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_59_CHECKER_TYPE,
4875  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_59_WIDTH },
4876  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_60_CHECKER_TYPE,
4877  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_60_WIDTH },
4878  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_61_CHECKER_TYPE,
4879  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_61_WIDTH },
4880  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_62_CHECKER_TYPE,
4881  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_62_WIDTH },
4882  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_63_CHECKER_TYPE,
4883  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_63_WIDTH },
4884  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_64_CHECKER_TYPE,
4885  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_64_WIDTH },
4886  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_65_CHECKER_TYPE,
4887  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_65_WIDTH },
4888  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_66_CHECKER_TYPE,
4889  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_66_WIDTH },
4890  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_67_CHECKER_TYPE,
4891  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_67_WIDTH },
4892  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_68_CHECKER_TYPE,
4893  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_68_WIDTH },
4894  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_69_CHECKER_TYPE,
4895  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_69_WIDTH },
4896  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_70_CHECKER_TYPE,
4897  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_70_WIDTH },
4898  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_71_CHECKER_TYPE,
4899  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_71_WIDTH },
4900  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_72_CHECKER_TYPE,
4901  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_72_WIDTH },
4902  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_73_CHECKER_TYPE,
4903  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_73_WIDTH },
4904  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_74_CHECKER_TYPE,
4905  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_74_WIDTH },
4906  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_75_CHECKER_TYPE,
4907  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_75_WIDTH },
4908  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_76_CHECKER_TYPE,
4909  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_76_WIDTH },
4910  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_77_CHECKER_TYPE,
4911  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_77_WIDTH },
4912  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_78_CHECKER_TYPE,
4913  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_78_WIDTH },
4914  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_79_CHECKER_TYPE,
4915  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_79_WIDTH },
4916  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_80_CHECKER_TYPE,
4917  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_80_WIDTH },
4918  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_81_CHECKER_TYPE,
4919  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_81_WIDTH },
4920  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_82_CHECKER_TYPE,
4921  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_82_WIDTH },
4922  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_83_CHECKER_TYPE,
4923  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_83_WIDTH },
4924  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_84_CHECKER_TYPE,
4925  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_84_WIDTH },
4926  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_85_CHECKER_TYPE,
4927  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_85_WIDTH },
4928  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_86_CHECKER_TYPE,
4929  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_86_WIDTH },
4930  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_87_CHECKER_TYPE,
4931  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_87_WIDTH },
4932  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_88_CHECKER_TYPE,
4933  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_88_WIDTH },
4934  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_89_CHECKER_TYPE,
4935  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_89_WIDTH },
4936  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_90_CHECKER_TYPE,
4937  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_90_WIDTH },
4938  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_91_CHECKER_TYPE,
4939  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_91_WIDTH },
4940  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_92_CHECKER_TYPE,
4941  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_92_WIDTH },
4942  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_93_CHECKER_TYPE,
4943  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_93_WIDTH },
4944  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_94_CHECKER_TYPE,
4945  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_94_WIDTH },
4946  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_95_CHECKER_TYPE,
4947  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_95_WIDTH },
4948  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_96_CHECKER_TYPE,
4949  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_96_WIDTH },
4950  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_97_CHECKER_TYPE,
4951  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_97_WIDTH },
4952  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_98_CHECKER_TYPE,
4953  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_98_WIDTH },
4954  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_99_CHECKER_TYPE,
4955  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_99_WIDTH },
4956  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_100_CHECKER_TYPE,
4957  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_100_WIDTH },
4958  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_101_CHECKER_TYPE,
4959  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_101_WIDTH },
4960  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_102_CHECKER_TYPE,
4961  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_102_WIDTH },
4962  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_103_CHECKER_TYPE,
4963  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_103_WIDTH },
4964  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_104_CHECKER_TYPE,
4965  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_104_WIDTH },
4966  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_105_CHECKER_TYPE,
4967  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_105_WIDTH },
4968  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_106_CHECKER_TYPE,
4969  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_106_WIDTH },
4970  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_107_CHECKER_TYPE,
4971  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_107_WIDTH },
4972  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_108_CHECKER_TYPE,
4973  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_108_WIDTH },
4974  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_109_CHECKER_TYPE,
4975  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_109_WIDTH },
4976  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_110_CHECKER_TYPE,
4977  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_110_WIDTH },
4978  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_111_CHECKER_TYPE,
4979  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_111_WIDTH },
4980  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_112_CHECKER_TYPE,
4981  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_112_WIDTH },
4982  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_113_CHECKER_TYPE,
4983  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_113_WIDTH },
4984  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_114_CHECKER_TYPE,
4985  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_114_WIDTH },
4986  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_115_CHECKER_TYPE,
4987  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_115_WIDTH },
4988  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_116_CHECKER_TYPE,
4989  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_116_WIDTH },
4990  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_117_CHECKER_TYPE,
4991  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_117_WIDTH },
4992  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_118_CHECKER_TYPE,
4993  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_118_WIDTH },
4994  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_119_CHECKER_TYPE,
4995  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_119_WIDTH },
4996  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_120_CHECKER_TYPE,
4997  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_120_WIDTH },
4998  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_121_CHECKER_TYPE,
4999  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_121_WIDTH },
5000  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_122_CHECKER_TYPE,
5001  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_122_WIDTH },
5002  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_123_CHECKER_TYPE,
5003  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_123_WIDTH },
5004  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_124_CHECKER_TYPE,
5005  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_124_WIDTH },
5006  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_125_CHECKER_TYPE,
5007  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_125_WIDTH },
5008  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_126_CHECKER_TYPE,
5009  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_126_WIDTH },
5010  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_127_CHECKER_TYPE,
5011  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_127_WIDTH },
5012  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_128_CHECKER_TYPE,
5013  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_128_WIDTH },
5014  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_129_CHECKER_TYPE,
5015  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_129_WIDTH },
5016  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_130_CHECKER_TYPE,
5017  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_130_WIDTH },
5018  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_131_CHECKER_TYPE,
5019  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_131_WIDTH },
5020  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_132_CHECKER_TYPE,
5021  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_132_WIDTH },
5022  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_133_CHECKER_TYPE,
5023  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_GROUP_133_WIDTH },
5024 };
5025 
5031 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] =
5032 {
5033  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_0_CHECKER_TYPE,
5034  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
5035  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_1_CHECKER_TYPE,
5036  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
5037  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_2_CHECKER_TYPE,
5038  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
5039  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_3_CHECKER_TYPE,
5040  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
5041  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_4_CHECKER_TYPE,
5042  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
5043  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_5_CHECKER_TYPE,
5044  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
5045  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_6_CHECKER_TYPE,
5046  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
5047  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_7_CHECKER_TYPE,
5048  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
5049  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_8_CHECKER_TYPE,
5050  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
5051  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_9_CHECKER_TYPE,
5052  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
5053  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_10_CHECKER_TYPE,
5054  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
5055  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_11_CHECKER_TYPE,
5056  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
5057  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_12_CHECKER_TYPE,
5058  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
5059  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_13_CHECKER_TYPE,
5060  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
5061  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_14_CHECKER_TYPE,
5062  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
5063  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_15_CHECKER_TYPE,
5064  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
5065  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_16_CHECKER_TYPE,
5066  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
5067  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_17_CHECKER_TYPE,
5068  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
5069  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_18_CHECKER_TYPE,
5070  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
5071  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_19_CHECKER_TYPE,
5072  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
5073  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_20_CHECKER_TYPE,
5074  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
5075  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_21_CHECKER_TYPE,
5076  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
5077  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_22_CHECKER_TYPE,
5078  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
5079  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_23_CHECKER_TYPE,
5080  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
5081  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_24_CHECKER_TYPE,
5082  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
5083  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_25_CHECKER_TYPE,
5084  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
5085  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_26_CHECKER_TYPE,
5086  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
5087  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_27_CHECKER_TYPE,
5088  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
5089  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_28_CHECKER_TYPE,
5090  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
5091  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_29_CHECKER_TYPE,
5092  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
5093  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_30_CHECKER_TYPE,
5094  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
5095  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_31_CHECKER_TYPE,
5096  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
5097  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_32_CHECKER_TYPE,
5098  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
5099  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_33_CHECKER_TYPE,
5100  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
5101  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_34_CHECKER_TYPE,
5102  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
5103  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_35_CHECKER_TYPE,
5104  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
5105  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_36_CHECKER_TYPE,
5106  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
5107  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_37_CHECKER_TYPE,
5108  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
5109  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_38_CHECKER_TYPE,
5110  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
5111  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_39_CHECKER_TYPE,
5112  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
5113  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_40_CHECKER_TYPE,
5114  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
5115  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_41_CHECKER_TYPE,
5116  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
5117  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_42_CHECKER_TYPE,
5118  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
5119  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_43_CHECKER_TYPE,
5120  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
5121  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_44_CHECKER_TYPE,
5122  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
5123  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_45_CHECKER_TYPE,
5124  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
5125  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_46_CHECKER_TYPE,
5126  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
5127  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_47_CHECKER_TYPE,
5128  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
5129  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_48_CHECKER_TYPE,
5130  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
5131  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_49_CHECKER_TYPE,
5132  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
5133  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_50_CHECKER_TYPE,
5134  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
5135  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_51_CHECKER_TYPE,
5136  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
5137  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_52_CHECKER_TYPE,
5138  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
5139  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_53_CHECKER_TYPE,
5140  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
5141  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_54_CHECKER_TYPE,
5142  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
5143  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_55_CHECKER_TYPE,
5144  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
5145  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_56_CHECKER_TYPE,
5146  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
5147  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_57_CHECKER_TYPE,
5148  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
5149  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_58_CHECKER_TYPE,
5150  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
5151  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_59_CHECKER_TYPE,
5152  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
5153  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_60_CHECKER_TYPE,
5154  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
5155  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_61_CHECKER_TYPE,
5156  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
5157  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_62_CHECKER_TYPE,
5158  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
5159  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_63_CHECKER_TYPE,
5160  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
5161  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_64_CHECKER_TYPE,
5162  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
5163  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_65_CHECKER_TYPE,
5164  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
5165  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_66_CHECKER_TYPE,
5166  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
5167  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_67_CHECKER_TYPE,
5168  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
5169  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_68_CHECKER_TYPE,
5170  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
5171  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_69_CHECKER_TYPE,
5172  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
5173  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_70_CHECKER_TYPE,
5174  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
5175  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_71_CHECKER_TYPE,
5176  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
5177  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_72_CHECKER_TYPE,
5178  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
5179  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_73_CHECKER_TYPE,
5180  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
5181  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_74_CHECKER_TYPE,
5182  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
5183  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_75_CHECKER_TYPE,
5184  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
5185  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_76_CHECKER_TYPE,
5186  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
5187  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_77_CHECKER_TYPE,
5188  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
5189  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_78_CHECKER_TYPE,
5190  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
5191  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_79_CHECKER_TYPE,
5192  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
5193  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_80_CHECKER_TYPE,
5194  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
5195  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_81_CHECKER_TYPE,
5196  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
5197  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_82_CHECKER_TYPE,
5198  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
5199  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_83_CHECKER_TYPE,
5200  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
5201  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_84_CHECKER_TYPE,
5202  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
5203  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_85_CHECKER_TYPE,
5204  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
5205  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_86_CHECKER_TYPE,
5206  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
5207  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_87_CHECKER_TYPE,
5208  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
5209  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_88_CHECKER_TYPE,
5210  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
5211  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_89_CHECKER_TYPE,
5212  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
5213  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_90_CHECKER_TYPE,
5214  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
5215  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_91_CHECKER_TYPE,
5216  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
5217  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_92_CHECKER_TYPE,
5218  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
5219  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_93_CHECKER_TYPE,
5220  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
5221  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_94_CHECKER_TYPE,
5222  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
5223  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_95_CHECKER_TYPE,
5224  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
5225  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_96_CHECKER_TYPE,
5226  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
5227  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_97_CHECKER_TYPE,
5228  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
5229  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_98_CHECKER_TYPE,
5230  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
5231  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_99_CHECKER_TYPE,
5232  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
5233  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_100_CHECKER_TYPE,
5234  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
5235  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_101_CHECKER_TYPE,
5236  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
5237  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_102_CHECKER_TYPE,
5238  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
5239  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_103_CHECKER_TYPE,
5240  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
5241  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_104_CHECKER_TYPE,
5242  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
5243  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_105_CHECKER_TYPE,
5244  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
5245  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_106_CHECKER_TYPE,
5246  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
5247  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_107_CHECKER_TYPE,
5248  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
5249  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_108_CHECKER_TYPE,
5250  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
5251  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_109_CHECKER_TYPE,
5252  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
5253  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_110_CHECKER_TYPE,
5254  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
5255  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_111_CHECKER_TYPE,
5256  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
5257  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_112_CHECKER_TYPE,
5258  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
5259  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_113_CHECKER_TYPE,
5260  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
5261  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_114_CHECKER_TYPE,
5262  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
5263  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_115_CHECKER_TYPE,
5264  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
5265  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_116_CHECKER_TYPE,
5266  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
5267  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_117_CHECKER_TYPE,
5268  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
5269  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_118_CHECKER_TYPE,
5270  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
5271  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_119_CHECKER_TYPE,
5272  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
5273  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_120_CHECKER_TYPE,
5274  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
5275  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_121_CHECKER_TYPE,
5276  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
5277  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_122_CHECKER_TYPE,
5278  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
5279  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_123_CHECKER_TYPE,
5280  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
5281  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_124_CHECKER_TYPE,
5282  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
5283  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_125_CHECKER_TYPE,
5284  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
5285  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_126_CHECKER_TYPE,
5286  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
5287  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_127_CHECKER_TYPE,
5288  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
5289  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_128_CHECKER_TYPE,
5290  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
5291  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_129_CHECKER_TYPE,
5292  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
5293  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_130_CHECKER_TYPE,
5294  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
5295  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_131_CHECKER_TYPE,
5296  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
5297  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_132_CHECKER_TYPE,
5298  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
5299  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_133_CHECKER_TYPE,
5300  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
5301  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_134_CHECKER_TYPE,
5302  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
5303  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_135_CHECKER_TYPE,
5304  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
5305  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_136_CHECKER_TYPE,
5306  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
5307  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_137_CHECKER_TYPE,
5308  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
5309  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_138_CHECKER_TYPE,
5310  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
5311  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_139_CHECKER_TYPE,
5312  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
5313  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_140_CHECKER_TYPE,
5314  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
5315  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_141_CHECKER_TYPE,
5316  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
5317  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_142_CHECKER_TYPE,
5318  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
5319  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_143_CHECKER_TYPE,
5320  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
5321  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_144_CHECKER_TYPE,
5322  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
5323  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_145_CHECKER_TYPE,
5324  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
5325  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_146_CHECKER_TYPE,
5326  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
5327  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_147_CHECKER_TYPE,
5328  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
5329  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_148_CHECKER_TYPE,
5330  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
5331  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_149_CHECKER_TYPE,
5332  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
5333  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_150_CHECKER_TYPE,
5334  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
5335  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_151_CHECKER_TYPE,
5336  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
5337  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_152_CHECKER_TYPE,
5338  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
5339  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_153_CHECKER_TYPE,
5340  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
5341  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_154_CHECKER_TYPE,
5342  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
5343  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_155_CHECKER_TYPE,
5344  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
5345  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_156_CHECKER_TYPE,
5346  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
5347  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_157_CHECKER_TYPE,
5348  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
5349  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_158_CHECKER_TYPE,
5350  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
5351  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_159_CHECKER_TYPE,
5352  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
5353  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_160_CHECKER_TYPE,
5354  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
5355  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_161_CHECKER_TYPE,
5356  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
5357  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_162_CHECKER_TYPE,
5358  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
5359  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_163_CHECKER_TYPE,
5360  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
5361  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_164_CHECKER_TYPE,
5362  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
5363  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_165_CHECKER_TYPE,
5364  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
5365  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_166_CHECKER_TYPE,
5366  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
5367  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_167_CHECKER_TYPE,
5368  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
5369  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_168_CHECKER_TYPE,
5370  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
5371  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_169_CHECKER_TYPE,
5372  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
5373  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_170_CHECKER_TYPE,
5374  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
5375  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_171_CHECKER_TYPE,
5376  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
5377  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_172_CHECKER_TYPE,
5378  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
5379  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_173_CHECKER_TYPE,
5380  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
5381  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_174_CHECKER_TYPE,
5382  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
5383  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_175_CHECKER_TYPE,
5384  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
5385  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_176_CHECKER_TYPE,
5386  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
5387  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_177_CHECKER_TYPE,
5388  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
5389  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_178_CHECKER_TYPE,
5390  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
5391  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_179_CHECKER_TYPE,
5392  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
5393  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_180_CHECKER_TYPE,
5394  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
5395  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_181_CHECKER_TYPE,
5396  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
5397  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_182_CHECKER_TYPE,
5398  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
5399  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_183_CHECKER_TYPE,
5400  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
5401  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_184_CHECKER_TYPE,
5402  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
5403  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_185_CHECKER_TYPE,
5404  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
5405  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_186_CHECKER_TYPE,
5406  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
5407  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_187_CHECKER_TYPE,
5408  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
5409  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_188_CHECKER_TYPE,
5410  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
5411  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_189_CHECKER_TYPE,
5412  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
5413  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_190_CHECKER_TYPE,
5414  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
5415  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_191_CHECKER_TYPE,
5416  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
5417  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_192_CHECKER_TYPE,
5418  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
5419  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_193_CHECKER_TYPE,
5420  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
5421  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_194_CHECKER_TYPE,
5422  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
5423  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_195_CHECKER_TYPE,
5424  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
5425  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_196_CHECKER_TYPE,
5426  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
5427  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_197_CHECKER_TYPE,
5428  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
5429  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_198_CHECKER_TYPE,
5430  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
5431  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_199_CHECKER_TYPE,
5432  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
5433  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_200_CHECKER_TYPE,
5434  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
5435  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_201_CHECKER_TYPE,
5436  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
5437  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_202_CHECKER_TYPE,
5438  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
5439  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_203_CHECKER_TYPE,
5440  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
5441  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_204_CHECKER_TYPE,
5442  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
5443  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_205_CHECKER_TYPE,
5444  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
5445  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_206_CHECKER_TYPE,
5446  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
5447  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_207_CHECKER_TYPE,
5448  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
5449  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_208_CHECKER_TYPE,
5450  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
5451  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_209_CHECKER_TYPE,
5452  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
5453  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_210_CHECKER_TYPE,
5454  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
5455  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_211_CHECKER_TYPE,
5456  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
5457  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_212_CHECKER_TYPE,
5458  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
5459  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_213_CHECKER_TYPE,
5460  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
5461  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_214_CHECKER_TYPE,
5462  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
5463  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_215_CHECKER_TYPE,
5464  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
5465  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_216_CHECKER_TYPE,
5466  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
5467  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_217_CHECKER_TYPE,
5468  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
5469  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_218_CHECKER_TYPE,
5470  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
5471  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_219_CHECKER_TYPE,
5472  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
5473  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_220_CHECKER_TYPE,
5474  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
5475  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_221_CHECKER_TYPE,
5476  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
5477  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_222_CHECKER_TYPE,
5478  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
5479  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_223_CHECKER_TYPE,
5480  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
5481  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_224_CHECKER_TYPE,
5482  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
5483  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_225_CHECKER_TYPE,
5484  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
5485  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_226_CHECKER_TYPE,
5486  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
5487  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_227_CHECKER_TYPE,
5488  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
5489  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_228_CHECKER_TYPE,
5490  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
5491  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_229_CHECKER_TYPE,
5492  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
5493  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_230_CHECKER_TYPE,
5494  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
5495  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_231_CHECKER_TYPE,
5496  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
5497  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_232_CHECKER_TYPE,
5498  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
5499  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_233_CHECKER_TYPE,
5500  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
5501  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_234_CHECKER_TYPE,
5502  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
5503  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_235_CHECKER_TYPE,
5504  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
5505  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_236_CHECKER_TYPE,
5506  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
5507  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_237_CHECKER_TYPE,
5508  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
5509  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_238_CHECKER_TYPE,
5510  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
5511  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_239_CHECKER_TYPE,
5512  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
5513  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_240_CHECKER_TYPE,
5514  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
5515  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_241_CHECKER_TYPE,
5516  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
5517  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_242_CHECKER_TYPE,
5518  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
5519  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_243_CHECKER_TYPE,
5520  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
5521  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_244_CHECKER_TYPE,
5522  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
5523  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_245_CHECKER_TYPE,
5524  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
5525  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_246_CHECKER_TYPE,
5526  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
5527  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_247_CHECKER_TYPE,
5528  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
5529  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_248_CHECKER_TYPE,
5530  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
5531  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_249_CHECKER_TYPE,
5532  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
5533  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_250_CHECKER_TYPE,
5534  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
5535  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_251_CHECKER_TYPE,
5536  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
5537  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_252_CHECKER_TYPE,
5538  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
5539  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_253_CHECKER_TYPE,
5540  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
5541  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_254_CHECKER_TYPE,
5542  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
5543  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_255_CHECKER_TYPE,
5544  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
5545 };
5546 
5552 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] =
5553 {
5554  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_0_CHECKER_TYPE,
5555  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
5556  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_1_CHECKER_TYPE,
5557  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
5558  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_2_CHECKER_TYPE,
5559  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
5560  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_3_CHECKER_TYPE,
5561  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
5562  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_4_CHECKER_TYPE,
5563  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
5564  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_5_CHECKER_TYPE,
5565  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
5566  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_6_CHECKER_TYPE,
5567  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
5568  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_7_CHECKER_TYPE,
5569  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
5570  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_8_CHECKER_TYPE,
5571  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
5572  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_9_CHECKER_TYPE,
5573  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
5574  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_10_CHECKER_TYPE,
5575  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
5576  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_11_CHECKER_TYPE,
5577  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
5578  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_12_CHECKER_TYPE,
5579  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
5580  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_13_CHECKER_TYPE,
5581  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
5582  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_14_CHECKER_TYPE,
5583  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
5584  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_15_CHECKER_TYPE,
5585  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
5586  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_16_CHECKER_TYPE,
5587  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
5588  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_17_CHECKER_TYPE,
5589  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
5590  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_18_CHECKER_TYPE,
5591  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
5592  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_19_CHECKER_TYPE,
5593  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
5594  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_20_CHECKER_TYPE,
5595  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
5596  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_21_CHECKER_TYPE,
5597  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
5598  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_22_CHECKER_TYPE,
5599  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
5600  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_23_CHECKER_TYPE,
5601  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
5602  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_24_CHECKER_TYPE,
5603  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH },
5604  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_25_CHECKER_TYPE,
5605  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH },
5606  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_26_CHECKER_TYPE,
5607  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH },
5608  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_27_CHECKER_TYPE,
5609  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH },
5610  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_28_CHECKER_TYPE,
5611  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH },
5612  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_29_CHECKER_TYPE,
5613  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH },
5614  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_30_CHECKER_TYPE,
5615  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH },
5616  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_31_CHECKER_TYPE,
5617  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH },
5618  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_32_CHECKER_TYPE,
5619  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH },
5620  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_33_CHECKER_TYPE,
5621  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH },
5622  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_34_CHECKER_TYPE,
5623  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH },
5624  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_35_CHECKER_TYPE,
5625  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH },
5626  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_36_CHECKER_TYPE,
5627  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH },
5628  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_37_CHECKER_TYPE,
5629  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH },
5630  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_38_CHECKER_TYPE,
5631  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH },
5632  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_39_CHECKER_TYPE,
5633  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH },
5634  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_40_CHECKER_TYPE,
5635  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH },
5636  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_41_CHECKER_TYPE,
5637  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH },
5638  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_42_CHECKER_TYPE,
5639  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH },
5640  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_43_CHECKER_TYPE,
5641  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_43_WIDTH },
5642  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_44_CHECKER_TYPE,
5643  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_44_WIDTH },
5644  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_45_CHECKER_TYPE,
5645  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_45_WIDTH },
5646  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_46_CHECKER_TYPE,
5647  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_46_WIDTH },
5648  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_47_CHECKER_TYPE,
5649  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_47_WIDTH },
5650  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_48_CHECKER_TYPE,
5651  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_48_WIDTH },
5652  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_49_CHECKER_TYPE,
5653  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_49_WIDTH },
5654  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_50_CHECKER_TYPE,
5655  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_50_WIDTH },
5656  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_51_CHECKER_TYPE,
5657  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_51_WIDTH },
5658  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_52_CHECKER_TYPE,
5659  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_52_WIDTH },
5660  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_53_CHECKER_TYPE,
5661  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_53_WIDTH },
5662  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_54_CHECKER_TYPE,
5663  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_54_WIDTH },
5664  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_55_CHECKER_TYPE,
5665  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_55_WIDTH },
5666  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_56_CHECKER_TYPE,
5667  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_56_WIDTH },
5668  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_57_CHECKER_TYPE,
5669  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_57_WIDTH },
5670  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_58_CHECKER_TYPE,
5671  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_58_WIDTH },
5672  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_59_CHECKER_TYPE,
5673  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_59_WIDTH },
5674  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_60_CHECKER_TYPE,
5675  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_60_WIDTH },
5676  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_61_CHECKER_TYPE,
5677  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_61_WIDTH },
5678  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_62_CHECKER_TYPE,
5679  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_62_WIDTH },
5680  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_63_CHECKER_TYPE,
5681  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_63_WIDTH },
5682  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_64_CHECKER_TYPE,
5683  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_64_WIDTH },
5684  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_65_CHECKER_TYPE,
5685  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_65_WIDTH },
5686  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_66_CHECKER_TYPE,
5687  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_66_WIDTH },
5688  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_67_CHECKER_TYPE,
5689  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_67_WIDTH },
5690  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_68_CHECKER_TYPE,
5691  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_68_WIDTH },
5692  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_69_CHECKER_TYPE,
5693  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_69_WIDTH },
5694  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_70_CHECKER_TYPE,
5695  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_70_WIDTH },
5696  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_71_CHECKER_TYPE,
5697  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_71_WIDTH },
5698  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_72_CHECKER_TYPE,
5699  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_72_WIDTH },
5700  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_73_CHECKER_TYPE,
5701  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_73_WIDTH },
5702  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_74_CHECKER_TYPE,
5703  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_74_WIDTH },
5704  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_75_CHECKER_TYPE,
5705  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_75_WIDTH },
5706  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_76_CHECKER_TYPE,
5707  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_76_WIDTH },
5708  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_77_CHECKER_TYPE,
5709  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_77_WIDTH },
5710  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_78_CHECKER_TYPE,
5711  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_78_WIDTH },
5712  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_79_CHECKER_TYPE,
5713  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_79_WIDTH },
5714  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_80_CHECKER_TYPE,
5715  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_80_WIDTH },
5716  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_81_CHECKER_TYPE,
5717  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_81_WIDTH },
5718  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_82_CHECKER_TYPE,
5719  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_82_WIDTH },
5720  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_83_CHECKER_TYPE,
5721  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_83_WIDTH },
5722  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_84_CHECKER_TYPE,
5723  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_84_WIDTH },
5724  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_85_CHECKER_TYPE,
5725  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_85_WIDTH },
5726  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_86_CHECKER_TYPE,
5727  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_86_WIDTH },
5728  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_87_CHECKER_TYPE,
5729  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_87_WIDTH },
5730  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_88_CHECKER_TYPE,
5731  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_88_WIDTH },
5732  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_89_CHECKER_TYPE,
5733  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_89_WIDTH },
5734  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_90_CHECKER_TYPE,
5735  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_90_WIDTH },
5736  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_91_CHECKER_TYPE,
5737  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_91_WIDTH },
5738  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_92_CHECKER_TYPE,
5739  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_92_WIDTH },
5740  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_93_CHECKER_TYPE,
5741  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_93_WIDTH },
5742  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_94_CHECKER_TYPE,
5743  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_94_WIDTH },
5744  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_95_CHECKER_TYPE,
5745  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_95_WIDTH },
5746  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_96_CHECKER_TYPE,
5747  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_96_WIDTH },
5748  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_97_CHECKER_TYPE,
5749  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_97_WIDTH },
5750  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_98_CHECKER_TYPE,
5751  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_98_WIDTH },
5752  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_99_CHECKER_TYPE,
5753  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_99_WIDTH },
5754  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_100_CHECKER_TYPE,
5755  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_100_WIDTH },
5756  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_101_CHECKER_TYPE,
5757  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_101_WIDTH },
5758  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_102_CHECKER_TYPE,
5759  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_102_WIDTH },
5760  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_103_CHECKER_TYPE,
5761  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_103_WIDTH },
5762  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_104_CHECKER_TYPE,
5763  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_104_WIDTH },
5764  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_105_CHECKER_TYPE,
5765  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_105_WIDTH },
5766  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_106_CHECKER_TYPE,
5767  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_106_WIDTH },
5768  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_107_CHECKER_TYPE,
5769  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_107_WIDTH },
5770  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_108_CHECKER_TYPE,
5771  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_108_WIDTH },
5772  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_109_CHECKER_TYPE,
5773  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_109_WIDTH },
5774  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_110_CHECKER_TYPE,
5775  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_110_WIDTH },
5776  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_111_CHECKER_TYPE,
5777  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_111_WIDTH },
5778  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_112_CHECKER_TYPE,
5779  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_112_WIDTH },
5780  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_113_CHECKER_TYPE,
5781  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_113_WIDTH },
5782  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_114_CHECKER_TYPE,
5783  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_114_WIDTH },
5784  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_115_CHECKER_TYPE,
5785  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_115_WIDTH },
5786  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_116_CHECKER_TYPE,
5787  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_116_WIDTH },
5788  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_117_CHECKER_TYPE,
5789  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_117_WIDTH },
5790  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_118_CHECKER_TYPE,
5791  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_118_WIDTH },
5792  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_119_CHECKER_TYPE,
5793  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_119_WIDTH },
5794  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_120_CHECKER_TYPE,
5795  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_120_WIDTH },
5796  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_121_CHECKER_TYPE,
5797  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_121_WIDTH },
5798  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_122_CHECKER_TYPE,
5799  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_122_WIDTH },
5800  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_123_CHECKER_TYPE,
5801  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_123_WIDTH },
5802  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_124_CHECKER_TYPE,
5803  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_124_WIDTH },
5804  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_125_CHECKER_TYPE,
5805  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_125_WIDTH },
5806  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_126_CHECKER_TYPE,
5807  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_126_WIDTH },
5808  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_127_CHECKER_TYPE,
5809  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_127_WIDTH },
5810  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_128_CHECKER_TYPE,
5811  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_128_WIDTH },
5812  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_129_CHECKER_TYPE,
5813  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_129_WIDTH },
5814  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_130_CHECKER_TYPE,
5815  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_130_WIDTH },
5816  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_131_CHECKER_TYPE,
5817  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_131_WIDTH },
5818  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_132_CHECKER_TYPE,
5819  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_132_WIDTH },
5820  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_133_CHECKER_TYPE,
5821  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_133_WIDTH },
5822  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_134_CHECKER_TYPE,
5823  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_134_WIDTH },
5824  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_135_CHECKER_TYPE,
5825  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_135_WIDTH },
5826  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_136_CHECKER_TYPE,
5827  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_136_WIDTH },
5828  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_137_CHECKER_TYPE,
5829  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_137_WIDTH },
5830  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_138_CHECKER_TYPE,
5831  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_138_WIDTH },
5832  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_139_CHECKER_TYPE,
5833  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_139_WIDTH },
5834  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_140_CHECKER_TYPE,
5835  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_140_WIDTH },
5836  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_141_CHECKER_TYPE,
5837  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_141_WIDTH },
5838  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_142_CHECKER_TYPE,
5839  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_142_WIDTH },
5840  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_143_CHECKER_TYPE,
5841  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_143_WIDTH },
5842  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_144_CHECKER_TYPE,
5843  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_144_WIDTH },
5844  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_145_CHECKER_TYPE,
5845  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_145_WIDTH },
5846  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_146_CHECKER_TYPE,
5847  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_146_WIDTH },
5848  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_147_CHECKER_TYPE,
5849  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_147_WIDTH },
5850  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_148_CHECKER_TYPE,
5851  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_148_WIDTH },
5852  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_149_CHECKER_TYPE,
5853  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_149_WIDTH },
5854  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_150_CHECKER_TYPE,
5855  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_GROUP_150_WIDTH },
5856 };
5857 
5863 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] =
5864 {
5865  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_0_CHECKER_TYPE,
5866  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
5867  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_1_CHECKER_TYPE,
5868  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
5869  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_2_CHECKER_TYPE,
5870  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
5871  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_3_CHECKER_TYPE,
5872  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
5873  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_4_CHECKER_TYPE,
5874  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
5875  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_5_CHECKER_TYPE,
5876  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
5877  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_6_CHECKER_TYPE,
5878  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
5879  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_7_CHECKER_TYPE,
5880  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
5881  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_8_CHECKER_TYPE,
5882  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
5883  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_9_CHECKER_TYPE,
5884  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
5885  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_10_CHECKER_TYPE,
5886  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
5887  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_11_CHECKER_TYPE,
5888  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
5889  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_12_CHECKER_TYPE,
5890  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
5891  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_13_CHECKER_TYPE,
5892  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
5893  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_14_CHECKER_TYPE,
5894  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
5895  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_15_CHECKER_TYPE,
5896  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
5897  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_16_CHECKER_TYPE,
5898  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
5899  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_17_CHECKER_TYPE,
5900  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
5901  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_18_CHECKER_TYPE,
5902  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
5903  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_19_CHECKER_TYPE,
5904  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
5905  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_20_CHECKER_TYPE,
5906  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
5907  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_21_CHECKER_TYPE,
5908  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
5909  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_22_CHECKER_TYPE,
5910  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
5911  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_23_CHECKER_TYPE,
5912  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
5913  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_24_CHECKER_TYPE,
5914  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
5915  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_25_CHECKER_TYPE,
5916  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
5917  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_26_CHECKER_TYPE,
5918  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
5919  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_27_CHECKER_TYPE,
5920  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
5921  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_28_CHECKER_TYPE,
5922  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
5923  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_29_CHECKER_TYPE,
5924  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
5925  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_30_CHECKER_TYPE,
5926  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
5927  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_31_CHECKER_TYPE,
5928  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
5929  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_32_CHECKER_TYPE,
5930  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
5931  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_33_CHECKER_TYPE,
5932  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
5933  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_34_CHECKER_TYPE,
5934  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
5935  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_35_CHECKER_TYPE,
5936  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
5937  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_36_CHECKER_TYPE,
5938  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
5939  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_37_CHECKER_TYPE,
5940  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
5941  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_38_CHECKER_TYPE,
5942  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
5943  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_39_CHECKER_TYPE,
5944  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
5945  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_40_CHECKER_TYPE,
5946  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
5947  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_41_CHECKER_TYPE,
5948  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
5949  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_42_CHECKER_TYPE,
5950  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
5951  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_43_CHECKER_TYPE,
5952  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
5953  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_44_CHECKER_TYPE,
5954  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
5955  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_45_CHECKER_TYPE,
5956  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
5957  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_46_CHECKER_TYPE,
5958  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
5959  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_47_CHECKER_TYPE,
5960  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
5961  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_48_CHECKER_TYPE,
5962  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
5963  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_49_CHECKER_TYPE,
5964  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
5965  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_50_CHECKER_TYPE,
5966  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
5967  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_51_CHECKER_TYPE,
5968  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
5969  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_52_CHECKER_TYPE,
5970  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
5971  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_53_CHECKER_TYPE,
5972  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
5973  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_54_CHECKER_TYPE,
5974  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
5975  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_55_CHECKER_TYPE,
5976  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
5977  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_56_CHECKER_TYPE,
5978  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
5979  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_57_CHECKER_TYPE,
5980  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
5981  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_58_CHECKER_TYPE,
5982  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
5983  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_59_CHECKER_TYPE,
5984  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
5985  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_60_CHECKER_TYPE,
5986  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
5987  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_61_CHECKER_TYPE,
5988  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
5989  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_62_CHECKER_TYPE,
5990  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
5991  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_63_CHECKER_TYPE,
5992  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
5993  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_64_CHECKER_TYPE,
5994  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
5995  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_65_CHECKER_TYPE,
5996  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
5997  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_66_CHECKER_TYPE,
5998  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
5999  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_67_CHECKER_TYPE,
6000  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
6001  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_68_CHECKER_TYPE,
6002  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
6003  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_69_CHECKER_TYPE,
6004  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
6005  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_70_CHECKER_TYPE,
6006  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
6007  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_71_CHECKER_TYPE,
6008  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
6009  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_72_CHECKER_TYPE,
6010  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
6011  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_73_CHECKER_TYPE,
6012  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
6013  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_74_CHECKER_TYPE,
6014  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
6015  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_75_CHECKER_TYPE,
6016  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
6017  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_76_CHECKER_TYPE,
6018  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
6019  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_77_CHECKER_TYPE,
6020  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
6021  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_78_CHECKER_TYPE,
6022  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
6023  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_79_CHECKER_TYPE,
6024  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
6025  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_80_CHECKER_TYPE,
6026  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
6027  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_81_CHECKER_TYPE,
6028  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
6029  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_82_CHECKER_TYPE,
6030  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
6031  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_83_CHECKER_TYPE,
6032  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
6033  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_84_CHECKER_TYPE,
6034  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
6035  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_85_CHECKER_TYPE,
6036  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
6037  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_86_CHECKER_TYPE,
6038  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
6039  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_87_CHECKER_TYPE,
6040  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
6041  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_88_CHECKER_TYPE,
6042  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
6043  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_89_CHECKER_TYPE,
6044  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
6045  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_90_CHECKER_TYPE,
6046  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
6047  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_91_CHECKER_TYPE,
6048  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
6049  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_92_CHECKER_TYPE,
6050  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
6051  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_93_CHECKER_TYPE,
6052  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
6053  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_94_CHECKER_TYPE,
6054  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
6055  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_95_CHECKER_TYPE,
6056  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
6057  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_96_CHECKER_TYPE,
6058  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
6059  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_97_CHECKER_TYPE,
6060  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
6061  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_98_CHECKER_TYPE,
6062  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
6063  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_99_CHECKER_TYPE,
6064  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
6065  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_100_CHECKER_TYPE,
6066  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
6067  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_101_CHECKER_TYPE,
6068  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
6069  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_102_CHECKER_TYPE,
6070  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
6071  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_103_CHECKER_TYPE,
6072  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
6073  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_104_CHECKER_TYPE,
6074  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
6075  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_105_CHECKER_TYPE,
6076  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
6077  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_106_CHECKER_TYPE,
6078  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
6079  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_107_CHECKER_TYPE,
6080  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
6081  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_108_CHECKER_TYPE,
6082  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
6083  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_109_CHECKER_TYPE,
6084  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
6085  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_110_CHECKER_TYPE,
6086  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
6087  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_111_CHECKER_TYPE,
6088  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
6089  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_112_CHECKER_TYPE,
6090  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
6091  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_113_CHECKER_TYPE,
6092  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
6093  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_114_CHECKER_TYPE,
6094  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
6095  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_115_CHECKER_TYPE,
6096  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
6097  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_116_CHECKER_TYPE,
6098  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
6099  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_117_CHECKER_TYPE,
6100  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
6101  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_118_CHECKER_TYPE,
6102  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
6103  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_119_CHECKER_TYPE,
6104  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
6105  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_120_CHECKER_TYPE,
6106  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
6107  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_121_CHECKER_TYPE,
6108  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
6109  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_122_CHECKER_TYPE,
6110  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
6111  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_123_CHECKER_TYPE,
6112  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
6113  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_124_CHECKER_TYPE,
6114  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
6115  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_125_CHECKER_TYPE,
6116  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
6117  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_126_CHECKER_TYPE,
6118  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
6119  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_127_CHECKER_TYPE,
6120  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
6121  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_128_CHECKER_TYPE,
6122  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
6123  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_129_CHECKER_TYPE,
6124  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
6125  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_130_CHECKER_TYPE,
6126  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
6127  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_131_CHECKER_TYPE,
6128  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
6129  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_132_CHECKER_TYPE,
6130  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
6131  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_133_CHECKER_TYPE,
6132  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
6133  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_134_CHECKER_TYPE,
6134  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
6135  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_135_CHECKER_TYPE,
6136  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
6137  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_136_CHECKER_TYPE,
6138  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
6139  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_137_CHECKER_TYPE,
6140  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
6141  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_138_CHECKER_TYPE,
6142  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
6143  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_139_CHECKER_TYPE,
6144  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
6145  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_140_CHECKER_TYPE,
6146  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
6147  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_141_CHECKER_TYPE,
6148  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
6149  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_142_CHECKER_TYPE,
6150  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
6151  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_143_CHECKER_TYPE,
6152  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
6153  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_144_CHECKER_TYPE,
6154  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
6155  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_145_CHECKER_TYPE,
6156  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
6157  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_146_CHECKER_TYPE,
6158  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
6159  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_147_CHECKER_TYPE,
6160  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
6161  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_148_CHECKER_TYPE,
6162  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
6163  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_149_CHECKER_TYPE,
6164  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
6165  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_150_CHECKER_TYPE,
6166  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
6167  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_151_CHECKER_TYPE,
6168  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
6169  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_152_CHECKER_TYPE,
6170  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
6171  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_153_CHECKER_TYPE,
6172  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
6173  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_154_CHECKER_TYPE,
6174  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
6175  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_155_CHECKER_TYPE,
6176  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
6177  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_156_CHECKER_TYPE,
6178  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
6179  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_157_CHECKER_TYPE,
6180  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
6181  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_158_CHECKER_TYPE,
6182  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
6183  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_159_CHECKER_TYPE,
6184  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
6185  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_160_CHECKER_TYPE,
6186  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
6187  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_161_CHECKER_TYPE,
6188  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
6189  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_162_CHECKER_TYPE,
6190  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
6191  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_163_CHECKER_TYPE,
6192  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
6193  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_164_CHECKER_TYPE,
6194  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
6195  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_165_CHECKER_TYPE,
6196  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
6197  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_166_CHECKER_TYPE,
6198  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
6199  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_167_CHECKER_TYPE,
6200  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
6201  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_168_CHECKER_TYPE,
6202  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
6203  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_169_CHECKER_TYPE,
6204  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
6205  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_170_CHECKER_TYPE,
6206  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
6207  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_171_CHECKER_TYPE,
6208  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
6209  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_172_CHECKER_TYPE,
6210  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
6211  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_173_CHECKER_TYPE,
6212  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
6213  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_174_CHECKER_TYPE,
6214  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
6215  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_175_CHECKER_TYPE,
6216  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
6217  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_176_CHECKER_TYPE,
6218  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
6219  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_177_CHECKER_TYPE,
6220  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
6221  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_178_CHECKER_TYPE,
6222  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
6223  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_179_CHECKER_TYPE,
6224  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
6225  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_180_CHECKER_TYPE,
6226  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
6227  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_181_CHECKER_TYPE,
6228  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
6229  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_182_CHECKER_TYPE,
6230  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
6231  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_183_CHECKER_TYPE,
6232  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
6233  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_184_CHECKER_TYPE,
6234  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
6235  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_185_CHECKER_TYPE,
6236  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
6237  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_186_CHECKER_TYPE,
6238  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
6239  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_187_CHECKER_TYPE,
6240  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
6241  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_188_CHECKER_TYPE,
6242  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
6243  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_189_CHECKER_TYPE,
6244  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
6245  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_190_CHECKER_TYPE,
6246  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
6247  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_191_CHECKER_TYPE,
6248  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
6249  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_192_CHECKER_TYPE,
6250  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
6251  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_193_CHECKER_TYPE,
6252  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
6253  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_194_CHECKER_TYPE,
6254  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
6255  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_195_CHECKER_TYPE,
6256  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
6257  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_196_CHECKER_TYPE,
6258  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
6259  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_197_CHECKER_TYPE,
6260  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
6261  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_198_CHECKER_TYPE,
6262  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
6263  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_199_CHECKER_TYPE,
6264  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
6265  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_200_CHECKER_TYPE,
6266  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
6267  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_201_CHECKER_TYPE,
6268  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
6269  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_202_CHECKER_TYPE,
6270  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
6271  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_203_CHECKER_TYPE,
6272  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
6273  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_204_CHECKER_TYPE,
6274  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
6275  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_205_CHECKER_TYPE,
6276  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
6277  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_206_CHECKER_TYPE,
6278  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
6279  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_207_CHECKER_TYPE,
6280  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
6281  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_208_CHECKER_TYPE,
6282  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
6283  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_209_CHECKER_TYPE,
6284  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
6285  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_210_CHECKER_TYPE,
6286  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
6287  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_211_CHECKER_TYPE,
6288  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
6289  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_212_CHECKER_TYPE,
6290  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
6291  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_213_CHECKER_TYPE,
6292  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
6293  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_214_CHECKER_TYPE,
6294  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
6295  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_215_CHECKER_TYPE,
6296  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
6297  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_216_CHECKER_TYPE,
6298  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
6299  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_217_CHECKER_TYPE,
6300  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
6301  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_218_CHECKER_TYPE,
6302  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
6303  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_219_CHECKER_TYPE,
6304  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
6305  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_220_CHECKER_TYPE,
6306  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
6307  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_221_CHECKER_TYPE,
6308  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
6309  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_222_CHECKER_TYPE,
6310  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
6311  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_223_CHECKER_TYPE,
6312  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
6313  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_224_CHECKER_TYPE,
6314  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
6315  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_225_CHECKER_TYPE,
6316  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
6317  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_226_CHECKER_TYPE,
6318  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
6319  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_227_CHECKER_TYPE,
6320  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
6321  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_228_CHECKER_TYPE,
6322  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
6323  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_229_CHECKER_TYPE,
6324  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
6325  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_230_CHECKER_TYPE,
6326  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
6327  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_231_CHECKER_TYPE,
6328  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
6329  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_232_CHECKER_TYPE,
6330  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
6331  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_233_CHECKER_TYPE,
6332  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
6333  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_234_CHECKER_TYPE,
6334  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
6335  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_235_CHECKER_TYPE,
6336  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
6337  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_236_CHECKER_TYPE,
6338  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
6339  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_237_CHECKER_TYPE,
6340  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
6341  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_238_CHECKER_TYPE,
6342  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
6343  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_239_CHECKER_TYPE,
6344  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
6345  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_240_CHECKER_TYPE,
6346  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
6347  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_241_CHECKER_TYPE,
6348  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
6349  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_242_CHECKER_TYPE,
6350  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
6351  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_243_CHECKER_TYPE,
6352  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
6353  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_244_CHECKER_TYPE,
6354  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
6355  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_245_CHECKER_TYPE,
6356  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
6357  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_246_CHECKER_TYPE,
6358  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
6359  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_247_CHECKER_TYPE,
6360  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
6361  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_248_CHECKER_TYPE,
6362  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
6363  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_249_CHECKER_TYPE,
6364  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
6365  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_250_CHECKER_TYPE,
6366  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
6367  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_251_CHECKER_TYPE,
6368  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
6369  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_252_CHECKER_TYPE,
6370  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
6371  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_253_CHECKER_TYPE,
6372  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
6373  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_254_CHECKER_TYPE,
6374  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
6375  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_255_CHECKER_TYPE,
6376  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
6377 };
6378 
6384 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] =
6385 {
6386  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_0_CHECKER_TYPE,
6387  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
6388  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_1_CHECKER_TYPE,
6389  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
6390  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_2_CHECKER_TYPE,
6391  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
6392  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_3_CHECKER_TYPE,
6393  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
6394  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_4_CHECKER_TYPE,
6395  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
6396  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_5_CHECKER_TYPE,
6397  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
6398  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_6_CHECKER_TYPE,
6399  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
6400  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_7_CHECKER_TYPE,
6401  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
6402  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_8_CHECKER_TYPE,
6403  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
6404  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_9_CHECKER_TYPE,
6405  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
6406  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_10_CHECKER_TYPE,
6407  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
6408  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_11_CHECKER_TYPE,
6409  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
6410  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_12_CHECKER_TYPE,
6411  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
6412  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_13_CHECKER_TYPE,
6413  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
6414  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_14_CHECKER_TYPE,
6415  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
6416  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_15_CHECKER_TYPE,
6417  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
6418  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_16_CHECKER_TYPE,
6419  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
6420  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_17_CHECKER_TYPE,
6421  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
6422  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_18_CHECKER_TYPE,
6423  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
6424  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_19_CHECKER_TYPE,
6425  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
6426  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_20_CHECKER_TYPE,
6427  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
6428  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_21_CHECKER_TYPE,
6429  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
6430  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_22_CHECKER_TYPE,
6431  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
6432  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_23_CHECKER_TYPE,
6433  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
6434  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_24_CHECKER_TYPE,
6435  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH },
6436  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_25_CHECKER_TYPE,
6437  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH },
6438  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_26_CHECKER_TYPE,
6439  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH },
6440  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_27_CHECKER_TYPE,
6441  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH },
6442  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_28_CHECKER_TYPE,
6443  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH },
6444  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_29_CHECKER_TYPE,
6445  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH },
6446  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_30_CHECKER_TYPE,
6447  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH },
6448  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_31_CHECKER_TYPE,
6449  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH },
6450  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_32_CHECKER_TYPE,
6451  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH },
6452  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_33_CHECKER_TYPE,
6453  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH },
6454  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_34_CHECKER_TYPE,
6455  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH },
6456  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_35_CHECKER_TYPE,
6457  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH },
6458  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_36_CHECKER_TYPE,
6459  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH },
6460  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_37_CHECKER_TYPE,
6461  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH },
6462  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_38_CHECKER_TYPE,
6463  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH },
6464  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_39_CHECKER_TYPE,
6465  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH },
6466  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_40_CHECKER_TYPE,
6467  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH },
6468  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_41_CHECKER_TYPE,
6469  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH },
6470  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_42_CHECKER_TYPE,
6471  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH },
6472  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_43_CHECKER_TYPE,
6473  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_43_WIDTH },
6474  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_44_CHECKER_TYPE,
6475  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_44_WIDTH },
6476  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_45_CHECKER_TYPE,
6477  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_45_WIDTH },
6478  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_46_CHECKER_TYPE,
6479  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_46_WIDTH },
6480  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_47_CHECKER_TYPE,
6481  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_47_WIDTH },
6482  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_48_CHECKER_TYPE,
6483  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_48_WIDTH },
6484  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_49_CHECKER_TYPE,
6485  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_49_WIDTH },
6486  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_50_CHECKER_TYPE,
6487  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_50_WIDTH },
6488  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_51_CHECKER_TYPE,
6489  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_51_WIDTH },
6490  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_52_CHECKER_TYPE,
6491  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_52_WIDTH },
6492  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_53_CHECKER_TYPE,
6493  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_53_WIDTH },
6494  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_54_CHECKER_TYPE,
6495  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_54_WIDTH },
6496  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_55_CHECKER_TYPE,
6497  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_55_WIDTH },
6498  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_56_CHECKER_TYPE,
6499  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_56_WIDTH },
6500  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_57_CHECKER_TYPE,
6501  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_57_WIDTH },
6502  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_58_CHECKER_TYPE,
6503  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_58_WIDTH },
6504  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_59_CHECKER_TYPE,
6505  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_59_WIDTH },
6506  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_60_CHECKER_TYPE,
6507  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_60_WIDTH },
6508  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_61_CHECKER_TYPE,
6509  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_61_WIDTH },
6510  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_62_CHECKER_TYPE,
6511  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_62_WIDTH },
6512  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_63_CHECKER_TYPE,
6513  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_63_WIDTH },
6514  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_64_CHECKER_TYPE,
6515  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_64_WIDTH },
6516  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_65_CHECKER_TYPE,
6517  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_65_WIDTH },
6518  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_66_CHECKER_TYPE,
6519  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_66_WIDTH },
6520  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_67_CHECKER_TYPE,
6521  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_67_WIDTH },
6522  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_68_CHECKER_TYPE,
6523  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_68_WIDTH },
6524  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_69_CHECKER_TYPE,
6525  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_69_WIDTH },
6526  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_70_CHECKER_TYPE,
6527  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_70_WIDTH },
6528  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_71_CHECKER_TYPE,
6529  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_71_WIDTH },
6530  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_72_CHECKER_TYPE,
6531  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_72_WIDTH },
6532  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_73_CHECKER_TYPE,
6533  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_73_WIDTH },
6534  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_74_CHECKER_TYPE,
6535  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_74_WIDTH },
6536  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_75_CHECKER_TYPE,
6537  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_75_WIDTH },
6538  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_76_CHECKER_TYPE,
6539  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_76_WIDTH },
6540  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_77_CHECKER_TYPE,
6541  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_77_WIDTH },
6542  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_78_CHECKER_TYPE,
6543  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_78_WIDTH },
6544  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_79_CHECKER_TYPE,
6545  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_79_WIDTH },
6546  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_80_CHECKER_TYPE,
6547  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_80_WIDTH },
6548  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_81_CHECKER_TYPE,
6549  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_81_WIDTH },
6550  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_82_CHECKER_TYPE,
6551  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_82_WIDTH },
6552  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_83_CHECKER_TYPE,
6553  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_83_WIDTH },
6554  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_84_CHECKER_TYPE,
6555  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_84_WIDTH },
6556  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_85_CHECKER_TYPE,
6557  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_85_WIDTH },
6558  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_86_CHECKER_TYPE,
6559  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_86_WIDTH },
6560  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_87_CHECKER_TYPE,
6561  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_87_WIDTH },
6562  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_88_CHECKER_TYPE,
6563  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_88_WIDTH },
6564  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_89_CHECKER_TYPE,
6565  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_89_WIDTH },
6566  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_90_CHECKER_TYPE,
6567  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_90_WIDTH },
6568  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_91_CHECKER_TYPE,
6569  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_91_WIDTH },
6570  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_92_CHECKER_TYPE,
6571  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_92_WIDTH },
6572  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_93_CHECKER_TYPE,
6573  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_93_WIDTH },
6574  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_94_CHECKER_TYPE,
6575  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_94_WIDTH },
6576  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_95_CHECKER_TYPE,
6577  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_95_WIDTH },
6578  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_96_CHECKER_TYPE,
6579  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_96_WIDTH },
6580  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_97_CHECKER_TYPE,
6581  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_97_WIDTH },
6582  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_98_CHECKER_TYPE,
6583  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_98_WIDTH },
6584  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_99_CHECKER_TYPE,
6585  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_99_WIDTH },
6586  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_100_CHECKER_TYPE,
6587  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_100_WIDTH },
6588  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_101_CHECKER_TYPE,
6589  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_101_WIDTH },
6590  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_102_CHECKER_TYPE,
6591  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_102_WIDTH },
6592  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_103_CHECKER_TYPE,
6593  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_103_WIDTH },
6594  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_104_CHECKER_TYPE,
6595  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_104_WIDTH },
6596  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_105_CHECKER_TYPE,
6597  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_105_WIDTH },
6598  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_106_CHECKER_TYPE,
6599  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_106_WIDTH },
6600  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_107_CHECKER_TYPE,
6601  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_107_WIDTH },
6602  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_108_CHECKER_TYPE,
6603  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_108_WIDTH },
6604  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_109_CHECKER_TYPE,
6605  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_109_WIDTH },
6606  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_110_CHECKER_TYPE,
6607  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_110_WIDTH },
6608  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_111_CHECKER_TYPE,
6609  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_111_WIDTH },
6610  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_112_CHECKER_TYPE,
6611  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_112_WIDTH },
6612  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_113_CHECKER_TYPE,
6613  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_113_WIDTH },
6614  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_114_CHECKER_TYPE,
6615  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_114_WIDTH },
6616  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_115_CHECKER_TYPE,
6617  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_115_WIDTH },
6618  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_116_CHECKER_TYPE,
6619  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_116_WIDTH },
6620  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_117_CHECKER_TYPE,
6621  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_117_WIDTH },
6622  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_118_CHECKER_TYPE,
6623  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_118_WIDTH },
6624  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_119_CHECKER_TYPE,
6625  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_119_WIDTH },
6626  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_120_CHECKER_TYPE,
6627  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_120_WIDTH },
6628  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_121_CHECKER_TYPE,
6629  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_121_WIDTH },
6630  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_122_CHECKER_TYPE,
6631  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_122_WIDTH },
6632  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_123_CHECKER_TYPE,
6633  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_123_WIDTH },
6634  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_124_CHECKER_TYPE,
6635  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_124_WIDTH },
6636  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_125_CHECKER_TYPE,
6637  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_125_WIDTH },
6638  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_126_CHECKER_TYPE,
6639  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_126_WIDTH },
6640  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_127_CHECKER_TYPE,
6641  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_127_WIDTH },
6642  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_128_CHECKER_TYPE,
6643  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_128_WIDTH },
6644  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_129_CHECKER_TYPE,
6645  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_129_WIDTH },
6646  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_130_CHECKER_TYPE,
6647  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_130_WIDTH },
6648  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_131_CHECKER_TYPE,
6649  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_131_WIDTH },
6650  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_132_CHECKER_TYPE,
6651  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_132_WIDTH },
6652  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_133_CHECKER_TYPE,
6653  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_133_WIDTH },
6654  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_134_CHECKER_TYPE,
6655  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_134_WIDTH },
6656  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_135_CHECKER_TYPE,
6657  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_135_WIDTH },
6658  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_136_CHECKER_TYPE,
6659  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_136_WIDTH },
6660  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_137_CHECKER_TYPE,
6661  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_137_WIDTH },
6662  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_138_CHECKER_TYPE,
6663  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_138_WIDTH },
6664  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_139_CHECKER_TYPE,
6665  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_139_WIDTH },
6666  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_140_CHECKER_TYPE,
6667  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_140_WIDTH },
6668  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_141_CHECKER_TYPE,
6669  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_141_WIDTH },
6670  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_142_CHECKER_TYPE,
6671  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_142_WIDTH },
6672  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_143_CHECKER_TYPE,
6673  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_143_WIDTH },
6674  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_144_CHECKER_TYPE,
6675  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_144_WIDTH },
6676  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_145_CHECKER_TYPE,
6677  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_145_WIDTH },
6678  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_146_CHECKER_TYPE,
6679  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_146_WIDTH },
6680  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_147_CHECKER_TYPE,
6681  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_147_WIDTH },
6682  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_148_CHECKER_TYPE,
6683  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_148_WIDTH },
6684  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_149_CHECKER_TYPE,
6685  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_149_WIDTH },
6686  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_150_CHECKER_TYPE,
6687  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_150_WIDTH },
6688  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_151_CHECKER_TYPE,
6689  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_151_WIDTH },
6690  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_152_CHECKER_TYPE,
6691  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_152_WIDTH },
6692  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_153_CHECKER_TYPE,
6693  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_153_WIDTH },
6694  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_154_CHECKER_TYPE,
6695  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_154_WIDTH },
6696  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_155_CHECKER_TYPE,
6697  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_155_WIDTH },
6698  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_156_CHECKER_TYPE,
6699  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_156_WIDTH },
6700  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_157_CHECKER_TYPE,
6701  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_157_WIDTH },
6702  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_158_CHECKER_TYPE,
6703  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_158_WIDTH },
6704  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_159_CHECKER_TYPE,
6705  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_159_WIDTH },
6706  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_160_CHECKER_TYPE,
6707  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_160_WIDTH },
6708  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_161_CHECKER_TYPE,
6709  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_161_WIDTH },
6710  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_162_CHECKER_TYPE,
6711  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_162_WIDTH },
6712  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_163_CHECKER_TYPE,
6713  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_163_WIDTH },
6714  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_164_CHECKER_TYPE,
6715  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_164_WIDTH },
6716  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_165_CHECKER_TYPE,
6717  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_165_WIDTH },
6718  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_166_CHECKER_TYPE,
6719  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_166_WIDTH },
6720  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_167_CHECKER_TYPE,
6721  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_167_WIDTH },
6722  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_168_CHECKER_TYPE,
6723  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_168_WIDTH },
6724  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_169_CHECKER_TYPE,
6725  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_169_WIDTH },
6726  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_170_CHECKER_TYPE,
6727  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_170_WIDTH },
6728  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_171_CHECKER_TYPE,
6729  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_171_WIDTH },
6730  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_172_CHECKER_TYPE,
6731  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_172_WIDTH },
6732  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_173_CHECKER_TYPE,
6733  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_173_WIDTH },
6734  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_174_CHECKER_TYPE,
6735  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_174_WIDTH },
6736  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_175_CHECKER_TYPE,
6737  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_175_WIDTH },
6738  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_176_CHECKER_TYPE,
6739  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_176_WIDTH },
6740  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_177_CHECKER_TYPE,
6741  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_177_WIDTH },
6742  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_178_CHECKER_TYPE,
6743  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_178_WIDTH },
6744  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_179_CHECKER_TYPE,
6745  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_179_WIDTH },
6746  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_180_CHECKER_TYPE,
6747  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_180_WIDTH },
6748  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_181_CHECKER_TYPE,
6749  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_181_WIDTH },
6750  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_182_CHECKER_TYPE,
6751  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_182_WIDTH },
6752  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_183_CHECKER_TYPE,
6753  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_183_WIDTH },
6754  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_184_CHECKER_TYPE,
6755  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_184_WIDTH },
6756  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_185_CHECKER_TYPE,
6757  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_185_WIDTH },
6758  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_186_CHECKER_TYPE,
6759  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_186_WIDTH },
6760  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_187_CHECKER_TYPE,
6761  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_187_WIDTH },
6762  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_188_CHECKER_TYPE,
6763  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_188_WIDTH },
6764  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_189_CHECKER_TYPE,
6765  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_189_WIDTH },
6766  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_190_CHECKER_TYPE,
6767  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_190_WIDTH },
6768  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_191_CHECKER_TYPE,
6769  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_191_WIDTH },
6770  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_192_CHECKER_TYPE,
6771  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_192_WIDTH },
6772  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_193_CHECKER_TYPE,
6773  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_193_WIDTH },
6774  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_194_CHECKER_TYPE,
6775  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_194_WIDTH },
6776  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_195_CHECKER_TYPE,
6777  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_195_WIDTH },
6778  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_196_CHECKER_TYPE,
6779  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_196_WIDTH },
6780  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_197_CHECKER_TYPE,
6781  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_197_WIDTH },
6782  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_198_CHECKER_TYPE,
6783  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_198_WIDTH },
6784  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_199_CHECKER_TYPE,
6785  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_199_WIDTH },
6786  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_200_CHECKER_TYPE,
6787  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_200_WIDTH },
6788  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_201_CHECKER_TYPE,
6789  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_201_WIDTH },
6790  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_202_CHECKER_TYPE,
6791  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_202_WIDTH },
6792  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_203_CHECKER_TYPE,
6793  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_203_WIDTH },
6794  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_204_CHECKER_TYPE,
6795  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_204_WIDTH },
6796  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_205_CHECKER_TYPE,
6797  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_205_WIDTH },
6798  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_206_CHECKER_TYPE,
6799  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_206_WIDTH },
6800  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_207_CHECKER_TYPE,
6801  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_207_WIDTH },
6802  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_208_CHECKER_TYPE,
6803  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_208_WIDTH },
6804  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_209_CHECKER_TYPE,
6805  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_209_WIDTH },
6806  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_210_CHECKER_TYPE,
6807  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_210_WIDTH },
6808  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_211_CHECKER_TYPE,
6809  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_211_WIDTH },
6810  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_212_CHECKER_TYPE,
6811  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_212_WIDTH },
6812  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_213_CHECKER_TYPE,
6813  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_213_WIDTH },
6814  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_214_CHECKER_TYPE,
6815  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_214_WIDTH },
6816  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_215_CHECKER_TYPE,
6817  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_215_WIDTH },
6818 };
6819 
6825 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
6826 {
6827  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
6828  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
6829  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
6830  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
6831  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
6832  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
6833  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
6834  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
6835  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_4_CHECKER_TYPE,
6836  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_4_WIDTH },
6837  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_5_CHECKER_TYPE,
6838  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_5_WIDTH },
6839  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_6_CHECKER_TYPE,
6840  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_6_WIDTH },
6841  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_7_CHECKER_TYPE,
6842  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_7_WIDTH },
6843  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_8_CHECKER_TYPE,
6844  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_8_WIDTH },
6845  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_9_CHECKER_TYPE,
6846  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_9_WIDTH },
6847  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_10_CHECKER_TYPE,
6848  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_10_WIDTH },
6849  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_11_CHECKER_TYPE,
6850  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_11_WIDTH },
6851  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_12_CHECKER_TYPE,
6852  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_12_WIDTH },
6853  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_13_CHECKER_TYPE,
6854  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_GROUP_13_WIDTH },
6855 };
6856 
6862 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
6863 {
6864  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
6865  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
6866  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
6867  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
6868  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
6869  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
6870  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
6871  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
6872  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
6873  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
6874  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
6875  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
6876  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
6877  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
6878  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
6879  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
6880  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
6881  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
6882  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
6883  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
6884  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
6885  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
6886  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
6887  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
6888  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
6889  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
6890  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
6891  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
6892  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
6893  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
6894  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_15_CHECKER_TYPE,
6895  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_15_WIDTH },
6896  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_16_CHECKER_TYPE,
6897  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_GROUP_16_WIDTH },
6898 };
6899 
6905 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
6906 {
6907  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
6908  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
6909  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
6910  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
6911  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
6912  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
6913  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
6914  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
6915  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_4_CHECKER_TYPE,
6916  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_4_WIDTH },
6917  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_5_CHECKER_TYPE,
6918  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_5_WIDTH },
6919  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_6_CHECKER_TYPE,
6920  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_6_WIDTH },
6921  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_7_CHECKER_TYPE,
6922  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_7_WIDTH },
6923  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_8_CHECKER_TYPE,
6924  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_8_WIDTH },
6925  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_9_CHECKER_TYPE,
6926  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_9_WIDTH },
6927  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_10_CHECKER_TYPE,
6928  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_GROUP_10_WIDTH },
6929 };
6930 
6936 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
6937 {
6938  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
6939  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
6940  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
6941  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
6942  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
6943  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
6944  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
6945  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
6946  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
6947  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
6948  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
6949  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
6950  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
6951  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
6952  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
6953  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
6954  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
6955  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
6956  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
6957  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
6958  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
6959  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
6960  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
6961  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
6962  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
6963  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
6964  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
6965  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
6966  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
6967  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
6968  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_15_CHECKER_TYPE,
6969  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_15_WIDTH },
6970  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_16_CHECKER_TYPE,
6971  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_GROUP_16_WIDTH },
6972 };
6973 
6979 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
6980 {
6981  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
6982  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
6983  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
6984  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
6985  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
6986  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
6987  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
6988  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
6989  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_GROUP_4_CHECKER_TYPE,
6990  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_GROUP_4_WIDTH },
6991 };
6992 
6998 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
6999 {
7000  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
7001  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
7002  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
7003  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
7004  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
7005  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
7006  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
7007  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
7008  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
7009  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
7010  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
7011  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
7012  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
7013  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
7014  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
7015  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
7016  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
7017  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
7018  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
7019  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
7020  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
7021  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
7022  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
7023  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
7024  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
7025  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
7026  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
7027  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
7028  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
7029  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
7030  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_15_CHECKER_TYPE,
7031  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_15_WIDTH },
7032  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_16_CHECKER_TYPE,
7033  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_GROUP_16_WIDTH },
7034 };
7035 
7041 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
7042 {
7043  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
7044  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
7045  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
7046  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
7047  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
7048  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
7049  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
7050  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
7051  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
7052  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
7053 };
7054 
7060 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
7061 {
7062  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
7063  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
7064  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
7065  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
7066  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
7067  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
7068  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
7069  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
7070  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
7071  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
7072  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
7073  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
7074  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
7075  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
7076  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
7077  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
7078 };
7079 
7085 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
7086 {
7087  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
7088  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
7089  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
7090  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
7091  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
7092  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
7093  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
7094  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
7095  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
7096  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
7097  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
7098  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
7099  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
7100  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
7101  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
7102  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
7103  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
7104  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
7105  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
7106  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
7107  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
7108  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
7109  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
7110  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
7111  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
7112  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
7113  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
7114  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
7115  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
7116  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
7117  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
7118  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
7119  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
7120  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
7121  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
7122  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
7123  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
7124  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
7125  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
7126  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
7127  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
7128  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
7129  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
7130  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
7131  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
7132  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
7133  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
7134  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
7135  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
7136  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
7137  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
7138  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
7139  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
7140  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
7141  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
7142  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
7143  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
7144  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
7145  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
7146  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
7147  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
7148  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
7149  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
7150  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
7151  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
7152  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
7153  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
7154  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
7155  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
7156  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
7157  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
7158  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
7159  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
7160  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
7161  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
7162  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
7163  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
7164  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
7165  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
7166  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
7167  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
7168  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
7169  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
7170  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
7171 };
7172 
7178 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
7179 {
7180  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
7181  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
7182  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
7183  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
7184  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
7185  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
7186  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
7187  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_3_WIDTH },
7188  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
7189  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_4_WIDTH },
7190  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
7191  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_5_WIDTH },
7192  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
7193  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_6_WIDTH },
7194  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
7195  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_7_WIDTH },
7196  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
7197  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_8_WIDTH },
7198  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
7199  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_9_WIDTH },
7200  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
7201  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_10_WIDTH },
7202  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
7203  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_11_WIDTH },
7204  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
7205  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_12_WIDTH },
7206  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_13_CHECKER_TYPE,
7207  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_13_WIDTH },
7208  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_14_CHECKER_TYPE,
7209  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_14_WIDTH },
7210  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_15_CHECKER_TYPE,
7211  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_15_WIDTH },
7212  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_16_CHECKER_TYPE,
7213  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_16_WIDTH },
7214  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_17_CHECKER_TYPE,
7215  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_17_WIDTH },
7216  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_18_CHECKER_TYPE,
7217  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_18_WIDTH },
7218 };
7219 
7225 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
7226 {
7227  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
7228  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
7229  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
7230  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
7231  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
7232  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
7233  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
7234  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
7235  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
7236  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
7237  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
7238  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
7239  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
7240  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
7241  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
7242  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
7243  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
7244  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
7245  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
7246  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
7247  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
7248  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
7249  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
7250  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
7251  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
7252  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
7253  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
7254  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
7255  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
7256  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
7257  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
7258  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
7259  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
7260  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
7261  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
7262  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
7263  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
7264  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
7265  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
7266  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
7267  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
7268  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
7269  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
7270  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
7271  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
7272  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
7273  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
7274  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
7275  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
7276  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
7277  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
7278  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
7279  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
7280  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
7281  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
7282  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
7283  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
7284  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
7285  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
7286  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
7287  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
7288  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
7289  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
7290  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
7291  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
7292  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
7293  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
7294  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
7295  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
7296  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
7297  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
7298  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
7299  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
7300  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
7301  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
7302  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
7303  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
7304  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
7305  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
7306  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
7307  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
7308  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
7309  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
7310  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
7311 };
7312 
7318 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
7319 {
7320  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
7321  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
7322  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
7323  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
7324  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
7325  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
7326  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
7327  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_3_WIDTH },
7328  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
7329  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_4_WIDTH },
7330  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
7331  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_5_WIDTH },
7332  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
7333  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_6_WIDTH },
7334  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
7335  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_7_WIDTH },
7336  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
7337  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_8_WIDTH },
7338  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
7339  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_9_WIDTH },
7340  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
7341  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_10_WIDTH },
7342  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
7343  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_11_WIDTH },
7344  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
7345  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_12_WIDTH },
7346  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_13_CHECKER_TYPE,
7347  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_13_WIDTH },
7348  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_14_CHECKER_TYPE,
7349  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_14_WIDTH },
7350  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_15_CHECKER_TYPE,
7351  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_15_WIDTH },
7352  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_16_CHECKER_TYPE,
7353  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_16_WIDTH },
7354  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_17_CHECKER_TYPE,
7355  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_17_WIDTH },
7356  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_18_CHECKER_TYPE,
7357  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_18_WIDTH },
7358 };
7359 
7365 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
7366 {
7367  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
7368  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
7369  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
7370  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
7371  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
7372  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
7373  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
7374  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
7375  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_4_CHECKER_TYPE,
7376  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_4_WIDTH },
7377  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_5_CHECKER_TYPE,
7378  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_5_WIDTH },
7379  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_6_CHECKER_TYPE,
7380  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_6_WIDTH },
7381  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_7_CHECKER_TYPE,
7382  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_7_WIDTH },
7383  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_8_CHECKER_TYPE,
7384  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_8_WIDTH },
7385  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_9_CHECKER_TYPE,
7386  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_9_WIDTH },
7387  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_10_CHECKER_TYPE,
7388  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_10_WIDTH },
7389  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_11_CHECKER_TYPE,
7390  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_11_WIDTH },
7391  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_12_CHECKER_TYPE,
7392  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_12_WIDTH },
7393  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_13_CHECKER_TYPE,
7394  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_GROUP_13_WIDTH },
7395 };
7396 
7402 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
7403 {
7404  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
7405  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
7406  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
7407  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
7408  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
7409  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
7410  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
7411  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
7412  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
7413  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
7414  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
7415  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
7416  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
7417  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
7418  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
7419  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
7420  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
7421  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
7422  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
7423  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
7424  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
7425  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
7426  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
7427  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
7428  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
7429  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
7430  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
7431  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
7432  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
7433  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
7434  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_15_CHECKER_TYPE,
7435  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_15_WIDTH },
7436  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_16_CHECKER_TYPE,
7437  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_GROUP_16_WIDTH },
7438 };
7439 
7445 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_SAM62A_MCU_MCU_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_SAM62A_MCU_MCU_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
7446 {
7447  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_SAM62A_MCU_MCU_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
7448  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_SAM62A_MCU_MCU_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
7449  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_SAM62A_MCU_MCU_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
7450  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_SAM62A_MCU_MCU_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
7451  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_SAM62A_MCU_MCU_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
7452  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_SAM62A_MCU_MCU_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
7453  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_SAM62A_MCU_MCU_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
7454  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_SAM62A_MCU_MCU_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
7455  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_SAM62A_MCU_MCU_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
7456  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_SAM62A_MCU_MCU_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
7457  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_SAM62A_MCU_MCU_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
7458  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_SAM62A_MCU_MCU_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
7459 };
7460 
7465 static const SDL_MemConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_MemEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_RAM_IDS_TOTAL_ENTRIES] =
7466 {
7467  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_CONFIG_RAM_ID, 0u,
7468  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_CONFIG_RAM_SIZE, 14u,
7469  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_CONFIG_ROW_WIDTH, ((bool)false) },
7470  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_STATE_RAM_ID, 0u,
7471  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_STATE_RAM_SIZE, 32u,
7472  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_STATE_ROW_WIDTH, ((bool)false) },
7473  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F0_RAM_ID, 0u,
7474  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F0_RAM_SIZE, 18u,
7475  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F0_ROW_WIDTH, ((bool)false) },
7476  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F1_RAM_ID, 0u,
7477  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F1_RAM_SIZE, 18u,
7478  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F1_ROW_WIDTH, ((bool)false) },
7479  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F0_RAM_ID, 0u,
7480  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F0_RAM_SIZE, 16u,
7481  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F0_ROW_WIDTH, ((bool)false) },
7482  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F1_RAM_ID, 0u,
7483  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F1_RAM_SIZE, 16u,
7484  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F1_ROW_WIDTH, ((bool)false) },
7485  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_WC_RAM_ID, 0u,
7486  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_WC_RAM_SIZE, 4u,
7487  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_WC_ROW_WIDTH, ((bool)false) },
7488  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STST0_RAM_ID, 0u,
7489  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STST0_RAM_SIZE, 12u,
7490  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STST0_ROW_WIDTH, ((bool)false) },
7491  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STSR0_RAM_ID, 0u,
7492  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STSR0_RAM_SIZE, 16u,
7493  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STSR0_ROW_WIDTH, ((bool)false) },
7494  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RINGOCC_CNTR_RAM_ID, 0u,
7495  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RINGOCC_CNTR_RAM_SIZE, 4u,
7496  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RINGOCC_CNTR_ROW_WIDTH, ((bool)false) },
7497  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_RAM_ID, 0u,
7498  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_RAM_SIZE, 16u,
7499  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_ROW_WIDTH, ((bool)false) },
7500  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_COMMON_IM_TPRAM_158X34_SWW_SR_RAM_ID, 0u,
7501  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_COMMON_IM_TPRAM_158X34_SWW_SR_RAM_SIZE, 5u,
7502  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_COMMON_IM_TPRAM_158X34_SWW_SR_ROW_WIDTH, ((bool)false) },
7503  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_STRAM_RAM_ID, 0u,
7504  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_STRAM_RAM_SIZE, 27u,
7505  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_STRAM_ROW_WIDTH, ((bool)false) },
7506  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_STRAM_RAM_ID, 0u,
7507  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_STRAM_RAM_SIZE, 12u,
7508  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_STRAM_ROW_WIDTH, ((bool)false) },
7509  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_BUFRAM_RAM_ID, 0u,
7510  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_BUFRAM_RAM_SIZE, 8u,
7511  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_BUFRAM_ROW_WIDTH, ((bool)false) },
7512  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_ECC0_RAM_ID, 0u,
7513  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_ECC0_RAM_SIZE, 8u,
7514  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_ECC0_ROW_WIDTH, ((bool)false) },
7515 };
7516 
7522 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
7523 {
7524  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
7525  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_0_WIDTH },
7526  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
7527  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_1_WIDTH },
7528  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
7529  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_2_WIDTH },
7530  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
7531  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_3_WIDTH },
7532  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
7533  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_4_WIDTH },
7534  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
7535  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_5_WIDTH },
7536 };
7537 
7543 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_MAX_NUM_CHECKERS] =
7544 {
7545  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
7546  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_0_WIDTH },
7547  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
7548  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_1_WIDTH },
7549  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
7550  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_2_WIDTH },
7551  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
7552  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_3_WIDTH },
7553  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
7554  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_4_WIDTH },
7555  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
7556  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_5_WIDTH },
7557  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
7558  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_6_WIDTH },
7559  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
7560  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_7_WIDTH },
7561  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
7562  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_8_WIDTH },
7563  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
7564  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_9_WIDTH },
7565  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
7566  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_10_WIDTH },
7567  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
7568  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_11_WIDTH },
7569  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
7570  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_12_WIDTH },
7571  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
7572  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_13_WIDTH },
7573  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
7574  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_14_WIDTH },
7575  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
7576  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_15_WIDTH },
7577  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
7578  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_16_WIDTH },
7579  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
7580  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_17_WIDTH },
7581  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
7582  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_18_WIDTH },
7583  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
7584  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_19_WIDTH },
7585  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
7586  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_20_WIDTH },
7587  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
7588  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_21_WIDTH },
7589  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
7590  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_22_WIDTH },
7591  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
7592  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_23_WIDTH },
7593  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
7594  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_24_WIDTH },
7595  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
7596  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_25_WIDTH },
7597  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
7598  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_26_WIDTH },
7599  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
7600  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_27_WIDTH },
7601  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
7602  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_28_WIDTH },
7603  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
7604  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_29_WIDTH },
7605  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
7606  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_30_WIDTH },
7607  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
7608  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_31_WIDTH },
7609  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
7610  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_32_WIDTH },
7611  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
7612  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_33_WIDTH },
7613  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
7614  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_34_WIDTH },
7615  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
7616  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_35_WIDTH },
7617  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
7618  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_36_WIDTH },
7619  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
7620  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_37_WIDTH },
7621  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
7622  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_38_WIDTH },
7623  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
7624  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_39_WIDTH },
7625  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
7626  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_40_WIDTH },
7627  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
7628  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_41_WIDTH },
7629  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
7630  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_42_WIDTH },
7631  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
7632  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_43_WIDTH },
7633  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
7634  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_44_WIDTH },
7635  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
7636  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_45_WIDTH },
7637  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
7638  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_46_WIDTH },
7639  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
7640  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_47_WIDTH },
7641  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
7642  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_48_WIDTH },
7643  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
7644  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_49_WIDTH },
7645  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
7646  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_50_WIDTH },
7647  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
7648  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_51_WIDTH },
7649  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
7650  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_52_WIDTH },
7651  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
7652  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_53_WIDTH },
7653  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
7654  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_54_WIDTH },
7655  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
7656  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_55_WIDTH },
7657  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
7658  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_56_WIDTH },
7659  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
7660  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_57_WIDTH },
7661  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
7662  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_58_WIDTH },
7663  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
7664  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_59_WIDTH },
7665  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
7666  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_60_WIDTH },
7667  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
7668  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_61_WIDTH },
7669  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
7670  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_62_WIDTH },
7671  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
7672  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_63_WIDTH },
7673  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
7674  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_64_WIDTH },
7675  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
7676  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_65_WIDTH },
7677  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
7678  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_66_WIDTH },
7679  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
7680  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_67_WIDTH },
7681  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
7682  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_68_WIDTH },
7683  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
7684  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_69_WIDTH },
7685  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
7686  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_70_WIDTH },
7687  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
7688  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_71_WIDTH },
7689 };
7690 
7696 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
7697 {
7698  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
7699  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_0_WIDTH },
7700  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
7701  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_1_WIDTH },
7702  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
7703  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_2_WIDTH },
7704  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
7705  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_3_WIDTH },
7706  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
7707  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_4_WIDTH },
7708  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
7709  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_5_WIDTH },
7710  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
7711  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_6_WIDTH },
7712  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
7713  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_7_WIDTH },
7714  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
7715  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_8_WIDTH },
7716  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
7717  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_9_WIDTH },
7718  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
7719  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_10_WIDTH },
7720  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
7721  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_11_WIDTH },
7722  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
7723  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_12_WIDTH },
7724  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
7725  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_13_WIDTH },
7726  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
7727  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_14_WIDTH },
7728  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
7729  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_15_WIDTH },
7730  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
7731  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_16_WIDTH },
7732  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
7733  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_17_WIDTH },
7734 };
7735 
7741 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
7742 {
7743  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
7744  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_0_WIDTH },
7745  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
7746  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_1_WIDTH },
7747  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
7748  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_2_WIDTH },
7749  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
7750  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_3_WIDTH },
7751  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
7752  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_4_WIDTH },
7753  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
7754  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_5_WIDTH },
7755  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
7756  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_6_WIDTH },
7757  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
7758  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_7_WIDTH },
7759  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
7760  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_8_WIDTH },
7761  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
7762  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_9_WIDTH },
7763  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
7764  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_10_WIDTH },
7765  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
7766  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_11_WIDTH },
7767  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
7768  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_12_WIDTH },
7769  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
7770  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_13_WIDTH },
7771  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
7772  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_14_WIDTH },
7773  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
7774  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_15_WIDTH },
7775  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
7776  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_16_WIDTH },
7777  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
7778  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_17_WIDTH },
7779  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
7780  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_18_WIDTH },
7781  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
7782  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_19_WIDTH },
7783  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
7784  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_20_WIDTH },
7785  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
7786  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_21_WIDTH },
7787  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
7788  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_22_WIDTH },
7789  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
7790  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_23_WIDTH },
7791  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
7792  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_24_WIDTH },
7793  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
7794  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_25_WIDTH },
7795  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
7796  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_26_WIDTH },
7797  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
7798  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_27_WIDTH },
7799  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
7800  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_28_WIDTH },
7801  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
7802  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_29_WIDTH },
7803  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
7804  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_30_WIDTH },
7805  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
7806  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_31_WIDTH },
7807  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
7808  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_32_WIDTH },
7809  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
7810  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_33_WIDTH },
7811  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
7812  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_34_WIDTH },
7813  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
7814  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_35_WIDTH },
7815  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
7816  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_36_WIDTH },
7817  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
7818  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_37_WIDTH },
7819  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
7820  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_38_WIDTH },
7821  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
7822  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_39_WIDTH },
7823  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
7824  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_40_WIDTH },
7825  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
7826  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_41_WIDTH },
7827  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
7828  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_42_WIDTH },
7829  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
7830  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_43_WIDTH },
7831  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
7832  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_44_WIDTH },
7833  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
7834  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_45_WIDTH },
7835  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
7836  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_46_WIDTH },
7837  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
7838  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_47_WIDTH },
7839  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
7840  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_48_WIDTH },
7841  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
7842  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_49_WIDTH },
7843  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
7844  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_50_WIDTH },
7845  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
7846  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_51_WIDTH },
7847  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
7848  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_52_WIDTH },
7849  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
7850  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_53_WIDTH },
7851  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
7852  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_54_WIDTH },
7853  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
7854  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_55_WIDTH },
7855  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
7856  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_56_WIDTH },
7857  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
7858  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_57_WIDTH },
7859  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
7860  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_58_WIDTH },
7861  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
7862  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_59_WIDTH },
7863  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
7864  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_60_WIDTH },
7865  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
7866  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_61_WIDTH },
7867  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
7868  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_62_WIDTH },
7869  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
7870  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_63_WIDTH },
7871  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
7872  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_64_WIDTH },
7873  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
7874  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_65_WIDTH },
7875  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
7876  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_66_WIDTH },
7877  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
7878  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_67_WIDTH },
7879  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
7880  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_68_WIDTH },
7881  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
7882  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_69_WIDTH },
7883  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
7884  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_70_WIDTH },
7885  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
7886  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_71_WIDTH },
7887  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
7888  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_72_WIDTH },
7889  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
7890  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_73_WIDTH },
7891  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
7892  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_74_WIDTH },
7893  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
7894  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_75_WIDTH },
7895  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
7896  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_76_WIDTH },
7897  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
7898  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_77_WIDTH },
7899  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
7900  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_78_WIDTH },
7901  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
7902  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_79_WIDTH },
7903  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
7904  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_80_WIDTH },
7905  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
7906  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_81_WIDTH },
7907  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
7908  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_82_WIDTH },
7909  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
7910  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_83_WIDTH },
7911  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
7912  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_84_WIDTH },
7913  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
7914  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_85_WIDTH },
7915  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
7916  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_86_WIDTH },
7917  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
7918  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_87_WIDTH },
7919  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
7920  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_88_WIDTH },
7921  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
7922  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_89_WIDTH },
7923  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
7924  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_90_WIDTH },
7925  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
7926  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_91_WIDTH },
7927  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
7928  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_92_WIDTH },
7929  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
7930  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_93_WIDTH },
7931  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
7932  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_94_WIDTH },
7933  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
7934  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_95_WIDTH },
7935  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
7936  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_96_WIDTH },
7937  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
7938  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_97_WIDTH },
7939  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
7940  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_98_WIDTH },
7941  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
7942  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_99_WIDTH },
7943  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
7944  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_100_WIDTH },
7945  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
7946  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_101_WIDTH },
7947  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
7948  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_102_WIDTH },
7949  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
7950  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_103_WIDTH },
7951  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
7952  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_104_WIDTH },
7953  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
7954  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_105_WIDTH },
7955  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
7956  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_106_WIDTH },
7957  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
7958  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_107_WIDTH },
7959  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
7960  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_108_WIDTH },
7961  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
7962  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_109_WIDTH },
7963  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
7964  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_110_WIDTH },
7965  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
7966  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_111_WIDTH },
7967  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
7968  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_112_WIDTH },
7969  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
7970  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_113_WIDTH },
7971  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
7972  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_114_WIDTH },
7973  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
7974  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_115_WIDTH },
7975  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
7976  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_116_WIDTH },
7977  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
7978  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_117_WIDTH },
7979  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
7980  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_118_WIDTH },
7981  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
7982  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_119_WIDTH },
7983  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
7984  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_120_WIDTH },
7985  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
7986  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_121_WIDTH },
7987  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
7988  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_122_WIDTH },
7989  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
7990  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_123_WIDTH },
7991  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
7992  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_124_WIDTH },
7993  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
7994  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_125_WIDTH },
7995  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
7996  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_126_WIDTH },
7997  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
7998  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_127_WIDTH },
7999  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
8000  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_128_WIDTH },
8001  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
8002  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_129_WIDTH },
8003  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
8004  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_130_WIDTH },
8005  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
8006  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_131_WIDTH },
8007  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
8008  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_132_WIDTH },
8009  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_133_CHECKER_TYPE,
8010  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_133_WIDTH },
8011  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_134_CHECKER_TYPE,
8012  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_134_WIDTH },
8013  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_135_CHECKER_TYPE,
8014  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_135_WIDTH },
8015  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_136_CHECKER_TYPE,
8016  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_136_WIDTH },
8017  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_137_CHECKER_TYPE,
8018  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_137_WIDTH },
8019  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_138_CHECKER_TYPE,
8020  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_138_WIDTH },
8021  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_139_CHECKER_TYPE,
8022  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_139_WIDTH },
8023  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_140_CHECKER_TYPE,
8024  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_140_WIDTH },
8025  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_141_CHECKER_TYPE,
8026  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_141_WIDTH },
8027  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_142_CHECKER_TYPE,
8028  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_142_WIDTH },
8029  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_143_CHECKER_TYPE,
8030  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_143_WIDTH },
8031  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_144_CHECKER_TYPE,
8032  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_144_WIDTH },
8033  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_145_CHECKER_TYPE,
8034  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_145_WIDTH },
8035  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_146_CHECKER_TYPE,
8036  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_146_WIDTH },
8037  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_147_CHECKER_TYPE,
8038  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_147_WIDTH },
8039  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_148_CHECKER_TYPE,
8040  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_148_WIDTH },
8041  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_149_CHECKER_TYPE,
8042  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_149_WIDTH },
8043  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_150_CHECKER_TYPE,
8044  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_150_WIDTH },
8045  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_151_CHECKER_TYPE,
8046  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_151_WIDTH },
8047  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_152_CHECKER_TYPE,
8048  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_152_WIDTH },
8049  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_153_CHECKER_TYPE,
8050  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_153_WIDTH },
8051  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_154_CHECKER_TYPE,
8052  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_154_WIDTH },
8053  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_155_CHECKER_TYPE,
8054  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_155_WIDTH },
8055  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_156_CHECKER_TYPE,
8056  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_156_WIDTH },
8057  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_157_CHECKER_TYPE,
8058  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_157_WIDTH },
8059  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_158_CHECKER_TYPE,
8060  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_158_WIDTH },
8061  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_159_CHECKER_TYPE,
8062  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_159_WIDTH },
8063  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_160_CHECKER_TYPE,
8064  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_160_WIDTH },
8065  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_161_CHECKER_TYPE,
8066  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_161_WIDTH },
8067  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_162_CHECKER_TYPE,
8068  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_162_WIDTH },
8069  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_163_CHECKER_TYPE,
8070  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_163_WIDTH },
8071  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_164_CHECKER_TYPE,
8072  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_164_WIDTH },
8073  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_165_CHECKER_TYPE,
8074  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_165_WIDTH },
8075  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_166_CHECKER_TYPE,
8076  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_166_WIDTH },
8077  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_167_CHECKER_TYPE,
8078  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_167_WIDTH },
8079  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_168_CHECKER_TYPE,
8080  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_168_WIDTH },
8081  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_169_CHECKER_TYPE,
8082  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_169_WIDTH },
8083  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_170_CHECKER_TYPE,
8084  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_170_WIDTH },
8085  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_171_CHECKER_TYPE,
8086  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_171_WIDTH },
8087  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_172_CHECKER_TYPE,
8088  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_172_WIDTH },
8089  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_173_CHECKER_TYPE,
8090  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_173_WIDTH },
8091  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_174_CHECKER_TYPE,
8092  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_174_WIDTH },
8093  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_175_CHECKER_TYPE,
8094  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_175_WIDTH },
8095  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_176_CHECKER_TYPE,
8096  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_176_WIDTH },
8097  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_177_CHECKER_TYPE,
8098  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_177_WIDTH },
8099  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_178_CHECKER_TYPE,
8100  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_178_WIDTH },
8101  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_179_CHECKER_TYPE,
8102  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_179_WIDTH },
8103  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_180_CHECKER_TYPE,
8104  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_180_WIDTH },
8105  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_181_CHECKER_TYPE,
8106  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_181_WIDTH },
8107  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_182_CHECKER_TYPE,
8108  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_182_WIDTH },
8109  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_183_CHECKER_TYPE,
8110  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_183_WIDTH },
8111  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_184_CHECKER_TYPE,
8112  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_184_WIDTH },
8113  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_185_CHECKER_TYPE,
8114  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_185_WIDTH },
8115  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_186_CHECKER_TYPE,
8116  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_186_WIDTH },
8117  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_187_CHECKER_TYPE,
8118  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_187_WIDTH },
8119  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_188_CHECKER_TYPE,
8120  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_188_WIDTH },
8121  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_189_CHECKER_TYPE,
8122  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_189_WIDTH },
8123  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_190_CHECKER_TYPE,
8124  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_190_WIDTH },
8125  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_191_CHECKER_TYPE,
8126  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_191_WIDTH },
8127  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_192_CHECKER_TYPE,
8128  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_192_WIDTH },
8129  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_193_CHECKER_TYPE,
8130  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_193_WIDTH },
8131  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_194_CHECKER_TYPE,
8132  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_194_WIDTH },
8133  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_195_CHECKER_TYPE,
8134  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_195_WIDTH },
8135  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_196_CHECKER_TYPE,
8136  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_196_WIDTH },
8137  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_197_CHECKER_TYPE,
8138  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_197_WIDTH },
8139  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_198_CHECKER_TYPE,
8140  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_198_WIDTH },
8141  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_199_CHECKER_TYPE,
8142  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_199_WIDTH },
8143  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_200_CHECKER_TYPE,
8144  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_200_WIDTH },
8145  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_201_CHECKER_TYPE,
8146  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_201_WIDTH },
8147  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_202_CHECKER_TYPE,
8148  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_202_WIDTH },
8149  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_203_CHECKER_TYPE,
8150  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_203_WIDTH },
8151  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_204_CHECKER_TYPE,
8152  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_204_WIDTH },
8153  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_205_CHECKER_TYPE,
8154  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_205_WIDTH },
8155  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_206_CHECKER_TYPE,
8156  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_206_WIDTH },
8157  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_207_CHECKER_TYPE,
8158  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_207_WIDTH },
8159  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_208_CHECKER_TYPE,
8160  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_208_WIDTH },
8161  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_209_CHECKER_TYPE,
8162  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_209_WIDTH },
8163  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_210_CHECKER_TYPE,
8164  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_210_WIDTH },
8165  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_211_CHECKER_TYPE,
8166  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_211_WIDTH },
8167  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_212_CHECKER_TYPE,
8168  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_212_WIDTH },
8169  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_213_CHECKER_TYPE,
8170  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_213_WIDTH },
8171  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_214_CHECKER_TYPE,
8172  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_214_WIDTH },
8173  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_215_CHECKER_TYPE,
8174  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_215_WIDTH },
8175  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_216_CHECKER_TYPE,
8176  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_216_WIDTH },
8177  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_217_CHECKER_TYPE,
8178  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_217_WIDTH },
8179  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_218_CHECKER_TYPE,
8180  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_218_WIDTH },
8181  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_219_CHECKER_TYPE,
8182  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_219_WIDTH },
8183  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_220_CHECKER_TYPE,
8184  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_220_WIDTH },
8185  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_221_CHECKER_TYPE,
8186  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_221_WIDTH },
8187  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_222_CHECKER_TYPE,
8188  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_222_WIDTH },
8189  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_223_CHECKER_TYPE,
8190  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_223_WIDTH },
8191  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_224_CHECKER_TYPE,
8192  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_224_WIDTH },
8193  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_225_CHECKER_TYPE,
8194  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_225_WIDTH },
8195  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_226_CHECKER_TYPE,
8196  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_226_WIDTH },
8197  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_227_CHECKER_TYPE,
8198  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_227_WIDTH },
8199  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_228_CHECKER_TYPE,
8200  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_228_WIDTH },
8201  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_229_CHECKER_TYPE,
8202  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_229_WIDTH },
8203  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_230_CHECKER_TYPE,
8204  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_230_WIDTH },
8205  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_231_CHECKER_TYPE,
8206  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_231_WIDTH },
8207  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_232_CHECKER_TYPE,
8208  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_232_WIDTH },
8209  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_233_CHECKER_TYPE,
8210  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_233_WIDTH },
8211  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_234_CHECKER_TYPE,
8212  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_234_WIDTH },
8213  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_235_CHECKER_TYPE,
8214  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_235_WIDTH },
8215  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_236_CHECKER_TYPE,
8216  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_236_WIDTH },
8217  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_237_CHECKER_TYPE,
8218  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_237_WIDTH },
8219  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_238_CHECKER_TYPE,
8220  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_238_WIDTH },
8221  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_239_CHECKER_TYPE,
8222  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_239_WIDTH },
8223  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_240_CHECKER_TYPE,
8224  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_240_WIDTH },
8225  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_241_CHECKER_TYPE,
8226  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_241_WIDTH },
8227  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_242_CHECKER_TYPE,
8228  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_242_WIDTH },
8229  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_243_CHECKER_TYPE,
8230  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_243_WIDTH },
8231  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_244_CHECKER_TYPE,
8232  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_244_WIDTH },
8233  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_245_CHECKER_TYPE,
8234  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_245_WIDTH },
8235  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_246_CHECKER_TYPE,
8236  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_246_WIDTH },
8237  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_247_CHECKER_TYPE,
8238  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_247_WIDTH },
8239  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_248_CHECKER_TYPE,
8240  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_248_WIDTH },
8241  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_249_CHECKER_TYPE,
8242  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_249_WIDTH },
8243  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_250_CHECKER_TYPE,
8244  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_250_WIDTH },
8245  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_251_CHECKER_TYPE,
8246  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_251_WIDTH },
8247  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_252_CHECKER_TYPE,
8248  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_252_WIDTH },
8249  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_253_CHECKER_TYPE,
8250  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_253_WIDTH },
8251  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_254_CHECKER_TYPE,
8252  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_254_WIDTH },
8253  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_255_CHECKER_TYPE,
8254  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_255_WIDTH },
8255 };
8256 
8262 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_MAX_NUM_CHECKERS] =
8263 {
8264  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_0_CHECKER_TYPE,
8265  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_0_WIDTH },
8266  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_1_CHECKER_TYPE,
8267  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_1_WIDTH },
8268  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_2_CHECKER_TYPE,
8269  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_2_WIDTH },
8270  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_3_CHECKER_TYPE,
8271  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_3_WIDTH },
8272  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_4_CHECKER_TYPE,
8273  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_4_WIDTH },
8274  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_5_CHECKER_TYPE,
8275  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_5_WIDTH },
8276  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_6_CHECKER_TYPE,
8277  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_6_WIDTH },
8278  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_7_CHECKER_TYPE,
8279  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_7_WIDTH },
8280  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_8_CHECKER_TYPE,
8281  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_8_WIDTH },
8282  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_9_CHECKER_TYPE,
8283  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_9_WIDTH },
8284  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_10_CHECKER_TYPE,
8285  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_10_WIDTH },
8286  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_11_CHECKER_TYPE,
8287  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_11_WIDTH },
8288  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_12_CHECKER_TYPE,
8289  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_12_WIDTH },
8290  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_13_CHECKER_TYPE,
8291  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_13_WIDTH },
8292  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_14_CHECKER_TYPE,
8293  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_14_WIDTH },
8294  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_15_CHECKER_TYPE,
8295  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_15_WIDTH },
8296  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_16_CHECKER_TYPE,
8297  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_16_WIDTH },
8298  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_17_CHECKER_TYPE,
8299  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_17_WIDTH },
8300  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_18_CHECKER_TYPE,
8301  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_18_WIDTH },
8302  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_19_CHECKER_TYPE,
8303  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_19_WIDTH },
8304  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_20_CHECKER_TYPE,
8305  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_20_WIDTH },
8306  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_21_CHECKER_TYPE,
8307  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_21_WIDTH },
8308  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_22_CHECKER_TYPE,
8309  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_22_WIDTH },
8310  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_23_CHECKER_TYPE,
8311  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_23_WIDTH },
8312  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_24_CHECKER_TYPE,
8313  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_24_WIDTH },
8314  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_25_CHECKER_TYPE,
8315  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_25_WIDTH },
8316  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_26_CHECKER_TYPE,
8317  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_26_WIDTH },
8318  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_27_CHECKER_TYPE,
8319  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_27_WIDTH },
8320  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_28_CHECKER_TYPE,
8321  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_28_WIDTH },
8322  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_29_CHECKER_TYPE,
8323  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_29_WIDTH },
8324  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_30_CHECKER_TYPE,
8325  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_30_WIDTH },
8326  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_31_CHECKER_TYPE,
8327  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_31_WIDTH },
8328  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_32_CHECKER_TYPE,
8329  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_32_WIDTH },
8330  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_33_CHECKER_TYPE,
8331  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_33_WIDTH },
8332  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_34_CHECKER_TYPE,
8333  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_34_WIDTH },
8334  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_35_CHECKER_TYPE,
8335  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_35_WIDTH },
8336  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_36_CHECKER_TYPE,
8337  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_36_WIDTH },
8338  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_37_CHECKER_TYPE,
8339  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_37_WIDTH },
8340  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_38_CHECKER_TYPE,
8341  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_38_WIDTH },
8342  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_39_CHECKER_TYPE,
8343  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_39_WIDTH },
8344  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_40_CHECKER_TYPE,
8345  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_40_WIDTH },
8346  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_41_CHECKER_TYPE,
8347  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_41_WIDTH },
8348  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_42_CHECKER_TYPE,
8349  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_42_WIDTH },
8350  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_43_CHECKER_TYPE,
8351  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_43_WIDTH },
8352  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_44_CHECKER_TYPE,
8353  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_44_WIDTH },
8354  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_45_CHECKER_TYPE,
8355  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_45_WIDTH },
8356  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_46_CHECKER_TYPE,
8357  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_46_WIDTH },
8358  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_47_CHECKER_TYPE,
8359  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_47_WIDTH },
8360  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_48_CHECKER_TYPE,
8361  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_48_WIDTH },
8362  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_49_CHECKER_TYPE,
8363  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_49_WIDTH },
8364  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_50_CHECKER_TYPE,
8365  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_50_WIDTH },
8366  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_51_CHECKER_TYPE,
8367  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_51_WIDTH },
8368  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_52_CHECKER_TYPE,
8369  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_52_WIDTH },
8370  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_53_CHECKER_TYPE,
8371  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_53_WIDTH },
8372  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_54_CHECKER_TYPE,
8373  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_54_WIDTH },
8374  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_55_CHECKER_TYPE,
8375  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_55_WIDTH },
8376  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_56_CHECKER_TYPE,
8377  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_56_WIDTH },
8378 };
8379 
8385 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_MAX_NUM_CHECKERS] =
8386 {
8387  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
8388  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_0_WIDTH },
8389  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
8390  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_1_WIDTH },
8391  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
8392  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_2_WIDTH },
8393  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
8394  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_3_WIDTH },
8395  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
8396  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_4_WIDTH },
8397  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
8398  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_5_WIDTH },
8399  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
8400  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_6_WIDTH },
8401  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
8402  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_7_WIDTH },
8403  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
8404  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_8_WIDTH },
8405  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
8406  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_9_WIDTH },
8407  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
8408  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_10_WIDTH },
8409  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
8410  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_11_WIDTH },
8411  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
8412  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_12_WIDTH },
8413  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
8414  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_13_WIDTH },
8415  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
8416  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_14_WIDTH },
8417  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
8418  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_15_WIDTH },
8419  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
8420  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_16_WIDTH },
8421  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
8422  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_17_WIDTH },
8423  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
8424  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_18_WIDTH },
8425  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
8426  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_19_WIDTH },
8427  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
8428  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_20_WIDTH },
8429  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
8430  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_21_WIDTH },
8431  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
8432  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_22_WIDTH },
8433  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
8434  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_23_WIDTH },
8435  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
8436  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_24_WIDTH },
8437  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
8438  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_25_WIDTH },
8439  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
8440  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_26_WIDTH },
8441  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
8442  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_27_WIDTH },
8443  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
8444  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_28_WIDTH },
8445  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
8446  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_29_WIDTH },
8447  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
8448  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_30_WIDTH },
8449  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
8450  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_31_WIDTH },
8451  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
8452  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_32_WIDTH },
8453  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
8454  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_33_WIDTH },
8455  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
8456  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_34_WIDTH },
8457  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
8458  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_35_WIDTH },
8459  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
8460  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_36_WIDTH },
8461  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
8462  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_37_WIDTH },
8463  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
8464  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_38_WIDTH },
8465  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
8466  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_39_WIDTH },
8467  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
8468  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_40_WIDTH },
8469  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
8470  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_41_WIDTH },
8471  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
8472  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_42_WIDTH },
8473  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
8474  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_43_WIDTH },
8475  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
8476  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_44_WIDTH },
8477  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
8478  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_45_WIDTH },
8479  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
8480  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_46_WIDTH },
8481  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
8482  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_47_WIDTH },
8483  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
8484  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_48_WIDTH },
8485  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
8486  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_49_WIDTH },
8487  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
8488  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_50_WIDTH },
8489  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
8490  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_51_WIDTH },
8491  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
8492  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_52_WIDTH },
8493  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
8494  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_53_WIDTH },
8495  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
8496  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_54_WIDTH },
8497  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
8498  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_55_WIDTH },
8499  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
8500  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_56_WIDTH },
8501  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
8502  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_57_WIDTH },
8503  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
8504  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_58_WIDTH },
8505  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
8506  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_59_WIDTH },
8507  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
8508  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_60_WIDTH },
8509  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
8510  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_61_WIDTH },
8511  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
8512  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_62_WIDTH },
8513  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
8514  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_63_WIDTH },
8515  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
8516  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_64_WIDTH },
8517  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
8518  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_65_WIDTH },
8519  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
8520  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_66_WIDTH },
8521 };
8522 
8528 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
8529 {
8530  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
8531  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
8532  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
8533  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
8534  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
8535  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
8536  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
8537  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
8538  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
8539  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
8540  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
8541  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
8542  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
8543  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
8544  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
8545  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
8546  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
8547  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
8548  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
8549  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
8550  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
8551  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
8552  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
8553  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
8554  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
8555  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
8556  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
8557  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
8558  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
8559  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
8560  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
8561  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
8562  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
8563  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
8564  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
8565  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
8566  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
8567  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
8568  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
8569  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
8570  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
8571  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
8572  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
8573  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
8574  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
8575  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
8576  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
8577  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
8578  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
8579  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
8580  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
8581  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
8582  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
8583  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
8584  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
8585  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
8586  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
8587  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
8588  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
8589  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
8590  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
8591  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
8592  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
8593  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
8594  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
8595  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
8596  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
8597  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
8598  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
8599  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
8600  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
8601  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
8602  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
8603  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
8604  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
8605  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
8606  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
8607  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
8608  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
8609  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
8610  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
8611  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
8612  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
8613  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_41_WIDTH },
8614  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
8615  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_42_WIDTH },
8616  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
8617  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_43_WIDTH },
8618  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
8619  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_44_WIDTH },
8620  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
8621  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_45_WIDTH },
8622  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
8623  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_46_WIDTH },
8624  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
8625  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_47_WIDTH },
8626  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
8627  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_48_WIDTH },
8628  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
8629  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_49_WIDTH },
8630  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
8631  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_50_WIDTH },
8632  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
8633  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_51_WIDTH },
8634  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
8635  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_52_WIDTH },
8636  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
8637  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_53_WIDTH },
8638  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
8639  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_54_WIDTH },
8640  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
8641  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_55_WIDTH },
8642  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
8643  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_56_WIDTH },
8644  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
8645  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_57_WIDTH },
8646  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
8647  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_58_WIDTH },
8648  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
8649  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_59_WIDTH },
8650  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
8651  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_60_WIDTH },
8652  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
8653  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_61_WIDTH },
8654  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
8655  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_62_WIDTH },
8656  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
8657  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_63_WIDTH },
8658  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
8659  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_64_WIDTH },
8660  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
8661  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_65_WIDTH },
8662  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
8663  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_66_WIDTH },
8664  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
8665  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_67_WIDTH },
8666  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
8667  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_68_WIDTH },
8668  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
8669  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_69_WIDTH },
8670  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
8671  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_70_WIDTH },
8672  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
8673  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_71_WIDTH },
8674 };
8675 
8681 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
8682 {
8683  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
8684  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
8685  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
8686  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
8687  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
8688  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
8689  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
8690  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
8691  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
8692  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
8693  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
8694  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
8695  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
8696  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
8697  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
8698  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
8699  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
8700  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
8701  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
8702  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
8703  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
8704  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
8705  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
8706  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
8707  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
8708  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
8709  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
8710  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
8711  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
8712  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
8713  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
8714  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
8715  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
8716  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
8717  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
8718  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
8719  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
8720  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
8721  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
8722  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
8723  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
8724  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
8725  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
8726  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
8727  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
8728  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
8729  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
8730  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
8731  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
8732  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
8733  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
8734  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
8735  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
8736  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
8737  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
8738  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
8739  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
8740  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
8741  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
8742  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
8743  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
8744  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
8745  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
8746  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
8747  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
8748  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
8749  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
8750  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
8751  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
8752  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
8753  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
8754  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
8755  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
8756  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
8757  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
8758  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
8759  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
8760  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
8761  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
8762  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
8763  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
8764  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
8765  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
8766  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
8767  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
8768  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
8769  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
8770  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
8771  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
8772  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
8773  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
8774  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
8775  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
8776  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
8777  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
8778  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
8779  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
8780  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
8781  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
8782  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
8783  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
8784  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
8785  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
8786  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
8787  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
8788  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
8789  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
8790  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
8791  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
8792  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
8793  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
8794  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
8795  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
8796  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
8797  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
8798  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
8799  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
8800  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
8801  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
8802  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
8803  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
8804  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
8805  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
8806  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
8807  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
8808  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
8809  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
8810  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
8811  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
8812  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
8813  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
8814  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
8815  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
8816  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
8817  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
8818  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
8819  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
8820  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
8821  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
8822  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
8823  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
8824  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
8825  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
8826  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
8827  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
8828  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
8829  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
8830  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
8831  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
8832  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_74_WIDTH },
8833  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
8834  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_75_WIDTH },
8835  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
8836  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_76_WIDTH },
8837  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
8838  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_77_WIDTH },
8839  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
8840  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_78_WIDTH },
8841  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
8842  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_79_WIDTH },
8843  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
8844  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_80_WIDTH },
8845  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
8846  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_81_WIDTH },
8847  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
8848  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_82_WIDTH },
8849  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
8850  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_83_WIDTH },
8851  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
8852  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_84_WIDTH },
8853  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
8854  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_85_WIDTH },
8855  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
8856  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_86_WIDTH },
8857  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
8858  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_87_WIDTH },
8859  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
8860  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_88_WIDTH },
8861  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
8862  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_89_WIDTH },
8863  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
8864  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_90_WIDTH },
8865  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
8866  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_91_WIDTH },
8867  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
8868  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_92_WIDTH },
8869  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
8870  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_93_WIDTH },
8871  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
8872  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_94_WIDTH },
8873  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
8874  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_95_WIDTH },
8875  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
8876  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_96_WIDTH },
8877  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
8878  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_97_WIDTH },
8879  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
8880  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_98_WIDTH },
8881  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
8882  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_99_WIDTH },
8883  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
8884  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_100_WIDTH },
8885  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
8886  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_101_WIDTH },
8887  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
8888  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_102_WIDTH },
8889  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
8890  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_103_WIDTH },
8891  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
8892  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_104_WIDTH },
8893  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
8894  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_105_WIDTH },
8895  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
8896  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_106_WIDTH },
8897  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
8898  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_107_WIDTH },
8899  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
8900  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_108_WIDTH },
8901  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
8902  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_109_WIDTH },
8903  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
8904  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_110_WIDTH },
8905  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
8906  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_111_WIDTH },
8907  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
8908  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_112_WIDTH },
8909  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
8910  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_113_WIDTH },
8911  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
8912  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_114_WIDTH },
8913  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
8914  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_115_WIDTH },
8915  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
8916  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_116_WIDTH },
8917  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
8918  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_117_WIDTH },
8919  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
8920  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_118_WIDTH },
8921  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
8922  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_119_WIDTH },
8923  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
8924  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_120_WIDTH },
8925  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
8926  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_121_WIDTH },
8927  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
8928  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_122_WIDTH },
8929  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
8930  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_123_WIDTH },
8931  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
8932  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_124_WIDTH },
8933  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
8934  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_125_WIDTH },
8935  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
8936  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_126_WIDTH },
8937  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
8938  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_127_WIDTH },
8939  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
8940  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_128_WIDTH },
8941  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
8942  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_129_WIDTH },
8943  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
8944  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_130_WIDTH },
8945  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
8946  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_131_WIDTH },
8947 };
8948 
8954 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS] =
8955 {
8956  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
8957  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_0_WIDTH },
8958  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
8959  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_1_WIDTH },
8960  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
8961  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_2_WIDTH },
8962 };
8963 
8969 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_MAX_NUM_CHECKERS] =
8970 {
8971  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
8972  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_0_WIDTH },
8973  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
8974  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_1_WIDTH },
8975  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
8976  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_2_WIDTH },
8977  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
8978  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_3_WIDTH },
8979  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
8980  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_4_WIDTH },
8981  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
8982  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_5_WIDTH },
8983  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
8984  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_6_WIDTH },
8985  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
8986  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_7_WIDTH },
8987  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
8988  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_8_WIDTH },
8989  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
8990  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_9_WIDTH },
8991  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
8992  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_10_WIDTH },
8993  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
8994  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_11_WIDTH },
8995  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
8996  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_12_WIDTH },
8997  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
8998  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_13_WIDTH },
8999  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
9000  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_14_WIDTH },
9001  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
9002  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_15_WIDTH },
9003  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
9004  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_16_WIDTH },
9005  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
9006  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_17_WIDTH },
9007  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
9008  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_18_WIDTH },
9009  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
9010  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_19_WIDTH },
9011  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
9012  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_20_WIDTH },
9013  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
9014  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_21_WIDTH },
9015  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
9016  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_22_WIDTH },
9017  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
9018  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_23_WIDTH },
9019  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
9020  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_24_WIDTH },
9021  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
9022  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_25_WIDTH },
9023  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
9024  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_26_WIDTH },
9025  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
9026  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_27_WIDTH },
9027  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
9028  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_28_WIDTH },
9029  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
9030  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_29_WIDTH },
9031  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
9032  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_30_WIDTH },
9033  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
9034  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_31_WIDTH },
9035  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
9036  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_32_WIDTH },
9037  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
9038  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_33_WIDTH },
9039  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
9040  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_34_WIDTH },
9041  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
9042  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_35_WIDTH },
9043  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
9044  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_36_WIDTH },
9045  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
9046  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_37_WIDTH },
9047  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
9048  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_38_WIDTH },
9049  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
9050  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_39_WIDTH },
9051  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
9052  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_40_WIDTH },
9053  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
9054  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_41_WIDTH },
9055  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
9056  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_42_WIDTH },
9057  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
9058  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_43_WIDTH },
9059  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
9060  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_44_WIDTH },
9061  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
9062  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_45_WIDTH },
9063  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
9064  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_46_WIDTH },
9065  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
9066  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_47_WIDTH },
9067  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
9068  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_48_WIDTH },
9069  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
9070  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_49_WIDTH },
9071  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
9072  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_50_WIDTH },
9073  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
9074  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_51_WIDTH },
9075  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
9076  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_52_WIDTH },
9077  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
9078  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_53_WIDTH },
9079  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
9080  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_54_WIDTH },
9081  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
9082  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_55_WIDTH },
9083  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
9084  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_56_WIDTH },
9085  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
9086  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_57_WIDTH },
9087  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
9088  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_58_WIDTH },
9089  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
9090  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_59_WIDTH },
9091  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
9092  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_60_WIDTH },
9093  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
9094  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_61_WIDTH },
9095  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
9096  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_62_WIDTH },
9097 };
9098 
9104 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS] =
9105 {
9106  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
9107  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_0_WIDTH },
9108  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
9109  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_1_WIDTH },
9110  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
9111  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_2_WIDTH },
9112  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
9113  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_3_WIDTH },
9114  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
9115  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_4_WIDTH },
9116  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
9117  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_5_WIDTH },
9118  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
9119  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_6_WIDTH },
9120  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
9121  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_7_WIDTH },
9122  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
9123  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_8_WIDTH },
9124  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
9125  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_9_WIDTH },
9126  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
9127  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_10_WIDTH },
9128  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
9129  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_11_WIDTH },
9130  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
9131  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_12_WIDTH },
9132  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
9133  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_13_WIDTH },
9134  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
9135  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_14_WIDTH },
9136  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
9137  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_15_WIDTH },
9138  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
9139  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_16_WIDTH },
9140  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
9141  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_17_WIDTH },
9142  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
9143  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_18_WIDTH },
9144  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
9145  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_19_WIDTH },
9146  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
9147  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_20_WIDTH },
9148  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
9149  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_21_WIDTH },
9150  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
9151  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_22_WIDTH },
9152  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
9153  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_23_WIDTH },
9154  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
9155  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_24_WIDTH },
9156  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
9157  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_25_WIDTH },
9158  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
9159  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_26_WIDTH },
9160  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
9161  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_27_WIDTH },
9162  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
9163  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_28_WIDTH },
9164  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
9165  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_29_WIDTH },
9166  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
9167  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_30_WIDTH },
9168  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
9169  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_31_WIDTH },
9170  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
9171  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_32_WIDTH },
9172 };
9173 
9179 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS] =
9180 {
9181  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
9182  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_0_WIDTH },
9183  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
9184  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_1_WIDTH },
9185  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
9186  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_2_WIDTH },
9187  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
9188  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_3_WIDTH },
9189  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
9190  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_4_WIDTH },
9191  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
9192  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_5_WIDTH },
9193  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
9194  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_6_WIDTH },
9195  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
9196  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_7_WIDTH },
9197  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
9198  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_8_WIDTH },
9199  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
9200  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_9_WIDTH },
9201  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
9202  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_10_WIDTH },
9203  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
9204  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_11_WIDTH },
9205  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
9206  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_12_WIDTH },
9207  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
9208  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_13_WIDTH },
9209  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
9210  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_14_WIDTH },
9211  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
9212  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_15_WIDTH },
9213  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
9214  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_16_WIDTH },
9215  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
9216  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_17_WIDTH },
9217  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
9218  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_18_WIDTH },
9219  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
9220  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_19_WIDTH },
9221  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
9222  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_20_WIDTH },
9223  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
9224  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_21_WIDTH },
9225  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
9226  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_22_WIDTH },
9227  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
9228  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_23_WIDTH },
9229  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
9230  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_24_WIDTH },
9231  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
9232  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_25_WIDTH },
9233  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
9234  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_26_WIDTH },
9235  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
9236  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_27_WIDTH },
9237  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
9238  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_28_WIDTH },
9239  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
9240  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_29_WIDTH },
9241  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
9242  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_30_WIDTH },
9243  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
9244  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_31_WIDTH },
9245  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
9246  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_32_WIDTH },
9247 };
9248 
9254 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS] =
9255 {
9256  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
9257  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_0_WIDTH },
9258  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
9259  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_1_WIDTH },
9260  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
9261  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_2_WIDTH },
9262  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
9263  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_3_WIDTH },
9264  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
9265  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_4_WIDTH },
9266  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
9267  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_5_WIDTH },
9268  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
9269  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_6_WIDTH },
9270  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
9271  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_7_WIDTH },
9272  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
9273  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_8_WIDTH },
9274  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
9275  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_9_WIDTH },
9276  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
9277  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_10_WIDTH },
9278  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
9279  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_11_WIDTH },
9280  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
9281  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_12_WIDTH },
9282  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
9283  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_13_WIDTH },
9284  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
9285  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_14_WIDTH },
9286  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
9287  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_15_WIDTH },
9288  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
9289  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_16_WIDTH },
9290  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
9291  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_17_WIDTH },
9292  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
9293  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_18_WIDTH },
9294  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
9295  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_19_WIDTH },
9296  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
9297  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_20_WIDTH },
9298  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
9299  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_21_WIDTH },
9300  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
9301  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_22_WIDTH },
9302  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
9303  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_23_WIDTH },
9304  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
9305  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_24_WIDTH },
9306  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
9307  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_25_WIDTH },
9308  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
9309  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_26_WIDTH },
9310  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
9311  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_27_WIDTH },
9312  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
9313  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_28_WIDTH },
9314  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
9315  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_29_WIDTH },
9316 };
9317 
9323 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS] =
9324 {
9325  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
9326  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_0_WIDTH },
9327  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
9328  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_1_WIDTH },
9329  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
9330  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_2_WIDTH },
9331  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
9332  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_3_WIDTH },
9333  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
9334  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_4_WIDTH },
9335  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
9336  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_5_WIDTH },
9337  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
9338  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_6_WIDTH },
9339  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
9340  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_7_WIDTH },
9341  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
9342  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_8_WIDTH },
9343  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
9344  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_9_WIDTH },
9345  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
9346  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_10_WIDTH },
9347  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
9348  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_11_WIDTH },
9349  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
9350  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_12_WIDTH },
9351  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
9352  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_13_WIDTH },
9353  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
9354  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_14_WIDTH },
9355  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
9356  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_15_WIDTH },
9357  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
9358  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_16_WIDTH },
9359  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
9360  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_17_WIDTH },
9361  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
9362  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_18_WIDTH },
9363  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
9364  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_19_WIDTH },
9365  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
9366  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_20_WIDTH },
9367  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
9368  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_21_WIDTH },
9369  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
9370  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_22_WIDTH },
9371  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
9372  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_23_WIDTH },
9373  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
9374  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_24_WIDTH },
9375  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
9376  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_25_WIDTH },
9377  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
9378  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_26_WIDTH },
9379  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
9380  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_27_WIDTH },
9381  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
9382  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_28_WIDTH },
9383  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
9384  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_29_WIDTH },
9385 };
9386 
9392 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
9393 {
9394  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
9395  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
9396  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
9397  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
9398  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
9399  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
9400  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
9401  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
9402  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
9403  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
9404  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
9405  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_5_WIDTH },
9406  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
9407  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_6_WIDTH },
9408  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
9409  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_7_WIDTH },
9410  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
9411  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_8_WIDTH },
9412  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
9413  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_9_WIDTH },
9414  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
9415  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_10_WIDTH },
9416  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
9417  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_11_WIDTH },
9418  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
9419  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_12_WIDTH },
9420  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
9421  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_13_WIDTH },
9422  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
9423  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_14_WIDTH },
9424  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
9425  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_15_WIDTH },
9426  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
9427  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_16_WIDTH },
9428  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
9429  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_17_WIDTH },
9430  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
9431  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_18_WIDTH },
9432  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
9433  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_19_WIDTH },
9434  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
9435  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_20_WIDTH },
9436  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
9437  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_21_WIDTH },
9438  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
9439  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_22_WIDTH },
9440  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
9441  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_23_WIDTH },
9442  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
9443  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_24_WIDTH },
9444  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
9445  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_25_WIDTH },
9446  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
9447  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_26_WIDTH },
9448  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
9449  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_27_WIDTH },
9450  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
9451  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_28_WIDTH },
9452  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
9453  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_29_WIDTH },
9454  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
9455  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_30_WIDTH },
9456  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
9457  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_31_WIDTH },
9458  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
9459  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_32_WIDTH },
9460  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
9461  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_33_WIDTH },
9462  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
9463  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_34_WIDTH },
9464  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
9465  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_35_WIDTH },
9466  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
9467  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_36_WIDTH },
9468  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
9469  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_37_WIDTH },
9470  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
9471  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_38_WIDTH },
9472  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
9473  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_39_WIDTH },
9474  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
9475  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_40_WIDTH },
9476  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
9477  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_41_WIDTH },
9478  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
9479  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_42_WIDTH },
9480  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
9481  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_43_WIDTH },
9482  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
9483  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_44_WIDTH },
9484  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
9485  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_45_WIDTH },
9486  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
9487  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_46_WIDTH },
9488  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
9489  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_47_WIDTH },
9490  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
9491  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_48_WIDTH },
9492  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
9493  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_49_WIDTH },
9494  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
9495  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_50_WIDTH },
9496  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
9497  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_51_WIDTH },
9498  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
9499  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_52_WIDTH },
9500  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
9501  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_53_WIDTH },
9502  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
9503  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_54_WIDTH },
9504  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
9505  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_55_WIDTH },
9506  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
9507  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_56_WIDTH },
9508  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
9509  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_57_WIDTH },
9510  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
9511  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_58_WIDTH },
9512  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
9513  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_59_WIDTH },
9514  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
9515  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_60_WIDTH },
9516  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
9517  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_61_WIDTH },
9518  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
9519  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_62_WIDTH },
9520  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
9521  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_63_WIDTH },
9522  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
9523  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_64_WIDTH },
9524  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
9525  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_65_WIDTH },
9526  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
9527  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_66_WIDTH },
9528  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
9529  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_67_WIDTH },
9530  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
9531  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_68_WIDTH },
9532  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
9533  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_69_WIDTH },
9534  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
9535  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_70_WIDTH },
9536  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
9537  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_71_WIDTH },
9538  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
9539  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_72_WIDTH },
9540  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
9541  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_73_WIDTH },
9542  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
9543  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_74_WIDTH },
9544  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
9545  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_75_WIDTH },
9546  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
9547  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_76_WIDTH },
9548  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
9549  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_77_WIDTH },
9550  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
9551  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_78_WIDTH },
9552  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
9553  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_79_WIDTH },
9554  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
9555  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_80_WIDTH },
9556  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
9557  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_81_WIDTH },
9558  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
9559  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_82_WIDTH },
9560  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
9561  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_83_WIDTH },
9562  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
9563  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_84_WIDTH },
9564  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
9565  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_85_WIDTH },
9566  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
9567  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_86_WIDTH },
9568  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
9569  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_87_WIDTH },
9570  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
9571  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_88_WIDTH },
9572  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
9573  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_89_WIDTH },
9574  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
9575  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_90_WIDTH },
9576  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
9577  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_91_WIDTH },
9578  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
9579  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_92_WIDTH },
9580  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
9581  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_93_WIDTH },
9582  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
9583  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_94_WIDTH },
9584  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
9585  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_95_WIDTH },
9586  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
9587  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_96_WIDTH },
9588  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
9589  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_97_WIDTH },
9590  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
9591  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_98_WIDTH },
9592  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
9593  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_99_WIDTH },
9594  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
9595  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_100_WIDTH },
9596 };
9597 
9603 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
9604 {
9605  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
9606  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
9607  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
9608  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
9609  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
9610  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
9611  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
9612  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
9613  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
9614  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
9615  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
9616  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_5_WIDTH },
9617  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
9618  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_6_WIDTH },
9619  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
9620  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_7_WIDTH },
9621  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
9622  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_8_WIDTH },
9623  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
9624  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_9_WIDTH },
9625  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
9626  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_10_WIDTH },
9627  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
9628  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_11_WIDTH },
9629  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
9630  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_12_WIDTH },
9631  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
9632  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_13_WIDTH },
9633  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
9634  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_14_WIDTH },
9635  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
9636  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_15_WIDTH },
9637  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
9638  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_16_WIDTH },
9639  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
9640  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_17_WIDTH },
9641  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
9642  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_18_WIDTH },
9643  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
9644  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_19_WIDTH },
9645  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
9646  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_20_WIDTH },
9647  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
9648  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_21_WIDTH },
9649  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
9650  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_22_WIDTH },
9651  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
9652  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_23_WIDTH },
9653  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
9654  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_24_WIDTH },
9655  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
9656  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_25_WIDTH },
9657  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
9658  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_26_WIDTH },
9659  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
9660  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_27_WIDTH },
9661  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
9662  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_28_WIDTH },
9663  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
9664  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_29_WIDTH },
9665  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
9666  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_30_WIDTH },
9667  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
9668  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_31_WIDTH },
9669  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
9670  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_32_WIDTH },
9671  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
9672  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_33_WIDTH },
9673  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
9674  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_34_WIDTH },
9675  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
9676  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_35_WIDTH },
9677  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
9678  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_36_WIDTH },
9679  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
9680  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_37_WIDTH },
9681  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
9682  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_38_WIDTH },
9683  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
9684  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_39_WIDTH },
9685  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
9686  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_40_WIDTH },
9687  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
9688  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_41_WIDTH },
9689  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
9690  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_42_WIDTH },
9691  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
9692  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_43_WIDTH },
9693  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
9694  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_44_WIDTH },
9695  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
9696  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_45_WIDTH },
9697  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
9698  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_46_WIDTH },
9699  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
9700  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_47_WIDTH },
9701  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
9702  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_48_WIDTH },
9703  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
9704  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_49_WIDTH },
9705  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
9706  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_50_WIDTH },
9707  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
9708  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_51_WIDTH },
9709  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
9710  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_52_WIDTH },
9711  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
9712  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_53_WIDTH },
9713  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
9714  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_54_WIDTH },
9715  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
9716  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_55_WIDTH },
9717  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
9718  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_56_WIDTH },
9719  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
9720  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_57_WIDTH },
9721  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
9722  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_58_WIDTH },
9723  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
9724  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_59_WIDTH },
9725  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
9726  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_60_WIDTH },
9727  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
9728  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_61_WIDTH },
9729  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
9730  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_62_WIDTH },
9731  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
9732  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_63_WIDTH },
9733  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
9734  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_64_WIDTH },
9735  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
9736  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_65_WIDTH },
9737  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
9738  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_66_WIDTH },
9739  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
9740  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_67_WIDTH },
9741  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
9742  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_68_WIDTH },
9743  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
9744  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_69_WIDTH },
9745  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
9746  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_70_WIDTH },
9747  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
9748  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_71_WIDTH },
9749  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
9750  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_72_WIDTH },
9751  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
9752  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_73_WIDTH },
9753  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
9754  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_74_WIDTH },
9755  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
9756  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_75_WIDTH },
9757  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
9758  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_76_WIDTH },
9759  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
9760  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_77_WIDTH },
9761  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
9762  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_78_WIDTH },
9763  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
9764  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_79_WIDTH },
9765  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
9766  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_80_WIDTH },
9767  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
9768  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_81_WIDTH },
9769  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
9770  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_82_WIDTH },
9771  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
9772  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_83_WIDTH },
9773  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
9774  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_84_WIDTH },
9775  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
9776  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_85_WIDTH },
9777  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
9778  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_86_WIDTH },
9779  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
9780  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_87_WIDTH },
9781  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
9782  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_88_WIDTH },
9783  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
9784  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_89_WIDTH },
9785  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
9786  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_90_WIDTH },
9787  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
9788  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_91_WIDTH },
9789  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
9790  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_92_WIDTH },
9791  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
9792  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_93_WIDTH },
9793  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
9794  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_94_WIDTH },
9795  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
9796  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_95_WIDTH },
9797  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
9798  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_96_WIDTH },
9799  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
9800  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_97_WIDTH },
9801  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
9802  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_98_WIDTH },
9803  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
9804  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_99_WIDTH },
9805  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
9806  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_100_WIDTH },
9807 };
9808 
9814 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS] =
9815 {
9816  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
9817  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_0_WIDTH },
9818  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
9819  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_1_WIDTH },
9820  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
9821  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_2_WIDTH },
9822  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
9823  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_3_WIDTH },
9824  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
9825  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_4_WIDTH },
9826  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
9827  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_5_WIDTH },
9828  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
9829  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_6_WIDTH },
9830  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
9831  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_7_WIDTH },
9832  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
9833  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_8_WIDTH },
9834  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
9835  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_9_WIDTH },
9836  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
9837  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_10_WIDTH },
9838  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
9839  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_11_WIDTH },
9840  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
9841  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_12_WIDTH },
9842  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
9843  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_13_WIDTH },
9844  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
9845  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_14_WIDTH },
9846  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
9847  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_15_WIDTH },
9848  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
9849  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_16_WIDTH },
9850  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
9851  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_17_WIDTH },
9852  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
9853  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_18_WIDTH },
9854  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
9855  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_19_WIDTH },
9856  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
9857  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_20_WIDTH },
9858  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
9859  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_21_WIDTH },
9860  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
9861  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_22_WIDTH },
9862  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
9863  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_23_WIDTH },
9864  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
9865  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_24_WIDTH },
9866  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
9867  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_25_WIDTH },
9868  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
9869  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_26_WIDTH },
9870  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
9871  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_27_WIDTH },
9872  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
9873  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_28_WIDTH },
9874  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
9875  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_29_WIDTH },
9876  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
9877  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_30_WIDTH },
9878  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
9879  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_31_WIDTH },
9880  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
9881  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_32_WIDTH },
9882  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
9883  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_33_WIDTH },
9884  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
9885  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_34_WIDTH },
9886 };
9887 
9893 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_MAX_NUM_CHECKERS] =
9894 {
9895  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
9896  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_0_WIDTH },
9897  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
9898  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_1_WIDTH },
9899  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
9900  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_2_WIDTH },
9901  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
9902  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_3_WIDTH },
9903  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
9904  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_4_WIDTH },
9905  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
9906  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_5_WIDTH },
9907  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
9908  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_6_WIDTH },
9909  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
9910  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_7_WIDTH },
9911  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
9912  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_8_WIDTH },
9913  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
9914  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_9_WIDTH },
9915  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
9916  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_10_WIDTH },
9917  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
9918  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_11_WIDTH },
9919  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
9920  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_12_WIDTH },
9921  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
9922  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_13_WIDTH },
9923  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
9924  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_14_WIDTH },
9925  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
9926  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_15_WIDTH },
9927  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
9928  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_16_WIDTH },
9929  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
9930  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_17_WIDTH },
9931  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
9932  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_18_WIDTH },
9933  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
9934  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_19_WIDTH },
9935  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
9936  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_20_WIDTH },
9937  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
9938  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_21_WIDTH },
9939  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
9940  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_22_WIDTH },
9941  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
9942  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_23_WIDTH },
9943  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
9944  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_24_WIDTH },
9945  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
9946  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_25_WIDTH },
9947  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
9948  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_26_WIDTH },
9949  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
9950  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_27_WIDTH },
9951  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
9952  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_28_WIDTH },
9953  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
9954  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_29_WIDTH },
9955  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
9956  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_30_WIDTH },
9957  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
9958  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_31_WIDTH },
9959  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
9960  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_32_WIDTH },
9961  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
9962  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_33_WIDTH },
9963  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
9964  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_34_WIDTH },
9965 };
9966 
9972 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS] =
9973 {
9974  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
9975  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_0_WIDTH },
9976  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
9977  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_1_WIDTH },
9978  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
9979  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_2_WIDTH },
9980  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
9981  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_3_WIDTH },
9982  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
9983  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_4_WIDTH },
9984  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
9985  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_5_WIDTH },
9986  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
9987  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_6_WIDTH },
9988  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
9989  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_7_WIDTH },
9990  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
9991  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_8_WIDTH },
9992  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
9993  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_9_WIDTH },
9994  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
9995  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_10_WIDTH },
9996  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
9997  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_11_WIDTH },
9998  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
9999  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_12_WIDTH },
10000  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
10001  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_13_WIDTH },
10002  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
10003  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_14_WIDTH },
10004  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
10005  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_15_WIDTH },
10006  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
10007  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_16_WIDTH },
10008  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
10009  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_17_WIDTH },
10010  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
10011  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_18_WIDTH },
10012  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
10013  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_19_WIDTH },
10014  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
10015  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_20_WIDTH },
10016  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
10017  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_21_WIDTH },
10018  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
10019  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_22_WIDTH },
10020  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
10021  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_23_WIDTH },
10022  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
10023  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_24_WIDTH },
10024  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
10025  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_25_WIDTH },
10026  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
10027  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_26_WIDTH },
10028  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
10029  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_27_WIDTH },
10030  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
10031  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_28_WIDTH },
10032  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
10033  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_29_WIDTH },
10034  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
10035  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_30_WIDTH },
10036  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
10037  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_31_WIDTH },
10038  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
10039  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_32_WIDTH },
10040  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
10041  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_33_WIDTH },
10042  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
10043  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_34_WIDTH },
10044 };
10045 
10051 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_MAX_NUM_CHECKERS] =
10052 {
10053  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
10054  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_GROUP_0_WIDTH },
10055  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
10056  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_GROUP_1_WIDTH },
10057 };
10058 
10064 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_MAX_NUM_CHECKERS] =
10065 {
10066  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
10067  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_GROUP_0_WIDTH },
10068  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
10069  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_GROUP_1_WIDTH },
10070 };
10071 
10077 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_MAX_NUM_CHECKERS] =
10078 {
10079  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
10080  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_GROUP_0_WIDTH },
10081  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
10082  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_GROUP_1_WIDTH },
10083 };
10084 
10090 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS] =
10091 {
10092  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
10093  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_0_WIDTH },
10094  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
10095  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_1_WIDTH },
10096  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
10097  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_2_WIDTH },
10098  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
10099  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_3_WIDTH },
10100  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
10101  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_4_WIDTH },
10102  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
10103  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_5_WIDTH },
10104  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
10105  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_6_WIDTH },
10106  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
10107  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_7_WIDTH },
10108  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
10109  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_8_WIDTH },
10110  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
10111  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_9_WIDTH },
10112  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
10113  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_10_WIDTH },
10114  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
10115  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_11_WIDTH },
10116  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
10117  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_12_WIDTH },
10118  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
10119  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_13_WIDTH },
10120  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
10121  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_14_WIDTH },
10122  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
10123  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_15_WIDTH },
10124  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
10125  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_16_WIDTH },
10126  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
10127  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_17_WIDTH },
10128  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
10129  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_18_WIDTH },
10130  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
10131  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_19_WIDTH },
10132  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
10133  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_20_WIDTH },
10134  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
10135  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_21_WIDTH },
10136  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
10137  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_22_WIDTH },
10138  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
10139  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_23_WIDTH },
10140  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
10141  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_24_WIDTH },
10142  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
10143  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_25_WIDTH },
10144  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
10145  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_26_WIDTH },
10146  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
10147  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_27_WIDTH },
10148  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
10149  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_28_WIDTH },
10150  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
10151  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_29_WIDTH },
10152  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
10153  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_30_WIDTH },
10154  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
10155  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_31_WIDTH },
10156  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
10157  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_32_WIDTH },
10158  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
10159  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_33_WIDTH },
10160  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
10161  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_34_WIDTH },
10162 };
10163 
10169 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_MAX_NUM_CHECKERS] =
10170 {
10171  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
10172  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_GROUP_0_WIDTH },
10173  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
10174  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_GROUP_1_WIDTH },
10175  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
10176  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_GROUP_2_WIDTH },
10177 };
10178 
10184 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
10185 {
10186  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
10187  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
10188  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
10189  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
10190  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
10191  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
10192  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
10193  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
10194  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
10195  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
10196  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
10197  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
10198  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
10199  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
10200  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
10201  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
10202  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
10203  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
10204  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
10205  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
10206  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
10207  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
10208  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
10209  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
10210  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
10211  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
10212  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
10213  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
10214  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
10215  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
10216  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
10217  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
10218  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
10219  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
10220  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
10221  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
10222  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
10223  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
10224  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
10225  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
10226  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
10227  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
10228  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
10229  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
10230  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
10231  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
10232  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
10233  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
10234  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
10235  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
10236  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
10237  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
10238  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
10239  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
10240  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
10241  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
10242  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
10243  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
10244  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
10245  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
10246  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
10247  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
10248  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
10249  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
10250  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
10251  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
10252  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
10253  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
10254  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
10255  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
10256  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
10257  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
10258  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
10259  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
10260  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
10261  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
10262  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
10263  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
10264  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
10265  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
10266  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
10267  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
10268  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
10269  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
10270  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
10271  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
10272  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
10273  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
10274  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
10275  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
10276  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
10277  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
10278  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
10279  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
10280  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
10281  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
10282  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
10283  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
10284  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
10285  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
10286  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
10287  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
10288  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
10289  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
10290  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
10291  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
10292  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
10293  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
10294  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
10295  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
10296  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
10297  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
10298  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
10299  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
10300  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
10301  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
10302  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
10303  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
10304  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
10305  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
10306  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
10307  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
10308  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
10309  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
10310  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
10311  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
10312  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
10313  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
10314  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
10315  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
10316  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
10317  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
10318  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
10319  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
10320  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
10321  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
10322  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
10323  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
10324  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
10325  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
10326  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
10327  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
10328  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
10329  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
10330  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
10331  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
10332  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
10333  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
10334  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
10335  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_74_WIDTH },
10336  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
10337  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_75_WIDTH },
10338  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
10339  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_76_WIDTH },
10340  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
10341  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_77_WIDTH },
10342  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
10343  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_78_WIDTH },
10344  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
10345  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_79_WIDTH },
10346  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
10347  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_80_WIDTH },
10348  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
10349  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_81_WIDTH },
10350  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
10351  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_82_WIDTH },
10352  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
10353  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_83_WIDTH },
10354  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
10355  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_84_WIDTH },
10356  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
10357  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_85_WIDTH },
10358  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
10359  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_86_WIDTH },
10360  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
10361  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_87_WIDTH },
10362  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
10363  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_88_WIDTH },
10364  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
10365  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_89_WIDTH },
10366  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
10367  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_90_WIDTH },
10368  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
10369  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_91_WIDTH },
10370  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
10371  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_92_WIDTH },
10372  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
10373  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_93_WIDTH },
10374  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
10375  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_94_WIDTH },
10376  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
10377  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_95_WIDTH },
10378  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
10379  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_96_WIDTH },
10380  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
10381  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_97_WIDTH },
10382  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
10383  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_98_WIDTH },
10384  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
10385  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_99_WIDTH },
10386  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
10387  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_100_WIDTH },
10388  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
10389  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_101_WIDTH },
10390  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
10391  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_102_WIDTH },
10392  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
10393  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_103_WIDTH },
10394  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
10395  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_104_WIDTH },
10396  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
10397  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_105_WIDTH },
10398 };
10399 
10405 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
10406 {
10407  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
10408  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
10409  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
10410  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
10411  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
10412  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
10413  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
10414  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
10415  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
10416  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
10417  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
10418  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
10419  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
10420  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
10421  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
10422  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
10423  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
10424  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
10425  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
10426  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
10427  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
10428  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
10429  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
10430  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
10431  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
10432  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
10433  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
10434  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
10435  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
10436  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
10437  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
10438  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
10439  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
10440  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
10441  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
10442  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
10443  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
10444  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
10445  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
10446  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
10447  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
10448  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
10449  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
10450  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
10451  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
10452  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
10453  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
10454  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
10455  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
10456  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
10457  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
10458  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
10459  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
10460  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
10461  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
10462  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
10463  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
10464  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
10465  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
10466  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
10467  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
10468  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
10469  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
10470  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
10471  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
10472  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
10473  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
10474  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
10475  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
10476  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
10477  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
10478  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
10479  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
10480  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
10481  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
10482  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
10483  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
10484  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
10485  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
10486  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
10487  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
10488  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
10489  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
10490  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
10491  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
10492  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
10493  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
10494  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
10495  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
10496  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
10497  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
10498  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
10499  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
10500  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
10501  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
10502  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
10503  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
10504  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
10505  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
10506  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
10507  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
10508  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
10509  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
10510  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
10511  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
10512  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
10513  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
10514  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
10515  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
10516  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
10517  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
10518  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
10519  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
10520  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
10521  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
10522  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
10523  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
10524  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
10525  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
10526  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
10527  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
10528  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
10529  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
10530  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
10531  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
10532  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
10533  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
10534  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
10535  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
10536  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
10537  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
10538  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
10539  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
10540  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
10541  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
10542  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
10543  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
10544  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
10545  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
10546  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
10547  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
10548  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
10549  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
10550  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
10551  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
10552  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
10553  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
10554  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
10555  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
10556  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_74_WIDTH },
10557  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
10558  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_75_WIDTH },
10559  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
10560  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_76_WIDTH },
10561  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
10562  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_77_WIDTH },
10563  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
10564  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_78_WIDTH },
10565  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
10566  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_79_WIDTH },
10567  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
10568  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_80_WIDTH },
10569  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
10570  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_81_WIDTH },
10571  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
10572  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_82_WIDTH },
10573  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
10574  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_83_WIDTH },
10575  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
10576  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_84_WIDTH },
10577  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
10578  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_85_WIDTH },
10579  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
10580  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_86_WIDTH },
10581  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
10582  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_87_WIDTH },
10583  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
10584  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_88_WIDTH },
10585  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
10586  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_89_WIDTH },
10587  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
10588  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_90_WIDTH },
10589  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
10590  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_91_WIDTH },
10591  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
10592  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_92_WIDTH },
10593  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
10594  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_93_WIDTH },
10595  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
10596  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_94_WIDTH },
10597  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
10598  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_95_WIDTH },
10599  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
10600  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_96_WIDTH },
10601  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
10602  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_97_WIDTH },
10603  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
10604  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_98_WIDTH },
10605  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
10606  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_99_WIDTH },
10607  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
10608  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_100_WIDTH },
10609  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
10610  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_101_WIDTH },
10611  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
10612  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_102_WIDTH },
10613 };
10614 
10620 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
10621 {
10622  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
10623  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
10624  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
10625  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
10626  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
10627  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
10628  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
10629  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
10630  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
10631  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
10632  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
10633  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
10634  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
10635  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
10636  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
10637  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
10638  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
10639  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
10640  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
10641  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
10642  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
10643  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
10644  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
10645  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
10646  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
10647  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
10648  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
10649  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
10650  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
10651  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
10652  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
10653  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
10654  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
10655  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
10656  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
10657  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
10658  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
10659  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
10660  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
10661  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
10662  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
10663  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
10664  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
10665  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
10666  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
10667  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
10668  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
10669  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
10670  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
10671  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
10672  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
10673  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
10674  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
10675  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
10676  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
10677  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
10678  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
10679  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
10680  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
10681  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
10682  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
10683  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
10684  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
10685  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
10686  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
10687  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
10688  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
10689  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
10690  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
10691  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
10692  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
10693  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
10694  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
10695  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
10696  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
10697  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
10698  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
10699  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
10700  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
10701  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
10702  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
10703  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
10704  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
10705  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
10706  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
10707  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
10708  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
10709  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
10710  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
10711  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
10712  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
10713  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
10714  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
10715  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
10716  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
10717  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
10718  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
10719  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
10720  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
10721  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
10722  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
10723  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
10724  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
10725  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
10726  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
10727  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
10728  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
10729  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
10730  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
10731  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
10732  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
10733  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
10734  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
10735  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
10736  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
10737  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
10738  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
10739  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
10740  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
10741  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
10742  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
10743  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
10744  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
10745  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
10746  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
10747  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
10748  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
10749  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
10750  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
10751  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
10752  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
10753  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
10754  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
10755  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
10756  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
10757  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
10758  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
10759  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
10760  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
10761  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
10762  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
10763  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
10764  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
10765  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
10766  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
10767  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
10768  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
10769  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
10770  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
10771  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_74_WIDTH },
10772  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
10773  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_75_WIDTH },
10774  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
10775  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_76_WIDTH },
10776  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
10777  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_77_WIDTH },
10778  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
10779  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_78_WIDTH },
10780  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
10781  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_79_WIDTH },
10782  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
10783  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_80_WIDTH },
10784  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
10785  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_81_WIDTH },
10786  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
10787  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_82_WIDTH },
10788  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
10789  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_83_WIDTH },
10790  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
10791  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_84_WIDTH },
10792  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
10793  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_85_WIDTH },
10794  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
10795  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_86_WIDTH },
10796  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
10797  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_87_WIDTH },
10798  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
10799  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_88_WIDTH },
10800  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
10801  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_89_WIDTH },
10802  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
10803  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_90_WIDTH },
10804  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
10805  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_91_WIDTH },
10806  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
10807  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_92_WIDTH },
10808  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
10809  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_93_WIDTH },
10810  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
10811  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_94_WIDTH },
10812  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
10813  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_95_WIDTH },
10814  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
10815  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_96_WIDTH },
10816  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
10817  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_97_WIDTH },
10818  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
10819  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_98_WIDTH },
10820  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
10821  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_99_WIDTH },
10822  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
10823  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_100_WIDTH },
10824  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
10825  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_101_WIDTH },
10826  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
10827  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_102_WIDTH },
10828  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
10829  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_103_WIDTH },
10830  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
10831  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_104_WIDTH },
10832  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
10833  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_105_WIDTH },
10834  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
10835  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_106_WIDTH },
10836  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
10837  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_107_WIDTH },
10838  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
10839  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_108_WIDTH },
10840  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
10841  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_109_WIDTH },
10842  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
10843  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_110_WIDTH },
10844  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
10845  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_111_WIDTH },
10846  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
10847  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_112_WIDTH },
10848  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
10849  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_113_WIDTH },
10850  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
10851  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_114_WIDTH },
10852  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
10853  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_115_WIDTH },
10854  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
10855  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_116_WIDTH },
10856  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
10857  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_117_WIDTH },
10858  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
10859  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_118_WIDTH },
10860  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
10861  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_119_WIDTH },
10862  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
10863  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_120_WIDTH },
10864  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
10865  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_121_WIDTH },
10866  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
10867  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_122_WIDTH },
10868  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
10869  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_123_WIDTH },
10870  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
10871  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_124_WIDTH },
10872  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
10873  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_125_WIDTH },
10874  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
10875  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_126_WIDTH },
10876  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
10877  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_127_WIDTH },
10878  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
10879  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_128_WIDTH },
10880  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
10881  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_129_WIDTH },
10882  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
10883  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_130_WIDTH },
10884 };
10885 
10891 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS] =
10892 {
10893  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
10894  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_0_WIDTH },
10895  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
10896  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_1_WIDTH },
10897  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
10898  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_2_WIDTH },
10899  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
10900  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_3_WIDTH },
10901  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
10902  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_4_WIDTH },
10903  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
10904  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_5_WIDTH },
10905  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
10906  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_6_WIDTH },
10907  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
10908  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_7_WIDTH },
10909  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
10910  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_8_WIDTH },
10911  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
10912  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_9_WIDTH },
10913 };
10914 
10920 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
10921 {
10922  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
10923  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
10924  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
10925  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
10926  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
10927  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
10928  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
10929  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
10930  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
10931  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
10932  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
10933  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_5_WIDTH },
10934  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
10935  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_6_WIDTH },
10936 };
10937 
10943 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
10944 {
10945  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
10946  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
10947  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
10948  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
10949  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
10950  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
10951  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
10952  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
10953  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
10954  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
10955  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
10956  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
10957  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
10958  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
10959  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
10960  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
10961  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
10962  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
10963  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
10964  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
10965  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
10966  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
10967  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
10968  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
10969  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
10970  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
10971  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
10972  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
10973  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
10974  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
10975  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
10976  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
10977  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
10978  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
10979  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
10980  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
10981  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
10982  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
10983  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
10984  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
10985  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
10986  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
10987  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
10988  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
10989  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
10990  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
10991  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
10992  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
10993  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
10994  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
10995  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
10996  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
10997  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
10998  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
10999  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
11000  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
11001  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
11002  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
11003  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
11004  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
11005  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
11006  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
11007  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
11008  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
11009  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
11010  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
11011  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
11012  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
11013  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
11014  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
11015  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
11016  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
11017  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
11018  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
11019  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
11020  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
11021  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
11022  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
11023  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
11024  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
11025  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
11026  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
11027  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
11028  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
11029  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
11030  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
11031  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
11032  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
11033  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
11034  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
11035  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
11036  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
11037  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
11038  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
11039  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
11040  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
11041  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
11042  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
11043  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
11044  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
11045  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
11046  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
11047  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
11048  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
11049  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
11050  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
11051  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
11052  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
11053  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
11054  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
11055  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
11056  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
11057  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
11058  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
11059  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
11060  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
11061  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
11062  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
11063  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
11064  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
11065  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
11066  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
11067  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
11068  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
11069  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
11070  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
11071  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
11072  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
11073  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
11074  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
11075  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
11076  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
11077  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
11078  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
11079  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
11080  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
11081  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
11082  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
11083  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
11084  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
11085  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
11086  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
11087  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
11088  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
11089  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
11090  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
11091  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
11092  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
11093  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
11094  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_74_WIDTH },
11095  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
11096  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_75_WIDTH },
11097  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
11098  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_76_WIDTH },
11099  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
11100  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_77_WIDTH },
11101  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
11102  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_78_WIDTH },
11103  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
11104  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_79_WIDTH },
11105  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
11106  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_80_WIDTH },
11107  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
11108  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_81_WIDTH },
11109  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
11110  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_82_WIDTH },
11111  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
11112  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_83_WIDTH },
11113  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
11114  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_84_WIDTH },
11115  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
11116  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_85_WIDTH },
11117  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
11118  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_86_WIDTH },
11119  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
11120  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_87_WIDTH },
11121  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
11122  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_88_WIDTH },
11123  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
11124  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_89_WIDTH },
11125  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
11126  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_90_WIDTH },
11127 };
11128 
11134 static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS] =
11135 {
11136  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
11137  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_0_WIDTH },
11138  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
11139  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_1_WIDTH },
11140  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
11141  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_2_WIDTH },
11142  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
11143  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_3_WIDTH },
11144  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
11145  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_4_WIDTH },
11146  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
11147  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_5_WIDTH },
11148  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
11149  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_6_WIDTH },
11150  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
11151  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_7_WIDTH },
11152  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
11153  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_8_WIDTH },
11154  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
11155  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_9_WIDTH },
11156  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
11157  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_10_WIDTH },
11158  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
11159  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_11_WIDTH },
11160  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
11161  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_12_WIDTH },
11162  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
11163  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_13_WIDTH },
11164  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
11165  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_14_WIDTH },
11166  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
11167  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_15_WIDTH },
11168  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
11169  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_16_WIDTH },
11170  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
11171  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_17_WIDTH },
11172  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
11173  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_18_WIDTH },
11174  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
11175  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_19_WIDTH },
11176  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
11177  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_20_WIDTH },
11178  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
11179  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_21_WIDTH },
11180  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
11181  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_22_WIDTH },
11182  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
11183  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_23_WIDTH },
11184  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
11185  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_24_WIDTH },
11186  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
11187  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_25_WIDTH },
11188  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
11189  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_26_WIDTH },
11190  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
11191  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_27_WIDTH },
11192  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
11193  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_28_WIDTH },
11194  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
11195  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_29_WIDTH },
11196  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
11197  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_30_WIDTH },
11198  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
11199  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_31_WIDTH },
11200  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
11201  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_32_WIDTH },
11202  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
11203  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_33_WIDTH },
11204  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
11205  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_34_WIDTH },
11206  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
11207  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_35_WIDTH },
11208  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
11209  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_36_WIDTH },
11210  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
11211  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_37_WIDTH },
11212  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
11213  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_38_WIDTH },
11214  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
11215  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_39_WIDTH },
11216  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
11217  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_40_WIDTH },
11218  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
11219  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_41_WIDTH },
11220  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
11221  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_42_WIDTH },
11222  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
11223  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_43_WIDTH },
11224  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
11225  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_44_WIDTH },
11226  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
11227  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_45_WIDTH },
11228  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
11229  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_46_WIDTH },
11230  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
11231  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_47_WIDTH },
11232  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
11233  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_48_WIDTH },
11234  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
11235  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_49_WIDTH },
11236  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
11237  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_50_WIDTH },
11238  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
11239  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_51_WIDTH },
11240  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
11241  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_52_WIDTH },
11242  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
11243  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_53_WIDTH },
11244  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
11245  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_54_WIDTH },
11246  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
11247  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_55_WIDTH },
11248  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
11249  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_56_WIDTH },
11250  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
11251  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_57_WIDTH },
11252  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
11253  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_58_WIDTH },
11254  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
11255  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_59_WIDTH },
11256  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
11257  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_60_WIDTH },
11258  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
11259  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_61_WIDTH },
11260 };
11261 
11266 static const SDL_MemConfig_t SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_MemEntries[SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
11267 {
11268  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM0_ECC_RAM_ID, 0u,
11269  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM0_ECC_RAM_SIZE, 8u,
11270  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM0_ECC_ROW_WIDTH, ((bool)false) },
11271  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM1_ECC_RAM_ID, 0u,
11272  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM1_ECC_RAM_SIZE, 8u,
11273  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM1_ECC_ROW_WIDTH, ((bool)false) },
11274  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKA_PROG_RAM_ECC_RAM_ID, 0u,
11275  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKA_PROG_RAM_ECC_RAM_SIZE, 4u,
11276  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKA_PROG_RAM_ECC_ROW_WIDTH, ((bool)false) },
11277  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK01_ECC_RAM_ID, 0u,
11278  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK01_ECC_RAM_SIZE, 32u,
11279  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK01_ECC_ROW_WIDTH, ((bool)false) },
11280  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK23_ECC_RAM_ID, 0u,
11281  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK23_ECC_RAM_SIZE, 32u,
11282  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK23_ECC_ROW_WIDTH, ((bool)false) },
11283  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK4_ECC_RAM_ID, 0u,
11284  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK4_ECC_RAM_SIZE, 32u,
11285  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK4_ECC_ROW_WIDTH, ((bool)false) },
11286  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK01_ECC_RAM_ID, 0u,
11287  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK01_ECC_RAM_SIZE, 32u,
11288  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK01_ECC_ROW_WIDTH, ((bool)false) },
11289  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK23_ECC_RAM_ID, 0u,
11290  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK23_ECC_RAM_SIZE, 32u,
11291  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK23_ECC_ROW_WIDTH, ((bool)false) },
11292  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK45_ECC_RAM_ID, 0u,
11293  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK45_ECC_RAM_SIZE, 32u,
11294  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK45_ECC_ROW_WIDTH, ((bool)false) },
11295  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK67_ECC_RAM_ID, 0u,
11296  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK67_ECC_RAM_SIZE, 32u,
11297  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK67_ECC_ROW_WIDTH, ((bool)false) },
11298  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK89_ECC_RAM_ID, 0u,
11299  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK89_ECC_RAM_SIZE, 32u,
11300  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK89_ECC_ROW_WIDTH, ((bool)false) },
11301  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK10_ECC_RAM_ID, 0u,
11302  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK10_ECC_RAM_SIZE, 32u,
11303  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK10_ECC_ROW_WIDTH, ((bool)false) },
11304 };
11305 
11311 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] =
11312 {
11313  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_0_CHECKER_TYPE,
11314  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
11315  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_1_CHECKER_TYPE,
11316  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
11317  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_2_CHECKER_TYPE,
11318  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
11319  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_3_CHECKER_TYPE,
11320  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
11321  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_4_CHECKER_TYPE,
11322  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
11323  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_5_CHECKER_TYPE,
11324  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
11325  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_6_CHECKER_TYPE,
11326  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
11327  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_7_CHECKER_TYPE,
11328  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
11329  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_8_CHECKER_TYPE,
11330  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
11331  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_9_CHECKER_TYPE,
11332  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
11333  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_10_CHECKER_TYPE,
11334  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
11335  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_11_CHECKER_TYPE,
11336  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
11337  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_12_CHECKER_TYPE,
11338  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
11339  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_13_CHECKER_TYPE,
11340  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
11341  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_14_CHECKER_TYPE,
11342  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
11343  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_15_CHECKER_TYPE,
11344  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
11345  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_16_CHECKER_TYPE,
11346  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
11347  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_17_CHECKER_TYPE,
11348  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
11349  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_18_CHECKER_TYPE,
11350  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
11351  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_19_CHECKER_TYPE,
11352  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
11353  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_20_CHECKER_TYPE,
11354  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
11355  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_21_CHECKER_TYPE,
11356  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
11357  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_22_CHECKER_TYPE,
11358  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
11359  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_23_CHECKER_TYPE,
11360  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
11361  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_24_CHECKER_TYPE,
11362  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
11363  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_25_CHECKER_TYPE,
11364  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
11365  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_26_CHECKER_TYPE,
11366  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
11367  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_27_CHECKER_TYPE,
11368  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
11369  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_28_CHECKER_TYPE,
11370  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
11371  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_29_CHECKER_TYPE,
11372  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
11373  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_30_CHECKER_TYPE,
11374  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
11375  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_31_CHECKER_TYPE,
11376  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
11377  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_32_CHECKER_TYPE,
11378  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
11379  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_33_CHECKER_TYPE,
11380  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
11381  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_34_CHECKER_TYPE,
11382  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
11383  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_35_CHECKER_TYPE,
11384  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
11385  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_36_CHECKER_TYPE,
11386  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
11387  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_37_CHECKER_TYPE,
11388  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
11389  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_38_CHECKER_TYPE,
11390  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
11391  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_39_CHECKER_TYPE,
11392  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
11393  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_40_CHECKER_TYPE,
11394  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
11395  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_41_CHECKER_TYPE,
11396  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
11397  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_42_CHECKER_TYPE,
11398  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
11399  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_43_CHECKER_TYPE,
11400  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
11401  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_44_CHECKER_TYPE,
11402  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
11403  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_45_CHECKER_TYPE,
11404  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
11405  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_46_CHECKER_TYPE,
11406  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
11407  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_47_CHECKER_TYPE,
11408  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
11409  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_48_CHECKER_TYPE,
11410  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
11411  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_49_CHECKER_TYPE,
11412  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
11413  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_50_CHECKER_TYPE,
11414  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
11415  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_51_CHECKER_TYPE,
11416  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
11417  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_52_CHECKER_TYPE,
11418  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
11419  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_53_CHECKER_TYPE,
11420  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
11421  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_54_CHECKER_TYPE,
11422  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
11423  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_55_CHECKER_TYPE,
11424  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
11425  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_56_CHECKER_TYPE,
11426  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
11427  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_57_CHECKER_TYPE,
11428  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
11429  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_58_CHECKER_TYPE,
11430  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
11431  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_59_CHECKER_TYPE,
11432  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
11433  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_60_CHECKER_TYPE,
11434  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
11435  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_61_CHECKER_TYPE,
11436  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
11437  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_62_CHECKER_TYPE,
11438  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
11439  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_63_CHECKER_TYPE,
11440  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
11441  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_64_CHECKER_TYPE,
11442  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
11443  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_65_CHECKER_TYPE,
11444  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
11445  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_66_CHECKER_TYPE,
11446  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
11447  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_67_CHECKER_TYPE,
11448  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
11449  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_68_CHECKER_TYPE,
11450  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
11451  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_69_CHECKER_TYPE,
11452  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
11453  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_70_CHECKER_TYPE,
11454  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
11455  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_71_CHECKER_TYPE,
11456  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
11457  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_72_CHECKER_TYPE,
11458  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
11459  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_73_CHECKER_TYPE,
11460  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
11461  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_74_CHECKER_TYPE,
11462  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
11463  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_75_CHECKER_TYPE,
11464  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
11465  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_76_CHECKER_TYPE,
11466  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
11467  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_77_CHECKER_TYPE,
11468  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
11469  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_78_CHECKER_TYPE,
11470  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
11471  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_79_CHECKER_TYPE,
11472  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
11473  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_80_CHECKER_TYPE,
11474  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
11475  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_81_CHECKER_TYPE,
11476  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
11477  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_82_CHECKER_TYPE,
11478  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
11479  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_83_CHECKER_TYPE,
11480  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
11481  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_84_CHECKER_TYPE,
11482  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
11483  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_85_CHECKER_TYPE,
11484  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
11485  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_86_CHECKER_TYPE,
11486  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
11487  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_87_CHECKER_TYPE,
11488  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
11489  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_88_CHECKER_TYPE,
11490  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
11491  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_89_CHECKER_TYPE,
11492  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
11493  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_90_CHECKER_TYPE,
11494  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
11495  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_91_CHECKER_TYPE,
11496  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
11497  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_92_CHECKER_TYPE,
11498  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
11499  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_93_CHECKER_TYPE,
11500  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
11501  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_94_CHECKER_TYPE,
11502  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
11503  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_95_CHECKER_TYPE,
11504  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
11505  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_96_CHECKER_TYPE,
11506  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
11507  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_97_CHECKER_TYPE,
11508  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
11509  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_98_CHECKER_TYPE,
11510  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
11511  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_99_CHECKER_TYPE,
11512  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
11513  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_100_CHECKER_TYPE,
11514  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
11515  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_101_CHECKER_TYPE,
11516  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
11517  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_102_CHECKER_TYPE,
11518  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
11519  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_103_CHECKER_TYPE,
11520  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
11521  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_104_CHECKER_TYPE,
11522  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
11523  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_105_CHECKER_TYPE,
11524  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
11525  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_106_CHECKER_TYPE,
11526  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
11527  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_107_CHECKER_TYPE,
11528  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
11529  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_108_CHECKER_TYPE,
11530  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
11531  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_109_CHECKER_TYPE,
11532  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
11533  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_110_CHECKER_TYPE,
11534  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
11535  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_111_CHECKER_TYPE,
11536  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
11537  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_112_CHECKER_TYPE,
11538  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
11539  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_113_CHECKER_TYPE,
11540  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
11541  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_114_CHECKER_TYPE,
11542  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
11543  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_115_CHECKER_TYPE,
11544  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
11545  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_116_CHECKER_TYPE,
11546  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
11547  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_117_CHECKER_TYPE,
11548  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
11549  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_118_CHECKER_TYPE,
11550  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
11551  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_119_CHECKER_TYPE,
11552  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
11553  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_120_CHECKER_TYPE,
11554  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
11555  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_121_CHECKER_TYPE,
11556  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
11557  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_122_CHECKER_TYPE,
11558  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
11559  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_123_CHECKER_TYPE,
11560  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
11561  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_124_CHECKER_TYPE,
11562  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
11563  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_125_CHECKER_TYPE,
11564  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
11565  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_126_CHECKER_TYPE,
11566  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
11567  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_127_CHECKER_TYPE,
11568  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
11569  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_128_CHECKER_TYPE,
11570  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
11571  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_129_CHECKER_TYPE,
11572  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
11573  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_130_CHECKER_TYPE,
11574  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
11575  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_131_CHECKER_TYPE,
11576  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
11577  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_132_CHECKER_TYPE,
11578  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
11579  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_133_CHECKER_TYPE,
11580  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
11581  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_134_CHECKER_TYPE,
11582  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
11583  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_135_CHECKER_TYPE,
11584  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
11585  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_136_CHECKER_TYPE,
11586  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
11587  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_137_CHECKER_TYPE,
11588  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
11589  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_138_CHECKER_TYPE,
11590  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
11591  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_139_CHECKER_TYPE,
11592  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
11593  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_140_CHECKER_TYPE,
11594  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
11595  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_141_CHECKER_TYPE,
11596  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
11597  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_142_CHECKER_TYPE,
11598  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
11599  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_143_CHECKER_TYPE,
11600  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
11601  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_144_CHECKER_TYPE,
11602  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
11603  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_145_CHECKER_TYPE,
11604  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
11605  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_146_CHECKER_TYPE,
11606  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
11607  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_147_CHECKER_TYPE,
11608  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
11609  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_148_CHECKER_TYPE,
11610  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
11611  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_149_CHECKER_TYPE,
11612  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
11613  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_150_CHECKER_TYPE,
11614  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
11615  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_151_CHECKER_TYPE,
11616  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
11617  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_152_CHECKER_TYPE,
11618  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
11619  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_153_CHECKER_TYPE,
11620  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
11621  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_154_CHECKER_TYPE,
11622  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
11623  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_155_CHECKER_TYPE,
11624  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
11625  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_156_CHECKER_TYPE,
11626  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
11627  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_157_CHECKER_TYPE,
11628  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
11629  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_158_CHECKER_TYPE,
11630  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
11631  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_159_CHECKER_TYPE,
11632  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
11633  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_160_CHECKER_TYPE,
11634  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
11635  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_161_CHECKER_TYPE,
11636  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
11637  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_162_CHECKER_TYPE,
11638  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
11639  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_163_CHECKER_TYPE,
11640  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
11641  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_164_CHECKER_TYPE,
11642  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
11643  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_165_CHECKER_TYPE,
11644  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
11645  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_166_CHECKER_TYPE,
11646  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
11647  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_167_CHECKER_TYPE,
11648  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
11649  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_168_CHECKER_TYPE,
11650  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
11651  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_169_CHECKER_TYPE,
11652  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
11653  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_170_CHECKER_TYPE,
11654  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
11655  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_171_CHECKER_TYPE,
11656  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
11657  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_172_CHECKER_TYPE,
11658  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
11659  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_173_CHECKER_TYPE,
11660  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
11661  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_174_CHECKER_TYPE,
11662  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
11663  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_175_CHECKER_TYPE,
11664  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
11665  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_176_CHECKER_TYPE,
11666  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
11667  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_177_CHECKER_TYPE,
11668  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
11669  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_178_CHECKER_TYPE,
11670  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
11671  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_179_CHECKER_TYPE,
11672  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
11673  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_180_CHECKER_TYPE,
11674  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
11675  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_181_CHECKER_TYPE,
11676  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
11677  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_182_CHECKER_TYPE,
11678  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
11679  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_183_CHECKER_TYPE,
11680  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
11681  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_184_CHECKER_TYPE,
11682  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
11683  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_185_CHECKER_TYPE,
11684  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
11685  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_186_CHECKER_TYPE,
11686  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
11687  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_187_CHECKER_TYPE,
11688  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
11689  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_188_CHECKER_TYPE,
11690  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
11691  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_189_CHECKER_TYPE,
11692  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
11693  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_190_CHECKER_TYPE,
11694  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
11695  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_191_CHECKER_TYPE,
11696  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
11697  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_192_CHECKER_TYPE,
11698  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
11699  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_193_CHECKER_TYPE,
11700  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
11701  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_194_CHECKER_TYPE,
11702  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
11703  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_195_CHECKER_TYPE,
11704  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
11705  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_196_CHECKER_TYPE,
11706  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
11707  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_197_CHECKER_TYPE,
11708  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
11709  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_198_CHECKER_TYPE,
11710  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
11711  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_199_CHECKER_TYPE,
11712  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
11713  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_200_CHECKER_TYPE,
11714  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
11715  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_201_CHECKER_TYPE,
11716  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
11717  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_202_CHECKER_TYPE,
11718  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
11719  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_203_CHECKER_TYPE,
11720  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
11721  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_204_CHECKER_TYPE,
11722  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
11723  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_205_CHECKER_TYPE,
11724  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
11725  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_206_CHECKER_TYPE,
11726  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
11727  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_207_CHECKER_TYPE,
11728  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
11729  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_208_CHECKER_TYPE,
11730  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
11731  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_209_CHECKER_TYPE,
11732  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
11733  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_210_CHECKER_TYPE,
11734  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
11735  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_211_CHECKER_TYPE,
11736  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
11737  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_212_CHECKER_TYPE,
11738  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
11739  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_213_CHECKER_TYPE,
11740  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
11741  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_214_CHECKER_TYPE,
11742  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
11743  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_215_CHECKER_TYPE,
11744  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
11745  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_216_CHECKER_TYPE,
11746  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
11747  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_217_CHECKER_TYPE,
11748  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
11749  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_218_CHECKER_TYPE,
11750  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
11751  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_219_CHECKER_TYPE,
11752  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
11753  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_220_CHECKER_TYPE,
11754  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
11755  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_221_CHECKER_TYPE,
11756  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
11757  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_222_CHECKER_TYPE,
11758  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
11759  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_223_CHECKER_TYPE,
11760  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
11761  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_224_CHECKER_TYPE,
11762  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
11763  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_225_CHECKER_TYPE,
11764  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
11765  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_226_CHECKER_TYPE,
11766  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
11767  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_227_CHECKER_TYPE,
11768  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
11769  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_228_CHECKER_TYPE,
11770  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
11771  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_229_CHECKER_TYPE,
11772  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
11773  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_230_CHECKER_TYPE,
11774  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
11775  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_231_CHECKER_TYPE,
11776  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
11777  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_232_CHECKER_TYPE,
11778  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
11779  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_233_CHECKER_TYPE,
11780  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
11781  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_234_CHECKER_TYPE,
11782  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
11783  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_235_CHECKER_TYPE,
11784  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
11785  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_236_CHECKER_TYPE,
11786  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
11787  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_237_CHECKER_TYPE,
11788  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
11789  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_238_CHECKER_TYPE,
11790  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
11791  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_239_CHECKER_TYPE,
11792  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
11793  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_240_CHECKER_TYPE,
11794  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
11795  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_241_CHECKER_TYPE,
11796  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
11797  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_242_CHECKER_TYPE,
11798  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
11799  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_243_CHECKER_TYPE,
11800  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
11801  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_244_CHECKER_TYPE,
11802  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
11803  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_245_CHECKER_TYPE,
11804  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
11805  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_246_CHECKER_TYPE,
11806  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
11807  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_247_CHECKER_TYPE,
11808  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
11809  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_248_CHECKER_TYPE,
11810  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
11811  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_249_CHECKER_TYPE,
11812  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
11813  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_250_CHECKER_TYPE,
11814  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
11815  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_251_CHECKER_TYPE,
11816  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
11817  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_252_CHECKER_TYPE,
11818  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
11819  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_253_CHECKER_TYPE,
11820  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
11821  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_254_CHECKER_TYPE,
11822  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
11823  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_255_CHECKER_TYPE,
11824  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
11825 };
11826 
11832 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] =
11833 {
11834  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_0_CHECKER_TYPE,
11835  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
11836  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_1_CHECKER_TYPE,
11837  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
11838  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_2_CHECKER_TYPE,
11839  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
11840  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_3_CHECKER_TYPE,
11841  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
11842  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_4_CHECKER_TYPE,
11843  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
11844  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_5_CHECKER_TYPE,
11845  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
11846  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_6_CHECKER_TYPE,
11847  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
11848  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_7_CHECKER_TYPE,
11849  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
11850  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_8_CHECKER_TYPE,
11851  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
11852  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_9_CHECKER_TYPE,
11853  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
11854  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_10_CHECKER_TYPE,
11855  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
11856  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_11_CHECKER_TYPE,
11857  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
11858  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_12_CHECKER_TYPE,
11859  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
11860  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_13_CHECKER_TYPE,
11861  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
11862  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_14_CHECKER_TYPE,
11863  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
11864  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_15_CHECKER_TYPE,
11865  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
11866  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_16_CHECKER_TYPE,
11867  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
11868  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_17_CHECKER_TYPE,
11869  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
11870  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_18_CHECKER_TYPE,
11871  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
11872  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_19_CHECKER_TYPE,
11873  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
11874  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_20_CHECKER_TYPE,
11875  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
11876  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_21_CHECKER_TYPE,
11877  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
11878  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_22_CHECKER_TYPE,
11879  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
11880  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_23_CHECKER_TYPE,
11881  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
11882  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_24_CHECKER_TYPE,
11883  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH },
11884  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_25_CHECKER_TYPE,
11885  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH },
11886  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_26_CHECKER_TYPE,
11887  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH },
11888  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_27_CHECKER_TYPE,
11889  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH },
11890  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_28_CHECKER_TYPE,
11891  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH },
11892  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_29_CHECKER_TYPE,
11893  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH },
11894  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_30_CHECKER_TYPE,
11895  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH },
11896  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_31_CHECKER_TYPE,
11897  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH },
11898  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_32_CHECKER_TYPE,
11899  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH },
11900  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_33_CHECKER_TYPE,
11901  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH },
11902  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_34_CHECKER_TYPE,
11903  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH },
11904  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_35_CHECKER_TYPE,
11905  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH },
11906  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_36_CHECKER_TYPE,
11907  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH },
11908  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_37_CHECKER_TYPE,
11909  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH },
11910  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_38_CHECKER_TYPE,
11911  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH },
11912  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_39_CHECKER_TYPE,
11913  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH },
11914  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_40_CHECKER_TYPE,
11915  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH },
11916  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_41_CHECKER_TYPE,
11917  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH },
11918  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_42_CHECKER_TYPE,
11919  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH },
11920  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_43_CHECKER_TYPE,
11921  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_43_WIDTH },
11922  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_44_CHECKER_TYPE,
11923  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_44_WIDTH },
11924  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_45_CHECKER_TYPE,
11925  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_45_WIDTH },
11926  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_46_CHECKER_TYPE,
11927  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_46_WIDTH },
11928  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_47_CHECKER_TYPE,
11929  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_47_WIDTH },
11930  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_48_CHECKER_TYPE,
11931  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_48_WIDTH },
11932  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_49_CHECKER_TYPE,
11933  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_49_WIDTH },
11934  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_50_CHECKER_TYPE,
11935  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_50_WIDTH },
11936  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_51_CHECKER_TYPE,
11937  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_51_WIDTH },
11938  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_52_CHECKER_TYPE,
11939  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_52_WIDTH },
11940  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_53_CHECKER_TYPE,
11941  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_53_WIDTH },
11942  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_54_CHECKER_TYPE,
11943  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_54_WIDTH },
11944  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_55_CHECKER_TYPE,
11945  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_55_WIDTH },
11946  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_56_CHECKER_TYPE,
11947  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_56_WIDTH },
11948  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_57_CHECKER_TYPE,
11949  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_57_WIDTH },
11950  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_58_CHECKER_TYPE,
11951  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_58_WIDTH },
11952  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_59_CHECKER_TYPE,
11953  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_59_WIDTH },
11954  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_60_CHECKER_TYPE,
11955  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_60_WIDTH },
11956  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_61_CHECKER_TYPE,
11957  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_61_WIDTH },
11958  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_62_CHECKER_TYPE,
11959  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_62_WIDTH },
11960  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_63_CHECKER_TYPE,
11961  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_63_WIDTH },
11962  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_64_CHECKER_TYPE,
11963  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_64_WIDTH },
11964  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_65_CHECKER_TYPE,
11965  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_65_WIDTH },
11966  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_66_CHECKER_TYPE,
11967  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_66_WIDTH },
11968  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_67_CHECKER_TYPE,
11969  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_67_WIDTH },
11970  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_68_CHECKER_TYPE,
11971  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_68_WIDTH },
11972  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_69_CHECKER_TYPE,
11973  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_69_WIDTH },
11974  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_70_CHECKER_TYPE,
11975  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_70_WIDTH },
11976  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_71_CHECKER_TYPE,
11977  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_71_WIDTH },
11978  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_72_CHECKER_TYPE,
11979  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_72_WIDTH },
11980  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_73_CHECKER_TYPE,
11981  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_73_WIDTH },
11982 };
11983 
11989 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
11990 {
11991  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
11992  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
11993  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
11994  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
11995  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
11996  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
11997  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
11998  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
11999  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
12000  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
12001  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
12002  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
12003  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
12004  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
12005  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
12006  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
12007  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
12008  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
12009  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
12010  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
12011  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
12012  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
12013  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
12014  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
12015  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
12016  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
12017  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
12018  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
12019  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
12020  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
12021  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
12022  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
12023  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
12024  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
12025  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
12026  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
12027  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
12028  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
12029  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
12030  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
12031  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
12032  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
12033  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
12034  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
12035  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
12036  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
12037  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
12038  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
12039  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
12040  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
12041  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
12042  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
12043  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
12044  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
12045  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
12046  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
12047  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
12048  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
12049  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
12050  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
12051  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
12052  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
12053  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
12054  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
12055  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
12056  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
12057  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
12058  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
12059  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
12060  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
12061  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
12062  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
12063  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
12064  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
12065  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
12066  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
12067  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
12068  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
12069  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
12070  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
12071  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
12072  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
12073  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
12074  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
12075  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
12076  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
12077  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
12078  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
12079  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
12080  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
12081  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
12082  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
12083  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
12084  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
12085  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
12086  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
12087  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
12088  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
12089  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
12090  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
12091  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
12092  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
12093  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
12094  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
12095  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
12096  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
12097 };
12098 
12104 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] =
12105 {
12106  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_0_CHECKER_TYPE,
12107  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
12108  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_1_CHECKER_TYPE,
12109  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
12110  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_2_CHECKER_TYPE,
12111  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
12112  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_3_CHECKER_TYPE,
12113  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
12114  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_4_CHECKER_TYPE,
12115  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
12116  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_5_CHECKER_TYPE,
12117  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
12118  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_6_CHECKER_TYPE,
12119  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
12120  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_7_CHECKER_TYPE,
12121  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
12122  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_8_CHECKER_TYPE,
12123  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
12124  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_9_CHECKER_TYPE,
12125  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
12126  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_10_CHECKER_TYPE,
12127  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
12128  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_11_CHECKER_TYPE,
12129  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
12130  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_12_CHECKER_TYPE,
12131  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
12132  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_13_CHECKER_TYPE,
12133  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
12134  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_14_CHECKER_TYPE,
12135  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
12136  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_15_CHECKER_TYPE,
12137  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
12138  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_16_CHECKER_TYPE,
12139  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
12140  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_17_CHECKER_TYPE,
12141  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
12142  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_18_CHECKER_TYPE,
12143  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
12144  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_19_CHECKER_TYPE,
12145  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
12146  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_20_CHECKER_TYPE,
12147  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
12148  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_21_CHECKER_TYPE,
12149  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
12150  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_22_CHECKER_TYPE,
12151  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
12152  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_23_CHECKER_TYPE,
12153  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
12154  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_24_CHECKER_TYPE,
12155  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
12156  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_25_CHECKER_TYPE,
12157  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
12158  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_26_CHECKER_TYPE,
12159  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
12160  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_27_CHECKER_TYPE,
12161  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
12162  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_28_CHECKER_TYPE,
12163  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
12164  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_29_CHECKER_TYPE,
12165  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
12166  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_30_CHECKER_TYPE,
12167  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
12168  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_31_CHECKER_TYPE,
12169  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
12170  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_32_CHECKER_TYPE,
12171  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
12172  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_33_CHECKER_TYPE,
12173  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
12174  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_34_CHECKER_TYPE,
12175  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
12176  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_35_CHECKER_TYPE,
12177  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
12178  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_36_CHECKER_TYPE,
12179  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
12180  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_37_CHECKER_TYPE,
12181  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
12182  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_38_CHECKER_TYPE,
12183  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
12184  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_39_CHECKER_TYPE,
12185  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
12186  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_40_CHECKER_TYPE,
12187  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
12188  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_41_CHECKER_TYPE,
12189  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
12190  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_42_CHECKER_TYPE,
12191  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
12192  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_43_CHECKER_TYPE,
12193  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
12194  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_44_CHECKER_TYPE,
12195  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
12196  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_45_CHECKER_TYPE,
12197  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
12198  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_46_CHECKER_TYPE,
12199  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
12200  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_47_CHECKER_TYPE,
12201  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
12202  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_48_CHECKER_TYPE,
12203  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
12204  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_49_CHECKER_TYPE,
12205  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
12206  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_50_CHECKER_TYPE,
12207  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
12208  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_51_CHECKER_TYPE,
12209  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
12210  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_52_CHECKER_TYPE,
12211  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
12212  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_53_CHECKER_TYPE,
12213  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
12214  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_54_CHECKER_TYPE,
12215  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
12216  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_55_CHECKER_TYPE,
12217  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
12218  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_56_CHECKER_TYPE,
12219  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
12220  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_57_CHECKER_TYPE,
12221  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
12222  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_58_CHECKER_TYPE,
12223  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
12224  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_59_CHECKER_TYPE,
12225  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
12226  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_60_CHECKER_TYPE,
12227  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
12228  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_61_CHECKER_TYPE,
12229  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
12230  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_62_CHECKER_TYPE,
12231  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
12232  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_63_CHECKER_TYPE,
12233  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
12234  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_64_CHECKER_TYPE,
12235  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
12236  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_65_CHECKER_TYPE,
12237  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
12238  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_66_CHECKER_TYPE,
12239  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
12240  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_67_CHECKER_TYPE,
12241  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
12242  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_68_CHECKER_TYPE,
12243  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
12244  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_69_CHECKER_TYPE,
12245  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
12246  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_70_CHECKER_TYPE,
12247  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
12248  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_71_CHECKER_TYPE,
12249  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
12250  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_72_CHECKER_TYPE,
12251  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
12252  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_73_CHECKER_TYPE,
12253  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
12254  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_74_CHECKER_TYPE,
12255  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
12256  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_75_CHECKER_TYPE,
12257  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
12258  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_76_CHECKER_TYPE,
12259  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
12260  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_77_CHECKER_TYPE,
12261  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
12262  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_78_CHECKER_TYPE,
12263  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
12264  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_79_CHECKER_TYPE,
12265  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
12266  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_80_CHECKER_TYPE,
12267  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
12268  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_81_CHECKER_TYPE,
12269  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
12270  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_82_CHECKER_TYPE,
12271  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
12272  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_83_CHECKER_TYPE,
12273  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
12274  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_84_CHECKER_TYPE,
12275  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
12276  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_85_CHECKER_TYPE,
12277  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
12278  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_86_CHECKER_TYPE,
12279  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
12280  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_87_CHECKER_TYPE,
12281  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
12282  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_88_CHECKER_TYPE,
12283  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
12284  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_89_CHECKER_TYPE,
12285  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
12286  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_90_CHECKER_TYPE,
12287  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
12288  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_91_CHECKER_TYPE,
12289  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
12290  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_92_CHECKER_TYPE,
12291  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
12292  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_93_CHECKER_TYPE,
12293  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
12294  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_94_CHECKER_TYPE,
12295  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
12296  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_95_CHECKER_TYPE,
12297  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
12298  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_96_CHECKER_TYPE,
12299  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
12300  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_97_CHECKER_TYPE,
12301  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
12302  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_98_CHECKER_TYPE,
12303  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
12304  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_99_CHECKER_TYPE,
12305  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
12306  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_100_CHECKER_TYPE,
12307  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
12308  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_101_CHECKER_TYPE,
12309  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
12310  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_102_CHECKER_TYPE,
12311  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
12312  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_103_CHECKER_TYPE,
12313  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
12314  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_104_CHECKER_TYPE,
12315  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
12316  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_105_CHECKER_TYPE,
12317  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
12318  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_106_CHECKER_TYPE,
12319  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
12320  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_107_CHECKER_TYPE,
12321  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
12322  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_108_CHECKER_TYPE,
12323  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
12324  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_109_CHECKER_TYPE,
12325  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
12326  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_110_CHECKER_TYPE,
12327  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
12328  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_111_CHECKER_TYPE,
12329  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
12330  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_112_CHECKER_TYPE,
12331  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
12332  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_113_CHECKER_TYPE,
12333  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
12334  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_114_CHECKER_TYPE,
12335  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
12336  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_115_CHECKER_TYPE,
12337  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
12338  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_116_CHECKER_TYPE,
12339  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
12340  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_117_CHECKER_TYPE,
12341  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
12342  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_118_CHECKER_TYPE,
12343  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
12344  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_119_CHECKER_TYPE,
12345  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
12346  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_120_CHECKER_TYPE,
12347  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
12348  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_121_CHECKER_TYPE,
12349  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
12350  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_122_CHECKER_TYPE,
12351  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
12352  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_123_CHECKER_TYPE,
12353  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
12354  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_124_CHECKER_TYPE,
12355  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
12356  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_125_CHECKER_TYPE,
12357  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
12358  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_126_CHECKER_TYPE,
12359  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
12360  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_127_CHECKER_TYPE,
12361  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
12362  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_128_CHECKER_TYPE,
12363  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
12364  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_129_CHECKER_TYPE,
12365  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
12366  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_130_CHECKER_TYPE,
12367  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
12368  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_131_CHECKER_TYPE,
12369  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
12370  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_132_CHECKER_TYPE,
12371  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
12372  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_133_CHECKER_TYPE,
12373  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
12374  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_134_CHECKER_TYPE,
12375  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
12376  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_135_CHECKER_TYPE,
12377  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
12378  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_136_CHECKER_TYPE,
12379  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
12380  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_137_CHECKER_TYPE,
12381  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
12382  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_138_CHECKER_TYPE,
12383  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
12384  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_139_CHECKER_TYPE,
12385  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
12386  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_140_CHECKER_TYPE,
12387  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
12388  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_141_CHECKER_TYPE,
12389  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
12390  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_142_CHECKER_TYPE,
12391  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
12392  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_143_CHECKER_TYPE,
12393  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
12394  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_144_CHECKER_TYPE,
12395  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
12396  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_145_CHECKER_TYPE,
12397  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
12398  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_146_CHECKER_TYPE,
12399  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
12400  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_147_CHECKER_TYPE,
12401  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
12402  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_148_CHECKER_TYPE,
12403  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
12404  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_149_CHECKER_TYPE,
12405  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
12406  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_150_CHECKER_TYPE,
12407  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
12408  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_151_CHECKER_TYPE,
12409  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
12410  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_152_CHECKER_TYPE,
12411  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
12412  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_153_CHECKER_TYPE,
12413  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
12414  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_154_CHECKER_TYPE,
12415  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
12416  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_155_CHECKER_TYPE,
12417  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
12418  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_156_CHECKER_TYPE,
12419  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
12420  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_157_CHECKER_TYPE,
12421  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
12422  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_158_CHECKER_TYPE,
12423  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
12424  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_159_CHECKER_TYPE,
12425  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
12426  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_160_CHECKER_TYPE,
12427  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
12428  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_161_CHECKER_TYPE,
12429  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
12430  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_162_CHECKER_TYPE,
12431  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
12432  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_163_CHECKER_TYPE,
12433  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
12434  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_164_CHECKER_TYPE,
12435  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
12436  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_165_CHECKER_TYPE,
12437  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
12438  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_166_CHECKER_TYPE,
12439  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
12440  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_167_CHECKER_TYPE,
12441  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
12442  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_168_CHECKER_TYPE,
12443  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
12444  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_169_CHECKER_TYPE,
12445  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
12446  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_170_CHECKER_TYPE,
12447  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
12448  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_171_CHECKER_TYPE,
12449  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
12450  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_172_CHECKER_TYPE,
12451  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
12452  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_173_CHECKER_TYPE,
12453  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
12454  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_174_CHECKER_TYPE,
12455  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
12456  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_175_CHECKER_TYPE,
12457  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
12458  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_176_CHECKER_TYPE,
12459  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
12460  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_177_CHECKER_TYPE,
12461  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
12462  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_178_CHECKER_TYPE,
12463  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
12464  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_179_CHECKER_TYPE,
12465  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
12466  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_180_CHECKER_TYPE,
12467  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
12468  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_181_CHECKER_TYPE,
12469  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
12470  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_182_CHECKER_TYPE,
12471  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
12472  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_183_CHECKER_TYPE,
12473  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
12474  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_184_CHECKER_TYPE,
12475  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
12476  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_185_CHECKER_TYPE,
12477  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
12478  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_186_CHECKER_TYPE,
12479  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
12480  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_187_CHECKER_TYPE,
12481  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
12482  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_188_CHECKER_TYPE,
12483  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
12484  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_189_CHECKER_TYPE,
12485  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
12486  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_190_CHECKER_TYPE,
12487  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
12488  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_191_CHECKER_TYPE,
12489  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
12490  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_192_CHECKER_TYPE,
12491  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
12492  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_193_CHECKER_TYPE,
12493  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
12494  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_194_CHECKER_TYPE,
12495  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
12496  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_195_CHECKER_TYPE,
12497  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
12498  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_196_CHECKER_TYPE,
12499  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
12500  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_197_CHECKER_TYPE,
12501  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
12502  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_198_CHECKER_TYPE,
12503  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
12504  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_199_CHECKER_TYPE,
12505  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
12506  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_200_CHECKER_TYPE,
12507  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
12508  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_201_CHECKER_TYPE,
12509  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
12510  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_202_CHECKER_TYPE,
12511  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
12512  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_203_CHECKER_TYPE,
12513  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
12514  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_204_CHECKER_TYPE,
12515  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
12516  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_205_CHECKER_TYPE,
12517  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
12518  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_206_CHECKER_TYPE,
12519  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
12520  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_207_CHECKER_TYPE,
12521  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
12522  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_208_CHECKER_TYPE,
12523  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
12524  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_209_CHECKER_TYPE,
12525  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
12526  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_210_CHECKER_TYPE,
12527  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
12528  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_211_CHECKER_TYPE,
12529  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
12530  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_212_CHECKER_TYPE,
12531  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
12532  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_213_CHECKER_TYPE,
12533  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
12534  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_214_CHECKER_TYPE,
12535  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
12536  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_215_CHECKER_TYPE,
12537  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
12538  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_216_CHECKER_TYPE,
12539  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
12540  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_217_CHECKER_TYPE,
12541  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
12542  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_218_CHECKER_TYPE,
12543  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
12544  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_219_CHECKER_TYPE,
12545  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
12546  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_220_CHECKER_TYPE,
12547  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
12548  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_221_CHECKER_TYPE,
12549  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
12550  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_222_CHECKER_TYPE,
12551  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
12552  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_223_CHECKER_TYPE,
12553  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
12554  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_224_CHECKER_TYPE,
12555  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
12556  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_225_CHECKER_TYPE,
12557  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
12558  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_226_CHECKER_TYPE,
12559  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
12560  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_227_CHECKER_TYPE,
12561  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
12562  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_228_CHECKER_TYPE,
12563  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
12564  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_229_CHECKER_TYPE,
12565  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
12566  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_230_CHECKER_TYPE,
12567  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
12568  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_231_CHECKER_TYPE,
12569  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
12570  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_232_CHECKER_TYPE,
12571  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
12572  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_233_CHECKER_TYPE,
12573  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
12574  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_234_CHECKER_TYPE,
12575  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
12576  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_235_CHECKER_TYPE,
12577  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
12578  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_236_CHECKER_TYPE,
12579  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
12580  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_237_CHECKER_TYPE,
12581  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
12582  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_238_CHECKER_TYPE,
12583  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
12584  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_239_CHECKER_TYPE,
12585  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
12586  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_240_CHECKER_TYPE,
12587  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
12588  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_241_CHECKER_TYPE,
12589  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
12590  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_242_CHECKER_TYPE,
12591  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
12592  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_243_CHECKER_TYPE,
12593  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
12594  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_244_CHECKER_TYPE,
12595  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
12596  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_245_CHECKER_TYPE,
12597  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
12598  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_246_CHECKER_TYPE,
12599  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
12600  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_247_CHECKER_TYPE,
12601  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
12602  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_248_CHECKER_TYPE,
12603  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
12604  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_249_CHECKER_TYPE,
12605  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
12606  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_250_CHECKER_TYPE,
12607  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
12608  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_251_CHECKER_TYPE,
12609  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
12610  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_252_CHECKER_TYPE,
12611  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
12612  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_253_CHECKER_TYPE,
12613  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
12614  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_254_CHECKER_TYPE,
12615  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
12616  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_255_CHECKER_TYPE,
12617  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
12618 };
12619 
12625 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] =
12626 {
12627  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_0_CHECKER_TYPE,
12628  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
12629  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_1_CHECKER_TYPE,
12630  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
12631  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_2_CHECKER_TYPE,
12632  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
12633  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_3_CHECKER_TYPE,
12634  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
12635  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_4_CHECKER_TYPE,
12636  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
12637  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_5_CHECKER_TYPE,
12638  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
12639  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_6_CHECKER_TYPE,
12640  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
12641  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_7_CHECKER_TYPE,
12642  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
12643  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_8_CHECKER_TYPE,
12644  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
12645  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_9_CHECKER_TYPE,
12646  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
12647  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_10_CHECKER_TYPE,
12648  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
12649  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_11_CHECKER_TYPE,
12650  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
12651  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_12_CHECKER_TYPE,
12652  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
12653  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_13_CHECKER_TYPE,
12654  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
12655  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_14_CHECKER_TYPE,
12656  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
12657  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_15_CHECKER_TYPE,
12658  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
12659  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_16_CHECKER_TYPE,
12660  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
12661  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_17_CHECKER_TYPE,
12662  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
12663  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_18_CHECKER_TYPE,
12664  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
12665  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_19_CHECKER_TYPE,
12666  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
12667  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_20_CHECKER_TYPE,
12668  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
12669  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_21_CHECKER_TYPE,
12670  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
12671  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_22_CHECKER_TYPE,
12672  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
12673  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_23_CHECKER_TYPE,
12674  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
12675  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_24_CHECKER_TYPE,
12676  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH },
12677  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_25_CHECKER_TYPE,
12678  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH },
12679  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_26_CHECKER_TYPE,
12680  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH },
12681  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_27_CHECKER_TYPE,
12682  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH },
12683  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_28_CHECKER_TYPE,
12684  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH },
12685  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_29_CHECKER_TYPE,
12686  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH },
12687  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_30_CHECKER_TYPE,
12688  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH },
12689  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_31_CHECKER_TYPE,
12690  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH },
12691  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_32_CHECKER_TYPE,
12692  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH },
12693  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_33_CHECKER_TYPE,
12694  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH },
12695  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_34_CHECKER_TYPE,
12696  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH },
12697  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_35_CHECKER_TYPE,
12698  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH },
12699  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_36_CHECKER_TYPE,
12700  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH },
12701  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_37_CHECKER_TYPE,
12702  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH },
12703  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_38_CHECKER_TYPE,
12704  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH },
12705  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_39_CHECKER_TYPE,
12706  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH },
12707  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_40_CHECKER_TYPE,
12708  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH },
12709  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_41_CHECKER_TYPE,
12710  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH },
12711  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_42_CHECKER_TYPE,
12712  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH },
12713  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_43_CHECKER_TYPE,
12714  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_43_WIDTH },
12715  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_44_CHECKER_TYPE,
12716  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_44_WIDTH },
12717  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_45_CHECKER_TYPE,
12718  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_45_WIDTH },
12719  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_46_CHECKER_TYPE,
12720  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_46_WIDTH },
12721  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_47_CHECKER_TYPE,
12722  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_47_WIDTH },
12723  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_48_CHECKER_TYPE,
12724  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_48_WIDTH },
12725  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_49_CHECKER_TYPE,
12726  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_49_WIDTH },
12727  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_50_CHECKER_TYPE,
12728  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_50_WIDTH },
12729  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_51_CHECKER_TYPE,
12730  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_51_WIDTH },
12731  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_52_CHECKER_TYPE,
12732  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_52_WIDTH },
12733  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_53_CHECKER_TYPE,
12734  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_53_WIDTH },
12735  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_54_CHECKER_TYPE,
12736  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_54_WIDTH },
12737  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_55_CHECKER_TYPE,
12738  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_55_WIDTH },
12739  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_56_CHECKER_TYPE,
12740  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_56_WIDTH },
12741  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_57_CHECKER_TYPE,
12742  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_57_WIDTH },
12743  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_58_CHECKER_TYPE,
12744  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_58_WIDTH },
12745  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_59_CHECKER_TYPE,
12746  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_59_WIDTH },
12747  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_60_CHECKER_TYPE,
12748  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_60_WIDTH },
12749  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_61_CHECKER_TYPE,
12750  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_61_WIDTH },
12751  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_62_CHECKER_TYPE,
12752  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_62_WIDTH },
12753  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_63_CHECKER_TYPE,
12754  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_63_WIDTH },
12755  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_64_CHECKER_TYPE,
12756  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_64_WIDTH },
12757  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_65_CHECKER_TYPE,
12758  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_65_WIDTH },
12759  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_66_CHECKER_TYPE,
12760  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_66_WIDTH },
12761  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_67_CHECKER_TYPE,
12762  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_67_WIDTH },
12763  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_68_CHECKER_TYPE,
12764  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_68_WIDTH },
12765  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_69_CHECKER_TYPE,
12766  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_69_WIDTH },
12767  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_70_CHECKER_TYPE,
12768  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_70_WIDTH },
12769  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_71_CHECKER_TYPE,
12770  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_71_WIDTH },
12771  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_72_CHECKER_TYPE,
12772  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_72_WIDTH },
12773  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_73_CHECKER_TYPE,
12774  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_73_WIDTH },
12775  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_74_CHECKER_TYPE,
12776  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_74_WIDTH },
12777  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_75_CHECKER_TYPE,
12778  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_75_WIDTH },
12779  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_76_CHECKER_TYPE,
12780  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_76_WIDTH },
12781  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_77_CHECKER_TYPE,
12782  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_77_WIDTH },
12783  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_78_CHECKER_TYPE,
12784  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_78_WIDTH },
12785  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_79_CHECKER_TYPE,
12786  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_79_WIDTH },
12787  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_80_CHECKER_TYPE,
12788  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_80_WIDTH },
12789  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_81_CHECKER_TYPE,
12790  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_81_WIDTH },
12791  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_82_CHECKER_TYPE,
12792  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_82_WIDTH },
12793  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_83_CHECKER_TYPE,
12794  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_83_WIDTH },
12795  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_84_CHECKER_TYPE,
12796  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_84_WIDTH },
12797  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_85_CHECKER_TYPE,
12798  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_85_WIDTH },
12799  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_86_CHECKER_TYPE,
12800  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_86_WIDTH },
12801  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_87_CHECKER_TYPE,
12802  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_87_WIDTH },
12803  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_88_CHECKER_TYPE,
12804  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_88_WIDTH },
12805  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_89_CHECKER_TYPE,
12806  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_89_WIDTH },
12807  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_90_CHECKER_TYPE,
12808  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_90_WIDTH },
12809  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_91_CHECKER_TYPE,
12810  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_91_WIDTH },
12811  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_92_CHECKER_TYPE,
12812  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_92_WIDTH },
12813  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_93_CHECKER_TYPE,
12814  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_93_WIDTH },
12815  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_94_CHECKER_TYPE,
12816  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_94_WIDTH },
12817  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_95_CHECKER_TYPE,
12818  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_95_WIDTH },
12819  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_96_CHECKER_TYPE,
12820  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_96_WIDTH },
12821  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_97_CHECKER_TYPE,
12822  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_97_WIDTH },
12823  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_98_CHECKER_TYPE,
12824  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_98_WIDTH },
12825  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_99_CHECKER_TYPE,
12826  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_99_WIDTH },
12827  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_100_CHECKER_TYPE,
12828  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_100_WIDTH },
12829  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_101_CHECKER_TYPE,
12830  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_101_WIDTH },
12831  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_102_CHECKER_TYPE,
12832  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_102_WIDTH },
12833  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_103_CHECKER_TYPE,
12834  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_103_WIDTH },
12835  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_104_CHECKER_TYPE,
12836  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_104_WIDTH },
12837  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_105_CHECKER_TYPE,
12838  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_105_WIDTH },
12839  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_106_CHECKER_TYPE,
12840  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_106_WIDTH },
12841  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_107_CHECKER_TYPE,
12842  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_107_WIDTH },
12843  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_108_CHECKER_TYPE,
12844  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_108_WIDTH },
12845  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_109_CHECKER_TYPE,
12846  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_109_WIDTH },
12847  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_110_CHECKER_TYPE,
12848  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_110_WIDTH },
12849  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_111_CHECKER_TYPE,
12850  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_111_WIDTH },
12851  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_112_CHECKER_TYPE,
12852  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_112_WIDTH },
12853  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_113_CHECKER_TYPE,
12854  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_113_WIDTH },
12855  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_114_CHECKER_TYPE,
12856  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_114_WIDTH },
12857  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_115_CHECKER_TYPE,
12858  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_115_WIDTH },
12859  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_116_CHECKER_TYPE,
12860  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_116_WIDTH },
12861  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_117_CHECKER_TYPE,
12862  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_117_WIDTH },
12863  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_118_CHECKER_TYPE,
12864  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_118_WIDTH },
12865  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_119_CHECKER_TYPE,
12866  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_119_WIDTH },
12867  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_120_CHECKER_TYPE,
12868  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_120_WIDTH },
12869  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_121_CHECKER_TYPE,
12870  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_121_WIDTH },
12871  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_122_CHECKER_TYPE,
12872  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_122_WIDTH },
12873  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_123_CHECKER_TYPE,
12874  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_123_WIDTH },
12875  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_124_CHECKER_TYPE,
12876  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_124_WIDTH },
12877  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_125_CHECKER_TYPE,
12878  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_125_WIDTH },
12879  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_126_CHECKER_TYPE,
12880  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_126_WIDTH },
12881  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_127_CHECKER_TYPE,
12882  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_127_WIDTH },
12883  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_128_CHECKER_TYPE,
12884  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_128_WIDTH },
12885  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_129_CHECKER_TYPE,
12886  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_129_WIDTH },
12887  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_130_CHECKER_TYPE,
12888  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_130_WIDTH },
12889  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_131_CHECKER_TYPE,
12890  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_131_WIDTH },
12891  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_132_CHECKER_TYPE,
12892  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_132_WIDTH },
12893  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_133_CHECKER_TYPE,
12894  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_133_WIDTH },
12895  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_134_CHECKER_TYPE,
12896  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_134_WIDTH },
12897  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_135_CHECKER_TYPE,
12898  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_135_WIDTH },
12899  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_136_CHECKER_TYPE,
12900  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_136_WIDTH },
12901  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_137_CHECKER_TYPE,
12902  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_137_WIDTH },
12903  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_138_CHECKER_TYPE,
12904  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_138_WIDTH },
12905  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_139_CHECKER_TYPE,
12906  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_139_WIDTH },
12907  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_140_CHECKER_TYPE,
12908  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_140_WIDTH },
12909  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_141_CHECKER_TYPE,
12910  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_141_WIDTH },
12911  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_142_CHECKER_TYPE,
12912  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_142_WIDTH },
12913  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_143_CHECKER_TYPE,
12914  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_143_WIDTH },
12915  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_144_CHECKER_TYPE,
12916  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_144_WIDTH },
12917  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_145_CHECKER_TYPE,
12918  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_145_WIDTH },
12919  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_146_CHECKER_TYPE,
12920  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_146_WIDTH },
12921  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_147_CHECKER_TYPE,
12922  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_147_WIDTH },
12923  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_148_CHECKER_TYPE,
12924  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_148_WIDTH },
12925  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_149_CHECKER_TYPE,
12926  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_149_WIDTH },
12927  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_150_CHECKER_TYPE,
12928  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_150_WIDTH },
12929  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_151_CHECKER_TYPE,
12930  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_151_WIDTH },
12931  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_152_CHECKER_TYPE,
12932  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_152_WIDTH },
12933  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_153_CHECKER_TYPE,
12934  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_153_WIDTH },
12935  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_154_CHECKER_TYPE,
12936  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_154_WIDTH },
12937  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_155_CHECKER_TYPE,
12938  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_155_WIDTH },
12939  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_156_CHECKER_TYPE,
12940  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_156_WIDTH },
12941  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_157_CHECKER_TYPE,
12942  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_157_WIDTH },
12943  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_158_CHECKER_TYPE,
12944  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_158_WIDTH },
12945  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_159_CHECKER_TYPE,
12946  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_159_WIDTH },
12947  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_160_CHECKER_TYPE,
12948  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_160_WIDTH },
12949  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_161_CHECKER_TYPE,
12950  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_161_WIDTH },
12951  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_162_CHECKER_TYPE,
12952  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_162_WIDTH },
12953  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_163_CHECKER_TYPE,
12954  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_163_WIDTH },
12955  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_164_CHECKER_TYPE,
12956  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_164_WIDTH },
12957  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_165_CHECKER_TYPE,
12958  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_165_WIDTH },
12959  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_166_CHECKER_TYPE,
12960  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_166_WIDTH },
12961  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_167_CHECKER_TYPE,
12962  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_167_WIDTH },
12963  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_168_CHECKER_TYPE,
12964  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_168_WIDTH },
12965  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_169_CHECKER_TYPE,
12966  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_169_WIDTH },
12967  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_170_CHECKER_TYPE,
12968  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_170_WIDTH },
12969  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_171_CHECKER_TYPE,
12970  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_171_WIDTH },
12971  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_172_CHECKER_TYPE,
12972  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_172_WIDTH },
12973  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_173_CHECKER_TYPE,
12974  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_173_WIDTH },
12975  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_174_CHECKER_TYPE,
12976  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_174_WIDTH },
12977  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_175_CHECKER_TYPE,
12978  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_175_WIDTH },
12979  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_176_CHECKER_TYPE,
12980  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_176_WIDTH },
12981  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_177_CHECKER_TYPE,
12982  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_177_WIDTH },
12983  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_178_CHECKER_TYPE,
12984  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_178_WIDTH },
12985  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_179_CHECKER_TYPE,
12986  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_179_WIDTH },
12987  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_180_CHECKER_TYPE,
12988  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_180_WIDTH },
12989  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_181_CHECKER_TYPE,
12990  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_181_WIDTH },
12991  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_182_CHECKER_TYPE,
12992  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_182_WIDTH },
12993  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_183_CHECKER_TYPE,
12994  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_183_WIDTH },
12995  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_184_CHECKER_TYPE,
12996  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_184_WIDTH },
12997  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_185_CHECKER_TYPE,
12998  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_185_WIDTH },
12999  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_186_CHECKER_TYPE,
13000  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_186_WIDTH },
13001  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_187_CHECKER_TYPE,
13002  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_187_WIDTH },
13003  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_188_CHECKER_TYPE,
13004  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_188_WIDTH },
13005  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_189_CHECKER_TYPE,
13006  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_189_WIDTH },
13007  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_190_CHECKER_TYPE,
13008  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_190_WIDTH },
13009  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_191_CHECKER_TYPE,
13010  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_191_WIDTH },
13011  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_192_CHECKER_TYPE,
13012  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_192_WIDTH },
13013  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_193_CHECKER_TYPE,
13014  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_193_WIDTH },
13015  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_194_CHECKER_TYPE,
13016  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_194_WIDTH },
13017  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_195_CHECKER_TYPE,
13018  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_195_WIDTH },
13019  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_196_CHECKER_TYPE,
13020  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_196_WIDTH },
13021  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_197_CHECKER_TYPE,
13022  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_197_WIDTH },
13023  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_198_CHECKER_TYPE,
13024  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_198_WIDTH },
13025  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_199_CHECKER_TYPE,
13026  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_199_WIDTH },
13027  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_200_CHECKER_TYPE,
13028  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_200_WIDTH },
13029  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_201_CHECKER_TYPE,
13030  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_201_WIDTH },
13031  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_202_CHECKER_TYPE,
13032  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_202_WIDTH },
13033  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_203_CHECKER_TYPE,
13034  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_203_WIDTH },
13035  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_204_CHECKER_TYPE,
13036  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_204_WIDTH },
13037  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_205_CHECKER_TYPE,
13038  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_205_WIDTH },
13039  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_206_CHECKER_TYPE,
13040  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_206_WIDTH },
13041  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_207_CHECKER_TYPE,
13042  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_207_WIDTH },
13043  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_208_CHECKER_TYPE,
13044  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_208_WIDTH },
13045  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_209_CHECKER_TYPE,
13046  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_209_WIDTH },
13047  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_210_CHECKER_TYPE,
13048  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_210_WIDTH },
13049  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_211_CHECKER_TYPE,
13050  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_211_WIDTH },
13051  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_212_CHECKER_TYPE,
13052  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_212_WIDTH },
13053  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_213_CHECKER_TYPE,
13054  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_213_WIDTH },
13055  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_214_CHECKER_TYPE,
13056  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_214_WIDTH },
13057  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_215_CHECKER_TYPE,
13058  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_215_WIDTH },
13059  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_216_CHECKER_TYPE,
13060  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_216_WIDTH },
13061  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_217_CHECKER_TYPE,
13062  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_217_WIDTH },
13063  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_218_CHECKER_TYPE,
13064  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_218_WIDTH },
13065  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_219_CHECKER_TYPE,
13066  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_219_WIDTH },
13067  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_220_CHECKER_TYPE,
13068  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_220_WIDTH },
13069  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_221_CHECKER_TYPE,
13070  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_221_WIDTH },
13071  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_222_CHECKER_TYPE,
13072  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_222_WIDTH },
13073  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_223_CHECKER_TYPE,
13074  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_223_WIDTH },
13075  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_224_CHECKER_TYPE,
13076  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_224_WIDTH },
13077  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_225_CHECKER_TYPE,
13078  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_225_WIDTH },
13079  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_226_CHECKER_TYPE,
13080  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_226_WIDTH },
13081  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_227_CHECKER_TYPE,
13082  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_227_WIDTH },
13083  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_228_CHECKER_TYPE,
13084  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_228_WIDTH },
13085  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_229_CHECKER_TYPE,
13086  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_229_WIDTH },
13087  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_230_CHECKER_TYPE,
13088  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_230_WIDTH },
13089  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_231_CHECKER_TYPE,
13090  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_231_WIDTH },
13091  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_232_CHECKER_TYPE,
13092  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_232_WIDTH },
13093  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_233_CHECKER_TYPE,
13094  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_233_WIDTH },
13095  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_234_CHECKER_TYPE,
13096  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_234_WIDTH },
13097  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_235_CHECKER_TYPE,
13098  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_235_WIDTH },
13099  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_236_CHECKER_TYPE,
13100  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_236_WIDTH },
13101  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_237_CHECKER_TYPE,
13102  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_237_WIDTH },
13103  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_238_CHECKER_TYPE,
13104  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_238_WIDTH },
13105  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_239_CHECKER_TYPE,
13106  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_239_WIDTH },
13107  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_240_CHECKER_TYPE,
13108  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_240_WIDTH },
13109  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_241_CHECKER_TYPE,
13110  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_241_WIDTH },
13111  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_242_CHECKER_TYPE,
13112  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_242_WIDTH },
13113  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_243_CHECKER_TYPE,
13114  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_243_WIDTH },
13115  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_244_CHECKER_TYPE,
13116  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_244_WIDTH },
13117  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_245_CHECKER_TYPE,
13118  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_245_WIDTH },
13119  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_246_CHECKER_TYPE,
13120  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_246_WIDTH },
13121  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_247_CHECKER_TYPE,
13122  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_247_WIDTH },
13123  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_248_CHECKER_TYPE,
13124  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_248_WIDTH },
13125  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_249_CHECKER_TYPE,
13126  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_249_WIDTH },
13127  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_250_CHECKER_TYPE,
13128  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_250_WIDTH },
13129  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_251_CHECKER_TYPE,
13130  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_251_WIDTH },
13131  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_252_CHECKER_TYPE,
13132  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_252_WIDTH },
13133  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_253_CHECKER_TYPE,
13134  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_253_WIDTH },
13135  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_254_CHECKER_TYPE,
13136  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_254_WIDTH },
13137  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_255_CHECKER_TYPE,
13138  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_255_WIDTH },
13139 };
13140 
13146 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS] =
13147 {
13148  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_0_CHECKER_TYPE,
13149  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_0_WIDTH },
13150  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_1_CHECKER_TYPE,
13151  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_1_WIDTH },
13152  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_2_CHECKER_TYPE,
13153  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_2_WIDTH },
13154  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_3_CHECKER_TYPE,
13155  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_3_WIDTH },
13156  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_4_CHECKER_TYPE,
13157  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_4_WIDTH },
13158  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_5_CHECKER_TYPE,
13159  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_5_WIDTH },
13160  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_6_CHECKER_TYPE,
13161  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_6_WIDTH },
13162  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_7_CHECKER_TYPE,
13163  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_7_WIDTH },
13164  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_8_CHECKER_TYPE,
13165  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_8_WIDTH },
13166  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_9_CHECKER_TYPE,
13167  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_9_WIDTH },
13168  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_10_CHECKER_TYPE,
13169  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_10_WIDTH },
13170  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_11_CHECKER_TYPE,
13171  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_11_WIDTH },
13172  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_12_CHECKER_TYPE,
13173  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_12_WIDTH },
13174  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_13_CHECKER_TYPE,
13175  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_13_WIDTH },
13176  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_14_CHECKER_TYPE,
13177  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_14_WIDTH },
13178  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_15_CHECKER_TYPE,
13179  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_15_WIDTH },
13180  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_16_CHECKER_TYPE,
13181  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_16_WIDTH },
13182  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_17_CHECKER_TYPE,
13183  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_17_WIDTH },
13184  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_18_CHECKER_TYPE,
13185  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_18_WIDTH },
13186  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_19_CHECKER_TYPE,
13187  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_19_WIDTH },
13188  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_20_CHECKER_TYPE,
13189  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_20_WIDTH },
13190  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_21_CHECKER_TYPE,
13191  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_21_WIDTH },
13192  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_22_CHECKER_TYPE,
13193  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_22_WIDTH },
13194  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_23_CHECKER_TYPE,
13195  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_23_WIDTH },
13196  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_24_CHECKER_TYPE,
13197  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_24_WIDTH },
13198  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_25_CHECKER_TYPE,
13199  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_25_WIDTH },
13200  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_26_CHECKER_TYPE,
13201  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_26_WIDTH },
13202  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_27_CHECKER_TYPE,
13203  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_27_WIDTH },
13204  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_28_CHECKER_TYPE,
13205  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_28_WIDTH },
13206  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_29_CHECKER_TYPE,
13207  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_29_WIDTH },
13208  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_30_CHECKER_TYPE,
13209  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_30_WIDTH },
13210  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_31_CHECKER_TYPE,
13211  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_31_WIDTH },
13212  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_32_CHECKER_TYPE,
13213  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_32_WIDTH },
13214  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_33_CHECKER_TYPE,
13215  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_33_WIDTH },
13216  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_34_CHECKER_TYPE,
13217  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_34_WIDTH },
13218  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_35_CHECKER_TYPE,
13219  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_35_WIDTH },
13220  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_36_CHECKER_TYPE,
13221  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_36_WIDTH },
13222  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_37_CHECKER_TYPE,
13223  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_37_WIDTH },
13224  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_38_CHECKER_TYPE,
13225  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_38_WIDTH },
13226  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_39_CHECKER_TYPE,
13227  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_39_WIDTH },
13228  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_40_CHECKER_TYPE,
13229  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_40_WIDTH },
13230  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_41_CHECKER_TYPE,
13231  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_41_WIDTH },
13232  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_42_CHECKER_TYPE,
13233  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_42_WIDTH },
13234  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_43_CHECKER_TYPE,
13235  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_43_WIDTH },
13236  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_44_CHECKER_TYPE,
13237  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_44_WIDTH },
13238  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_45_CHECKER_TYPE,
13239  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_45_WIDTH },
13240  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_46_CHECKER_TYPE,
13241  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_46_WIDTH },
13242  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_47_CHECKER_TYPE,
13243  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_47_WIDTH },
13244  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_48_CHECKER_TYPE,
13245  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_48_WIDTH },
13246  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_49_CHECKER_TYPE,
13247  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_49_WIDTH },
13248  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_50_CHECKER_TYPE,
13249  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_50_WIDTH },
13250  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_51_CHECKER_TYPE,
13251  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_51_WIDTH },
13252  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_52_CHECKER_TYPE,
13253  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_52_WIDTH },
13254  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_53_CHECKER_TYPE,
13255  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_53_WIDTH },
13256  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_54_CHECKER_TYPE,
13257  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_54_WIDTH },
13258  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_55_CHECKER_TYPE,
13259  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_55_WIDTH },
13260  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_56_CHECKER_TYPE,
13261  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_56_WIDTH },
13262  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_57_CHECKER_TYPE,
13263  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_57_WIDTH },
13264  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_58_CHECKER_TYPE,
13265  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_58_WIDTH },
13266  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_59_CHECKER_TYPE,
13267  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_59_WIDTH },
13268  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_60_CHECKER_TYPE,
13269  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_60_WIDTH },
13270  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_61_CHECKER_TYPE,
13271  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_61_WIDTH },
13272  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_62_CHECKER_TYPE,
13273  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_62_WIDTH },
13274  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_63_CHECKER_TYPE,
13275  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_63_WIDTH },
13276  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_64_CHECKER_TYPE,
13277  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_64_WIDTH },
13278  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_65_CHECKER_TYPE,
13279  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_65_WIDTH },
13280  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_66_CHECKER_TYPE,
13281  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_66_WIDTH },
13282  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_67_CHECKER_TYPE,
13283  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_67_WIDTH },
13284  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_68_CHECKER_TYPE,
13285  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_68_WIDTH },
13286  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_69_CHECKER_TYPE,
13287  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_69_WIDTH },
13288  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_70_CHECKER_TYPE,
13289  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_70_WIDTH },
13290  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_71_CHECKER_TYPE,
13291  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_71_WIDTH },
13292  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_72_CHECKER_TYPE,
13293  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_72_WIDTH },
13294  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_73_CHECKER_TYPE,
13295  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_73_WIDTH },
13296  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_74_CHECKER_TYPE,
13297  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_74_WIDTH },
13298  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_75_CHECKER_TYPE,
13299  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_75_WIDTH },
13300  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_76_CHECKER_TYPE,
13301  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_76_WIDTH },
13302  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_77_CHECKER_TYPE,
13303  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_77_WIDTH },
13304  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_78_CHECKER_TYPE,
13305  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_78_WIDTH },
13306  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_79_CHECKER_TYPE,
13307  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_79_WIDTH },
13308  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_80_CHECKER_TYPE,
13309  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_80_WIDTH },
13310  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_81_CHECKER_TYPE,
13311  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_81_WIDTH },
13312  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_82_CHECKER_TYPE,
13313  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_82_WIDTH },
13314  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_83_CHECKER_TYPE,
13315  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_83_WIDTH },
13316  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_84_CHECKER_TYPE,
13317  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_84_WIDTH },
13318  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_85_CHECKER_TYPE,
13319  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_85_WIDTH },
13320  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_86_CHECKER_TYPE,
13321  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_86_WIDTH },
13322  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_87_CHECKER_TYPE,
13323  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_87_WIDTH },
13324  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_88_CHECKER_TYPE,
13325  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_88_WIDTH },
13326  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_89_CHECKER_TYPE,
13327  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_89_WIDTH },
13328  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_90_CHECKER_TYPE,
13329  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_90_WIDTH },
13330  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_91_CHECKER_TYPE,
13331  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_91_WIDTH },
13332  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_92_CHECKER_TYPE,
13333  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_92_WIDTH },
13334  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_93_CHECKER_TYPE,
13335  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_93_WIDTH },
13336  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_94_CHECKER_TYPE,
13337  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_94_WIDTH },
13338  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_95_CHECKER_TYPE,
13339  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_95_WIDTH },
13340  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_96_CHECKER_TYPE,
13341  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_96_WIDTH },
13342  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_97_CHECKER_TYPE,
13343  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_97_WIDTH },
13344  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_98_CHECKER_TYPE,
13345  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_98_WIDTH },
13346  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_99_CHECKER_TYPE,
13347  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_99_WIDTH },
13348  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_100_CHECKER_TYPE,
13349  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_100_WIDTH },
13350  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_101_CHECKER_TYPE,
13351  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_101_WIDTH },
13352  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_102_CHECKER_TYPE,
13353  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_102_WIDTH },
13354  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_103_CHECKER_TYPE,
13355  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_103_WIDTH },
13356  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_104_CHECKER_TYPE,
13357  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_104_WIDTH },
13358  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_105_CHECKER_TYPE,
13359  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_105_WIDTH },
13360  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_106_CHECKER_TYPE,
13361  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_106_WIDTH },
13362  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_107_CHECKER_TYPE,
13363  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_107_WIDTH },
13364  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_108_CHECKER_TYPE,
13365  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_108_WIDTH },
13366  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_109_CHECKER_TYPE,
13367  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_109_WIDTH },
13368  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_110_CHECKER_TYPE,
13369  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_110_WIDTH },
13370  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_111_CHECKER_TYPE,
13371  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_111_WIDTH },
13372  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_112_CHECKER_TYPE,
13373  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_112_WIDTH },
13374  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_113_CHECKER_TYPE,
13375  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_113_WIDTH },
13376  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_114_CHECKER_TYPE,
13377  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_114_WIDTH },
13378  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_115_CHECKER_TYPE,
13379  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_115_WIDTH },
13380  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_116_CHECKER_TYPE,
13381  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_116_WIDTH },
13382  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_117_CHECKER_TYPE,
13383  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_117_WIDTH },
13384  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_118_CHECKER_TYPE,
13385  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_118_WIDTH },
13386  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_119_CHECKER_TYPE,
13387  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_119_WIDTH },
13388  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_120_CHECKER_TYPE,
13389  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_120_WIDTH },
13390  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_121_CHECKER_TYPE,
13391  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_121_WIDTH },
13392  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_122_CHECKER_TYPE,
13393  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_122_WIDTH },
13394  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_123_CHECKER_TYPE,
13395  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_123_WIDTH },
13396  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_124_CHECKER_TYPE,
13397  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_124_WIDTH },
13398  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_125_CHECKER_TYPE,
13399  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_125_WIDTH },
13400  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_126_CHECKER_TYPE,
13401  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_126_WIDTH },
13402  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_127_CHECKER_TYPE,
13403  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_127_WIDTH },
13404  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_128_CHECKER_TYPE,
13405  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_128_WIDTH },
13406  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_129_CHECKER_TYPE,
13407  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_129_WIDTH },
13408  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_130_CHECKER_TYPE,
13409  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_130_WIDTH },
13410  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_131_CHECKER_TYPE,
13411  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_131_WIDTH },
13412  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_132_CHECKER_TYPE,
13413  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_132_WIDTH },
13414  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_133_CHECKER_TYPE,
13415  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_133_WIDTH },
13416  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_134_CHECKER_TYPE,
13417  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_134_WIDTH },
13418  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_135_CHECKER_TYPE,
13419  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_135_WIDTH },
13420  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_136_CHECKER_TYPE,
13421  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_136_WIDTH },
13422  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_137_CHECKER_TYPE,
13423  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_137_WIDTH },
13424  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_138_CHECKER_TYPE,
13425  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_138_WIDTH },
13426  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_139_CHECKER_TYPE,
13427  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_139_WIDTH },
13428  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_140_CHECKER_TYPE,
13429  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_140_WIDTH },
13430  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_141_CHECKER_TYPE,
13431  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_141_WIDTH },
13432  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_142_CHECKER_TYPE,
13433  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_142_WIDTH },
13434  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_143_CHECKER_TYPE,
13435  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_143_WIDTH },
13436  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_144_CHECKER_TYPE,
13437  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_144_WIDTH },
13438  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_145_CHECKER_TYPE,
13439  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_145_WIDTH },
13440  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_146_CHECKER_TYPE,
13441  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_146_WIDTH },
13442  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_147_CHECKER_TYPE,
13443  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_147_WIDTH },
13444  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_148_CHECKER_TYPE,
13445  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_148_WIDTH },
13446  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_149_CHECKER_TYPE,
13447  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_149_WIDTH },
13448  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_150_CHECKER_TYPE,
13449  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_150_WIDTH },
13450  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_151_CHECKER_TYPE,
13451  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_151_WIDTH },
13452  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_152_CHECKER_TYPE,
13453  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_152_WIDTH },
13454  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_153_CHECKER_TYPE,
13455  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_153_WIDTH },
13456  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_154_CHECKER_TYPE,
13457  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_154_WIDTH },
13458  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_155_CHECKER_TYPE,
13459  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_155_WIDTH },
13460  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_156_CHECKER_TYPE,
13461  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_156_WIDTH },
13462  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_157_CHECKER_TYPE,
13463  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_157_WIDTH },
13464  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_158_CHECKER_TYPE,
13465  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_158_WIDTH },
13466  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_159_CHECKER_TYPE,
13467  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_159_WIDTH },
13468  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_160_CHECKER_TYPE,
13469  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_160_WIDTH },
13470  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_161_CHECKER_TYPE,
13471  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_161_WIDTH },
13472  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_162_CHECKER_TYPE,
13473  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_162_WIDTH },
13474  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_163_CHECKER_TYPE,
13475  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_163_WIDTH },
13476  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_164_CHECKER_TYPE,
13477  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_164_WIDTH },
13478  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_165_CHECKER_TYPE,
13479  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_165_WIDTH },
13480  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_166_CHECKER_TYPE,
13481  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_166_WIDTH },
13482  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_167_CHECKER_TYPE,
13483  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_167_WIDTH },
13484  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_168_CHECKER_TYPE,
13485  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_168_WIDTH },
13486  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_169_CHECKER_TYPE,
13487  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_169_WIDTH },
13488  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_170_CHECKER_TYPE,
13489  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_170_WIDTH },
13490  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_171_CHECKER_TYPE,
13491  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_171_WIDTH },
13492 };
13493 
13499 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_ISAM62A_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_ISAM62A_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_MAX_NUM_CHECKERS] =
13500 {
13501  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_ISAM62A_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_0_CHECKER_TYPE,
13502  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_ISAM62A_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_GROUP_0_WIDTH },
13503 };
13504 
13510 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
13511 {
13512  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
13513  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
13514  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
13515  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
13516  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
13517  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
13518  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
13519  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_3_WIDTH },
13520  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
13521  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_4_WIDTH },
13522  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
13523  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_5_WIDTH },
13524  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
13525  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_6_WIDTH },
13526  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
13527  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_7_WIDTH },
13528  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
13529  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_8_WIDTH },
13530  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
13531  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_9_WIDTH },
13532  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
13533  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_10_WIDTH },
13534  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
13535  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_11_WIDTH },
13536  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
13537  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_12_WIDTH },
13538 };
13539 
13545 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
13546 {
13547  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
13548  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
13549  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
13550  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
13551  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
13552  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
13553  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
13554  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_3_WIDTH },
13555  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
13556  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_4_WIDTH },
13557  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
13558  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_5_WIDTH },
13559  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
13560  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_6_WIDTH },
13561  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
13562  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_7_WIDTH },
13563  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
13564  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_8_WIDTH },
13565  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
13566  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_9_WIDTH },
13567  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
13568  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_10_WIDTH },
13569  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
13570  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_11_WIDTH },
13571  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
13572  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_12_WIDTH },
13573 };
13574 
13580 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS] =
13581 {
13582  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_0_CHECKER_TYPE,
13583  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_0_WIDTH },
13584  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_1_CHECKER_TYPE,
13585  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_1_WIDTH },
13586  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_2_CHECKER_TYPE,
13587  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_2_WIDTH },
13588  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_3_CHECKER_TYPE,
13589  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_3_WIDTH },
13590  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_4_CHECKER_TYPE,
13591  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_4_WIDTH },
13592  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_5_CHECKER_TYPE,
13593  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_5_WIDTH },
13594  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_6_CHECKER_TYPE,
13595  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_6_WIDTH },
13596  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_7_CHECKER_TYPE,
13597  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_7_WIDTH },
13598  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_8_CHECKER_TYPE,
13599  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_8_WIDTH },
13600  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_9_CHECKER_TYPE,
13601  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_9_WIDTH },
13602  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_10_CHECKER_TYPE,
13603  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_10_WIDTH },
13604  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_11_CHECKER_TYPE,
13605  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_11_WIDTH },
13606  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_12_CHECKER_TYPE,
13607  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_12_WIDTH },
13608  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_13_CHECKER_TYPE,
13609  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_13_WIDTH },
13610  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_14_CHECKER_TYPE,
13611  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_14_WIDTH },
13612  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_15_CHECKER_TYPE,
13613  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_15_WIDTH },
13614  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_16_CHECKER_TYPE,
13615  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_16_WIDTH },
13616  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_17_CHECKER_TYPE,
13617  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_17_WIDTH },
13618  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_18_CHECKER_TYPE,
13619  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_18_WIDTH },
13620  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_19_CHECKER_TYPE,
13621  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_19_WIDTH },
13622  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_20_CHECKER_TYPE,
13623  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_20_WIDTH },
13624  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_21_CHECKER_TYPE,
13625  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_21_WIDTH },
13626  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_22_CHECKER_TYPE,
13627  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_22_WIDTH },
13628  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_23_CHECKER_TYPE,
13629  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_23_WIDTH },
13630  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_24_CHECKER_TYPE,
13631  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_24_WIDTH },
13632  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_25_CHECKER_TYPE,
13633  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_25_WIDTH },
13634  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_26_CHECKER_TYPE,
13635  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_26_WIDTH },
13636  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_27_CHECKER_TYPE,
13637  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_27_WIDTH },
13638  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_28_CHECKER_TYPE,
13639  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_28_WIDTH },
13640  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_29_CHECKER_TYPE,
13641  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_29_WIDTH },
13642  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_30_CHECKER_TYPE,
13643  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_30_WIDTH },
13644  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_31_CHECKER_TYPE,
13645  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_31_WIDTH },
13646  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_32_CHECKER_TYPE,
13647  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_32_WIDTH },
13648  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_33_CHECKER_TYPE,
13649  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_33_WIDTH },
13650  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_34_CHECKER_TYPE,
13651  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_34_WIDTH },
13652  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_35_CHECKER_TYPE,
13653  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_35_WIDTH },
13654  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_36_CHECKER_TYPE,
13655  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_36_WIDTH },
13656  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_37_CHECKER_TYPE,
13657  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_37_WIDTH },
13658  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_38_CHECKER_TYPE,
13659  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_38_WIDTH },
13660  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_39_CHECKER_TYPE,
13661  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_39_WIDTH },
13662  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_40_CHECKER_TYPE,
13663  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_40_WIDTH },
13664  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_41_CHECKER_TYPE,
13665  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_41_WIDTH },
13666  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_42_CHECKER_TYPE,
13667  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_42_WIDTH },
13668  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_43_CHECKER_TYPE,
13669  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_43_WIDTH },
13670  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_44_CHECKER_TYPE,
13671  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_44_WIDTH },
13672  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_45_CHECKER_TYPE,
13673  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_45_WIDTH },
13674  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_46_CHECKER_TYPE,
13675  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_46_WIDTH },
13676  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_47_CHECKER_TYPE,
13677  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_47_WIDTH },
13678  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_48_CHECKER_TYPE,
13679  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_48_WIDTH },
13680  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_49_CHECKER_TYPE,
13681  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_49_WIDTH },
13682  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_50_CHECKER_TYPE,
13683  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_50_WIDTH },
13684  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_51_CHECKER_TYPE,
13685  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_51_WIDTH },
13686  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_52_CHECKER_TYPE,
13687  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_52_WIDTH },
13688  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_53_CHECKER_TYPE,
13689  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_53_WIDTH },
13690  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_54_CHECKER_TYPE,
13691  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_54_WIDTH },
13692  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_55_CHECKER_TYPE,
13693  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_55_WIDTH },
13694  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_56_CHECKER_TYPE,
13695  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_56_WIDTH },
13696  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_57_CHECKER_TYPE,
13697  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_57_WIDTH },
13698  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_58_CHECKER_TYPE,
13699  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_58_WIDTH },
13700  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_59_CHECKER_TYPE,
13701  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_59_WIDTH },
13702  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_60_CHECKER_TYPE,
13703  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_60_WIDTH },
13704  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_61_CHECKER_TYPE,
13705  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_61_WIDTH },
13706  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_62_CHECKER_TYPE,
13707  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_62_WIDTH },
13708  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_63_CHECKER_TYPE,
13709  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_63_WIDTH },
13710  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_64_CHECKER_TYPE,
13711  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_64_WIDTH },
13712  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_65_CHECKER_TYPE,
13713  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_65_WIDTH },
13714  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_66_CHECKER_TYPE,
13715  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_66_WIDTH },
13716  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_67_CHECKER_TYPE,
13717  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_67_WIDTH },
13718  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_68_CHECKER_TYPE,
13719  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_68_WIDTH },
13720  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_69_CHECKER_TYPE,
13721  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_69_WIDTH },
13722  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_70_CHECKER_TYPE,
13723  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_70_WIDTH },
13724  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_71_CHECKER_TYPE,
13725  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_71_WIDTH },
13726  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_72_CHECKER_TYPE,
13727  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_72_WIDTH },
13728  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_73_CHECKER_TYPE,
13729  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_73_WIDTH },
13730  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_74_CHECKER_TYPE,
13731  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_74_WIDTH },
13732  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_75_CHECKER_TYPE,
13733  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_75_WIDTH },
13734  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_76_CHECKER_TYPE,
13735  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_76_WIDTH },
13736  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_77_CHECKER_TYPE,
13737  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_77_WIDTH },
13738  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_78_CHECKER_TYPE,
13739  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_78_WIDTH },
13740  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_79_CHECKER_TYPE,
13741  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_79_WIDTH },
13742  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_80_CHECKER_TYPE,
13743  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_80_WIDTH },
13744  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_81_CHECKER_TYPE,
13745  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_81_WIDTH },
13746  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_82_CHECKER_TYPE,
13747  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_82_WIDTH },
13748  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_83_CHECKER_TYPE,
13749  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_83_WIDTH },
13750  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_84_CHECKER_TYPE,
13751  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_84_WIDTH },
13752  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_85_CHECKER_TYPE,
13753  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_85_WIDTH },
13754  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_86_CHECKER_TYPE,
13755  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_86_WIDTH },
13756  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_87_CHECKER_TYPE,
13757  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_87_WIDTH },
13758  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_88_CHECKER_TYPE,
13759  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_88_WIDTH },
13760  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_89_CHECKER_TYPE,
13761  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_89_WIDTH },
13762  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_90_CHECKER_TYPE,
13763  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_90_WIDTH },
13764  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_91_CHECKER_TYPE,
13765  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_91_WIDTH },
13766  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_92_CHECKER_TYPE,
13767  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_92_WIDTH },
13768  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_93_CHECKER_TYPE,
13769  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_93_WIDTH },
13770  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_94_CHECKER_TYPE,
13771  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_94_WIDTH },
13772  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_95_CHECKER_TYPE,
13773  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_95_WIDTH },
13774  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_96_CHECKER_TYPE,
13775  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_96_WIDTH },
13776  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_97_CHECKER_TYPE,
13777  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_97_WIDTH },
13778  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_98_CHECKER_TYPE,
13779  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_98_WIDTH },
13780  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_99_CHECKER_TYPE,
13781  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_99_WIDTH },
13782  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_100_CHECKER_TYPE,
13783  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_100_WIDTH },
13784  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_101_CHECKER_TYPE,
13785  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_101_WIDTH },
13786  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_102_CHECKER_TYPE,
13787  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_102_WIDTH },
13788  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_103_CHECKER_TYPE,
13789  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_103_WIDTH },
13790  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_104_CHECKER_TYPE,
13791  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_104_WIDTH },
13792  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_105_CHECKER_TYPE,
13793  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_105_WIDTH },
13794  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_106_CHECKER_TYPE,
13795  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_106_WIDTH },
13796  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_107_CHECKER_TYPE,
13797  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_107_WIDTH },
13798  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_108_CHECKER_TYPE,
13799  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_108_WIDTH },
13800  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_109_CHECKER_TYPE,
13801  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_109_WIDTH },
13802  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_110_CHECKER_TYPE,
13803  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_110_WIDTH },
13804  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_111_CHECKER_TYPE,
13805  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_111_WIDTH },
13806  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_112_CHECKER_TYPE,
13807  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_112_WIDTH },
13808  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_113_CHECKER_TYPE,
13809  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_113_WIDTH },
13810  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_114_CHECKER_TYPE,
13811  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_114_WIDTH },
13812  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_115_CHECKER_TYPE,
13813  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_115_WIDTH },
13814  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_116_CHECKER_TYPE,
13815  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_116_WIDTH },
13816  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_117_CHECKER_TYPE,
13817  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_117_WIDTH },
13818  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_118_CHECKER_TYPE,
13819  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_118_WIDTH },
13820  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_119_CHECKER_TYPE,
13821  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_119_WIDTH },
13822  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_120_CHECKER_TYPE,
13823  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_120_WIDTH },
13824 };
13825 
13831 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] =
13832 {
13833  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_0_CHECKER_TYPE,
13834  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
13835  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_1_CHECKER_TYPE,
13836  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
13837  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_2_CHECKER_TYPE,
13838  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
13839  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_3_CHECKER_TYPE,
13840  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
13841  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_4_CHECKER_TYPE,
13842  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
13843  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_5_CHECKER_TYPE,
13844  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
13845  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_6_CHECKER_TYPE,
13846  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
13847  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_7_CHECKER_TYPE,
13848  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
13849  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_8_CHECKER_TYPE,
13850  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
13851  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_9_CHECKER_TYPE,
13852  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
13853  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_10_CHECKER_TYPE,
13854  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
13855  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_11_CHECKER_TYPE,
13856  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
13857  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_12_CHECKER_TYPE,
13858  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
13859  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_13_CHECKER_TYPE,
13860  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
13861  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_14_CHECKER_TYPE,
13862  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
13863  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_15_CHECKER_TYPE,
13864  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
13865  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_16_CHECKER_TYPE,
13866  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
13867  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_17_CHECKER_TYPE,
13868  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
13869  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_18_CHECKER_TYPE,
13870  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
13871  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_19_CHECKER_TYPE,
13872  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
13873  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_20_CHECKER_TYPE,
13874  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
13875  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_21_CHECKER_TYPE,
13876  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
13877  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_22_CHECKER_TYPE,
13878  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
13879  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_23_CHECKER_TYPE,
13880  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
13881  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_24_CHECKER_TYPE,
13882  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
13883  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_25_CHECKER_TYPE,
13884  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
13885  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_26_CHECKER_TYPE,
13886  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
13887  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_27_CHECKER_TYPE,
13888  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
13889  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_28_CHECKER_TYPE,
13890  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
13891  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_29_CHECKER_TYPE,
13892  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
13893  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_30_CHECKER_TYPE,
13894  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
13895  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_31_CHECKER_TYPE,
13896  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
13897  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_32_CHECKER_TYPE,
13898  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
13899  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_33_CHECKER_TYPE,
13900  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
13901  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_34_CHECKER_TYPE,
13902  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
13903  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_35_CHECKER_TYPE,
13904  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
13905  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_36_CHECKER_TYPE,
13906  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
13907  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_37_CHECKER_TYPE,
13908  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
13909  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_38_CHECKER_TYPE,
13910  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
13911  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_39_CHECKER_TYPE,
13912  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
13913  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_40_CHECKER_TYPE,
13914  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
13915  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_41_CHECKER_TYPE,
13916  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
13917  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_42_CHECKER_TYPE,
13918  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
13919  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_43_CHECKER_TYPE,
13920  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
13921  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_44_CHECKER_TYPE,
13922  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
13923  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_45_CHECKER_TYPE,
13924  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
13925  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_46_CHECKER_TYPE,
13926  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
13927  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_47_CHECKER_TYPE,
13928  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
13929  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_48_CHECKER_TYPE,
13930  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
13931  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_49_CHECKER_TYPE,
13932  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
13933  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_50_CHECKER_TYPE,
13934  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
13935  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_51_CHECKER_TYPE,
13936  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
13937  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_52_CHECKER_TYPE,
13938  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
13939  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_53_CHECKER_TYPE,
13940  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
13941  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_54_CHECKER_TYPE,
13942  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
13943  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_55_CHECKER_TYPE,
13944  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
13945  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_56_CHECKER_TYPE,
13946  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
13947  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_57_CHECKER_TYPE,
13948  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
13949  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_58_CHECKER_TYPE,
13950  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
13951  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_59_CHECKER_TYPE,
13952  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
13953  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_60_CHECKER_TYPE,
13954  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
13955  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_61_CHECKER_TYPE,
13956  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
13957  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_62_CHECKER_TYPE,
13958  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
13959  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_63_CHECKER_TYPE,
13960  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
13961  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_64_CHECKER_TYPE,
13962  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
13963  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_65_CHECKER_TYPE,
13964  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
13965  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_66_CHECKER_TYPE,
13966  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
13967  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_67_CHECKER_TYPE,
13968  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
13969  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_68_CHECKER_TYPE,
13970  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
13971  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_69_CHECKER_TYPE,
13972  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
13973  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_70_CHECKER_TYPE,
13974  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
13975  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_71_CHECKER_TYPE,
13976  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
13977  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_72_CHECKER_TYPE,
13978  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
13979  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_73_CHECKER_TYPE,
13980  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
13981  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_74_CHECKER_TYPE,
13982  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
13983  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_75_CHECKER_TYPE,
13984  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
13985  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_76_CHECKER_TYPE,
13986  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
13987  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_77_CHECKER_TYPE,
13988  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
13989  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_78_CHECKER_TYPE,
13990  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
13991  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_79_CHECKER_TYPE,
13992  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
13993  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_80_CHECKER_TYPE,
13994  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
13995  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_81_CHECKER_TYPE,
13996  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
13997  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_82_CHECKER_TYPE,
13998  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
13999  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_83_CHECKER_TYPE,
14000  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
14001  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_84_CHECKER_TYPE,
14002  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
14003  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_85_CHECKER_TYPE,
14004  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
14005  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_86_CHECKER_TYPE,
14006  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
14007  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_87_CHECKER_TYPE,
14008  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
14009  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_88_CHECKER_TYPE,
14010  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
14011  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_89_CHECKER_TYPE,
14012  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
14013  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_90_CHECKER_TYPE,
14014  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
14015  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_91_CHECKER_TYPE,
14016  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
14017  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_92_CHECKER_TYPE,
14018  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
14019  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_93_CHECKER_TYPE,
14020  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
14021  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_94_CHECKER_TYPE,
14022  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
14023  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_95_CHECKER_TYPE,
14024  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
14025  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_96_CHECKER_TYPE,
14026  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
14027  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_97_CHECKER_TYPE,
14028  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
14029  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_98_CHECKER_TYPE,
14030  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
14031  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_99_CHECKER_TYPE,
14032  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
14033  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_100_CHECKER_TYPE,
14034  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
14035  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_101_CHECKER_TYPE,
14036  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
14037  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_102_CHECKER_TYPE,
14038  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
14039  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_103_CHECKER_TYPE,
14040  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
14041  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_104_CHECKER_TYPE,
14042  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
14043  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_105_CHECKER_TYPE,
14044  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
14045  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_106_CHECKER_TYPE,
14046  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
14047  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_107_CHECKER_TYPE,
14048  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
14049  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_108_CHECKER_TYPE,
14050  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
14051  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_109_CHECKER_TYPE,
14052  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
14053  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_110_CHECKER_TYPE,
14054  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
14055  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_111_CHECKER_TYPE,
14056  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
14057  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_112_CHECKER_TYPE,
14058  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
14059  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_113_CHECKER_TYPE,
14060  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
14061  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_114_CHECKER_TYPE,
14062  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
14063  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_115_CHECKER_TYPE,
14064  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
14065  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_116_CHECKER_TYPE,
14066  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
14067  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_117_CHECKER_TYPE,
14068  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
14069  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_118_CHECKER_TYPE,
14070  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
14071  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_119_CHECKER_TYPE,
14072  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
14073  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_120_CHECKER_TYPE,
14074  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
14075  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_121_CHECKER_TYPE,
14076  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
14077  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_122_CHECKER_TYPE,
14078  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
14079  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_123_CHECKER_TYPE,
14080  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
14081  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_124_CHECKER_TYPE,
14082  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
14083  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_125_CHECKER_TYPE,
14084  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
14085  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_126_CHECKER_TYPE,
14086  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
14087  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_127_CHECKER_TYPE,
14088  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
14089  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_128_CHECKER_TYPE,
14090  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
14091  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_129_CHECKER_TYPE,
14092  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
14093  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_130_CHECKER_TYPE,
14094  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
14095  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_131_CHECKER_TYPE,
14096  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
14097  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_132_CHECKER_TYPE,
14098  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
14099  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_133_CHECKER_TYPE,
14100  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
14101  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_134_CHECKER_TYPE,
14102  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
14103  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_135_CHECKER_TYPE,
14104  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
14105  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_136_CHECKER_TYPE,
14106  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
14107  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_137_CHECKER_TYPE,
14108  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
14109  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_138_CHECKER_TYPE,
14110  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
14111  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_139_CHECKER_TYPE,
14112  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
14113  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_140_CHECKER_TYPE,
14114  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
14115  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_141_CHECKER_TYPE,
14116  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
14117  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_142_CHECKER_TYPE,
14118  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
14119  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_143_CHECKER_TYPE,
14120  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
14121  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_144_CHECKER_TYPE,
14122  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
14123  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_145_CHECKER_TYPE,
14124  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
14125  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_146_CHECKER_TYPE,
14126  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
14127  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_147_CHECKER_TYPE,
14128  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
14129  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_148_CHECKER_TYPE,
14130  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
14131  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_149_CHECKER_TYPE,
14132  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
14133  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_150_CHECKER_TYPE,
14134  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
14135  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_151_CHECKER_TYPE,
14136  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
14137  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_152_CHECKER_TYPE,
14138  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
14139  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_153_CHECKER_TYPE,
14140  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
14141  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_154_CHECKER_TYPE,
14142  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
14143  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_155_CHECKER_TYPE,
14144  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
14145  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_156_CHECKER_TYPE,
14146  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
14147  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_157_CHECKER_TYPE,
14148  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
14149  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_158_CHECKER_TYPE,
14150  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
14151  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_159_CHECKER_TYPE,
14152  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
14153  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_160_CHECKER_TYPE,
14154  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
14155  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_161_CHECKER_TYPE,
14156  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
14157  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_162_CHECKER_TYPE,
14158  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
14159  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_163_CHECKER_TYPE,
14160  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
14161  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_164_CHECKER_TYPE,
14162  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
14163  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_165_CHECKER_TYPE,
14164  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
14165  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_166_CHECKER_TYPE,
14166  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
14167  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_167_CHECKER_TYPE,
14168  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
14169  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_168_CHECKER_TYPE,
14170  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
14171  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_169_CHECKER_TYPE,
14172  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
14173  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_170_CHECKER_TYPE,
14174  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
14175  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_171_CHECKER_TYPE,
14176  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
14177  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_172_CHECKER_TYPE,
14178  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
14179  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_173_CHECKER_TYPE,
14180  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
14181  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_174_CHECKER_TYPE,
14182  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
14183  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_175_CHECKER_TYPE,
14184  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
14185  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_176_CHECKER_TYPE,
14186  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
14187  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_177_CHECKER_TYPE,
14188  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
14189  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_178_CHECKER_TYPE,
14190  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
14191  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_179_CHECKER_TYPE,
14192  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
14193  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_180_CHECKER_TYPE,
14194  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
14195  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_181_CHECKER_TYPE,
14196  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
14197  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_182_CHECKER_TYPE,
14198  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
14199  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_183_CHECKER_TYPE,
14200  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
14201  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_184_CHECKER_TYPE,
14202  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
14203  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_185_CHECKER_TYPE,
14204  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
14205  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_186_CHECKER_TYPE,
14206  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
14207  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_187_CHECKER_TYPE,
14208  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
14209  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_188_CHECKER_TYPE,
14210  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
14211  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_189_CHECKER_TYPE,
14212  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
14213  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_190_CHECKER_TYPE,
14214  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
14215  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_191_CHECKER_TYPE,
14216  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
14217  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_192_CHECKER_TYPE,
14218  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
14219  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_193_CHECKER_TYPE,
14220  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
14221  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_194_CHECKER_TYPE,
14222  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
14223  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_195_CHECKER_TYPE,
14224  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
14225  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_196_CHECKER_TYPE,
14226  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
14227  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_197_CHECKER_TYPE,
14228  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
14229  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_198_CHECKER_TYPE,
14230  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
14231  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_199_CHECKER_TYPE,
14232  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
14233  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_200_CHECKER_TYPE,
14234  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
14235  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_201_CHECKER_TYPE,
14236  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
14237  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_202_CHECKER_TYPE,
14238  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
14239  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_203_CHECKER_TYPE,
14240  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
14241  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_204_CHECKER_TYPE,
14242  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
14243  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_205_CHECKER_TYPE,
14244  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
14245  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_206_CHECKER_TYPE,
14246  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
14247  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_207_CHECKER_TYPE,
14248  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
14249  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_208_CHECKER_TYPE,
14250  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
14251  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_209_CHECKER_TYPE,
14252  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
14253  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_210_CHECKER_TYPE,
14254  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
14255  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_211_CHECKER_TYPE,
14256  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
14257  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_212_CHECKER_TYPE,
14258  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
14259  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_213_CHECKER_TYPE,
14260  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
14261  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_214_CHECKER_TYPE,
14262  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
14263  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_215_CHECKER_TYPE,
14264  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
14265  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_216_CHECKER_TYPE,
14266  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
14267  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_217_CHECKER_TYPE,
14268  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
14269  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_218_CHECKER_TYPE,
14270  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
14271  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_219_CHECKER_TYPE,
14272  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
14273  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_220_CHECKER_TYPE,
14274  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
14275  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_221_CHECKER_TYPE,
14276  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
14277  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_222_CHECKER_TYPE,
14278  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
14279  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_223_CHECKER_TYPE,
14280  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
14281  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_224_CHECKER_TYPE,
14282  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
14283  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_225_CHECKER_TYPE,
14284  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
14285  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_226_CHECKER_TYPE,
14286  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
14287  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_227_CHECKER_TYPE,
14288  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
14289  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_228_CHECKER_TYPE,
14290  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
14291  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_229_CHECKER_TYPE,
14292  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
14293  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_230_CHECKER_TYPE,
14294  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
14295  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_231_CHECKER_TYPE,
14296  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
14297  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_232_CHECKER_TYPE,
14298  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
14299  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_233_CHECKER_TYPE,
14300  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
14301  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_234_CHECKER_TYPE,
14302  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
14303  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_235_CHECKER_TYPE,
14304  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
14305  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_236_CHECKER_TYPE,
14306  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
14307  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_237_CHECKER_TYPE,
14308  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
14309  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_238_CHECKER_TYPE,
14310  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
14311  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_239_CHECKER_TYPE,
14312  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
14313  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_240_CHECKER_TYPE,
14314  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
14315  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_241_CHECKER_TYPE,
14316  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
14317  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_242_CHECKER_TYPE,
14318  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
14319  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_243_CHECKER_TYPE,
14320  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
14321  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_244_CHECKER_TYPE,
14322  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
14323  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_245_CHECKER_TYPE,
14324  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
14325  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_246_CHECKER_TYPE,
14326  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
14327  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_247_CHECKER_TYPE,
14328  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
14329  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_248_CHECKER_TYPE,
14330  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
14331  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_249_CHECKER_TYPE,
14332  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
14333  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_250_CHECKER_TYPE,
14334  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
14335  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_251_CHECKER_TYPE,
14336  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
14337  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_252_CHECKER_TYPE,
14338  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
14339  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_253_CHECKER_TYPE,
14340  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
14341  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_254_CHECKER_TYPE,
14342  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
14343  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_255_CHECKER_TYPE,
14344  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
14345 };
14346 
14352 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] =
14353 {
14354  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_0_CHECKER_TYPE,
14355  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
14356  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_1_CHECKER_TYPE,
14357  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
14358  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_2_CHECKER_TYPE,
14359  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
14360  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_3_CHECKER_TYPE,
14361  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
14362  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_4_CHECKER_TYPE,
14363  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
14364  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_5_CHECKER_TYPE,
14365  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
14366  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_6_CHECKER_TYPE,
14367  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
14368  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_7_CHECKER_TYPE,
14369  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
14370  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_8_CHECKER_TYPE,
14371  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
14372  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_9_CHECKER_TYPE,
14373  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
14374  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_10_CHECKER_TYPE,
14375  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
14376  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_11_CHECKER_TYPE,
14377  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
14378  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_12_CHECKER_TYPE,
14379  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
14380  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_13_CHECKER_TYPE,
14381  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
14382  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_14_CHECKER_TYPE,
14383  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
14384  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_15_CHECKER_TYPE,
14385  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
14386  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_16_CHECKER_TYPE,
14387  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
14388  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_17_CHECKER_TYPE,
14389  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
14390  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_18_CHECKER_TYPE,
14391  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
14392  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_19_CHECKER_TYPE,
14393  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
14394  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_20_CHECKER_TYPE,
14395  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
14396  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_21_CHECKER_TYPE,
14397  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
14398  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_22_CHECKER_TYPE,
14399  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
14400  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_23_CHECKER_TYPE,
14401  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
14402  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_24_CHECKER_TYPE,
14403  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH },
14404  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_25_CHECKER_TYPE,
14405  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH },
14406  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_26_CHECKER_TYPE,
14407  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH },
14408  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_27_CHECKER_TYPE,
14409  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH },
14410  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_28_CHECKER_TYPE,
14411  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH },
14412  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_29_CHECKER_TYPE,
14413  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH },
14414  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_30_CHECKER_TYPE,
14415  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH },
14416  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_31_CHECKER_TYPE,
14417  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH },
14418  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_32_CHECKER_TYPE,
14419  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH },
14420  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_33_CHECKER_TYPE,
14421  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH },
14422  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_34_CHECKER_TYPE,
14423  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH },
14424  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_35_CHECKER_TYPE,
14425  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH },
14426  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_36_CHECKER_TYPE,
14427  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH },
14428  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_37_CHECKER_TYPE,
14429  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH },
14430  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_38_CHECKER_TYPE,
14431  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH },
14432  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_39_CHECKER_TYPE,
14433  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH },
14434  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_40_CHECKER_TYPE,
14435  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH },
14436  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_41_CHECKER_TYPE,
14437  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH },
14438  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_42_CHECKER_TYPE,
14439  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH },
14440  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_43_CHECKER_TYPE,
14441  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_43_WIDTH },
14442  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_44_CHECKER_TYPE,
14443  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_44_WIDTH },
14444  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_45_CHECKER_TYPE,
14445  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_45_WIDTH },
14446  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_46_CHECKER_TYPE,
14447  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_46_WIDTH },
14448  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_47_CHECKER_TYPE,
14449  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_47_WIDTH },
14450  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_48_CHECKER_TYPE,
14451  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_48_WIDTH },
14452  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_49_CHECKER_TYPE,
14453  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_49_WIDTH },
14454  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_50_CHECKER_TYPE,
14455  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_50_WIDTH },
14456  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_51_CHECKER_TYPE,
14457  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_51_WIDTH },
14458  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_52_CHECKER_TYPE,
14459  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_52_WIDTH },
14460  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_53_CHECKER_TYPE,
14461  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_53_WIDTH },
14462  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_54_CHECKER_TYPE,
14463  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_54_WIDTH },
14464  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_55_CHECKER_TYPE,
14465  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_55_WIDTH },
14466  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_56_CHECKER_TYPE,
14467  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_56_WIDTH },
14468  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_57_CHECKER_TYPE,
14469  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_57_WIDTH },
14470  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_58_CHECKER_TYPE,
14471  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_58_WIDTH },
14472  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_59_CHECKER_TYPE,
14473  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_59_WIDTH },
14474  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_60_CHECKER_TYPE,
14475  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_60_WIDTH },
14476  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_61_CHECKER_TYPE,
14477  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_61_WIDTH },
14478  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_62_CHECKER_TYPE,
14479  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_62_WIDTH },
14480  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_63_CHECKER_TYPE,
14481  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_63_WIDTH },
14482  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_64_CHECKER_TYPE,
14483  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_64_WIDTH },
14484  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_65_CHECKER_TYPE,
14485  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_65_WIDTH },
14486  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_66_CHECKER_TYPE,
14487  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_66_WIDTH },
14488  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_67_CHECKER_TYPE,
14489  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_67_WIDTH },
14490  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_68_CHECKER_TYPE,
14491  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_68_WIDTH },
14492  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_69_CHECKER_TYPE,
14493  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_69_WIDTH },
14494  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_70_CHECKER_TYPE,
14495  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_70_WIDTH },
14496  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_71_CHECKER_TYPE,
14497  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_71_WIDTH },
14498  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_72_CHECKER_TYPE,
14499  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_72_WIDTH },
14500  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_73_CHECKER_TYPE,
14501  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_73_WIDTH },
14502  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_74_CHECKER_TYPE,
14503  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_74_WIDTH },
14504  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_75_CHECKER_TYPE,
14505  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_75_WIDTH },
14506  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_76_CHECKER_TYPE,
14507  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_76_WIDTH },
14508  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_77_CHECKER_TYPE,
14509  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_77_WIDTH },
14510  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_78_CHECKER_TYPE,
14511  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_78_WIDTH },
14512  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_79_CHECKER_TYPE,
14513  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_79_WIDTH },
14514  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_80_CHECKER_TYPE,
14515  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_80_WIDTH },
14516  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_81_CHECKER_TYPE,
14517  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_81_WIDTH },
14518  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_82_CHECKER_TYPE,
14519  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_82_WIDTH },
14520  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_83_CHECKER_TYPE,
14521  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_83_WIDTH },
14522  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_84_CHECKER_TYPE,
14523  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_84_WIDTH },
14524  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_85_CHECKER_TYPE,
14525  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_85_WIDTH },
14526  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_86_CHECKER_TYPE,
14527  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_86_WIDTH },
14528  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_87_CHECKER_TYPE,
14529  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_87_WIDTH },
14530  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_88_CHECKER_TYPE,
14531  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_88_WIDTH },
14532  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_89_CHECKER_TYPE,
14533  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_89_WIDTH },
14534  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_90_CHECKER_TYPE,
14535  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_90_WIDTH },
14536  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_91_CHECKER_TYPE,
14537  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_91_WIDTH },
14538  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_92_CHECKER_TYPE,
14539  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_92_WIDTH },
14540  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_93_CHECKER_TYPE,
14541  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_93_WIDTH },
14542  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_94_CHECKER_TYPE,
14543  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_94_WIDTH },
14544  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_95_CHECKER_TYPE,
14545  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_95_WIDTH },
14546  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_96_CHECKER_TYPE,
14547  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_96_WIDTH },
14548  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_97_CHECKER_TYPE,
14549  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_97_WIDTH },
14550  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_98_CHECKER_TYPE,
14551  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_98_WIDTH },
14552  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_99_CHECKER_TYPE,
14553  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_99_WIDTH },
14554  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_100_CHECKER_TYPE,
14555  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_100_WIDTH },
14556  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_101_CHECKER_TYPE,
14557  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_101_WIDTH },
14558  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_102_CHECKER_TYPE,
14559  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_102_WIDTH },
14560  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_103_CHECKER_TYPE,
14561  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_103_WIDTH },
14562  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_104_CHECKER_TYPE,
14563  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_104_WIDTH },
14564  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_105_CHECKER_TYPE,
14565  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_105_WIDTH },
14566  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_106_CHECKER_TYPE,
14567  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_106_WIDTH },
14568  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_107_CHECKER_TYPE,
14569  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_107_WIDTH },
14570  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_108_CHECKER_TYPE,
14571  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_108_WIDTH },
14572  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_109_CHECKER_TYPE,
14573  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_109_WIDTH },
14574  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_110_CHECKER_TYPE,
14575  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_110_WIDTH },
14576  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_111_CHECKER_TYPE,
14577  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_111_WIDTH },
14578  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_112_CHECKER_TYPE,
14579  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_112_WIDTH },
14580  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_113_CHECKER_TYPE,
14581  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_113_WIDTH },
14582  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_114_CHECKER_TYPE,
14583  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_114_WIDTH },
14584  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_115_CHECKER_TYPE,
14585  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_115_WIDTH },
14586  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_116_CHECKER_TYPE,
14587  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_116_WIDTH },
14588  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_117_CHECKER_TYPE,
14589  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_117_WIDTH },
14590  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_118_CHECKER_TYPE,
14591  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_118_WIDTH },
14592  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_119_CHECKER_TYPE,
14593  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_119_WIDTH },
14594  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_120_CHECKER_TYPE,
14595  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_120_WIDTH },
14596  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_121_CHECKER_TYPE,
14597  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_121_WIDTH },
14598  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_122_CHECKER_TYPE,
14599  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_122_WIDTH },
14600  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_123_CHECKER_TYPE,
14601  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_123_WIDTH },
14602  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_124_CHECKER_TYPE,
14603  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_124_WIDTH },
14604  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_125_CHECKER_TYPE,
14605  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_125_WIDTH },
14606  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_126_CHECKER_TYPE,
14607  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_126_WIDTH },
14608  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_127_CHECKER_TYPE,
14609  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_127_WIDTH },
14610  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_128_CHECKER_TYPE,
14611  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_128_WIDTH },
14612  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_129_CHECKER_TYPE,
14613  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_129_WIDTH },
14614  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_130_CHECKER_TYPE,
14615  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_130_WIDTH },
14616  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_131_CHECKER_TYPE,
14617  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_131_WIDTH },
14618  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_132_CHECKER_TYPE,
14619  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_132_WIDTH },
14620  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_133_CHECKER_TYPE,
14621  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_133_WIDTH },
14622  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_134_CHECKER_TYPE,
14623  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_134_WIDTH },
14624  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_135_CHECKER_TYPE,
14625  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_135_WIDTH },
14626  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_136_CHECKER_TYPE,
14627  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_136_WIDTH },
14628  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_137_CHECKER_TYPE,
14629  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_137_WIDTH },
14630  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_138_CHECKER_TYPE,
14631  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_138_WIDTH },
14632  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_139_CHECKER_TYPE,
14633  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_139_WIDTH },
14634  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_140_CHECKER_TYPE,
14635  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_140_WIDTH },
14636  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_141_CHECKER_TYPE,
14637  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_141_WIDTH },
14638  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_142_CHECKER_TYPE,
14639  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_142_WIDTH },
14640  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_143_CHECKER_TYPE,
14641  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_143_WIDTH },
14642  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_144_CHECKER_TYPE,
14643  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_144_WIDTH },
14644  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_145_CHECKER_TYPE,
14645  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_145_WIDTH },
14646  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_146_CHECKER_TYPE,
14647  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_146_WIDTH },
14648  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_147_CHECKER_TYPE,
14649  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_147_WIDTH },
14650  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_148_CHECKER_TYPE,
14651  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_148_WIDTH },
14652  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_149_CHECKER_TYPE,
14653  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_149_WIDTH },
14654  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_150_CHECKER_TYPE,
14655  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_150_WIDTH },
14656  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_151_CHECKER_TYPE,
14657  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_151_WIDTH },
14658  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_152_CHECKER_TYPE,
14659  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_152_WIDTH },
14660  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_153_CHECKER_TYPE,
14661  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_GROUP_153_WIDTH },
14662 };
14663 
14669 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
14670 {
14671  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
14672  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
14673  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
14674  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
14675  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
14676  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
14677  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
14678  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
14679  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
14680  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
14681 };
14682 
14688 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
14689 {
14690  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
14691  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
14692  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
14693  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
14694  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
14695  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
14696  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
14697  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
14698  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
14699  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
14700  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
14701  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
14702  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
14703  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
14704  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
14705  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
14706  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
14707  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
14708  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
14709  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
14710  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
14711  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
14712  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
14713  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
14714  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
14715  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
14716  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
14717  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
14718  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
14719  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
14720  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
14721  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
14722  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
14723  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
14724  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
14725  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
14726  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
14727  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
14728  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
14729  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
14730  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
14731  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
14732  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
14733  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
14734  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
14735  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
14736  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
14737  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
14738  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
14739  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
14740  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
14741  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
14742  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
14743  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
14744  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
14745  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
14746  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
14747  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
14748  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
14749  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
14750  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
14751  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
14752  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
14753  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
14754  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
14755  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
14756  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
14757  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
14758  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
14759  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
14760  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
14761  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
14762  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
14763  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
14764  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
14765  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
14766  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
14767  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
14768  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
14769  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
14770  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
14771  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
14772  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
14773  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
14774 };
14775 
14781 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
14782 {
14783  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
14784  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
14785  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
14786  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
14787  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
14788  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
14789  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
14790  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_3_WIDTH },
14791  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
14792  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_4_WIDTH },
14793  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
14794  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_5_WIDTH },
14795  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
14796  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_6_WIDTH },
14797  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
14798  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_7_WIDTH },
14799  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
14800  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_8_WIDTH },
14801  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
14802  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_9_WIDTH },
14803  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
14804  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_10_WIDTH },
14805  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
14806  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_11_WIDTH },
14807  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
14808  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_12_WIDTH },
14809  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_13_CHECKER_TYPE,
14810  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_13_WIDTH },
14811  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_14_CHECKER_TYPE,
14812  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_14_WIDTH },
14813  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_15_CHECKER_TYPE,
14814  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_15_WIDTH },
14815  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_16_CHECKER_TYPE,
14816  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_16_WIDTH },
14817  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_17_CHECKER_TYPE,
14818  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_17_WIDTH },
14819  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_18_CHECKER_TYPE,
14820  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_18_WIDTH },
14821 };
14822 
14828 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
14829 {
14830  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
14831  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_0_WIDTH },
14832  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
14833  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_1_WIDTH },
14834  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
14835  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_2_WIDTH },
14836  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
14837  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_3_WIDTH },
14838  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
14839  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_4_WIDTH },
14840  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
14841  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_5_WIDTH },
14842  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
14843  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_6_WIDTH },
14844  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
14845  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_7_WIDTH },
14846  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
14847  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_8_WIDTH },
14848  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
14849  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_9_WIDTH },
14850  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
14851  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_10_WIDTH },
14852  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
14853  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_11_WIDTH },
14854  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
14855  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_12_WIDTH },
14856  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_13_CHECKER_TYPE,
14857  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_13_WIDTH },
14858  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_14_CHECKER_TYPE,
14859  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_14_WIDTH },
14860  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_15_CHECKER_TYPE,
14861  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_15_WIDTH },
14862  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_16_CHECKER_TYPE,
14863  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_16_WIDTH },
14864  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_17_CHECKER_TYPE,
14865  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_17_WIDTH },
14866  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_18_CHECKER_TYPE,
14867  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_18_WIDTH },
14868  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_19_CHECKER_TYPE,
14869  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_19_WIDTH },
14870  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_20_CHECKER_TYPE,
14871  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_20_WIDTH },
14872  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_21_CHECKER_TYPE,
14873  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_21_WIDTH },
14874  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_22_CHECKER_TYPE,
14875  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_22_WIDTH },
14876  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_23_CHECKER_TYPE,
14877  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_23_WIDTH },
14878  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_24_CHECKER_TYPE,
14879  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_24_WIDTH },
14880  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_25_CHECKER_TYPE,
14881  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_25_WIDTH },
14882  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_26_CHECKER_TYPE,
14883  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_26_WIDTH },
14884  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_27_CHECKER_TYPE,
14885  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_27_WIDTH },
14886  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_28_CHECKER_TYPE,
14887  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_28_WIDTH },
14888  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_29_CHECKER_TYPE,
14889  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_29_WIDTH },
14890  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_30_CHECKER_TYPE,
14891  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_30_WIDTH },
14892 };
14893 
14899 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_SAM62A_WKUP_SAFE_ECC_AGGR_EDC_CTRL_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_SAM62A_WKUP_SAFE_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
14900 {
14901  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_SAM62A_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
14902  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_SAM62A_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
14903  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_SAM62A_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
14904  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_SAM62A_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
14905  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_SAM62A_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
14906  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_SAM62A_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
14907  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_SAM62A_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
14908  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_SAM62A_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
14909  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_SAM62A_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
14910  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_SAM62A_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
14911  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_SAM62A_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
14912  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_SAM62A_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
14913 };
14914 
14919 static const SDL_MemConfig_t SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_MemEntries[SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
14920 {
14921  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID, 0u,
14922  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_SIZE, 4u,
14923  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_ROW_WIDTH, ((bool)false) },
14924  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID, 0u,
14925  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_SIZE, 4u,
14926  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_ROW_WIDTH, ((bool)false) },
14927  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID, 0u,
14928  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_SIZE, 4u,
14929  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_ROW_WIDTH, ((bool)false) },
14930  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID, 0u,
14931  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_SIZE, 4u,
14932  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_ROW_WIDTH, ((bool)false) },
14933  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID, 0u,
14934  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_SIZE, 8u,
14935  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_ROW_WIDTH, ((bool)true) },
14936  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID, 0u,
14937  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_SIZE, 8u,
14938  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_ROW_WIDTH, ((bool)true) },
14939  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID, 0u,
14940  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_SIZE, 8u,
14941  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_ROW_WIDTH, ((bool)true) },
14942  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID, 0u,
14943  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_SIZE, 8u,
14944  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_ROW_WIDTH, ((bool)true) },
14945  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID, 0u,
14946  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_SIZE, 4u,
14947  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_ROW_WIDTH, ((bool)false) },
14948  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID, 0u,
14949  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_SIZE, 4u,
14950  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_ROW_WIDTH, ((bool)false) },
14951  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID, 0u,
14952  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_SIZE, 4u,
14953  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_ROW_WIDTH, ((bool)false) },
14954  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID, 0u,
14955  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_SIZE, 4u,
14956  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_ROW_WIDTH, ((bool)false) },
14957  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID, 0u,
14958  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_SIZE, 4u,
14959  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_ROW_WIDTH, ((bool)false) },
14960  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID, 0u,
14961  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_SIZE, 4u,
14962  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_ROW_WIDTH, ((bool)true) },
14963  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID, 0u,
14964  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_SIZE, 4u,
14965  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_ROW_WIDTH, ((bool)true) },
14966  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID, 0u,
14967  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_SIZE, 4u,
14968  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_ROW_WIDTH, ((bool)true) },
14969  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID, 0u,
14970  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_SIZE, 4u,
14971  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_ROW_WIDTH, ((bool)true) },
14972  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID, 0u,
14973  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_SIZE, 4u,
14974  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_ROW_WIDTH, ((bool)true) },
14975  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID, 0u,
14976  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_SIZE, 4u,
14977  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_ROW_WIDTH, ((bool)true) },
14978  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID, 0u,
14979  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_SIZE, 4u,
14980  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_ROW_WIDTH, ((bool)true) },
14981  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID, 0u,
14982  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_SIZE, 4u,
14983  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_ROW_WIDTH, ((bool)true) },
14984  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK0_RAM_ID, 0x0078000000u,
14985  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK0_RAM_SIZE, 4u,
14986  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK0_ROW_WIDTH, ((bool)true) },
14987  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK1_RAM_ID, 0x0078000000u,
14988  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK1_RAM_SIZE, 4u,
14989  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK1_ROW_WIDTH, ((bool)true) },
14990  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK0_RAM_ID, 0x0078100000u,
14991  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK0_RAM_SIZE, 4u,
14992  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK0_ROW_WIDTH, ((bool)true) },
14993  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK1_RAM_ID, 0x0078100000u,
14994  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK1_RAM_SIZE, 4u,
14995  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK1_ROW_WIDTH, ((bool)true) },
14996  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK0_RAM_ID, 0x0078100000u,
14997  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK0_RAM_SIZE, 4u,
14998  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK0_ROW_WIDTH, ((bool)true) },
14999  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK1_RAM_ID, 0x0078100000u,
15000  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK1_RAM_SIZE, 4u,
15001  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK1_ROW_WIDTH, ((bool)true) },
15002  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_PULSAR_KS_VIM_COMMON_CORE0_RAM_RAM_ID, 0u,
15003  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_PULSAR_KS_VIM_COMMON_CORE0_RAM_RAM_SIZE, 4u,
15004  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_PULSAR_KS_VIM_COMMON_CORE0_RAM_ROW_WIDTH, ((bool)false) },
15005  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_MEM_MST0_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID, 0u,
15006  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_MEM_MST0_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_SIZE, 8u,
15007  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_MEM_MST0_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ROW_WIDTH, ((bool)false) },
15008 };
15009 
15014 static const SDL_MemConfig_t SDL_SMS0_SMS_HSM_ECC_MemEntries[SDL_SMS0_SMS_HSM_ECC_RAM_IDS_TOTAL_ENTRIES] =
15015 {
15016  { SDL_SMS0_SMS_HSM_ECC_ISRAM0_RAMECC_RAM_ID, 0u,
15017  SDL_SMS0_SMS_HSM_ECC_ISRAM0_RAMECC_RAM_SIZE, 4u,
15018  SDL_SMS0_SMS_HSM_ECC_ISRAM0_RAMECC_ROW_WIDTH, ((bool)false) },
15019  { SDL_SMS0_SMS_HSM_ECC_ISRAM1_RAMECC_RAM_ID, 0u,
15020  SDL_SMS0_SMS_HSM_ECC_ISRAM1_RAMECC_RAM_SIZE, 4u,
15021  SDL_SMS0_SMS_HSM_ECC_ISRAM1_RAMECC_ROW_WIDTH, ((bool)false) },
15022 };
15023 
15029 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_MAX_NUM_CHECKERS] =
15030 {
15031  { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_0_CHECKER_TYPE,
15032  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_0_WIDTH },
15033  { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_1_CHECKER_TYPE,
15034  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_1_WIDTH },
15035  { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_2_CHECKER_TYPE,
15036  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_2_WIDTH },
15037  { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_3_CHECKER_TYPE,
15038  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_3_WIDTH },
15039  { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_4_CHECKER_TYPE,
15040  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_4_WIDTH },
15041  { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_5_CHECKER_TYPE,
15042  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_5_WIDTH },
15043  { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_6_CHECKER_TYPE,
15044  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_6_WIDTH },
15045  { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_7_CHECKER_TYPE,
15046  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_7_WIDTH },
15047  { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_8_CHECKER_TYPE,
15048  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_8_WIDTH },
15049  { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_9_CHECKER_TYPE,
15050  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_9_WIDTH },
15051  { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_10_CHECKER_TYPE,
15052  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_10_WIDTH },
15053  { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_11_CHECKER_TYPE,
15054  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_11_WIDTH },
15055  { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_12_CHECKER_TYPE,
15056  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_12_WIDTH },
15057  { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_13_CHECKER_TYPE,
15058  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_13_WIDTH },
15059  { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_14_CHECKER_TYPE,
15060  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_14_WIDTH },
15061  { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_15_CHECKER_TYPE,
15062  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_15_WIDTH },
15063  { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_16_CHECKER_TYPE,
15064  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_16_WIDTH },
15065  { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_17_CHECKER_TYPE,
15066  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_17_WIDTH },
15067  { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_18_CHECKER_TYPE,
15068  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_18_WIDTH },
15069  { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_19_CHECKER_TYPE,
15070  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_19_WIDTH },
15071 };
15072 
15078 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_MAX_NUM_CHECKERS] =
15079 {
15080  { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_0_CHECKER_TYPE,
15081  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_0_WIDTH },
15082  { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_1_CHECKER_TYPE,
15083  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_1_WIDTH },
15084  { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_2_CHECKER_TYPE,
15085  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_2_WIDTH },
15086  { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_3_CHECKER_TYPE,
15087  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_3_WIDTH },
15088  { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_4_CHECKER_TYPE,
15089  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_4_WIDTH },
15090  { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_5_CHECKER_TYPE,
15091  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_5_WIDTH },
15092  { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_6_CHECKER_TYPE,
15093  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_6_WIDTH },
15094  { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_7_CHECKER_TYPE,
15095  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_7_WIDTH },
15096  { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_8_CHECKER_TYPE,
15097  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_8_WIDTH },
15098  { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_9_CHECKER_TYPE,
15099  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_9_WIDTH },
15100  { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_10_CHECKER_TYPE,
15101  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_10_WIDTH },
15102  { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_11_CHECKER_TYPE,
15103  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_11_WIDTH },
15104  { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_12_CHECKER_TYPE,
15105  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_12_WIDTH },
15106  { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_13_CHECKER_TYPE,
15107  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_13_WIDTH },
15108  { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_14_CHECKER_TYPE,
15109  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_14_WIDTH },
15110  { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_15_CHECKER_TYPE,
15111  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_15_WIDTH },
15112  { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_16_CHECKER_TYPE,
15113  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_16_WIDTH },
15114  { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_17_CHECKER_TYPE,
15115  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_17_WIDTH },
15116  { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_18_CHECKER_TYPE,
15117  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_18_WIDTH },
15118  { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_19_CHECKER_TYPE,
15119  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_19_WIDTH },
15120 };
15121 
15127 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_MAX_NUM_CHECKERS] =
15128 {
15129  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_0_CHECKER_TYPE,
15130  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_0_WIDTH },
15131  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_1_CHECKER_TYPE,
15132  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_1_WIDTH },
15133  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_2_CHECKER_TYPE,
15134  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_2_WIDTH },
15135  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_3_CHECKER_TYPE,
15136  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_3_WIDTH },
15137  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_4_CHECKER_TYPE,
15138  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_4_WIDTH },
15139  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_5_CHECKER_TYPE,
15140  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_5_WIDTH },
15141  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_6_CHECKER_TYPE,
15142  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_6_WIDTH },
15143  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_7_CHECKER_TYPE,
15144  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_7_WIDTH },
15145  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_8_CHECKER_TYPE,
15146  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_8_WIDTH },
15147  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_9_CHECKER_TYPE,
15148  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_9_WIDTH },
15149  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_10_CHECKER_TYPE,
15150  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_10_WIDTH },
15151  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_11_CHECKER_TYPE,
15152  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_11_WIDTH },
15153  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_12_CHECKER_TYPE,
15154  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_12_WIDTH },
15155  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_13_CHECKER_TYPE,
15156  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_13_WIDTH },
15157  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_14_CHECKER_TYPE,
15158  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_14_WIDTH },
15159  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_15_CHECKER_TYPE,
15160  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_15_WIDTH },
15161  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_16_CHECKER_TYPE,
15162  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_16_WIDTH },
15163  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_17_CHECKER_TYPE,
15164  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_17_WIDTH },
15165  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_18_CHECKER_TYPE,
15166  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_18_WIDTH },
15167  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_19_CHECKER_TYPE,
15168  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_19_WIDTH },
15169  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_20_CHECKER_TYPE,
15170  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_20_WIDTH },
15171  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_21_CHECKER_TYPE,
15172  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_21_WIDTH },
15173  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_22_CHECKER_TYPE,
15174  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_22_WIDTH },
15175  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_23_CHECKER_TYPE,
15176  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_23_WIDTH },
15177  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_24_CHECKER_TYPE,
15178  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_24_WIDTH },
15179  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_25_CHECKER_TYPE,
15180  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_25_WIDTH },
15181  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_26_CHECKER_TYPE,
15182  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_26_WIDTH },
15183  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_27_CHECKER_TYPE,
15184  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_27_WIDTH },
15185  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_28_CHECKER_TYPE,
15186  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_28_WIDTH },
15187  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_29_CHECKER_TYPE,
15188  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_29_WIDTH },
15189  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_30_CHECKER_TYPE,
15190  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_30_WIDTH },
15191  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_31_CHECKER_TYPE,
15192  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_31_WIDTH },
15193  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_32_CHECKER_TYPE,
15194  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_32_WIDTH },
15195  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_33_CHECKER_TYPE,
15196  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_33_WIDTH },
15197  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_34_CHECKER_TYPE,
15198  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_34_WIDTH },
15199  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_35_CHECKER_TYPE,
15200  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_35_WIDTH },
15201  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_36_CHECKER_TYPE,
15202  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_36_WIDTH },
15203  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_37_CHECKER_TYPE,
15204  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_37_WIDTH },
15205  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_38_CHECKER_TYPE,
15206  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_38_WIDTH },
15207  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_39_CHECKER_TYPE,
15208  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_39_WIDTH },
15209  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_40_CHECKER_TYPE,
15210  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_40_WIDTH },
15211  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_41_CHECKER_TYPE,
15212  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_41_WIDTH },
15213  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_42_CHECKER_TYPE,
15214  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_42_WIDTH },
15215  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_43_CHECKER_TYPE,
15216  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_43_WIDTH },
15217  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_44_CHECKER_TYPE,
15218  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_44_WIDTH },
15219  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_45_CHECKER_TYPE,
15220  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_45_WIDTH },
15221  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_46_CHECKER_TYPE,
15222  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_46_WIDTH },
15223  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_47_CHECKER_TYPE,
15224  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_47_WIDTH },
15225  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_48_CHECKER_TYPE,
15226  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_48_WIDTH },
15227  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_49_CHECKER_TYPE,
15228  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_49_WIDTH },
15229  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_50_CHECKER_TYPE,
15230  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_50_WIDTH },
15231  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_51_CHECKER_TYPE,
15232  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_51_WIDTH },
15233  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_52_CHECKER_TYPE,
15234  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_52_WIDTH },
15235  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_53_CHECKER_TYPE,
15236  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_53_WIDTH },
15237  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_54_CHECKER_TYPE,
15238  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_54_WIDTH },
15239  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_55_CHECKER_TYPE,
15240  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_55_WIDTH },
15241  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_56_CHECKER_TYPE,
15242  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_56_WIDTH },
15243  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_57_CHECKER_TYPE,
15244  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_57_WIDTH },
15245  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_58_CHECKER_TYPE,
15246  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_58_WIDTH },
15247  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_59_CHECKER_TYPE,
15248  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_59_WIDTH },
15249  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_60_CHECKER_TYPE,
15250  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_60_WIDTH },
15251  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_61_CHECKER_TYPE,
15252  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_61_WIDTH },
15253  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_62_CHECKER_TYPE,
15254  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_62_WIDTH },
15255  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_63_CHECKER_TYPE,
15256  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_63_WIDTH },
15257  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_64_CHECKER_TYPE,
15258  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_64_WIDTH },
15259  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_65_CHECKER_TYPE,
15260  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_65_WIDTH },
15261  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_66_CHECKER_TYPE,
15262  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_66_WIDTH },
15263  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_67_CHECKER_TYPE,
15264  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_67_WIDTH },
15265  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_68_CHECKER_TYPE,
15266  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_68_WIDTH },
15267  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_69_CHECKER_TYPE,
15268  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_69_WIDTH },
15269  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_70_CHECKER_TYPE,
15270  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_70_WIDTH },
15271  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_71_CHECKER_TYPE,
15272  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_71_WIDTH },
15273  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_72_CHECKER_TYPE,
15274  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_72_WIDTH },
15275  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_73_CHECKER_TYPE,
15276  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_73_WIDTH },
15277  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_74_CHECKER_TYPE,
15278  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_74_WIDTH },
15279  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_75_CHECKER_TYPE,
15280  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_75_WIDTH },
15281  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_76_CHECKER_TYPE,
15282  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_76_WIDTH },
15283  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_77_CHECKER_TYPE,
15284  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_77_WIDTH },
15285  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_78_CHECKER_TYPE,
15286  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_78_WIDTH },
15287  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_79_CHECKER_TYPE,
15288  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_79_WIDTH },
15289  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_80_CHECKER_TYPE,
15290  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_80_WIDTH },
15291  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_81_CHECKER_TYPE,
15292  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_81_WIDTH },
15293  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_82_CHECKER_TYPE,
15294  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_82_WIDTH },
15295  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_83_CHECKER_TYPE,
15296  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_83_WIDTH },
15297  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_84_CHECKER_TYPE,
15298  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_84_WIDTH },
15299  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_85_CHECKER_TYPE,
15300  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_85_WIDTH },
15301  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_86_CHECKER_TYPE,
15302  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_86_WIDTH },
15303  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_87_CHECKER_TYPE,
15304  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_87_WIDTH },
15305  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_88_CHECKER_TYPE,
15306  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_88_WIDTH },
15307  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_89_CHECKER_TYPE,
15308  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_89_WIDTH },
15309  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_90_CHECKER_TYPE,
15310  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_90_WIDTH },
15311  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_91_CHECKER_TYPE,
15312  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_91_WIDTH },
15313  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_92_CHECKER_TYPE,
15314  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_92_WIDTH },
15315  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_93_CHECKER_TYPE,
15316  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_93_WIDTH },
15317  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_94_CHECKER_TYPE,
15318  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_94_WIDTH },
15319  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_95_CHECKER_TYPE,
15320  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_95_WIDTH },
15321  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_96_CHECKER_TYPE,
15322  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_96_WIDTH },
15323  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_97_CHECKER_TYPE,
15324  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_97_WIDTH },
15325  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_98_CHECKER_TYPE,
15326  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_98_WIDTH },
15327  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_99_CHECKER_TYPE,
15328  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_99_WIDTH },
15329  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_100_CHECKER_TYPE,
15330  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_100_WIDTH },
15331  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_101_CHECKER_TYPE,
15332  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_101_WIDTH },
15333  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_102_CHECKER_TYPE,
15334  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_102_WIDTH },
15335  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_103_CHECKER_TYPE,
15336  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_103_WIDTH },
15337  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_104_CHECKER_TYPE,
15338  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_104_WIDTH },
15339  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_105_CHECKER_TYPE,
15340  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_105_WIDTH },
15341  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_106_CHECKER_TYPE,
15342  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_106_WIDTH },
15343  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_107_CHECKER_TYPE,
15344  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_107_WIDTH },
15345  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_108_CHECKER_TYPE,
15346  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_108_WIDTH },
15347  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_109_CHECKER_TYPE,
15348  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_109_WIDTH },
15349  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_110_CHECKER_TYPE,
15350  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_110_WIDTH },
15351  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_111_CHECKER_TYPE,
15352  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_111_WIDTH },
15353  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_112_CHECKER_TYPE,
15354  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_112_WIDTH },
15355  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_113_CHECKER_TYPE,
15356  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_113_WIDTH },
15357  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_114_CHECKER_TYPE,
15358  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_114_WIDTH },
15359  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_115_CHECKER_TYPE,
15360  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_115_WIDTH },
15361  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_116_CHECKER_TYPE,
15362  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_116_WIDTH },
15363  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_117_CHECKER_TYPE,
15364  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_117_WIDTH },
15365  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_118_CHECKER_TYPE,
15366  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_118_WIDTH },
15367  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_119_CHECKER_TYPE,
15368  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_119_WIDTH },
15369  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_120_CHECKER_TYPE,
15370  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_120_WIDTH },
15371  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_121_CHECKER_TYPE,
15372  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_121_WIDTH },
15373  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_122_CHECKER_TYPE,
15374  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_122_WIDTH },
15375  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_123_CHECKER_TYPE,
15376  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_123_WIDTH },
15377  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_124_CHECKER_TYPE,
15378  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_124_WIDTH },
15379  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_125_CHECKER_TYPE,
15380  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_125_WIDTH },
15381  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_126_CHECKER_TYPE,
15382  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_126_WIDTH },
15383  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_127_CHECKER_TYPE,
15384  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_127_WIDTH },
15385  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_128_CHECKER_TYPE,
15386  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_128_WIDTH },
15387  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_129_CHECKER_TYPE,
15388  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_129_WIDTH },
15389  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_130_CHECKER_TYPE,
15390  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_130_WIDTH },
15391  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_131_CHECKER_TYPE,
15392  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_131_WIDTH },
15393  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_132_CHECKER_TYPE,
15394  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_132_WIDTH },
15395  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_133_CHECKER_TYPE,
15396  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_133_WIDTH },
15397  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_134_CHECKER_TYPE,
15398  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_134_WIDTH },
15399  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_135_CHECKER_TYPE,
15400  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_135_WIDTH },
15401  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_136_CHECKER_TYPE,
15402  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_136_WIDTH },
15403  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_137_CHECKER_TYPE,
15404  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_137_WIDTH },
15405  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_138_CHECKER_TYPE,
15406  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_138_WIDTH },
15407  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_139_CHECKER_TYPE,
15408  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_139_WIDTH },
15409  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_140_CHECKER_TYPE,
15410  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_140_WIDTH },
15411  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_141_CHECKER_TYPE,
15412  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_141_WIDTH },
15413  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_142_CHECKER_TYPE,
15414  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_142_WIDTH },
15415  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_143_CHECKER_TYPE,
15416  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_143_WIDTH },
15417  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_144_CHECKER_TYPE,
15418  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_144_WIDTH },
15419  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_145_CHECKER_TYPE,
15420  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_145_WIDTH },
15421  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_146_CHECKER_TYPE,
15422  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_146_WIDTH },
15423  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_147_CHECKER_TYPE,
15424  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_147_WIDTH },
15425  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_148_CHECKER_TYPE,
15426  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_148_WIDTH },
15427  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_149_CHECKER_TYPE,
15428  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_149_WIDTH },
15429  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_150_CHECKER_TYPE,
15430  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_150_WIDTH },
15431  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_151_CHECKER_TYPE,
15432  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_151_WIDTH },
15433  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_152_CHECKER_TYPE,
15434  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_152_WIDTH },
15435  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_153_CHECKER_TYPE,
15436  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_153_WIDTH },
15437  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_154_CHECKER_TYPE,
15438  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_154_WIDTH },
15439  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_155_CHECKER_TYPE,
15440  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_155_WIDTH },
15441  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_156_CHECKER_TYPE,
15442  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_156_WIDTH },
15443  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_157_CHECKER_TYPE,
15444  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_157_WIDTH },
15445  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_158_CHECKER_TYPE,
15446  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_158_WIDTH },
15447  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_159_CHECKER_TYPE,
15448  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_159_WIDTH },
15449  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_160_CHECKER_TYPE,
15450  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_160_WIDTH },
15451  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_161_CHECKER_TYPE,
15452  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_161_WIDTH },
15453  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_162_CHECKER_TYPE,
15454  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_162_WIDTH },
15455  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_163_CHECKER_TYPE,
15456  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_163_WIDTH },
15457  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_164_CHECKER_TYPE,
15458  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_164_WIDTH },
15459  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_165_CHECKER_TYPE,
15460  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_165_WIDTH },
15461  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_166_CHECKER_TYPE,
15462  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_166_WIDTH },
15463  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_167_CHECKER_TYPE,
15464  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_167_WIDTH },
15465  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_168_CHECKER_TYPE,
15466  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_168_WIDTH },
15467  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_169_CHECKER_TYPE,
15468  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_169_WIDTH },
15469  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_170_CHECKER_TYPE,
15470  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_170_WIDTH },
15471  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_171_CHECKER_TYPE,
15472  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_171_WIDTH },
15473  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_172_CHECKER_TYPE,
15474  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_172_WIDTH },
15475  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_173_CHECKER_TYPE,
15476  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_173_WIDTH },
15477  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_174_CHECKER_TYPE,
15478  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_174_WIDTH },
15479  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_175_CHECKER_TYPE,
15480  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_175_WIDTH },
15481  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_176_CHECKER_TYPE,
15482  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_176_WIDTH },
15483  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_177_CHECKER_TYPE,
15484  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_177_WIDTH },
15485  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_178_CHECKER_TYPE,
15486  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_178_WIDTH },
15487  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_179_CHECKER_TYPE,
15488  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_179_WIDTH },
15489  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_180_CHECKER_TYPE,
15490  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_180_WIDTH },
15491  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_181_CHECKER_TYPE,
15492  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_181_WIDTH },
15493  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_182_CHECKER_TYPE,
15494  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_182_WIDTH },
15495  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_183_CHECKER_TYPE,
15496  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_183_WIDTH },
15497  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_184_CHECKER_TYPE,
15498  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_184_WIDTH },
15499  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_185_CHECKER_TYPE,
15500  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_185_WIDTH },
15501 };
15502 
15508 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
15509 {
15510  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
15511  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_0_WIDTH },
15512  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
15513  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_1_WIDTH },
15514  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
15515  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_2_WIDTH },
15516  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
15517  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_3_WIDTH },
15518  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
15519  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_4_WIDTH },
15520  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
15521  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_5_WIDTH },
15522  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
15523  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_6_WIDTH },
15524  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
15525  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_7_WIDTH },
15526  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
15527  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_8_WIDTH },
15528  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
15529  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_9_WIDTH },
15530  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
15531  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_10_WIDTH },
15532  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
15533  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_11_WIDTH },
15534  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
15535  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_12_WIDTH },
15536 };
15537 
15543 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
15544 {
15545  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
15546  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
15547  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
15548  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
15549  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
15550  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
15551  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
15552  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
15553  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
15554  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
15555  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
15556  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
15557  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
15558  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
15559  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
15560  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
15561  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
15562  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
15563  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
15564  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
15565  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
15566  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
15567  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
15568  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
15569  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
15570  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
15571  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
15572  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
15573  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
15574  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
15575  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
15576  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
15577  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
15578  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
15579  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
15580  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
15581  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
15582  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
15583  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
15584  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
15585  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
15586  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
15587  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
15588  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
15589  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
15590  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
15591  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
15592  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
15593  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
15594  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
15595  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
15596  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
15597  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
15598  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
15599  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
15600  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
15601  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
15602  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
15603  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
15604  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
15605  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
15606  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
15607  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
15608  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
15609  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
15610  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
15611  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
15612  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
15613  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
15614  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
15615  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
15616  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
15617  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
15618  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
15619  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
15620  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
15621  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
15622  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
15623  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
15624  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
15625  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
15626  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
15627  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
15628  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
15629  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
15630  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
15631  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
15632  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
15633  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
15634  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
15635  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
15636  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
15637  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
15638  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
15639  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
15640  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
15641  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
15642  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
15643  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
15644  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
15645  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
15646  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
15647  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
15648  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
15649  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
15650  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
15651  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
15652  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
15653  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
15654  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
15655  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
15656  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
15657  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
15658  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
15659  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
15660  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
15661  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
15662  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
15663  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
15664  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
15665  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
15666  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
15667  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
15668  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
15669  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
15670  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
15671  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
15672  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
15673  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
15674  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
15675  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
15676  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
15677  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
15678  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
15679  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
15680  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
15681  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
15682  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
15683  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_69_CHECKER_TYPE,
15684  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
15685  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_70_CHECKER_TYPE,
15686  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_70_WIDTH },
15687  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_71_CHECKER_TYPE,
15688  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_71_WIDTH },
15689  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_72_CHECKER_TYPE,
15690  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_72_WIDTH },
15691  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_73_CHECKER_TYPE,
15692  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_73_WIDTH },
15693  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_74_CHECKER_TYPE,
15694  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_74_WIDTH },
15695  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_75_CHECKER_TYPE,
15696  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_75_WIDTH },
15697  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_76_CHECKER_TYPE,
15698  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_76_WIDTH },
15699  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_77_CHECKER_TYPE,
15700  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_77_WIDTH },
15701  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_78_CHECKER_TYPE,
15702  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_78_WIDTH },
15703  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_79_CHECKER_TYPE,
15704  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_79_WIDTH },
15705  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_80_CHECKER_TYPE,
15706  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_80_WIDTH },
15707  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_81_CHECKER_TYPE,
15708  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_81_WIDTH },
15709  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_82_CHECKER_TYPE,
15710  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_82_WIDTH },
15711  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_83_CHECKER_TYPE,
15712  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_83_WIDTH },
15713  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_84_CHECKER_TYPE,
15714  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_84_WIDTH },
15715  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_85_CHECKER_TYPE,
15716  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_85_WIDTH },
15717  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_86_CHECKER_TYPE,
15718  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_86_WIDTH },
15719  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_87_CHECKER_TYPE,
15720  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_87_WIDTH },
15721  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_88_CHECKER_TYPE,
15722  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_88_WIDTH },
15723  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_89_CHECKER_TYPE,
15724  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_89_WIDTH },
15725  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_90_CHECKER_TYPE,
15726  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_90_WIDTH },
15727  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_91_CHECKER_TYPE,
15728  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_91_WIDTH },
15729  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_92_CHECKER_TYPE,
15730  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_92_WIDTH },
15731  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_93_CHECKER_TYPE,
15732  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_93_WIDTH },
15733  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_94_CHECKER_TYPE,
15734  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_94_WIDTH },
15735  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_95_CHECKER_TYPE,
15736  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_95_WIDTH },
15737  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_96_CHECKER_TYPE,
15738  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_96_WIDTH },
15739  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_97_CHECKER_TYPE,
15740  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_97_WIDTH },
15741  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_98_CHECKER_TYPE,
15742  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_98_WIDTH },
15743  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_99_CHECKER_TYPE,
15744  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_99_WIDTH },
15745  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_100_CHECKER_TYPE,
15746  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_100_WIDTH },
15747  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_101_CHECKER_TYPE,
15748  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_101_WIDTH },
15749  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_102_CHECKER_TYPE,
15750  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_102_WIDTH },
15751  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_103_CHECKER_TYPE,
15752  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_103_WIDTH },
15753  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_104_CHECKER_TYPE,
15754  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_104_WIDTH },
15755  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_105_CHECKER_TYPE,
15756  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_105_WIDTH },
15757  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_106_CHECKER_TYPE,
15758  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_106_WIDTH },
15759  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_107_CHECKER_TYPE,
15760  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_107_WIDTH },
15761  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_108_CHECKER_TYPE,
15762  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_108_WIDTH },
15763  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_109_CHECKER_TYPE,
15764  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_109_WIDTH },
15765  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_110_CHECKER_TYPE,
15766  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_110_WIDTH },
15767  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_111_CHECKER_TYPE,
15768  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_111_WIDTH },
15769  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_112_CHECKER_TYPE,
15770  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_112_WIDTH },
15771  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_113_CHECKER_TYPE,
15772  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_113_WIDTH },
15773  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_114_CHECKER_TYPE,
15774  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_114_WIDTH },
15775  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_115_CHECKER_TYPE,
15776  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_115_WIDTH },
15777  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_116_CHECKER_TYPE,
15778  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_116_WIDTH },
15779  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_117_CHECKER_TYPE,
15780  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_117_WIDTH },
15781  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_118_CHECKER_TYPE,
15782  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_118_WIDTH },
15783  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_119_CHECKER_TYPE,
15784  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_119_WIDTH },
15785  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_120_CHECKER_TYPE,
15786  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_120_WIDTH },
15787  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_121_CHECKER_TYPE,
15788  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_121_WIDTH },
15789  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_122_CHECKER_TYPE,
15790  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_122_WIDTH },
15791  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_123_CHECKER_TYPE,
15792  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_123_WIDTH },
15793  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_124_CHECKER_TYPE,
15794  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_124_WIDTH },
15795  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_125_CHECKER_TYPE,
15796  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_125_WIDTH },
15797  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_126_CHECKER_TYPE,
15798  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_126_WIDTH },
15799  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_127_CHECKER_TYPE,
15800  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_127_WIDTH },
15801  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_128_CHECKER_TYPE,
15802  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_128_WIDTH },
15803  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_129_CHECKER_TYPE,
15804  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_129_WIDTH },
15805  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_130_CHECKER_TYPE,
15806  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_130_WIDTH },
15807  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_131_CHECKER_TYPE,
15808  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_131_WIDTH },
15809  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_132_CHECKER_TYPE,
15810  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_132_WIDTH },
15811  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_133_CHECKER_TYPE,
15812  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_133_WIDTH },
15813  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_134_CHECKER_TYPE,
15814  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_134_WIDTH },
15815  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_135_CHECKER_TYPE,
15816  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_135_WIDTH },
15817  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_136_CHECKER_TYPE,
15818  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_136_WIDTH },
15819  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_137_CHECKER_TYPE,
15820  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_137_WIDTH },
15821  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_138_CHECKER_TYPE,
15822  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_138_WIDTH },
15823  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_139_CHECKER_TYPE,
15824  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_139_WIDTH },
15825  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_140_CHECKER_TYPE,
15826  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_140_WIDTH },
15827  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_141_CHECKER_TYPE,
15828  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_141_WIDTH },
15829  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_142_CHECKER_TYPE,
15830  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_142_WIDTH },
15831  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_143_CHECKER_TYPE,
15832  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_143_WIDTH },
15833  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_144_CHECKER_TYPE,
15834  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_144_WIDTH },
15835  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_145_CHECKER_TYPE,
15836  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_145_WIDTH },
15837  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_146_CHECKER_TYPE,
15838  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_146_WIDTH },
15839  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_147_CHECKER_TYPE,
15840  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_147_WIDTH },
15841  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_148_CHECKER_TYPE,
15842  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_148_WIDTH },
15843  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_149_CHECKER_TYPE,
15844  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_149_WIDTH },
15845  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_150_CHECKER_TYPE,
15846  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_150_WIDTH },
15847  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_151_CHECKER_TYPE,
15848  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_151_WIDTH },
15849  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_152_CHECKER_TYPE,
15850  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_152_WIDTH },
15851  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_153_CHECKER_TYPE,
15852  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_153_WIDTH },
15853  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_154_CHECKER_TYPE,
15854  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_154_WIDTH },
15855  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_155_CHECKER_TYPE,
15856  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_155_WIDTH },
15857  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_156_CHECKER_TYPE,
15858  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_156_WIDTH },
15859  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_157_CHECKER_TYPE,
15860  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_157_WIDTH },
15861  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_158_CHECKER_TYPE,
15862  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_158_WIDTH },
15863  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_159_CHECKER_TYPE,
15864  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_159_WIDTH },
15865  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_160_CHECKER_TYPE,
15866  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_160_WIDTH },
15867  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_161_CHECKER_TYPE,
15868  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_161_WIDTH },
15869  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_162_CHECKER_TYPE,
15870  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_162_WIDTH },
15871  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_163_CHECKER_TYPE,
15872  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_163_WIDTH },
15873  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_164_CHECKER_TYPE,
15874  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_164_WIDTH },
15875  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_165_CHECKER_TYPE,
15876  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_165_WIDTH },
15877 };
15878 
15884 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
15885 {
15886  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
15887  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
15888  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
15889  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
15890  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
15891  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
15892  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
15893  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
15894  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
15895  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
15896  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
15897  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
15898  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
15899  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
15900  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
15901  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
15902  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
15903  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
15904  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
15905  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
15906  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
15907  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
15908  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
15909  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
15910  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
15911  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
15912  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
15913  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
15914  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
15915  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
15916  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
15917  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
15918  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
15919  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
15920  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
15921  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
15922  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
15923  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
15924  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
15925  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
15926  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
15927  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
15928  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
15929  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
15930  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
15931  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
15932  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
15933  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
15934  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
15935  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
15936  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
15937  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
15938  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
15939  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
15940  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
15941  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
15942  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
15943  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
15944  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
15945  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
15946  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
15947  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
15948  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
15949  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
15950  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
15951  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
15952  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
15953  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
15954  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
15955  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
15956  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
15957  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
15958  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
15959  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
15960  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
15961  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
15962  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
15963  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
15964  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
15965  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
15966  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
15967  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
15968  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
15969  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
15970  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
15971  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
15972  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
15973  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
15974  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
15975  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
15976  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
15977  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
15978  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
15979  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
15980  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
15981  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
15982  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
15983  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
15984  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
15985  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
15986  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
15987  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
15988  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
15989  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
15990  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
15991  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
15992  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
15993  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
15994  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
15995  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
15996  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
15997  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
15998  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
15999  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
16000  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
16001  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
16002  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
16003  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
16004  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
16005  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
16006  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
16007  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
16008  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
16009  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
16010  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
16011  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
16012 };
16013 
16019 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
16020 {
16021  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
16022  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
16023  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
16024  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
16025  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
16026  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
16027  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
16028  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
16029  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
16030  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
16031  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
16032  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
16033  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
16034  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
16035  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
16036  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
16037 };
16038 
16044 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
16045 {
16046  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
16047  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
16048  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
16049  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
16050  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
16051  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
16052  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
16053  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
16054  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
16055  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
16056  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
16057  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
16058  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
16059  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
16060  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
16061  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
16062  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
16063  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
16064  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
16065  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
16066  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
16067  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
16068  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
16069  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
16070  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
16071  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
16072  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
16073  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
16074  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
16075  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
16076  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
16077  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
16078  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
16079  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
16080  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
16081  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
16082  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
16083  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
16084  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
16085  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
16086  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
16087  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
16088  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
16089  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
16090  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
16091  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
16092  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
16093  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
16094  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
16095  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
16096  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
16097  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
16098  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
16099  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
16100  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
16101  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
16102  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
16103  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
16104  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
16105  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
16106  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
16107  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
16108  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
16109  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
16110  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
16111  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
16112  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
16113  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
16114  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
16115  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
16116  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
16117  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
16118  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
16119  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
16120  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
16121  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
16122  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
16123  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
16124  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
16125  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
16126  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
16127  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
16128  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
16129  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
16130 };
16131 
16137 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
16138 {
16139  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
16140  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
16141  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
16142  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
16143  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
16144  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
16145  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
16146  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_3_WIDTH },
16147  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
16148  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_4_WIDTH },
16149  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
16150  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_5_WIDTH },
16151  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
16152  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_6_WIDTH },
16153  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
16154  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_7_WIDTH },
16155  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
16156  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_8_WIDTH },
16157  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
16158  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_9_WIDTH },
16159  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
16160  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_10_WIDTH },
16161  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
16162  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_11_WIDTH },
16163  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
16164  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_12_WIDTH },
16165  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_13_CHECKER_TYPE,
16166  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_13_WIDTH },
16167  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_14_CHECKER_TYPE,
16168  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_14_WIDTH },
16169  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_15_CHECKER_TYPE,
16170  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_15_WIDTH },
16171  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_16_CHECKER_TYPE,
16172  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_16_WIDTH },
16173  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_17_CHECKER_TYPE,
16174  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_17_WIDTH },
16175  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_18_CHECKER_TYPE,
16176  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_18_WIDTH },
16177 };
16178 
16184 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
16185 {
16186  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
16187  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
16188  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
16189  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
16190  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
16191  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
16192  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
16193  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
16194  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
16195  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
16196  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
16197  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
16198  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
16199  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
16200  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
16201  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
16202  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
16203  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
16204  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
16205  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
16206  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
16207  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
16208  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
16209  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
16210  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
16211  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
16212  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
16213  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
16214  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
16215  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
16216  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
16217  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
16218 };
16219 
16225 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_MAX_NUM_CHECKERS] =
16226 {
16227  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_0_CHECKER_TYPE,
16228  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_0_WIDTH },
16229  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_1_CHECKER_TYPE,
16230  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_1_WIDTH },
16231  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_2_CHECKER_TYPE,
16232  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_2_WIDTH },
16233  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_3_CHECKER_TYPE,
16234  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_3_WIDTH },
16235  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_4_CHECKER_TYPE,
16236  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_4_WIDTH },
16237  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_5_CHECKER_TYPE,
16238  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_5_WIDTH },
16239 };
16240 
16245 static const SDL_MemConfig_t SDL_SMS0_SMS_TIFS_ECC_MemEntries[SDL_SMS0_SMS_TIFS_ECC_RAM_IDS_TOTAL_ENTRIES] =
16246 {
16247  { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_RAMECC_RAM_ID, 0u,
16248  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_RAMECC_RAM_SIZE, 4u,
16249  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_RAMECC_ROW_WIDTH, ((bool)false) },
16250  { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_RAMECC_RAM_ID, 0u,
16251  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_RAMECC_RAM_SIZE, 4u,
16252  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_RAMECC_ROW_WIDTH, ((bool)false) },
16253 };
16254 
16260 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_MAX_NUM_CHECKERS] =
16261 {
16262  { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_0_CHECKER_TYPE,
16263  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_0_WIDTH },
16264  { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_1_CHECKER_TYPE,
16265  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_1_WIDTH },
16266  { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_2_CHECKER_TYPE,
16267  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_2_WIDTH },
16268  { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_3_CHECKER_TYPE,
16269  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_3_WIDTH },
16270  { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_4_CHECKER_TYPE,
16271  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_4_WIDTH },
16272  { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_5_CHECKER_TYPE,
16273  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_5_WIDTH },
16274  { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_6_CHECKER_TYPE,
16275  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_6_WIDTH },
16276  { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_7_CHECKER_TYPE,
16277  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_7_WIDTH },
16278  { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_8_CHECKER_TYPE,
16279  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_8_WIDTH },
16280  { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_9_CHECKER_TYPE,
16281  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_9_WIDTH },
16282  { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_10_CHECKER_TYPE,
16283  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_10_WIDTH },
16284  { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_11_CHECKER_TYPE,
16285  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_11_WIDTH },
16286  { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_12_CHECKER_TYPE,
16287  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_12_WIDTH },
16288  { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_13_CHECKER_TYPE,
16289  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_13_WIDTH },
16290  { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_14_CHECKER_TYPE,
16291  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_14_WIDTH },
16292  { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_15_CHECKER_TYPE,
16293  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_15_WIDTH },
16294  { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_16_CHECKER_TYPE,
16295  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_16_WIDTH },
16296  { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_17_CHECKER_TYPE,
16297  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_17_WIDTH },
16298  { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_18_CHECKER_TYPE,
16299  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_18_WIDTH },
16300  { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_19_CHECKER_TYPE,
16301  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_19_WIDTH },
16302 };
16303 
16309 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_MAX_NUM_CHECKERS] =
16310 {
16311  { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_0_CHECKER_TYPE,
16312  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_0_WIDTH },
16313  { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_1_CHECKER_TYPE,
16314  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_1_WIDTH },
16315  { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_2_CHECKER_TYPE,
16316  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_2_WIDTH },
16317  { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_3_CHECKER_TYPE,
16318  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_3_WIDTH },
16319  { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_4_CHECKER_TYPE,
16320  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_4_WIDTH },
16321  { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_5_CHECKER_TYPE,
16322  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_5_WIDTH },
16323  { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_6_CHECKER_TYPE,
16324  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_6_WIDTH },
16325  { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_7_CHECKER_TYPE,
16326  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_7_WIDTH },
16327  { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_8_CHECKER_TYPE,
16328  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_8_WIDTH },
16329  { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_9_CHECKER_TYPE,
16330  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_9_WIDTH },
16331  { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_10_CHECKER_TYPE,
16332  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_10_WIDTH },
16333  { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_11_CHECKER_TYPE,
16334  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_11_WIDTH },
16335  { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_12_CHECKER_TYPE,
16336  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_12_WIDTH },
16337  { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_13_CHECKER_TYPE,
16338  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_13_WIDTH },
16339  { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_14_CHECKER_TYPE,
16340  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_14_WIDTH },
16341  { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_15_CHECKER_TYPE,
16342  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_15_WIDTH },
16343  { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_16_CHECKER_TYPE,
16344  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_16_WIDTH },
16345  { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_17_CHECKER_TYPE,
16346  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_17_WIDTH },
16347  { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_18_CHECKER_TYPE,
16348  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_18_WIDTH },
16349  { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_19_CHECKER_TYPE,
16350  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_19_WIDTH },
16351 };
16352 
16358 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_MAX_NUM_CHECKERS] =
16359 {
16360  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_0_CHECKER_TYPE,
16361  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_0_WIDTH },
16362  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_1_CHECKER_TYPE,
16363  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_1_WIDTH },
16364  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_2_CHECKER_TYPE,
16365  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_2_WIDTH },
16366  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_3_CHECKER_TYPE,
16367  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_3_WIDTH },
16368  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_4_CHECKER_TYPE,
16369  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_4_WIDTH },
16370  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_5_CHECKER_TYPE,
16371  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_5_WIDTH },
16372  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_6_CHECKER_TYPE,
16373  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_6_WIDTH },
16374  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_7_CHECKER_TYPE,
16375  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_7_WIDTH },
16376  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_8_CHECKER_TYPE,
16377  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_8_WIDTH },
16378  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_9_CHECKER_TYPE,
16379  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_9_WIDTH },
16380  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_10_CHECKER_TYPE,
16381  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_10_WIDTH },
16382  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_11_CHECKER_TYPE,
16383  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_11_WIDTH },
16384  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_12_CHECKER_TYPE,
16385  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_12_WIDTH },
16386  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_13_CHECKER_TYPE,
16387  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_13_WIDTH },
16388  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_14_CHECKER_TYPE,
16389  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_14_WIDTH },
16390  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_15_CHECKER_TYPE,
16391  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_15_WIDTH },
16392  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_16_CHECKER_TYPE,
16393  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_16_WIDTH },
16394  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_17_CHECKER_TYPE,
16395  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_17_WIDTH },
16396  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_18_CHECKER_TYPE,
16397  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_18_WIDTH },
16398  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_19_CHECKER_TYPE,
16399  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_19_WIDTH },
16400  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_20_CHECKER_TYPE,
16401  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_20_WIDTH },
16402  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_21_CHECKER_TYPE,
16403  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_21_WIDTH },
16404  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_22_CHECKER_TYPE,
16405  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_22_WIDTH },
16406  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_23_CHECKER_TYPE,
16407  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_23_WIDTH },
16408  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_24_CHECKER_TYPE,
16409  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_24_WIDTH },
16410  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_25_CHECKER_TYPE,
16411  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_25_WIDTH },
16412  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_26_CHECKER_TYPE,
16413  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_26_WIDTH },
16414  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_27_CHECKER_TYPE,
16415  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_27_WIDTH },
16416  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_28_CHECKER_TYPE,
16417  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_28_WIDTH },
16418  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_29_CHECKER_TYPE,
16419  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_29_WIDTH },
16420  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_30_CHECKER_TYPE,
16421  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_30_WIDTH },
16422  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_31_CHECKER_TYPE,
16423  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_31_WIDTH },
16424  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_32_CHECKER_TYPE,
16425  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_32_WIDTH },
16426  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_33_CHECKER_TYPE,
16427  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_33_WIDTH },
16428  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_34_CHECKER_TYPE,
16429  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_34_WIDTH },
16430  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_35_CHECKER_TYPE,
16431  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_35_WIDTH },
16432  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_36_CHECKER_TYPE,
16433  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_36_WIDTH },
16434  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_37_CHECKER_TYPE,
16435  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_37_WIDTH },
16436  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_38_CHECKER_TYPE,
16437  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_38_WIDTH },
16438  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_39_CHECKER_TYPE,
16439  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_39_WIDTH },
16440  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_40_CHECKER_TYPE,
16441  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_40_WIDTH },
16442  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_41_CHECKER_TYPE,
16443  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_41_WIDTH },
16444  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_42_CHECKER_TYPE,
16445  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_42_WIDTH },
16446  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_43_CHECKER_TYPE,
16447  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_43_WIDTH },
16448  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_44_CHECKER_TYPE,
16449  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_44_WIDTH },
16450  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_45_CHECKER_TYPE,
16451  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_45_WIDTH },
16452  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_46_CHECKER_TYPE,
16453  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_46_WIDTH },
16454  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_47_CHECKER_TYPE,
16455  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_47_WIDTH },
16456  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_48_CHECKER_TYPE,
16457  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_48_WIDTH },
16458  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_49_CHECKER_TYPE,
16459  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_49_WIDTH },
16460  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_50_CHECKER_TYPE,
16461  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_50_WIDTH },
16462  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_51_CHECKER_TYPE,
16463  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_51_WIDTH },
16464  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_52_CHECKER_TYPE,
16465  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_52_WIDTH },
16466  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_53_CHECKER_TYPE,
16467  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_53_WIDTH },
16468  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_54_CHECKER_TYPE,
16469  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_54_WIDTH },
16470  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_55_CHECKER_TYPE,
16471  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_55_WIDTH },
16472  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_56_CHECKER_TYPE,
16473  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_56_WIDTH },
16474  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_57_CHECKER_TYPE,
16475  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_57_WIDTH },
16476  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_58_CHECKER_TYPE,
16477  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_58_WIDTH },
16478  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_59_CHECKER_TYPE,
16479  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_59_WIDTH },
16480  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_60_CHECKER_TYPE,
16481  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_60_WIDTH },
16482  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_61_CHECKER_TYPE,
16483  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_61_WIDTH },
16484  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_62_CHECKER_TYPE,
16485  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_62_WIDTH },
16486  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_63_CHECKER_TYPE,
16487  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_63_WIDTH },
16488  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_64_CHECKER_TYPE,
16489  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_64_WIDTH },
16490  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_65_CHECKER_TYPE,
16491  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_65_WIDTH },
16492  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_66_CHECKER_TYPE,
16493  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_66_WIDTH },
16494  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_67_CHECKER_TYPE,
16495  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_67_WIDTH },
16496  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_68_CHECKER_TYPE,
16497  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_68_WIDTH },
16498  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_69_CHECKER_TYPE,
16499  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_69_WIDTH },
16500  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_70_CHECKER_TYPE,
16501  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_70_WIDTH },
16502  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_71_CHECKER_TYPE,
16503  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_71_WIDTH },
16504  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_72_CHECKER_TYPE,
16505  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_72_WIDTH },
16506  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_73_CHECKER_TYPE,
16507  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_73_WIDTH },
16508  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_74_CHECKER_TYPE,
16509  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_74_WIDTH },
16510  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_75_CHECKER_TYPE,
16511  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_75_WIDTH },
16512  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_76_CHECKER_TYPE,
16513  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_76_WIDTH },
16514  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_77_CHECKER_TYPE,
16515  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_77_WIDTH },
16516  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_78_CHECKER_TYPE,
16517  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_78_WIDTH },
16518  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_79_CHECKER_TYPE,
16519  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_79_WIDTH },
16520  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_80_CHECKER_TYPE,
16521  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_80_WIDTH },
16522  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_81_CHECKER_TYPE,
16523  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_81_WIDTH },
16524  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_82_CHECKER_TYPE,
16525  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_82_WIDTH },
16526  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_83_CHECKER_TYPE,
16527  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_83_WIDTH },
16528  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_84_CHECKER_TYPE,
16529  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_84_WIDTH },
16530  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_85_CHECKER_TYPE,
16531  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_85_WIDTH },
16532  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_86_CHECKER_TYPE,
16533  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_86_WIDTH },
16534  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_87_CHECKER_TYPE,
16535  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_87_WIDTH },
16536  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_88_CHECKER_TYPE,
16537  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_88_WIDTH },
16538  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_89_CHECKER_TYPE,
16539  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_89_WIDTH },
16540  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_90_CHECKER_TYPE,
16541  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_90_WIDTH },
16542  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_91_CHECKER_TYPE,
16543  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_91_WIDTH },
16544  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_92_CHECKER_TYPE,
16545  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_92_WIDTH },
16546  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_93_CHECKER_TYPE,
16547  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_93_WIDTH },
16548  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_94_CHECKER_TYPE,
16549  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_94_WIDTH },
16550  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_95_CHECKER_TYPE,
16551  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_95_WIDTH },
16552  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_96_CHECKER_TYPE,
16553  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_96_WIDTH },
16554  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_97_CHECKER_TYPE,
16555  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_97_WIDTH },
16556  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_98_CHECKER_TYPE,
16557  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_98_WIDTH },
16558  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_99_CHECKER_TYPE,
16559  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_99_WIDTH },
16560  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_100_CHECKER_TYPE,
16561  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_100_WIDTH },
16562  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_101_CHECKER_TYPE,
16563  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_101_WIDTH },
16564  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_102_CHECKER_TYPE,
16565  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_102_WIDTH },
16566  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_103_CHECKER_TYPE,
16567  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_103_WIDTH },
16568  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_104_CHECKER_TYPE,
16569  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_104_WIDTH },
16570  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_105_CHECKER_TYPE,
16571  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_105_WIDTH },
16572  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_106_CHECKER_TYPE,
16573  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_106_WIDTH },
16574  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_107_CHECKER_TYPE,
16575  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_107_WIDTH },
16576  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_108_CHECKER_TYPE,
16577  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_108_WIDTH },
16578  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_109_CHECKER_TYPE,
16579  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_109_WIDTH },
16580  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_110_CHECKER_TYPE,
16581  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_110_WIDTH },
16582  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_111_CHECKER_TYPE,
16583  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_111_WIDTH },
16584  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_112_CHECKER_TYPE,
16585  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_112_WIDTH },
16586  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_113_CHECKER_TYPE,
16587  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_113_WIDTH },
16588  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_114_CHECKER_TYPE,
16589  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_114_WIDTH },
16590  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_115_CHECKER_TYPE,
16591  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_115_WIDTH },
16592  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_116_CHECKER_TYPE,
16593  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_116_WIDTH },
16594  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_117_CHECKER_TYPE,
16595  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_117_WIDTH },
16596  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_118_CHECKER_TYPE,
16597  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_118_WIDTH },
16598  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_119_CHECKER_TYPE,
16599  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_119_WIDTH },
16600  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_120_CHECKER_TYPE,
16601  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_120_WIDTH },
16602  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_121_CHECKER_TYPE,
16603  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_121_WIDTH },
16604  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_122_CHECKER_TYPE,
16605  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_122_WIDTH },
16606  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_123_CHECKER_TYPE,
16607  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_123_WIDTH },
16608  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_124_CHECKER_TYPE,
16609  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_124_WIDTH },
16610  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_125_CHECKER_TYPE,
16611  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_125_WIDTH },
16612  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_126_CHECKER_TYPE,
16613  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_126_WIDTH },
16614  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_127_CHECKER_TYPE,
16615  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_127_WIDTH },
16616  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_128_CHECKER_TYPE,
16617  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_128_WIDTH },
16618  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_129_CHECKER_TYPE,
16619  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_129_WIDTH },
16620  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_130_CHECKER_TYPE,
16621  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_130_WIDTH },
16622  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_131_CHECKER_TYPE,
16623  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_131_WIDTH },
16624  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_132_CHECKER_TYPE,
16625  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_132_WIDTH },
16626  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_133_CHECKER_TYPE,
16627  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_133_WIDTH },
16628  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_134_CHECKER_TYPE,
16629  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_134_WIDTH },
16630  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_135_CHECKER_TYPE,
16631  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_135_WIDTH },
16632  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_136_CHECKER_TYPE,
16633  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_136_WIDTH },
16634  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_137_CHECKER_TYPE,
16635  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_137_WIDTH },
16636  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_138_CHECKER_TYPE,
16637  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_138_WIDTH },
16638  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_139_CHECKER_TYPE,
16639  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_139_WIDTH },
16640  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_140_CHECKER_TYPE,
16641  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_140_WIDTH },
16642  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_141_CHECKER_TYPE,
16643  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_141_WIDTH },
16644  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_142_CHECKER_TYPE,
16645  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_142_WIDTH },
16646  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_143_CHECKER_TYPE,
16647  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_143_WIDTH },
16648  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_144_CHECKER_TYPE,
16649  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_144_WIDTH },
16650  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_145_CHECKER_TYPE,
16651  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_145_WIDTH },
16652  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_146_CHECKER_TYPE,
16653  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_146_WIDTH },
16654  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_147_CHECKER_TYPE,
16655  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_147_WIDTH },
16656  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_148_CHECKER_TYPE,
16657  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_148_WIDTH },
16658  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_149_CHECKER_TYPE,
16659  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_149_WIDTH },
16660  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_150_CHECKER_TYPE,
16661  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_150_WIDTH },
16662  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_151_CHECKER_TYPE,
16663  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_151_WIDTH },
16664  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_152_CHECKER_TYPE,
16665  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_152_WIDTH },
16666  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_153_CHECKER_TYPE,
16667  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_153_WIDTH },
16668  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_154_CHECKER_TYPE,
16669  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_154_WIDTH },
16670  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_155_CHECKER_TYPE,
16671  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_155_WIDTH },
16672  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_156_CHECKER_TYPE,
16673  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_156_WIDTH },
16674  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_157_CHECKER_TYPE,
16675  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_157_WIDTH },
16676  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_158_CHECKER_TYPE,
16677  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_158_WIDTH },
16678  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_159_CHECKER_TYPE,
16679  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_159_WIDTH },
16680  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_160_CHECKER_TYPE,
16681  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_160_WIDTH },
16682  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_161_CHECKER_TYPE,
16683  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_161_WIDTH },
16684  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_162_CHECKER_TYPE,
16685  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_162_WIDTH },
16686  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_163_CHECKER_TYPE,
16687  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_163_WIDTH },
16688  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_164_CHECKER_TYPE,
16689  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_164_WIDTH },
16690  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_165_CHECKER_TYPE,
16691  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_165_WIDTH },
16692  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_166_CHECKER_TYPE,
16693  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_166_WIDTH },
16694  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_167_CHECKER_TYPE,
16695  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_167_WIDTH },
16696  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_168_CHECKER_TYPE,
16697  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_168_WIDTH },
16698  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_169_CHECKER_TYPE,
16699  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_169_WIDTH },
16700  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_170_CHECKER_TYPE,
16701  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_170_WIDTH },
16702  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_171_CHECKER_TYPE,
16703  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_171_WIDTH },
16704  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_172_CHECKER_TYPE,
16705  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_172_WIDTH },
16706  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_173_CHECKER_TYPE,
16707  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_173_WIDTH },
16708  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_174_CHECKER_TYPE,
16709  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_174_WIDTH },
16710  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_175_CHECKER_TYPE,
16711  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_175_WIDTH },
16712  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_176_CHECKER_TYPE,
16713  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_176_WIDTH },
16714  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_177_CHECKER_TYPE,
16715  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_177_WIDTH },
16716  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_178_CHECKER_TYPE,
16717  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_178_WIDTH },
16718  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_179_CHECKER_TYPE,
16719  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_179_WIDTH },
16720  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_180_CHECKER_TYPE,
16721  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_180_WIDTH },
16722  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_181_CHECKER_TYPE,
16723  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_181_WIDTH },
16724  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_182_CHECKER_TYPE,
16725  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_182_WIDTH },
16726  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_183_CHECKER_TYPE,
16727  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_183_WIDTH },
16728  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_184_CHECKER_TYPE,
16729  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_184_WIDTH },
16730  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_185_CHECKER_TYPE,
16731  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_185_WIDTH },
16732  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_186_CHECKER_TYPE,
16733  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_186_WIDTH },
16734  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_187_CHECKER_TYPE,
16735  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_187_WIDTH },
16736  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_188_CHECKER_TYPE,
16737  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_188_WIDTH },
16738  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_189_CHECKER_TYPE,
16739  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_189_WIDTH },
16740  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_190_CHECKER_TYPE,
16741  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_190_WIDTH },
16742  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_191_CHECKER_TYPE,
16743  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_191_WIDTH },
16744  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_192_CHECKER_TYPE,
16745  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_192_WIDTH },
16746  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_193_CHECKER_TYPE,
16747  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_193_WIDTH },
16748  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_194_CHECKER_TYPE,
16749  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_194_WIDTH },
16750  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_195_CHECKER_TYPE,
16751  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_195_WIDTH },
16752  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_196_CHECKER_TYPE,
16753  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_196_WIDTH },
16754  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_197_CHECKER_TYPE,
16755  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_197_WIDTH },
16756  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_198_CHECKER_TYPE,
16757  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_198_WIDTH },
16758  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_199_CHECKER_TYPE,
16759  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_199_WIDTH },
16760  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_200_CHECKER_TYPE,
16761  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_200_WIDTH },
16762  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_201_CHECKER_TYPE,
16763  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_201_WIDTH },
16764  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_202_CHECKER_TYPE,
16765  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_202_WIDTH },
16766  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_203_CHECKER_TYPE,
16767  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_203_WIDTH },
16768  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_204_CHECKER_TYPE,
16769  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_204_WIDTH },
16770  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_205_CHECKER_TYPE,
16771  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_205_WIDTH },
16772  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_206_CHECKER_TYPE,
16773  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_206_WIDTH },
16774  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_207_CHECKER_TYPE,
16775  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_207_WIDTH },
16776  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_208_CHECKER_TYPE,
16777  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_208_WIDTH },
16778  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_209_CHECKER_TYPE,
16779  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_209_WIDTH },
16780  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_210_CHECKER_TYPE,
16781  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_210_WIDTH },
16782  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_211_CHECKER_TYPE,
16783  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_211_WIDTH },
16784  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_212_CHECKER_TYPE,
16785  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_212_WIDTH },
16786  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_213_CHECKER_TYPE,
16787  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_213_WIDTH },
16788  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_214_CHECKER_TYPE,
16789  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_214_WIDTH },
16790  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_215_CHECKER_TYPE,
16791  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_215_WIDTH },
16792  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_216_CHECKER_TYPE,
16793  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_216_WIDTH },
16794  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_217_CHECKER_TYPE,
16795  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_217_WIDTH },
16796  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_218_CHECKER_TYPE,
16797  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_218_WIDTH },
16798  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_219_CHECKER_TYPE,
16799  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_219_WIDTH },
16800  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_220_CHECKER_TYPE,
16801  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_220_WIDTH },
16802  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_221_CHECKER_TYPE,
16803  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_221_WIDTH },
16804  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_222_CHECKER_TYPE,
16805  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_222_WIDTH },
16806  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_223_CHECKER_TYPE,
16807  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_223_WIDTH },
16808  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_224_CHECKER_TYPE,
16809  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_224_WIDTH },
16810  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_225_CHECKER_TYPE,
16811  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_225_WIDTH },
16812  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_226_CHECKER_TYPE,
16813  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_226_WIDTH },
16814  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_227_CHECKER_TYPE,
16815  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_227_WIDTH },
16816  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_228_CHECKER_TYPE,
16817  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_228_WIDTH },
16818  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_229_CHECKER_TYPE,
16819  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_229_WIDTH },
16820  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_230_CHECKER_TYPE,
16821  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_230_WIDTH },
16822  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_231_CHECKER_TYPE,
16823  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_231_WIDTH },
16824  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_232_CHECKER_TYPE,
16825  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_232_WIDTH },
16826  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_233_CHECKER_TYPE,
16827  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_233_WIDTH },
16828  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_234_CHECKER_TYPE,
16829  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_234_WIDTH },
16830  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_235_CHECKER_TYPE,
16831  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_235_WIDTH },
16832  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_236_CHECKER_TYPE,
16833  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_236_WIDTH },
16834  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_237_CHECKER_TYPE,
16835  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_237_WIDTH },
16836  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_238_CHECKER_TYPE,
16837  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_238_WIDTH },
16838  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_239_CHECKER_TYPE,
16839  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_239_WIDTH },
16840  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_240_CHECKER_TYPE,
16841  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_240_WIDTH },
16842  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_241_CHECKER_TYPE,
16843  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_241_WIDTH },
16844  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_242_CHECKER_TYPE,
16845  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_242_WIDTH },
16846  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_243_CHECKER_TYPE,
16847  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_243_WIDTH },
16848  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_244_CHECKER_TYPE,
16849  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_244_WIDTH },
16850  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_245_CHECKER_TYPE,
16851  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_245_WIDTH },
16852  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_246_CHECKER_TYPE,
16853  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_246_WIDTH },
16854  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_247_CHECKER_TYPE,
16855  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_247_WIDTH },
16856  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_248_CHECKER_TYPE,
16857  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_248_WIDTH },
16858  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_249_CHECKER_TYPE,
16859  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_249_WIDTH },
16860  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_250_CHECKER_TYPE,
16861  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_250_WIDTH },
16862  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_251_CHECKER_TYPE,
16863  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_251_WIDTH },
16864  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_252_CHECKER_TYPE,
16865  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_252_WIDTH },
16866  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_253_CHECKER_TYPE,
16867  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_253_WIDTH },
16868  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_254_CHECKER_TYPE,
16869  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_254_WIDTH },
16870  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_255_CHECKER_TYPE,
16871  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_255_WIDTH },
16872 };
16873 
16879 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_MAX_NUM_CHECKERS] =
16880 {
16881  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_0_CHECKER_TYPE,
16882  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_0_WIDTH },
16883  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_1_CHECKER_TYPE,
16884  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_1_WIDTH },
16885  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_2_CHECKER_TYPE,
16886  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_2_WIDTH },
16887  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_3_CHECKER_TYPE,
16888  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_3_WIDTH },
16889  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_4_CHECKER_TYPE,
16890  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_4_WIDTH },
16891  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_5_CHECKER_TYPE,
16892  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_5_WIDTH },
16893  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_6_CHECKER_TYPE,
16894  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_6_WIDTH },
16895  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_7_CHECKER_TYPE,
16896  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_7_WIDTH },
16897  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_8_CHECKER_TYPE,
16898  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_8_WIDTH },
16899  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_9_CHECKER_TYPE,
16900  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_9_WIDTH },
16901  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_10_CHECKER_TYPE,
16902  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_10_WIDTH },
16903  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_11_CHECKER_TYPE,
16904  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_11_WIDTH },
16905  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_12_CHECKER_TYPE,
16906  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_12_WIDTH },
16907  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_13_CHECKER_TYPE,
16908  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_13_WIDTH },
16909  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_14_CHECKER_TYPE,
16910  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_14_WIDTH },
16911  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_15_CHECKER_TYPE,
16912  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_15_WIDTH },
16913  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_16_CHECKER_TYPE,
16914  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_16_WIDTH },
16915  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_17_CHECKER_TYPE,
16916  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_17_WIDTH },
16917  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_18_CHECKER_TYPE,
16918  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_18_WIDTH },
16919  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_19_CHECKER_TYPE,
16920  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_19_WIDTH },
16921  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_20_CHECKER_TYPE,
16922  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_20_WIDTH },
16923  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_21_CHECKER_TYPE,
16924  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_21_WIDTH },
16925  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_22_CHECKER_TYPE,
16926  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_22_WIDTH },
16927  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_23_CHECKER_TYPE,
16928  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_23_WIDTH },
16929  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_24_CHECKER_TYPE,
16930  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_24_WIDTH },
16931  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_25_CHECKER_TYPE,
16932  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_25_WIDTH },
16933  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_26_CHECKER_TYPE,
16934  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_26_WIDTH },
16935  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_27_CHECKER_TYPE,
16936  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_27_WIDTH },
16937  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_28_CHECKER_TYPE,
16938  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_28_WIDTH },
16939  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_29_CHECKER_TYPE,
16940  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_29_WIDTH },
16941  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_30_CHECKER_TYPE,
16942  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_30_WIDTH },
16943  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_31_CHECKER_TYPE,
16944  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_31_WIDTH },
16945  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_32_CHECKER_TYPE,
16946  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_32_WIDTH },
16947  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_33_CHECKER_TYPE,
16948  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_33_WIDTH },
16949  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_34_CHECKER_TYPE,
16950  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_34_WIDTH },
16951  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_35_CHECKER_TYPE,
16952  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_35_WIDTH },
16953  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_36_CHECKER_TYPE,
16954  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_36_WIDTH },
16955  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_37_CHECKER_TYPE,
16956  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_37_WIDTH },
16957  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_38_CHECKER_TYPE,
16958  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_38_WIDTH },
16959  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_39_CHECKER_TYPE,
16960  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_39_WIDTH },
16961  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_40_CHECKER_TYPE,
16962  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_40_WIDTH },
16963  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_41_CHECKER_TYPE,
16964  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_41_WIDTH },
16965  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_42_CHECKER_TYPE,
16966  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_42_WIDTH },
16967  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_43_CHECKER_TYPE,
16968  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_43_WIDTH },
16969  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_44_CHECKER_TYPE,
16970  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_44_WIDTH },
16971  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_45_CHECKER_TYPE,
16972  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_45_WIDTH },
16973  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_46_CHECKER_TYPE,
16974  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_46_WIDTH },
16975  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_47_CHECKER_TYPE,
16976  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_47_WIDTH },
16977  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_48_CHECKER_TYPE,
16978  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_48_WIDTH },
16979  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_49_CHECKER_TYPE,
16980  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_49_WIDTH },
16981  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_50_CHECKER_TYPE,
16982  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_50_WIDTH },
16983  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_51_CHECKER_TYPE,
16984  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_51_WIDTH },
16985  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_52_CHECKER_TYPE,
16986  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_52_WIDTH },
16987  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_53_CHECKER_TYPE,
16988  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_53_WIDTH },
16989  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_54_CHECKER_TYPE,
16990  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_54_WIDTH },
16991  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_55_CHECKER_TYPE,
16992  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_55_WIDTH },
16993  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_56_CHECKER_TYPE,
16994  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_56_WIDTH },
16995  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_57_CHECKER_TYPE,
16996  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_57_WIDTH },
16997  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_58_CHECKER_TYPE,
16998  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_58_WIDTH },
16999  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_59_CHECKER_TYPE,
17000  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_59_WIDTH },
17001  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_60_CHECKER_TYPE,
17002  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_60_WIDTH },
17003  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_61_CHECKER_TYPE,
17004  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_61_WIDTH },
17005  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_62_CHECKER_TYPE,
17006  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_62_WIDTH },
17007  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_63_CHECKER_TYPE,
17008  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_63_WIDTH },
17009  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_64_CHECKER_TYPE,
17010  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_64_WIDTH },
17011  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_65_CHECKER_TYPE,
17012  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_65_WIDTH },
17013  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_66_CHECKER_TYPE,
17014  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_66_WIDTH },
17015  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_67_CHECKER_TYPE,
17016  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_67_WIDTH },
17017  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_68_CHECKER_TYPE,
17018  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_68_WIDTH },
17019  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_69_CHECKER_TYPE,
17020  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_69_WIDTH },
17021  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_70_CHECKER_TYPE,
17022  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_70_WIDTH },
17023  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_71_CHECKER_TYPE,
17024  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_71_WIDTH },
17025  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_72_CHECKER_TYPE,
17026  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_72_WIDTH },
17027  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_73_CHECKER_TYPE,
17028  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_73_WIDTH },
17029  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_74_CHECKER_TYPE,
17030  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_74_WIDTH },
17031  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_75_CHECKER_TYPE,
17032  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_75_WIDTH },
17033  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_76_CHECKER_TYPE,
17034  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_76_WIDTH },
17035  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_77_CHECKER_TYPE,
17036  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_77_WIDTH },
17037  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_78_CHECKER_TYPE,
17038  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_78_WIDTH },
17039  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_79_CHECKER_TYPE,
17040  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_79_WIDTH },
17041  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_80_CHECKER_TYPE,
17042  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_80_WIDTH },
17043  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_81_CHECKER_TYPE,
17044  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_81_WIDTH },
17045  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_82_CHECKER_TYPE,
17046  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_82_WIDTH },
17047  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_83_CHECKER_TYPE,
17048  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_83_WIDTH },
17049  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_84_CHECKER_TYPE,
17050  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_84_WIDTH },
17051  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_85_CHECKER_TYPE,
17052  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_85_WIDTH },
17053  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_86_CHECKER_TYPE,
17054  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_86_WIDTH },
17055  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_87_CHECKER_TYPE,
17056  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_87_WIDTH },
17057  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_88_CHECKER_TYPE,
17058  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_88_WIDTH },
17059  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_89_CHECKER_TYPE,
17060  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_89_WIDTH },
17061  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_90_CHECKER_TYPE,
17062  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_90_WIDTH },
17063  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_91_CHECKER_TYPE,
17064  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_91_WIDTH },
17065  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_92_CHECKER_TYPE,
17066  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_92_WIDTH },
17067  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_93_CHECKER_TYPE,
17068  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_93_WIDTH },
17069  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_94_CHECKER_TYPE,
17070  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_94_WIDTH },
17071  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_95_CHECKER_TYPE,
17072  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_95_WIDTH },
17073  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_96_CHECKER_TYPE,
17074  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_96_WIDTH },
17075  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_97_CHECKER_TYPE,
17076  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_97_WIDTH },
17077  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_98_CHECKER_TYPE,
17078  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_98_WIDTH },
17079  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_99_CHECKER_TYPE,
17080  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_99_WIDTH },
17081  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_100_CHECKER_TYPE,
17082  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_100_WIDTH },
17083  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_101_CHECKER_TYPE,
17084  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_101_WIDTH },
17085  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_102_CHECKER_TYPE,
17086  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_102_WIDTH },
17087  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_103_CHECKER_TYPE,
17088  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_103_WIDTH },
17089  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_104_CHECKER_TYPE,
17090  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_104_WIDTH },
17091  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_105_CHECKER_TYPE,
17092  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_105_WIDTH },
17093  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_106_CHECKER_TYPE,
17094  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_106_WIDTH },
17095  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_107_CHECKER_TYPE,
17096  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_107_WIDTH },
17097  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_108_CHECKER_TYPE,
17098  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_108_WIDTH },
17099  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_109_CHECKER_TYPE,
17100  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_109_WIDTH },
17101  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_110_CHECKER_TYPE,
17102  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_110_WIDTH },
17103  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_111_CHECKER_TYPE,
17104  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_111_WIDTH },
17105  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_112_CHECKER_TYPE,
17106  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_112_WIDTH },
17107  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_113_CHECKER_TYPE,
17108  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_113_WIDTH },
17109  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_114_CHECKER_TYPE,
17110  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_114_WIDTH },
17111  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_115_CHECKER_TYPE,
17112  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_115_WIDTH },
17113  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_116_CHECKER_TYPE,
17114  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_116_WIDTH },
17115  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_117_CHECKER_TYPE,
17116  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_117_WIDTH },
17117  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_118_CHECKER_TYPE,
17118  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_118_WIDTH },
17119  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_119_CHECKER_TYPE,
17120  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_119_WIDTH },
17121  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_120_CHECKER_TYPE,
17122  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_120_WIDTH },
17123  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_121_CHECKER_TYPE,
17124  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_121_WIDTH },
17125  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_122_CHECKER_TYPE,
17126  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_122_WIDTH },
17127  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_123_CHECKER_TYPE,
17128  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_123_WIDTH },
17129  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_124_CHECKER_TYPE,
17130  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_124_WIDTH },
17131  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_125_CHECKER_TYPE,
17132  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_125_WIDTH },
17133  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_126_CHECKER_TYPE,
17134  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_126_WIDTH },
17135  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_127_CHECKER_TYPE,
17136  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_127_WIDTH },
17137  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_128_CHECKER_TYPE,
17138  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_128_WIDTH },
17139  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_129_CHECKER_TYPE,
17140  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_129_WIDTH },
17141  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_130_CHECKER_TYPE,
17142  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_130_WIDTH },
17143  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_131_CHECKER_TYPE,
17144  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_131_WIDTH },
17145  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_132_CHECKER_TYPE,
17146  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_132_WIDTH },
17147  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_133_CHECKER_TYPE,
17148  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_133_WIDTH },
17149  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_134_CHECKER_TYPE,
17150  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_134_WIDTH },
17151  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_135_CHECKER_TYPE,
17152  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_135_WIDTH },
17153  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_136_CHECKER_TYPE,
17154  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_136_WIDTH },
17155  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_137_CHECKER_TYPE,
17156  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_137_WIDTH },
17157  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_138_CHECKER_TYPE,
17158  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_138_WIDTH },
17159  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_139_CHECKER_TYPE,
17160  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_139_WIDTH },
17161  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_140_CHECKER_TYPE,
17162  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_140_WIDTH },
17163  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_141_CHECKER_TYPE,
17164  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_141_WIDTH },
17165  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_142_CHECKER_TYPE,
17166  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_142_WIDTH },
17167  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_143_CHECKER_TYPE,
17168  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_143_WIDTH },
17169  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_144_CHECKER_TYPE,
17170  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_144_WIDTH },
17171  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_145_CHECKER_TYPE,
17172  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_145_WIDTH },
17173  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_146_CHECKER_TYPE,
17174  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_146_WIDTH },
17175  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_147_CHECKER_TYPE,
17176  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_147_WIDTH },
17177  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_148_CHECKER_TYPE,
17178  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_148_WIDTH },
17179  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_149_CHECKER_TYPE,
17180  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_149_WIDTH },
17181  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_150_CHECKER_TYPE,
17182  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_150_WIDTH },
17183  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_151_CHECKER_TYPE,
17184  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_151_WIDTH },
17185  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_152_CHECKER_TYPE,
17186  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_152_WIDTH },
17187  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_153_CHECKER_TYPE,
17188  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_153_WIDTH },
17189  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_154_CHECKER_TYPE,
17190  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_154_WIDTH },
17191  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_155_CHECKER_TYPE,
17192  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_155_WIDTH },
17193  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_156_CHECKER_TYPE,
17194  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_156_WIDTH },
17195  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_157_CHECKER_TYPE,
17196  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_157_WIDTH },
17197  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_158_CHECKER_TYPE,
17198  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_158_WIDTH },
17199  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_159_CHECKER_TYPE,
17200  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_159_WIDTH },
17201  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_160_CHECKER_TYPE,
17202  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_160_WIDTH },
17203  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_161_CHECKER_TYPE,
17204  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_161_WIDTH },
17205  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_162_CHECKER_TYPE,
17206  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_162_WIDTH },
17207  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_163_CHECKER_TYPE,
17208  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_163_WIDTH },
17209  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_164_CHECKER_TYPE,
17210  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_164_WIDTH },
17211  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_165_CHECKER_TYPE,
17212  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_165_WIDTH },
17213  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_166_CHECKER_TYPE,
17214  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_166_WIDTH },
17215  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_167_CHECKER_TYPE,
17216  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_167_WIDTH },
17217  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_168_CHECKER_TYPE,
17218  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_168_WIDTH },
17219  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_169_CHECKER_TYPE,
17220  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_169_WIDTH },
17221  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_170_CHECKER_TYPE,
17222  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_170_WIDTH },
17223  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_171_CHECKER_TYPE,
17224  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_171_WIDTH },
17225  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_172_CHECKER_TYPE,
17226  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_172_WIDTH },
17227  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_173_CHECKER_TYPE,
17228  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_173_WIDTH },
17229  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_174_CHECKER_TYPE,
17230  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_174_WIDTH },
17231  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_175_CHECKER_TYPE,
17232  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_175_WIDTH },
17233  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_176_CHECKER_TYPE,
17234  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_176_WIDTH },
17235  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_177_CHECKER_TYPE,
17236  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_177_WIDTH },
17237  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_178_CHECKER_TYPE,
17238  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_178_WIDTH },
17239  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_179_CHECKER_TYPE,
17240  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_179_WIDTH },
17241  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_180_CHECKER_TYPE,
17242  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_180_WIDTH },
17243  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_181_CHECKER_TYPE,
17244  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_181_WIDTH },
17245  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_182_CHECKER_TYPE,
17246  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_182_WIDTH },
17247  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_183_CHECKER_TYPE,
17248  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_183_WIDTH },
17249  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_184_CHECKER_TYPE,
17250  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_184_WIDTH },
17251  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_185_CHECKER_TYPE,
17252  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_185_WIDTH },
17253  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_186_CHECKER_TYPE,
17254  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_186_WIDTH },
17255  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_187_CHECKER_TYPE,
17256  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_187_WIDTH },
17257  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_188_CHECKER_TYPE,
17258  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_188_WIDTH },
17259  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_189_CHECKER_TYPE,
17260  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_189_WIDTH },
17261  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_190_CHECKER_TYPE,
17262  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_190_WIDTH },
17263  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_191_CHECKER_TYPE,
17264  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_191_WIDTH },
17265  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_192_CHECKER_TYPE,
17266  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_192_WIDTH },
17267  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_193_CHECKER_TYPE,
17268  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_193_WIDTH },
17269  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_194_CHECKER_TYPE,
17270  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_194_WIDTH },
17271  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_195_CHECKER_TYPE,
17272  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_195_WIDTH },
17273  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_196_CHECKER_TYPE,
17274  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_196_WIDTH },
17275  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_197_CHECKER_TYPE,
17276  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_197_WIDTH },
17277  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_198_CHECKER_TYPE,
17278  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_198_WIDTH },
17279  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_199_CHECKER_TYPE,
17280  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_199_WIDTH },
17281  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_200_CHECKER_TYPE,
17282  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_200_WIDTH },
17283  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_201_CHECKER_TYPE,
17284  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_201_WIDTH },
17285  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_202_CHECKER_TYPE,
17286  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_202_WIDTH },
17287  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_203_CHECKER_TYPE,
17288  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_203_WIDTH },
17289  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_204_CHECKER_TYPE,
17290  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_204_WIDTH },
17291  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_205_CHECKER_TYPE,
17292  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_205_WIDTH },
17293  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_206_CHECKER_TYPE,
17294  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_206_WIDTH },
17295  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_207_CHECKER_TYPE,
17296  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_207_WIDTH },
17297  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_208_CHECKER_TYPE,
17298  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_208_WIDTH },
17299  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_209_CHECKER_TYPE,
17300  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_209_WIDTH },
17301  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_210_CHECKER_TYPE,
17302  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_210_WIDTH },
17303  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_211_CHECKER_TYPE,
17304  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_211_WIDTH },
17305  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_212_CHECKER_TYPE,
17306  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_212_WIDTH },
17307  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_213_CHECKER_TYPE,
17308  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_213_WIDTH },
17309  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_214_CHECKER_TYPE,
17310  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_214_WIDTH },
17311  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_215_CHECKER_TYPE,
17312  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_215_WIDTH },
17313  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_216_CHECKER_TYPE,
17314  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_216_WIDTH },
17315  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_217_CHECKER_TYPE,
17316  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_217_WIDTH },
17317  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_218_CHECKER_TYPE,
17318  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_218_WIDTH },
17319  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_219_CHECKER_TYPE,
17320  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_219_WIDTH },
17321  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_220_CHECKER_TYPE,
17322  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_220_WIDTH },
17323  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_221_CHECKER_TYPE,
17324  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_221_WIDTH },
17325  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_222_CHECKER_TYPE,
17326  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_222_WIDTH },
17327  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_223_CHECKER_TYPE,
17328  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_223_WIDTH },
17329  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_224_CHECKER_TYPE,
17330  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_224_WIDTH },
17331  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_225_CHECKER_TYPE,
17332  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_225_WIDTH },
17333  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_226_CHECKER_TYPE,
17334  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_226_WIDTH },
17335  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_227_CHECKER_TYPE,
17336  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_227_WIDTH },
17337  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_228_CHECKER_TYPE,
17338  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_228_WIDTH },
17339  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_229_CHECKER_TYPE,
17340  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_229_WIDTH },
17341  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_230_CHECKER_TYPE,
17342  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_230_WIDTH },
17343  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_231_CHECKER_TYPE,
17344  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_231_WIDTH },
17345  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_232_CHECKER_TYPE,
17346  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_232_WIDTH },
17347  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_233_CHECKER_TYPE,
17348  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_233_WIDTH },
17349  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_234_CHECKER_TYPE,
17350  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_234_WIDTH },
17351  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_235_CHECKER_TYPE,
17352  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_235_WIDTH },
17353  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_236_CHECKER_TYPE,
17354  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_236_WIDTH },
17355  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_237_CHECKER_TYPE,
17356  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_237_WIDTH },
17357  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_238_CHECKER_TYPE,
17358  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_238_WIDTH },
17359  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_239_CHECKER_TYPE,
17360  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_239_WIDTH },
17361  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_240_CHECKER_TYPE,
17362  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_240_WIDTH },
17363  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_241_CHECKER_TYPE,
17364  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_241_WIDTH },
17365  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_242_CHECKER_TYPE,
17366  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_242_WIDTH },
17367  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_243_CHECKER_TYPE,
17368  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_243_WIDTH },
17369  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_244_CHECKER_TYPE,
17370  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_244_WIDTH },
17371  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_245_CHECKER_TYPE,
17372  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_245_WIDTH },
17373  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_246_CHECKER_TYPE,
17374  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_246_WIDTH },
17375  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_247_CHECKER_TYPE,
17376  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_247_WIDTH },
17377  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_248_CHECKER_TYPE,
17378  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_248_WIDTH },
17379  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_249_CHECKER_TYPE,
17380  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_249_WIDTH },
17381  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_250_CHECKER_TYPE,
17382  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_250_WIDTH },
17383  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_251_CHECKER_TYPE,
17384  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_251_WIDTH },
17385  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_252_CHECKER_TYPE,
17386  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_252_WIDTH },
17387  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_253_CHECKER_TYPE,
17388  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_253_WIDTH },
17389  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_254_CHECKER_TYPE,
17390  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_254_WIDTH },
17391  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_255_CHECKER_TYPE,
17392  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_255_WIDTH },
17393 };
17394 
17400 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_MAX_NUM_CHECKERS] =
17401 {
17402  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_0_CHECKER_TYPE,
17403  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_0_WIDTH },
17404  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_1_CHECKER_TYPE,
17405  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_1_WIDTH },
17406  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_2_CHECKER_TYPE,
17407  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_2_WIDTH },
17408  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_3_CHECKER_TYPE,
17409  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_3_WIDTH },
17410  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_4_CHECKER_TYPE,
17411  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_4_WIDTH },
17412  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_5_CHECKER_TYPE,
17413  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_5_WIDTH },
17414  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_6_CHECKER_TYPE,
17415  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_6_WIDTH },
17416  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_7_CHECKER_TYPE,
17417  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_7_WIDTH },
17418  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_8_CHECKER_TYPE,
17419  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_8_WIDTH },
17420  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_9_CHECKER_TYPE,
17421  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_9_WIDTH },
17422  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_10_CHECKER_TYPE,
17423  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_10_WIDTH },
17424  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_11_CHECKER_TYPE,
17425  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_11_WIDTH },
17426  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_12_CHECKER_TYPE,
17427  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_12_WIDTH },
17428  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_13_CHECKER_TYPE,
17429  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_13_WIDTH },
17430  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_14_CHECKER_TYPE,
17431  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_14_WIDTH },
17432  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_15_CHECKER_TYPE,
17433  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_15_WIDTH },
17434  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_16_CHECKER_TYPE,
17435  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_16_WIDTH },
17436  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_17_CHECKER_TYPE,
17437  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_17_WIDTH },
17438  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_18_CHECKER_TYPE,
17439  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_18_WIDTH },
17440  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_19_CHECKER_TYPE,
17441  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_19_WIDTH },
17442  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_20_CHECKER_TYPE,
17443  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_20_WIDTH },
17444  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_21_CHECKER_TYPE,
17445  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_21_WIDTH },
17446  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_22_CHECKER_TYPE,
17447  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_22_WIDTH },
17448  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_23_CHECKER_TYPE,
17449  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_23_WIDTH },
17450  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_24_CHECKER_TYPE,
17451  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_24_WIDTH },
17452  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_25_CHECKER_TYPE,
17453  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_25_WIDTH },
17454 };
17455 
17461 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
17462 {
17463  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
17464  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_0_WIDTH },
17465  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
17466  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_1_WIDTH },
17467  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
17468  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_2_WIDTH },
17469  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
17470  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_3_WIDTH },
17471  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
17472  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_4_WIDTH },
17473  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
17474  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_5_WIDTH },
17475  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
17476  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_6_WIDTH },
17477  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
17478  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_7_WIDTH },
17479  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
17480  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_8_WIDTH },
17481  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
17482  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_9_WIDTH },
17483  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
17484  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_10_WIDTH },
17485  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
17486  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_11_WIDTH },
17487  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
17488  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_12_WIDTH },
17489 };
17490 
17496 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
17497 {
17498  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
17499  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_0_WIDTH },
17500  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
17501  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_1_WIDTH },
17502  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
17503  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_2_WIDTH },
17504  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
17505  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_3_WIDTH },
17506  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
17507  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_4_WIDTH },
17508  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
17509  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_5_WIDTH },
17510  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
17511  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_6_WIDTH },
17512  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
17513  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_7_WIDTH },
17514  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
17515  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_8_WIDTH },
17516  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
17517  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_9_WIDTH },
17518  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
17519  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_10_WIDTH },
17520  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
17521  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_11_WIDTH },
17522  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
17523  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_12_WIDTH },
17524 };
17525 
17531 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] =
17532 {
17533  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_0_CHECKER_TYPE,
17534  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
17535  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_1_CHECKER_TYPE,
17536  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
17537  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_2_CHECKER_TYPE,
17538  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
17539  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_3_CHECKER_TYPE,
17540  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
17541  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_4_CHECKER_TYPE,
17542  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
17543  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_5_CHECKER_TYPE,
17544  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
17545  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_6_CHECKER_TYPE,
17546  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
17547  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_7_CHECKER_TYPE,
17548  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
17549  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_8_CHECKER_TYPE,
17550  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
17551  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_9_CHECKER_TYPE,
17552  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
17553  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_10_CHECKER_TYPE,
17554  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
17555  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_11_CHECKER_TYPE,
17556  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
17557  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_12_CHECKER_TYPE,
17558  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
17559  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_13_CHECKER_TYPE,
17560  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
17561  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_14_CHECKER_TYPE,
17562  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
17563  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_15_CHECKER_TYPE,
17564  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
17565  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_16_CHECKER_TYPE,
17566  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
17567  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_17_CHECKER_TYPE,
17568  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
17569  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_18_CHECKER_TYPE,
17570  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
17571  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_19_CHECKER_TYPE,
17572  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
17573  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_20_CHECKER_TYPE,
17574  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
17575  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_21_CHECKER_TYPE,
17576  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
17577  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_22_CHECKER_TYPE,
17578  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
17579  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_23_CHECKER_TYPE,
17580  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
17581  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_24_CHECKER_TYPE,
17582  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
17583  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_25_CHECKER_TYPE,
17584  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
17585  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_26_CHECKER_TYPE,
17586  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
17587  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_27_CHECKER_TYPE,
17588  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
17589  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_28_CHECKER_TYPE,
17590  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
17591  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_29_CHECKER_TYPE,
17592  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
17593  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_30_CHECKER_TYPE,
17594  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
17595  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_31_CHECKER_TYPE,
17596  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
17597  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_32_CHECKER_TYPE,
17598  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
17599  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_33_CHECKER_TYPE,
17600  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
17601  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_34_CHECKER_TYPE,
17602  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
17603  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_35_CHECKER_TYPE,
17604  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
17605  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_36_CHECKER_TYPE,
17606  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
17607  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_37_CHECKER_TYPE,
17608  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
17609  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_38_CHECKER_TYPE,
17610  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
17611  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_39_CHECKER_TYPE,
17612  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
17613  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_40_CHECKER_TYPE,
17614  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
17615  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_41_CHECKER_TYPE,
17616  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
17617  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_42_CHECKER_TYPE,
17618  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
17619  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_43_CHECKER_TYPE,
17620  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
17621  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_44_CHECKER_TYPE,
17622  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
17623  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_45_CHECKER_TYPE,
17624  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
17625  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_46_CHECKER_TYPE,
17626  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
17627  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_47_CHECKER_TYPE,
17628  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
17629  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_48_CHECKER_TYPE,
17630  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
17631  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_49_CHECKER_TYPE,
17632  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
17633  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_50_CHECKER_TYPE,
17634  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
17635  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_51_CHECKER_TYPE,
17636  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
17637  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_52_CHECKER_TYPE,
17638  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
17639  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_53_CHECKER_TYPE,
17640  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
17641  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_54_CHECKER_TYPE,
17642  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
17643  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_55_CHECKER_TYPE,
17644  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
17645  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_56_CHECKER_TYPE,
17646  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
17647  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_57_CHECKER_TYPE,
17648  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
17649  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_58_CHECKER_TYPE,
17650  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
17651  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_59_CHECKER_TYPE,
17652  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
17653  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_60_CHECKER_TYPE,
17654  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
17655  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_61_CHECKER_TYPE,
17656  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
17657  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_62_CHECKER_TYPE,
17658  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
17659  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_63_CHECKER_TYPE,
17660  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
17661  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_64_CHECKER_TYPE,
17662  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
17663  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_65_CHECKER_TYPE,
17664  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
17665  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_66_CHECKER_TYPE,
17666  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
17667  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_67_CHECKER_TYPE,
17668  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
17669  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_68_CHECKER_TYPE,
17670  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
17671  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_69_CHECKER_TYPE,
17672  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
17673  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_70_CHECKER_TYPE,
17674  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
17675  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_71_CHECKER_TYPE,
17676  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
17677  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_72_CHECKER_TYPE,
17678  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
17679  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_73_CHECKER_TYPE,
17680  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
17681  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_74_CHECKER_TYPE,
17682  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
17683  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_75_CHECKER_TYPE,
17684  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
17685  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_76_CHECKER_TYPE,
17686  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
17687  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_77_CHECKER_TYPE,
17688  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
17689  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_78_CHECKER_TYPE,
17690  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
17691  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_79_CHECKER_TYPE,
17692  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
17693  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_80_CHECKER_TYPE,
17694  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
17695  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_81_CHECKER_TYPE,
17696  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
17697  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_82_CHECKER_TYPE,
17698  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
17699  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_83_CHECKER_TYPE,
17700  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
17701  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_84_CHECKER_TYPE,
17702  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
17703  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_85_CHECKER_TYPE,
17704  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
17705  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_86_CHECKER_TYPE,
17706  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
17707  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_87_CHECKER_TYPE,
17708  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
17709  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_88_CHECKER_TYPE,
17710  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
17711  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_89_CHECKER_TYPE,
17712  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
17713  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_90_CHECKER_TYPE,
17714  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
17715  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_91_CHECKER_TYPE,
17716  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
17717  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_92_CHECKER_TYPE,
17718  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
17719  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_93_CHECKER_TYPE,
17720  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
17721  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_94_CHECKER_TYPE,
17722  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
17723  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_95_CHECKER_TYPE,
17724  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
17725  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_96_CHECKER_TYPE,
17726  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
17727  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_97_CHECKER_TYPE,
17728  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
17729  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_98_CHECKER_TYPE,
17730  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
17731  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_99_CHECKER_TYPE,
17732  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
17733  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_100_CHECKER_TYPE,
17734  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
17735  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_101_CHECKER_TYPE,
17736  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
17737  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_102_CHECKER_TYPE,
17738  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
17739  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_103_CHECKER_TYPE,
17740  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
17741  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_104_CHECKER_TYPE,
17742  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
17743  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_105_CHECKER_TYPE,
17744  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
17745  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_106_CHECKER_TYPE,
17746  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
17747  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_107_CHECKER_TYPE,
17748  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
17749  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_108_CHECKER_TYPE,
17750  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
17751  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_109_CHECKER_TYPE,
17752  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
17753  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_110_CHECKER_TYPE,
17754  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
17755  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_111_CHECKER_TYPE,
17756  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
17757  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_112_CHECKER_TYPE,
17758  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
17759  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_113_CHECKER_TYPE,
17760  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
17761  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_114_CHECKER_TYPE,
17762  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
17763  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_115_CHECKER_TYPE,
17764  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
17765  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_116_CHECKER_TYPE,
17766  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
17767  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_117_CHECKER_TYPE,
17768  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
17769  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_118_CHECKER_TYPE,
17770  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
17771  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_119_CHECKER_TYPE,
17772  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
17773  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_120_CHECKER_TYPE,
17774  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
17775  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_121_CHECKER_TYPE,
17776  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
17777  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_122_CHECKER_TYPE,
17778  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
17779  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_123_CHECKER_TYPE,
17780  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
17781  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_124_CHECKER_TYPE,
17782  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
17783  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_125_CHECKER_TYPE,
17784  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
17785  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_126_CHECKER_TYPE,
17786  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
17787  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_127_CHECKER_TYPE,
17788  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
17789  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_128_CHECKER_TYPE,
17790  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
17791  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_129_CHECKER_TYPE,
17792  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
17793  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_130_CHECKER_TYPE,
17794  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
17795  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_131_CHECKER_TYPE,
17796  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
17797  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_132_CHECKER_TYPE,
17798  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
17799  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_133_CHECKER_TYPE,
17800  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
17801  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_134_CHECKER_TYPE,
17802  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
17803  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_135_CHECKER_TYPE,
17804  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
17805  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_136_CHECKER_TYPE,
17806  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
17807  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_137_CHECKER_TYPE,
17808  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
17809  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_138_CHECKER_TYPE,
17810  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
17811  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_139_CHECKER_TYPE,
17812  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
17813  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_140_CHECKER_TYPE,
17814  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
17815  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_141_CHECKER_TYPE,
17816  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
17817  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_142_CHECKER_TYPE,
17818  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
17819  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_143_CHECKER_TYPE,
17820  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
17821  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_144_CHECKER_TYPE,
17822  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
17823  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_145_CHECKER_TYPE,
17824  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
17825  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_146_CHECKER_TYPE,
17826  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
17827  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_147_CHECKER_TYPE,
17828  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
17829  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_148_CHECKER_TYPE,
17830  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
17831  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_149_CHECKER_TYPE,
17832  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
17833  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_150_CHECKER_TYPE,
17834  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
17835  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_151_CHECKER_TYPE,
17836  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
17837  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_152_CHECKER_TYPE,
17838  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
17839  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_153_CHECKER_TYPE,
17840  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
17841  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_154_CHECKER_TYPE,
17842  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
17843  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_155_CHECKER_TYPE,
17844  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
17845  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_156_CHECKER_TYPE,
17846  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
17847  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_157_CHECKER_TYPE,
17848  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
17849  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_158_CHECKER_TYPE,
17850  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
17851  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_159_CHECKER_TYPE,
17852  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
17853  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_160_CHECKER_TYPE,
17854  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
17855  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_161_CHECKER_TYPE,
17856  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
17857  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_162_CHECKER_TYPE,
17858  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
17859  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_163_CHECKER_TYPE,
17860  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
17861  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_164_CHECKER_TYPE,
17862  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
17863  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_165_CHECKER_TYPE,
17864  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
17865  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_166_CHECKER_TYPE,
17866  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
17867  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_167_CHECKER_TYPE,
17868  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
17869  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_168_CHECKER_TYPE,
17870  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
17871  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_169_CHECKER_TYPE,
17872  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
17873  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_170_CHECKER_TYPE,
17874  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
17875  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_171_CHECKER_TYPE,
17876  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
17877  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_172_CHECKER_TYPE,
17878  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
17879  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_173_CHECKER_TYPE,
17880  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
17881  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_174_CHECKER_TYPE,
17882  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
17883  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_175_CHECKER_TYPE,
17884  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
17885  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_176_CHECKER_TYPE,
17886  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
17887  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_177_CHECKER_TYPE,
17888  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
17889  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_178_CHECKER_TYPE,
17890  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
17891  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_179_CHECKER_TYPE,
17892  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
17893  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_180_CHECKER_TYPE,
17894  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
17895  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_181_CHECKER_TYPE,
17896  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
17897  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_182_CHECKER_TYPE,
17898  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
17899  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_183_CHECKER_TYPE,
17900  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
17901  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_184_CHECKER_TYPE,
17902  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
17903  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_185_CHECKER_TYPE,
17904  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
17905  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_186_CHECKER_TYPE,
17906  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
17907  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_187_CHECKER_TYPE,
17908  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
17909  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_188_CHECKER_TYPE,
17910  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
17911  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_189_CHECKER_TYPE,
17912  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
17913  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_190_CHECKER_TYPE,
17914  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
17915  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_191_CHECKER_TYPE,
17916  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
17917  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_192_CHECKER_TYPE,
17918  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
17919  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_193_CHECKER_TYPE,
17920  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
17921  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_194_CHECKER_TYPE,
17922  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
17923  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_195_CHECKER_TYPE,
17924  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
17925  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_196_CHECKER_TYPE,
17926  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
17927  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_197_CHECKER_TYPE,
17928  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
17929  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_198_CHECKER_TYPE,
17930  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
17931  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_199_CHECKER_TYPE,
17932  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
17933  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_200_CHECKER_TYPE,
17934  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
17935  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_201_CHECKER_TYPE,
17936  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
17937  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_202_CHECKER_TYPE,
17938  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
17939  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_203_CHECKER_TYPE,
17940  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
17941  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_204_CHECKER_TYPE,
17942  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
17943  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_205_CHECKER_TYPE,
17944  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
17945  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_206_CHECKER_TYPE,
17946  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
17947  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_207_CHECKER_TYPE,
17948  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
17949  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_208_CHECKER_TYPE,
17950  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
17951  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_209_CHECKER_TYPE,
17952  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
17953  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_210_CHECKER_TYPE,
17954  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
17955  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_211_CHECKER_TYPE,
17956  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
17957  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_212_CHECKER_TYPE,
17958  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
17959  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_213_CHECKER_TYPE,
17960  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
17961  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_214_CHECKER_TYPE,
17962  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
17963  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_215_CHECKER_TYPE,
17964  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
17965  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_216_CHECKER_TYPE,
17966  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
17967  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_217_CHECKER_TYPE,
17968  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
17969  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_218_CHECKER_TYPE,
17970  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
17971  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_219_CHECKER_TYPE,
17972  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
17973  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_220_CHECKER_TYPE,
17974  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
17975  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_221_CHECKER_TYPE,
17976  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
17977  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_222_CHECKER_TYPE,
17978  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
17979  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_223_CHECKER_TYPE,
17980  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
17981  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_224_CHECKER_TYPE,
17982  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
17983  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_225_CHECKER_TYPE,
17984  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
17985  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_226_CHECKER_TYPE,
17986  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
17987  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_227_CHECKER_TYPE,
17988  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
17989  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_228_CHECKER_TYPE,
17990  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
17991  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_229_CHECKER_TYPE,
17992  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
17993  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_230_CHECKER_TYPE,
17994  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
17995  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_231_CHECKER_TYPE,
17996  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
17997  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_232_CHECKER_TYPE,
17998  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
17999  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_233_CHECKER_TYPE,
18000  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
18001  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_234_CHECKER_TYPE,
18002  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
18003  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_235_CHECKER_TYPE,
18004  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
18005  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_236_CHECKER_TYPE,
18006  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
18007  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_237_CHECKER_TYPE,
18008  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
18009  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_238_CHECKER_TYPE,
18010  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
18011  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_239_CHECKER_TYPE,
18012  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
18013  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_240_CHECKER_TYPE,
18014  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
18015  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_241_CHECKER_TYPE,
18016  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
18017  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_242_CHECKER_TYPE,
18018  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
18019  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_243_CHECKER_TYPE,
18020  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
18021  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_244_CHECKER_TYPE,
18022  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
18023  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_245_CHECKER_TYPE,
18024  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
18025  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_246_CHECKER_TYPE,
18026  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
18027  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_247_CHECKER_TYPE,
18028  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
18029  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_248_CHECKER_TYPE,
18030  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
18031  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_249_CHECKER_TYPE,
18032  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
18033  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_250_CHECKER_TYPE,
18034  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
18035  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_251_CHECKER_TYPE,
18036  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
18037  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_252_CHECKER_TYPE,
18038  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
18039  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_253_CHECKER_TYPE,
18040  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
18041  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_254_CHECKER_TYPE,
18042  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
18043  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_255_CHECKER_TYPE,
18044  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
18045 };
18046 
18052 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] =
18053 {
18054  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_0_CHECKER_TYPE,
18055  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
18056  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_1_CHECKER_TYPE,
18057  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
18058  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_2_CHECKER_TYPE,
18059  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
18060  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_3_CHECKER_TYPE,
18061  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
18062  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_4_CHECKER_TYPE,
18063  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
18064  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_5_CHECKER_TYPE,
18065  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
18066  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_6_CHECKER_TYPE,
18067  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
18068  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_7_CHECKER_TYPE,
18069  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
18070  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_8_CHECKER_TYPE,
18071  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
18072  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_9_CHECKER_TYPE,
18073  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
18074  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_10_CHECKER_TYPE,
18075  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
18076  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_11_CHECKER_TYPE,
18077  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
18078  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_12_CHECKER_TYPE,
18079  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
18080  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_13_CHECKER_TYPE,
18081  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
18082  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_14_CHECKER_TYPE,
18083  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
18084  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_15_CHECKER_TYPE,
18085  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
18086  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_16_CHECKER_TYPE,
18087  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
18088  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_17_CHECKER_TYPE,
18089  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
18090  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_18_CHECKER_TYPE,
18091  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
18092  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_19_CHECKER_TYPE,
18093  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
18094  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_20_CHECKER_TYPE,
18095  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
18096  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_21_CHECKER_TYPE,
18097  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
18098  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_22_CHECKER_TYPE,
18099  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
18100  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_23_CHECKER_TYPE,
18101  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
18102  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_24_CHECKER_TYPE,
18103  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH },
18104  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_25_CHECKER_TYPE,
18105  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH },
18106  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_26_CHECKER_TYPE,
18107  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH },
18108  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_27_CHECKER_TYPE,
18109  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH },
18110  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_28_CHECKER_TYPE,
18111  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH },
18112  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_29_CHECKER_TYPE,
18113  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH },
18114  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_30_CHECKER_TYPE,
18115  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH },
18116  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_31_CHECKER_TYPE,
18117  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH },
18118  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_32_CHECKER_TYPE,
18119  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH },
18120  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_33_CHECKER_TYPE,
18121  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH },
18122  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_34_CHECKER_TYPE,
18123  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH },
18124  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_35_CHECKER_TYPE,
18125  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH },
18126  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_36_CHECKER_TYPE,
18127  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH },
18128  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_37_CHECKER_TYPE,
18129  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH },
18130  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_38_CHECKER_TYPE,
18131  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH },
18132  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_39_CHECKER_TYPE,
18133  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH },
18134  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_40_CHECKER_TYPE,
18135  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH },
18136  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_41_CHECKER_TYPE,
18137  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH },
18138  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_42_CHECKER_TYPE,
18139  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH },
18140 };
18141 
18147 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
18148 {
18149  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
18150  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
18151  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
18152  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
18153  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
18154  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
18155  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
18156  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
18157  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
18158  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
18159  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
18160  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
18161  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
18162  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
18163  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
18164  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
18165  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
18166  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
18167  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
18168  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
18169  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
18170  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
18171  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
18172  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
18173  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
18174  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
18175  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
18176  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
18177  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
18178  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
18179  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
18180  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
18181  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
18182  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
18183  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
18184  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
18185  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
18186  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
18187  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
18188  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
18189  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
18190  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
18191  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
18192  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
18193  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
18194  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
18195  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
18196  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
18197  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
18198  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
18199  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
18200  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
18201  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
18202  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
18203  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
18204  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
18205  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
18206  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
18207  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
18208  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
18209  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
18210  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
18211  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
18212  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
18213  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
18214  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
18215  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
18216  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
18217  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
18218  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
18219  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
18220  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
18221  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
18222  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
18223  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
18224  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
18225  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
18226  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
18227  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
18228  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
18229  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
18230  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
18231  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
18232  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
18233  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
18234  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
18235  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
18236  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
18237  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
18238  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
18239  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
18240  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
18241  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
18242  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
18243  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
18244  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
18245  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
18246  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
18247  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
18248  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
18249  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
18250  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
18251  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
18252  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
18253  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
18254  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
18255  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
18256  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
18257  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
18258  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
18259  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
18260  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
18261  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
18262  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
18263  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
18264  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
18265  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
18266  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
18267  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
18268  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
18269  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
18270  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
18271  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
18272  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
18273  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
18274  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
18275 };
18276 
18282 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
18283 {
18284  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
18285  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
18286  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
18287  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
18288  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
18289  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
18290  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
18291  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
18292  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
18293  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
18294  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
18295  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
18296  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
18297  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
18298  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
18299  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
18300 };
18301 
18307 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
18308 {
18309  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
18310  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
18311  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
18312  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
18313  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
18314  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
18315  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
18316  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
18317  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
18318  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
18319  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
18320  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
18321  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
18322  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
18323  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
18324  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
18325  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
18326  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
18327  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
18328  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
18329  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
18330  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
18331  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
18332  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
18333  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
18334  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
18335  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
18336  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
18337  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
18338  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
18339  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
18340  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
18341  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
18342  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
18343  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
18344  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
18345  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
18346  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
18347  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
18348  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
18349  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
18350  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
18351  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
18352  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
18353  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
18354  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
18355  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
18356  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
18357  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
18358  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
18359  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
18360  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
18361  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
18362  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
18363  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
18364  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
18365  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
18366  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
18367  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
18368  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
18369  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
18370  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
18371  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
18372  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
18373  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
18374  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
18375  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
18376  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
18377  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
18378  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
18379  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
18380  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
18381  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
18382  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
18383  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
18384  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
18385  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
18386  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
18387  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
18388  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
18389  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
18390  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
18391  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
18392  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
18393 };
18394 
18400 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
18401 {
18402  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
18403  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
18404  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
18405  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
18406  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
18407  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
18408  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
18409  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_3_WIDTH },
18410  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
18411  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_4_WIDTH },
18412  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
18413  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_5_WIDTH },
18414  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
18415  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_6_WIDTH },
18416  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
18417  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_7_WIDTH },
18418  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
18419  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_8_WIDTH },
18420  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
18421  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_9_WIDTH },
18422  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
18423  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_10_WIDTH },
18424  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
18425  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_11_WIDTH },
18426  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
18427  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_12_WIDTH },
18428  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_13_CHECKER_TYPE,
18429  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_13_WIDTH },
18430  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_14_CHECKER_TYPE,
18431  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_14_WIDTH },
18432  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_15_CHECKER_TYPE,
18433  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_15_WIDTH },
18434  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_16_CHECKER_TYPE,
18435  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_16_WIDTH },
18436  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_17_CHECKER_TYPE,
18437  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_17_WIDTH },
18438  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_18_CHECKER_TYPE,
18439  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_18_WIDTH },
18440 };
18441 
18447 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
18448 {
18449  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
18450  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
18451  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
18452  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
18453  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
18454  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
18455  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
18456  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
18457  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
18458  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
18459  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
18460  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
18461  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
18462  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
18463  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
18464  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
18465  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
18466  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
18467  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
18468  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
18469  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
18470  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
18471  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
18472  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
18473  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
18474  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
18475  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
18476  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
18477  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
18478  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
18479  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
18480  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
18481  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
18482  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
18483  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
18484  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
18485  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
18486  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
18487  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
18488  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
18489  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
18490  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
18491  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
18492  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
18493  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
18494  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
18495  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
18496  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
18497  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
18498  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
18499  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
18500  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
18501  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
18502  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
18503  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
18504  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
18505  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
18506  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
18507  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
18508  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
18509  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
18510  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
18511  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
18512  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
18513  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
18514  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
18515  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
18516  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
18517  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
18518  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
18519  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
18520  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
18521  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
18522  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
18523  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
18524  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
18525  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
18526  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
18527  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
18528  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
18529  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
18530  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
18531  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
18532  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
18533  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
18534  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
18535  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
18536  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
18537  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
18538  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
18539  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
18540  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
18541  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
18542  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
18543  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
18544  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
18545  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
18546  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
18547  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
18548  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
18549  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
18550  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
18551  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
18552  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
18553  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
18554  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
18555  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
18556  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
18557  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
18558  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
18559  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
18560  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
18561  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
18562  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
18563  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
18564  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
18565  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
18566  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
18567  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
18568  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
18569  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
18570  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
18571  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
18572  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
18573  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
18574  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
18575  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
18576  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
18577  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
18578  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
18579  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
18580  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
18581 };
18582 
18588 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
18589 {
18590  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
18591  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_0_WIDTH },
18592  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
18593  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_1_WIDTH },
18594  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
18595  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_2_WIDTH },
18596  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
18597  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_3_WIDTH },
18598  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
18599  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_4_WIDTH },
18600  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
18601  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_5_WIDTH },
18602  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
18603  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_6_WIDTH },
18604  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
18605  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_7_WIDTH },
18606  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
18607  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_8_WIDTH },
18608  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
18609  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_9_WIDTH },
18610  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
18611  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_10_WIDTH },
18612  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
18613  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_11_WIDTH },
18614  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
18615  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_12_WIDTH },
18616 };
18617 
18623 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
18624 {
18625  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
18626  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
18627  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
18628  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
18629  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
18630  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
18631  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
18632  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
18633  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
18634  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
18635  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
18636  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
18637 };
18638 
18644 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
18645 {
18646  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
18647  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
18648  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
18649  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
18650  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
18651  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
18652  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
18653  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
18654  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
18655  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
18656  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
18657  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
18658  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
18659  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
18660  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
18661  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
18662  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
18663  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
18664  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
18665  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
18666  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
18667  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
18668  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
18669  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
18670  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
18671  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
18672  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
18673  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
18674  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
18675  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
18676  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
18677  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
18678  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
18679  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
18680  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
18681  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
18682  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
18683  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
18684  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
18685  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
18686  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
18687  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
18688  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
18689  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
18690  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
18691  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
18692  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
18693  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
18694  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
18695  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
18696  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
18697  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
18698  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
18699  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
18700  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
18701  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
18702  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
18703  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
18704  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
18705  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
18706  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
18707  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
18708  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
18709  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
18710  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
18711  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
18712  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
18713  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
18714  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
18715  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
18716  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
18717  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
18718 };
18719 
18725 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
18726 {
18727  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
18728  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
18729  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
18730  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
18731  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
18732  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
18733  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
18734  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
18735  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
18736  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
18737  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
18738  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
18739  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
18740  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
18741  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
18742  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
18743  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
18744  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
18745  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
18746  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
18747  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
18748  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
18749  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
18750  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
18751  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
18752  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
18753  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
18754  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
18755  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
18756  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
18757  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
18758  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
18759  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
18760  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
18761  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
18762  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
18763  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
18764  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
18765  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
18766  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
18767  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
18768  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
18769  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
18770  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
18771  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
18772  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
18773  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
18774  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
18775  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
18776  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
18777  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
18778  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
18779  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
18780  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
18781  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
18782  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
18783  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
18784  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
18785  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
18786  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
18787  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
18788  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
18789  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
18790  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
18791  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
18792  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
18793  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
18794  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
18795  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
18796  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
18797  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
18798  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
18799  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
18800  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
18801 };
18802 
18808 static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_MAX_NUM_CHECKERS] =
18809 {
18810  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_0_CHECKER_TYPE,
18811  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_0_WIDTH },
18812  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_1_CHECKER_TYPE,
18813  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_1_WIDTH },
18814  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_2_CHECKER_TYPE,
18815  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_2_WIDTH },
18816  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_3_CHECKER_TYPE,
18817  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_3_WIDTH },
18818  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_4_CHECKER_TYPE,
18819  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_4_WIDTH },
18820  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_5_CHECKER_TYPE,
18821  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_5_WIDTH },
18822 };
18823 
18828 static const SDL_MemConfig_t SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_MemEntries[SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
18829 {
18830  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_RESPONSE_BUFFER0_RAM_ID, 0u,
18831  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_RESPONSE_BUFFER0_RAM_SIZE, 32u,
18832  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_RESPONSE_BUFFER0_ROW_WIDTH, ((bool)false) },
18833  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_QUEUE_BUFFER0_RAM_ID, 0u,
18834  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_QUEUE_BUFFER0_RAM_SIZE, 32u,
18835  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_QUEUE_BUFFER0_ROW_WIDTH, ((bool)false) },
18836  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_QUEUE_BUFFER1_RAM_ID, 0u,
18837  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_QUEUE_BUFFER1_RAM_SIZE, 32u,
18838  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_QUEUE_BUFFER1_ROW_WIDTH, ((bool)false) },
18839  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_QUEUE_BUFFER2_RAM_ID, 0u,
18840  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_QUEUE_BUFFER2_RAM_SIZE, 4u,
18841  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_QUEUE_BUFFER2_ROW_WIDTH, ((bool)false) },
18842  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_STATE_BUFFER0_RAM_ID, 0u,
18843  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_STATE_BUFFER0_RAM_SIZE, 32u,
18844  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_STATE_BUFFER0_ROW_WIDTH, ((bool)false) },
18845  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_RING_MEMORY_RAM_ID, 0u,
18846  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_RING_MEMORY_RAM_SIZE, 32u,
18847  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_RING_MEMORY_ROW_WIDTH, ((bool)false) },
18848 };
18849 
18854 static const SDL_MemConfig_t SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_MemEntries[SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
18855 {
18856  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALY_LUT_B0_MEMECC_RAM_ID, 0u,
18857  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALY_LUT_B0_MEMECC_RAM_SIZE, 4u,
18858  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALY_LUT_B0_MEMECC_ROW_WIDTH, ((bool)false) },
18859  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALY_LUT_B1_MEMECC_RAM_ID, 0u,
18860  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALY_LUT_B1_MEMECC_RAM_SIZE, 4u,
18861  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALY_LUT_B1_MEMECC_ROW_WIDTH, ((bool)false) },
18862  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALC_LUT_B0_MEMECC_RAM_ID, 0u,
18863  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALC_LUT_B0_MEMECC_RAM_SIZE, 4u,
18864  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALC_LUT_B0_MEMECC_ROW_WIDTH, ((bool)false) },
18865  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALC_LUT_B1_MEMECC_RAM_ID, 0u,
18866  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALC_LUT_B1_MEMECC_RAM_SIZE, 4u,
18867  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALC_LUT_B1_MEMECC_ROW_WIDTH, ((bool)false) },
18868  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B0_P0_MEMECC_RAM_ID, 0u,
18869  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B0_P0_MEMECC_RAM_SIZE, 4u,
18870  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B0_P0_MEMECC_ROW_WIDTH, ((bool)false) },
18871  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B1_P0_MEMECC_RAM_ID, 0u,
18872  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B1_P0_MEMECC_RAM_SIZE, 4u,
18873  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B1_P0_MEMECC_ROW_WIDTH, ((bool)false) },
18874  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B2_P0_MEMECC_RAM_ID, 0u,
18875  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B2_P0_MEMECC_RAM_SIZE, 4u,
18876  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B2_P0_MEMECC_ROW_WIDTH, ((bool)false) },
18877  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B3_P0_MEMECC_RAM_ID, 0u,
18878  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B3_P0_MEMECC_RAM_SIZE, 4u,
18879  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B3_P0_MEMECC_ROW_WIDTH, ((bool)false) },
18880  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B0_P1_MEMECC_RAM_ID, 0u,
18881  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B0_P1_MEMECC_RAM_SIZE, 4u,
18882  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B0_P1_MEMECC_ROW_WIDTH, ((bool)false) },
18883  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B1_P1_MEMECC_RAM_ID, 0u,
18884  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B1_P1_MEMECC_RAM_SIZE, 4u,
18885  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B1_P1_MEMECC_ROW_WIDTH, ((bool)false) },
18886  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B2_P1_MEMECC_RAM_ID, 0u,
18887  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B2_P1_MEMECC_RAM_SIZE, 4u,
18888  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B2_P1_MEMECC_ROW_WIDTH, ((bool)false) },
18889  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B3_P1_MEMECC_RAM_ID, 0u,
18890  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B3_P1_MEMECC_RAM_SIZE, 4u,
18891  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B3_P1_MEMECC_ROW_WIDTH, ((bool)false) },
18892 };
18893 
18898 static const SDL_MemConfig_t SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_MemEntries[SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
18899 {
18900  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT1_RAM_INTF_RAM0_RAM_ID, 0u,
18901  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT1_RAM_INTF_RAM0_RAM_SIZE, 4u,
18902  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT1_RAM_INTF_RAM0_ROW_WIDTH, ((bool)false) },
18903  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT1_RAM_INTF_RAM1_RAM_ID, 0u,
18904  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT1_RAM_INTF_RAM1_RAM_SIZE, 4u,
18905  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT1_RAM_INTF_RAM1_ROW_WIDTH, ((bool)false) },
18906  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT2_RAM_INTF_RAM0_RAM_ID, 0u,
18907  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT2_RAM_INTF_RAM0_RAM_SIZE, 4u,
18908  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT2_RAM_INTF_RAM0_ROW_WIDTH, ((bool)false) },
18909  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT2_RAM_INTF_RAM1_RAM_ID, 0u,
18910  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT2_RAM_INTF_RAM1_RAM_SIZE, 4u,
18911  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT2_RAM_INTF_RAM1_ROW_WIDTH, ((bool)false) },
18912  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT3_RAM_INTF_RAM0_RAM_ID, 0u,
18913  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT3_RAM_INTF_RAM0_RAM_SIZE, 4u,
18914  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT3_RAM_INTF_RAM0_ROW_WIDTH, ((bool)false) },
18915  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT3_RAM_INTF_RAM1_RAM_ID, 0u,
18916  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT3_RAM_INTF_RAM1_RAM_SIZE, 4u,
18917  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT3_RAM_INTF_RAM1_ROW_WIDTH, ((bool)false) },
18918  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_WDR_LUT_RAM_INTF_RAM0_RAM_ID, 0u,
18919  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_WDR_LUT_RAM_INTF_RAM0_RAM_SIZE, 4u,
18920  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_WDR_LUT_RAM_INTF_RAM0_ROW_WIDTH, ((bool)false) },
18921  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_WDR_LUT_RAM_INTF_RAM1_RAM_ID, 0u,
18922  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_WDR_LUT_RAM_INTF_RAM1_RAM_SIZE, 4u,
18923  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_WDR_LUT_RAM_INTF_RAM1_ROW_WIDTH, ((bool)false) },
18924  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_DPC_DPC_LUT_RAM_INTF_RAM0_RAM_ID, 0u,
18925  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_DPC_DPC_LUT_RAM_INTF_RAM0_RAM_SIZE, 4u,
18926  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_DPC_DPC_LUT_RAM_INTF_RAM0_ROW_WIDTH, ((bool)false) },
18927  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LSC_RAM_INTF_RAM0_RAM_ID, 0u,
18928  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LSC_RAM_INTF_RAM0_RAM_SIZE, 4u,
18929  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LSC_RAM_INTF_RAM0_ROW_WIDTH, ((bool)false) },
18930  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_H3A_LUT_RAM_INTF_RAM0_RAM_ID, 0u,
18931  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_H3A_LUT_RAM_INTF_RAM0_RAM_SIZE, 4u,
18932  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_H3A_LUT_RAM_INTF_RAM0_ROW_WIDTH, ((bool)false) },
18933  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_H3A_LUT_RAM_INTF_RAM1_RAM_ID, 0u,
18934  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_H3A_LUT_RAM_INTF_RAM1_RAM_SIZE, 4u,
18935  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_H3A_LUT_RAM_INTF_RAM1_ROW_WIDTH, ((bool)false) },
18936  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_DPC_STATS_RAM0_RAM_ID, 0u,
18937  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_DPC_STATS_RAM0_RAM_SIZE, 4u,
18938  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_DPC_STATS_RAM0_ROW_WIDTH, ((bool)false) },
18939  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM0_RAMECC_RAM_ID, 0u,
18940  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM0_RAMECC_RAM_SIZE, 4u,
18941  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM0_RAMECC_ROW_WIDTH, ((bool)false) },
18942  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM1_RAMECC_RAM_ID, 0u,
18943  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM1_RAMECC_RAM_SIZE, 4u,
18944  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM1_RAMECC_ROW_WIDTH, ((bool)false) },
18945  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM2_RAMECC_RAM_ID, 0u,
18946  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM2_RAMECC_RAM_SIZE, 4u,
18947  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM2_RAMECC_ROW_WIDTH, ((bool)false) },
18948  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM3_RAMECC_RAM_ID, 0u,
18949  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM3_RAMECC_RAM_SIZE, 4u,
18950  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM3_RAMECC_ROW_WIDTH, ((bool)false) },
18951  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM4_RAMECC_RAM_ID, 0u,
18952  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM4_RAMECC_RAM_SIZE, 4u,
18953  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM4_RAMECC_ROW_WIDTH, ((bool)false) },
18954  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM5_RAMECC_RAM_ID, 0u,
18955  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM5_RAMECC_RAM_SIZE, 4u,
18956  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM5_RAMECC_ROW_WIDTH, ((bool)false) },
18957  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM6_RAMECC_RAM_ID, 0u,
18958  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM6_RAMECC_RAM_SIZE, 4u,
18959  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM6_RAMECC_ROW_WIDTH, ((bool)false) },
18960  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM7_RAMECC_RAM_ID, 0u,
18961  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM7_RAMECC_RAM_SIZE, 4u,
18962  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM7_RAMECC_ROW_WIDTH, ((bool)false) },
18963  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_HIST_BANK0_MEMECC_RAM_ID, 0u,
18964  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_HIST_BANK0_MEMECC_RAM_SIZE, 4u,
18965  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_HIST_BANK0_MEMECC_ROW_WIDTH, ((bool)false) },
18966  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_HIST_BANK1_MEMECC_RAM_ID, 0u,
18967  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_HIST_BANK1_MEMECC_RAM_SIZE, 4u,
18968  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_HIST_BANK1_MEMECC_ROW_WIDTH, ((bool)false) },
18969  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX0_BANK0_MEMECC_RAM_ID, 0u,
18970  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX0_BANK0_MEMECC_RAM_SIZE, 4u,
18971  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX0_BANK0_MEMECC_ROW_WIDTH, ((bool)false) },
18972  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX0_BANK1_MEMECC_RAM_ID, 0u,
18973  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX0_BANK1_MEMECC_RAM_SIZE, 4u,
18974  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX0_BANK1_MEMECC_ROW_WIDTH, ((bool)false) },
18975  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX1_BANK0_MEMECC_RAM_ID, 0u,
18976  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX1_BANK0_MEMECC_RAM_SIZE, 4u,
18977  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX1_BANK0_MEMECC_ROW_WIDTH, ((bool)false) },
18978  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX1_BANK1_MEMECC_RAM_ID, 0u,
18979  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX1_BANK1_MEMECC_RAM_SIZE, 4u,
18980  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX1_BANK1_MEMECC_ROW_WIDTH, ((bool)false) },
18981  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX2_BANK0_MEMECC_RAM_ID, 0u,
18982  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX2_BANK0_MEMECC_RAM_SIZE, 4u,
18983  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX2_BANK0_MEMECC_ROW_WIDTH, ((bool)false) },
18984  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX2_BANK1_MEMECC_RAM_ID, 0u,
18985  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX2_BANK1_MEMECC_RAM_SIZE, 4u,
18986  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX2_BANK1_MEMECC_ROW_WIDTH, ((bool)false) },
18987  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_Y8R8_BANK0_MEMECC_RAM_ID, 0u,
18988  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_Y8R8_BANK0_MEMECC_RAM_SIZE, 4u,
18989  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_Y8R8_BANK0_MEMECC_ROW_WIDTH, ((bool)false) },
18990  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_Y8R8_BANK1_MEMECC_RAM_ID, 0u,
18991  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_Y8R8_BANK1_MEMECC_RAM_SIZE, 4u,
18992  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_Y8R8_BANK1_MEMECC_ROW_WIDTH, ((bool)false) },
18993  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_UV8G8_BANK0_MEMECC_RAM_ID, 0u,
18994  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_UV8G8_BANK0_MEMECC_RAM_SIZE, 4u,
18995  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_UV8G8_BANK0_MEMECC_ROW_WIDTH, ((bool)false) },
18996  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_UV8G8_BANK1_MEMECC_RAM_ID, 0u,
18997  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_UV8G8_BANK1_MEMECC_RAM_SIZE, 4u,
18998  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_UV8G8_BANK1_MEMECC_ROW_WIDTH, ((bool)false) },
18999  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_S8B8_BANK0_MEMECC_RAM_ID, 0u,
19000  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_S8B8_BANK0_MEMECC_RAM_SIZE, 4u,
19001  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_S8B8_BANK0_MEMECC_ROW_WIDTH, ((bool)false) },
19002  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_S8B8_BANK1_MEMECC_RAM_ID, 0u,
19003  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_S8B8_BANK1_MEMECC_RAM_SIZE, 4u,
19004  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_S8B8_BANK1_MEMECC_ROW_WIDTH, ((bool)false) },
19005  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_LUT_0_RAMECC_RAM_ID, 0u,
19006  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_LUT_0_RAMECC_RAM_SIZE, 4u,
19007  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_LUT_0_RAMECC_ROW_WIDTH, ((bool)false) },
19008  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_LUT_1_RAMECC_RAM_ID, 0u,
19009  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_LUT_1_RAMECC_RAM_SIZE, 4u,
19010  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_LUT_1_RAMECC_ROW_WIDTH, ((bool)false) },
19011  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_EELUT_0_RAMECC_RAM_ID, 0u,
19012  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_EELUT_0_RAMECC_RAM_SIZE, 4u,
19013  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_EELUT_0_RAMECC_ROW_WIDTH, ((bool)false) },
19014  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_EELUT_1_RAMECC_RAM_ID, 0u,
19015  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_EELUT_1_RAMECC_RAM_SIZE, 4u,
19016  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_EELUT_1_RAMECC_ROW_WIDTH, ((bool)false) },
19017  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_NSF4V_RAWHIST_MEMWRAP_HIST_LUT_B0_MEMECC_RAM_ID, 0u,
19018  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_NSF4V_RAWHIST_MEMWRAP_HIST_LUT_B0_MEMECC_RAM_SIZE, 4u,
19019  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_NSF4V_RAWHIST_MEMWRAP_HIST_LUT_B0_MEMECC_ROW_WIDTH, ((bool)false) },
19020  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_NSF4V_RAWHIST_MEMWRAP_HIST_LUT_B1_MEMECC_RAM_ID, 0u,
19021  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_NSF4V_RAWHIST_MEMWRAP_HIST_LUT_B1_MEMECC_RAM_SIZE, 4u,
19022  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_NSF4V_RAWHIST_MEMWRAP_HIST_LUT_B1_MEMECC_ROW_WIDTH, ((bool)false) },
19023  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_NSF4V_RAWHIST_MEMWRAP_HIST_DATA_B0_MEMECC_RAM_ID, 0u,
19024  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_NSF4V_RAWHIST_MEMWRAP_HIST_DATA_B0_MEMECC_RAM_SIZE, 4u,
19025  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_NSF4V_RAWHIST_MEMWRAP_HIST_DATA_B0_MEMECC_ROW_WIDTH, ((bool)false) },
19026  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_NSF4V_RAWHIST_MEMWRAP_HIST_DATA_B1_MEMECC_RAM_ID, 0u,
19027  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_NSF4V_RAWHIST_MEMWRAP_HIST_DATA_B1_MEMECC_RAM_SIZE, 4u,
19028  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_NSF4V_RAWHIST_MEMWRAP_HIST_DATA_B1_MEMECC_ROW_WIDTH, ((bool)false) },
19029  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT0_0_RAMECC_RAM_ID, 0u,
19030  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT0_0_RAMECC_RAM_SIZE, 4u,
19031  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT0_0_RAMECC_ROW_WIDTH, ((bool)false) },
19032  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT0_1_RAMECC_RAM_ID, 0u,
19033  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT0_1_RAMECC_RAM_SIZE, 4u,
19034  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT0_1_RAMECC_ROW_WIDTH, ((bool)false) },
19035  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT1_0_RAMECC_RAM_ID, 0u,
19036  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT1_0_RAMECC_RAM_SIZE, 4u,
19037  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT1_0_RAMECC_ROW_WIDTH, ((bool)false) },
19038  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT1_1_RAMECC_RAM_ID, 0u,
19039  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT1_1_RAMECC_RAM_SIZE, 4u,
19040  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT1_1_RAMECC_ROW_WIDTH, ((bool)false) },
19041  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT2_0_RAMECC_RAM_ID, 0u,
19042  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT2_0_RAMECC_RAM_SIZE, 4u,
19043  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT2_0_RAMECC_ROW_WIDTH, ((bool)false) },
19044  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT2_1_RAMECC_RAM_ID, 0u,
19045  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT2_1_RAMECC_RAM_SIZE, 4u,
19046  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT2_1_RAMECC_ROW_WIDTH, ((bool)false) },
19047  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT3_0_RAMECC_RAM_ID, 0u,
19048  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT3_0_RAMECC_RAM_SIZE, 4u,
19049  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT3_0_RAMECC_ROW_WIDTH, ((bool)false) },
19050  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT3_1_RAMECC_RAM_ID, 0u,
19051  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT3_1_RAMECC_RAM_SIZE, 4u,
19052  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT3_1_RAMECC_ROW_WIDTH, ((bool)false) },
19053  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT0_0_RAMECC_RAM_ID, 0u,
19054  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT0_0_RAMECC_RAM_SIZE, 4u,
19055  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT0_0_RAMECC_ROW_WIDTH, ((bool)false) },
19056  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT0_1_RAMECC_RAM_ID, 0u,
19057  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT0_1_RAMECC_RAM_SIZE, 4u,
19058  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT0_1_RAMECC_ROW_WIDTH, ((bool)false) },
19059  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT1_0_RAMECC_RAM_ID, 0u,
19060  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT1_0_RAMECC_RAM_SIZE, 4u,
19061  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT1_0_RAMECC_ROW_WIDTH, ((bool)false) },
19062  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT1_1_RAMECC_RAM_ID, 0u,
19063  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT1_1_RAMECC_RAM_SIZE, 4u,
19064  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT1_1_RAMECC_ROW_WIDTH, ((bool)false) },
19065  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT2_0_RAMECC_RAM_ID, 0u,
19066  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT2_0_RAMECC_RAM_SIZE, 4u,
19067  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT2_0_RAMECC_ROW_WIDTH, ((bool)false) },
19068  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT2_1_RAMECC_RAM_ID, 0u,
19069  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT2_1_RAMECC_RAM_SIZE, 4u,
19070  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT2_1_RAMECC_ROW_WIDTH, ((bool)false) },
19071  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT3_0_RAMECC_RAM_ID, 0u,
19072  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT3_0_RAMECC_RAM_SIZE, 4u,
19073  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT3_0_RAMECC_ROW_WIDTH, ((bool)false) },
19074  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT3_1_RAMECC_RAM_ID, 0u,
19075  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT3_1_RAMECC_RAM_SIZE, 4u,
19076  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT3_1_RAMECC_ROW_WIDTH, ((bool)false) },
19077  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_CAC_MEMWRAP_MESHLUT_MEMECC_RAM_ID, 0u,
19078  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_CAC_MEMWRAP_MESHLUT_MEMECC_RAM_SIZE, 4u,
19079  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_CAC_MEMWRAP_MESHLUT_MEMECC_ROW_WIDTH, ((bool)false) },
19080  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_PCID_MEMWRAP_REMAPLUT_MEMECC_B0_RAM_ID, 0u,
19081  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_PCID_MEMWRAP_REMAPLUT_MEMECC_B0_RAM_SIZE, 4u,
19082  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_PCID_MEMWRAP_REMAPLUT_MEMECC_B0_ROW_WIDTH, ((bool)false) },
19083  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_PCID_MEMWRAP_REMAPLUT_MEMECC_B1_RAM_ID, 0u,
19084  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_PCID_MEMWRAP_REMAPLUT_MEMECC_B1_RAM_SIZE, 4u,
19085  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_PCID_MEMWRAP_REMAPLUT_MEMECC_B1_ROW_WIDTH, ((bool)false) },
19086 };
19087 
19093 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_MAX_NUM_CHECKERS] =
19094 {
19095  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
19096  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_0_WIDTH },
19097  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
19098  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_1_WIDTH },
19099  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
19100  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_2_WIDTH },
19101  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
19102  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_3_WIDTH },
19103  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
19104  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_4_WIDTH },
19105  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
19106  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_5_WIDTH },
19107  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
19108  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_6_WIDTH },
19109  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
19110  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_7_WIDTH },
19111  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
19112  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_8_WIDTH },
19113  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
19114  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_9_WIDTH },
19115  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
19116  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_10_WIDTH },
19117  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
19118  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_11_WIDTH },
19119  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
19120  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_12_WIDTH },
19121  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
19122  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_13_WIDTH },
19123  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
19124  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_14_WIDTH },
19125  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_15_CHECKER_TYPE,
19126  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_15_WIDTH },
19127  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_16_CHECKER_TYPE,
19128  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_16_WIDTH },
19129  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_17_CHECKER_TYPE,
19130  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_17_WIDTH },
19131  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_18_CHECKER_TYPE,
19132  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_18_WIDTH },
19133  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_19_CHECKER_TYPE,
19134  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_19_WIDTH },
19135  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_20_CHECKER_TYPE,
19136  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_20_WIDTH },
19137  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_21_CHECKER_TYPE,
19138  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_21_WIDTH },
19139  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_22_CHECKER_TYPE,
19140  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_22_WIDTH },
19141  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_23_CHECKER_TYPE,
19142  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_23_WIDTH },
19143  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_24_CHECKER_TYPE,
19144  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_24_WIDTH },
19145  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_25_CHECKER_TYPE,
19146  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_25_WIDTH },
19147  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_26_CHECKER_TYPE,
19148  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_26_WIDTH },
19149  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_27_CHECKER_TYPE,
19150  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_27_WIDTH },
19151  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_28_CHECKER_TYPE,
19152  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_28_WIDTH },
19153  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_29_CHECKER_TYPE,
19154  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_29_WIDTH },
19155  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_30_CHECKER_TYPE,
19156  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_30_WIDTH },
19157  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_31_CHECKER_TYPE,
19158  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_31_WIDTH },
19159  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_32_CHECKER_TYPE,
19160  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_32_WIDTH },
19161  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_33_CHECKER_TYPE,
19162  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_33_WIDTH },
19163  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_34_CHECKER_TYPE,
19164  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_34_WIDTH },
19165  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_35_CHECKER_TYPE,
19166  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_35_WIDTH },
19167  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_36_CHECKER_TYPE,
19168  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_36_WIDTH },
19169  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_37_CHECKER_TYPE,
19170  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_37_WIDTH },
19171  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_38_CHECKER_TYPE,
19172  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_38_WIDTH },
19173  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_39_CHECKER_TYPE,
19174  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_39_WIDTH },
19175  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_40_CHECKER_TYPE,
19176  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_40_WIDTH },
19177  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_41_CHECKER_TYPE,
19178  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_41_WIDTH },
19179  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_42_CHECKER_TYPE,
19180  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_42_WIDTH },
19181  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_43_CHECKER_TYPE,
19182  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_43_WIDTH },
19183  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_44_CHECKER_TYPE,
19184  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_44_WIDTH },
19185  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_45_CHECKER_TYPE,
19186  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_45_WIDTH },
19187  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_46_CHECKER_TYPE,
19188  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_46_WIDTH },
19189  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_47_CHECKER_TYPE,
19190  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_47_WIDTH },
19191  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_48_CHECKER_TYPE,
19192  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_48_WIDTH },
19193  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_49_CHECKER_TYPE,
19194  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_49_WIDTH },
19195  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_50_CHECKER_TYPE,
19196  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_50_WIDTH },
19197  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_51_CHECKER_TYPE,
19198  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_51_WIDTH },
19199  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_52_CHECKER_TYPE,
19200  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_52_WIDTH },
19201  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_53_CHECKER_TYPE,
19202  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_53_WIDTH },
19203  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_54_CHECKER_TYPE,
19204  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_54_WIDTH },
19205  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_55_CHECKER_TYPE,
19206  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_55_WIDTH },
19207  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_56_CHECKER_TYPE,
19208  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_56_WIDTH },
19209  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_57_CHECKER_TYPE,
19210  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_57_WIDTH },
19211  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_58_CHECKER_TYPE,
19212  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_58_WIDTH },
19213  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_59_CHECKER_TYPE,
19214  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_59_WIDTH },
19215  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_60_CHECKER_TYPE,
19216  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_60_WIDTH },
19217  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_61_CHECKER_TYPE,
19218  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_61_WIDTH },
19219  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_62_CHECKER_TYPE,
19220  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_62_WIDTH },
19221  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_63_CHECKER_TYPE,
19222  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_63_WIDTH },
19223  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_64_CHECKER_TYPE,
19224  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_64_WIDTH },
19225  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_65_CHECKER_TYPE,
19226  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_65_WIDTH },
19227  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_66_CHECKER_TYPE,
19228  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_66_WIDTH },
19229  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_67_CHECKER_TYPE,
19230  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_67_WIDTH },
19231  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_68_CHECKER_TYPE,
19232  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_GROUP_68_WIDTH },
19233 };
19234 
19240 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_MAX_NUM_CHECKERS] =
19241 {
19242  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_0_CHECKER_TYPE,
19243  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_0_WIDTH },
19244  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_1_CHECKER_TYPE,
19245  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_1_WIDTH },
19246  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_2_CHECKER_TYPE,
19247  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_2_WIDTH },
19248  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_3_CHECKER_TYPE,
19249  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_3_WIDTH },
19250  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_4_CHECKER_TYPE,
19251  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_4_WIDTH },
19252  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_5_CHECKER_TYPE,
19253  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_5_WIDTH },
19254  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_6_CHECKER_TYPE,
19255  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_6_WIDTH },
19256  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_7_CHECKER_TYPE,
19257  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_7_WIDTH },
19258  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_8_CHECKER_TYPE,
19259  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_8_WIDTH },
19260  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_9_CHECKER_TYPE,
19261  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_9_WIDTH },
19262  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_10_CHECKER_TYPE,
19263  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_10_WIDTH },
19264  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_11_CHECKER_TYPE,
19265  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_11_WIDTH },
19266  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_12_CHECKER_TYPE,
19267  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_12_WIDTH },
19268  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_13_CHECKER_TYPE,
19269  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_13_WIDTH },
19270  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_14_CHECKER_TYPE,
19271  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_14_WIDTH },
19272  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_15_CHECKER_TYPE,
19273  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_15_WIDTH },
19274  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_16_CHECKER_TYPE,
19275  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_16_WIDTH },
19276  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_17_CHECKER_TYPE,
19277  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_17_WIDTH },
19278  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_18_CHECKER_TYPE,
19279  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_18_WIDTH },
19280  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_19_CHECKER_TYPE,
19281  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_19_WIDTH },
19282  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_20_CHECKER_TYPE,
19283  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_20_WIDTH },
19284  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_21_CHECKER_TYPE,
19285  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_21_WIDTH },
19286  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_22_CHECKER_TYPE,
19287  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_22_WIDTH },
19288  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_23_CHECKER_TYPE,
19289  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_23_WIDTH },
19290  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_24_CHECKER_TYPE,
19291  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_24_WIDTH },
19292  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_25_CHECKER_TYPE,
19293  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_25_WIDTH },
19294  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_26_CHECKER_TYPE,
19295  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_26_WIDTH },
19296  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_27_CHECKER_TYPE,
19297  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_27_WIDTH },
19298  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_28_CHECKER_TYPE,
19299  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_28_WIDTH },
19300  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_29_CHECKER_TYPE,
19301  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_29_WIDTH },
19302  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_30_CHECKER_TYPE,
19303  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_30_WIDTH },
19304  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_31_CHECKER_TYPE,
19305  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_31_WIDTH },
19306  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_32_CHECKER_TYPE,
19307  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_32_WIDTH },
19308  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_33_CHECKER_TYPE,
19309  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_33_WIDTH },
19310  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_34_CHECKER_TYPE,
19311  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_34_WIDTH },
19312  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_35_CHECKER_TYPE,
19313  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_35_WIDTH },
19314  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_36_CHECKER_TYPE,
19315  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_36_WIDTH },
19316  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_37_CHECKER_TYPE,
19317  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_37_WIDTH },
19318  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_38_CHECKER_TYPE,
19319  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_38_WIDTH },
19320  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_39_CHECKER_TYPE,
19321  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_39_WIDTH },
19322  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_40_CHECKER_TYPE,
19323  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_40_WIDTH },
19324  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_41_CHECKER_TYPE,
19325  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_41_WIDTH },
19326  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_42_CHECKER_TYPE,
19327  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_42_WIDTH },
19328  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_43_CHECKER_TYPE,
19329  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_43_WIDTH },
19330  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_44_CHECKER_TYPE,
19331  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_44_WIDTH },
19332  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_45_CHECKER_TYPE,
19333  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_45_WIDTH },
19334  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_46_CHECKER_TYPE,
19335  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_46_WIDTH },
19336  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_47_CHECKER_TYPE,
19337  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_47_WIDTH },
19338  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_48_CHECKER_TYPE,
19339  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_48_WIDTH },
19340  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_49_CHECKER_TYPE,
19341  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_49_WIDTH },
19342  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_50_CHECKER_TYPE,
19343  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_50_WIDTH },
19344  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_51_CHECKER_TYPE,
19345  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_51_WIDTH },
19346  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_52_CHECKER_TYPE,
19347  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_52_WIDTH },
19348  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_53_CHECKER_TYPE,
19349  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_53_WIDTH },
19350  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_54_CHECKER_TYPE,
19351  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_54_WIDTH },
19352  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_55_CHECKER_TYPE,
19353  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_55_WIDTH },
19354  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_56_CHECKER_TYPE,
19355  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_56_WIDTH },
19356  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_57_CHECKER_TYPE,
19357  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_57_WIDTH },
19358  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_58_CHECKER_TYPE,
19359  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_58_WIDTH },
19360  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_59_CHECKER_TYPE,
19361  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_59_WIDTH },
19362  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_60_CHECKER_TYPE,
19363  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_60_WIDTH },
19364  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_61_CHECKER_TYPE,
19365  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_61_WIDTH },
19366  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_62_CHECKER_TYPE,
19367  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_62_WIDTH },
19368  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_63_CHECKER_TYPE,
19369  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_63_WIDTH },
19370  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_64_CHECKER_TYPE,
19371  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_GROUP_64_WIDTH },
19372 };
19373 
19379 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_MAX_NUM_CHECKERS] =
19380 {
19381  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
19382  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_0_WIDTH },
19383  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
19384  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_1_WIDTH },
19385  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
19386  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_2_WIDTH },
19387  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
19388  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_3_WIDTH },
19389  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
19390  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_4_WIDTH },
19391  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
19392  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_5_WIDTH },
19393  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
19394  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_6_WIDTH },
19395  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
19396  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_7_WIDTH },
19397  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
19398  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_8_WIDTH },
19399  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
19400  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_9_WIDTH },
19401  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
19402  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_10_WIDTH },
19403  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
19404  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_11_WIDTH },
19405  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
19406  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_12_WIDTH },
19407  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
19408  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_13_WIDTH },
19409  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
19410  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_14_WIDTH },
19411  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_15_CHECKER_TYPE,
19412  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_15_WIDTH },
19413  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_16_CHECKER_TYPE,
19414  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_16_WIDTH },
19415  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_17_CHECKER_TYPE,
19416  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_17_WIDTH },
19417  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_18_CHECKER_TYPE,
19418  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_18_WIDTH },
19419  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_19_CHECKER_TYPE,
19420  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_19_WIDTH },
19421  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_20_CHECKER_TYPE,
19422  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_20_WIDTH },
19423  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_21_CHECKER_TYPE,
19424  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_21_WIDTH },
19425  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_22_CHECKER_TYPE,
19426  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_22_WIDTH },
19427  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_23_CHECKER_TYPE,
19428  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_23_WIDTH },
19429  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_24_CHECKER_TYPE,
19430  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_24_WIDTH },
19431  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_25_CHECKER_TYPE,
19432  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_25_WIDTH },
19433  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_26_CHECKER_TYPE,
19434  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_26_WIDTH },
19435  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_27_CHECKER_TYPE,
19436  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_27_WIDTH },
19437  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_28_CHECKER_TYPE,
19438  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_28_WIDTH },
19439  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_29_CHECKER_TYPE,
19440  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_29_WIDTH },
19441  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_30_CHECKER_TYPE,
19442  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_30_WIDTH },
19443  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_31_CHECKER_TYPE,
19444  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_31_WIDTH },
19445  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_32_CHECKER_TYPE,
19446  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_32_WIDTH },
19447  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_33_CHECKER_TYPE,
19448  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_33_WIDTH },
19449  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_34_CHECKER_TYPE,
19450  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_34_WIDTH },
19451  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_35_CHECKER_TYPE,
19452  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_35_WIDTH },
19453  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_36_CHECKER_TYPE,
19454  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_36_WIDTH },
19455  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_37_CHECKER_TYPE,
19456  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_37_WIDTH },
19457  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_38_CHECKER_TYPE,
19458  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_38_WIDTH },
19459  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_39_CHECKER_TYPE,
19460  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_39_WIDTH },
19461  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_40_CHECKER_TYPE,
19462  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_40_WIDTH },
19463  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_41_CHECKER_TYPE,
19464  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_41_WIDTH },
19465  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_42_CHECKER_TYPE,
19466  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_42_WIDTH },
19467  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_43_CHECKER_TYPE,
19468  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_43_WIDTH },
19469  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_44_CHECKER_TYPE,
19470  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_44_WIDTH },
19471  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_45_CHECKER_TYPE,
19472  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_45_WIDTH },
19473  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_46_CHECKER_TYPE,
19474  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_46_WIDTH },
19475  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_47_CHECKER_TYPE,
19476  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_47_WIDTH },
19477  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_48_CHECKER_TYPE,
19478  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_48_WIDTH },
19479  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_49_CHECKER_TYPE,
19480  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_49_WIDTH },
19481  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_50_CHECKER_TYPE,
19482  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_50_WIDTH },
19483  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_51_CHECKER_TYPE,
19484  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_51_WIDTH },
19485  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_52_CHECKER_TYPE,
19486  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_52_WIDTH },
19487  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_53_CHECKER_TYPE,
19488  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_53_WIDTH },
19489  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_54_CHECKER_TYPE,
19490  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_54_WIDTH },
19491  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_55_CHECKER_TYPE,
19492  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_55_WIDTH },
19493  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_56_CHECKER_TYPE,
19494  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_56_WIDTH },
19495  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_57_CHECKER_TYPE,
19496  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_57_WIDTH },
19497  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_58_CHECKER_TYPE,
19498  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_58_WIDTH },
19499  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_59_CHECKER_TYPE,
19500  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_59_WIDTH },
19501  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_60_CHECKER_TYPE,
19502  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_60_WIDTH },
19503  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_61_CHECKER_TYPE,
19504  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_61_WIDTH },
19505  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_62_CHECKER_TYPE,
19506  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_62_WIDTH },
19507  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_63_CHECKER_TYPE,
19508  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_63_WIDTH },
19509  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_64_CHECKER_TYPE,
19510  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_64_WIDTH },
19511  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_65_CHECKER_TYPE,
19512  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_65_WIDTH },
19513  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_66_CHECKER_TYPE,
19514  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_66_WIDTH },
19515  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_67_CHECKER_TYPE,
19516  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_67_WIDTH },
19517  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_68_CHECKER_TYPE,
19518  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_GROUP_68_WIDTH },
19519 };
19520 
19526 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_MAX_NUM_CHECKERS] =
19527 {
19528  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_GROUP_0_CHECKER_TYPE,
19529  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_GROUP_0_WIDTH },
19530  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_GROUP_1_CHECKER_TYPE,
19531  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_GROUP_1_WIDTH },
19532  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_GROUP_2_CHECKER_TYPE,
19533  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_GROUP_2_WIDTH },
19534  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_GROUP_3_CHECKER_TYPE,
19535  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_GROUP_3_WIDTH },
19536 };
19537 
19543 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_MAX_NUM_CHECKERS] =
19544 {
19545  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
19546  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_0_WIDTH },
19547  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
19548  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_1_WIDTH },
19549  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
19550  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_2_WIDTH },
19551  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
19552  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_3_WIDTH },
19553  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
19554  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_4_WIDTH },
19555  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
19556  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_5_WIDTH },
19557  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
19558  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_6_WIDTH },
19559  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
19560  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_7_WIDTH },
19561  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
19562  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_8_WIDTH },
19563  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
19564  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_9_WIDTH },
19565  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
19566  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_10_WIDTH },
19567  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
19568  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_11_WIDTH },
19569  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
19570  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_12_WIDTH },
19571  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
19572  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_13_WIDTH },
19573  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
19574  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_GROUP_14_WIDTH },
19575 };
19576 
19582 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_MAX_NUM_CHECKERS] =
19583 {
19584  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_GROUP_0_CHECKER_TYPE,
19585  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_GROUP_0_WIDTH },
19586  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_GROUP_1_CHECKER_TYPE,
19587  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_GROUP_1_WIDTH },
19588  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_GROUP_2_CHECKER_TYPE,
19589  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_GROUP_2_WIDTH },
19590  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_GROUP_3_CHECKER_TYPE,
19591  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_GROUP_3_WIDTH },
19592 };
19593 
19599 static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
19600 {
19601  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
19602  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
19603  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
19604  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
19605  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
19606  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
19607  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
19608  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
19609  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
19610  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
19611  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
19612  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
19613 };
19614 
19619 static const SDL_MemConfig_t SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_MemEntries[SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
19620 {
19621  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_SAM62A_C7XV_CLEC_CLEC_SRAM_RAM_ID, 0u,
19622  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_SAM62A_C7XV_CLEC_CLEC_SRAM_RAM_SIZE, 4u,
19623  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_SAM62A_C7XV_CLEC_CLEC_SRAM_ROW_WIDTH, ((bool)false) },
19624 };
19625 
19631 static const SDL_GrpChkConfig_t SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_groupEntries[SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_MAX_NUM_CHECKERS] =
19632 {
19633  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_0_CHECKER_TYPE,
19634  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_0_WIDTH },
19635  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_1_CHECKER_TYPE,
19636  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_1_WIDTH },
19637  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_2_CHECKER_TYPE,
19638  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_2_WIDTH },
19639  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_3_CHECKER_TYPE,
19640  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_3_WIDTH },
19641 };
19642 
19648 static const SDL_GrpChkConfig_t SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_groupEntries[SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_MAX_NUM_CHECKERS] =
19649 {
19650  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
19651  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_GROUP_0_WIDTH },
19652  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
19653  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_GROUP_1_WIDTH },
19654 };
19655 
19661 static const SDL_GrpChkConfig_t SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_groupEntries[SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_MAX_NUM_CHECKERS] =
19662 {
19663  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
19664  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_0_WIDTH },
19665  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
19666  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_1_WIDTH },
19667  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
19668  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_2_WIDTH },
19669  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
19670  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_3_WIDTH },
19671  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
19672  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_4_WIDTH },
19673  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
19674  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_5_WIDTH },
19675  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
19676  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_6_WIDTH },
19677  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
19678  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_7_WIDTH },
19679  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
19680  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_8_WIDTH },
19681  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
19682  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_9_WIDTH },
19683  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
19684  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_10_WIDTH },
19685  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
19686  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_11_WIDTH },
19687  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
19688  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_12_WIDTH },
19689  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
19690  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_13_WIDTH },
19691  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
19692  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_14_WIDTH },
19693  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
19694  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_15_WIDTH },
19695  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
19696  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_16_WIDTH },
19697  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
19698  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_17_WIDTH },
19699  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
19700  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_18_WIDTH },
19701  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
19702  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_19_WIDTH },
19703  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
19704  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_20_WIDTH },
19705  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
19706  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_21_WIDTH },
19707  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
19708  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_22_WIDTH },
19709  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
19710  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_23_WIDTH },
19711  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
19712  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_24_WIDTH },
19713  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
19714  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_25_WIDTH },
19715  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
19716  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_26_WIDTH },
19717  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
19718  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_27_WIDTH },
19719  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
19720  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_28_WIDTH },
19721  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
19722  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_29_WIDTH },
19723  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
19724  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_30_WIDTH },
19725  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
19726  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_31_WIDTH },
19727  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
19728  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_32_WIDTH },
19729  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
19730  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_33_WIDTH },
19731  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
19732  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_34_WIDTH },
19733  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
19734  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_35_WIDTH },
19735  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
19736  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_36_WIDTH },
19737  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
19738  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_37_WIDTH },
19739  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
19740  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_38_WIDTH },
19741  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
19742  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_39_WIDTH },
19743  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
19744  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_40_WIDTH },
19745  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
19746  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_41_WIDTH },
19747  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
19748  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_42_WIDTH },
19749  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
19750  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_43_WIDTH },
19751  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
19752  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_44_WIDTH },
19753  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
19754  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_45_WIDTH },
19755  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
19756  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_46_WIDTH },
19757  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
19758  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_47_WIDTH },
19759  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
19760  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_48_WIDTH },
19761  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
19762  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_49_WIDTH },
19763  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
19764  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_50_WIDTH },
19765  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
19766  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_51_WIDTH },
19767  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
19768  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_52_WIDTH },
19769  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
19770  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_53_WIDTH },
19771  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
19772  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_54_WIDTH },
19773  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
19774  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_55_WIDTH },
19775  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
19776  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_56_WIDTH },
19777  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
19778  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_57_WIDTH },
19779  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
19780  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_58_WIDTH },
19781  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
19782  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_59_WIDTH },
19783  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
19784  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_60_WIDTH },
19785  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
19786  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_61_WIDTH },
19787  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
19788  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_62_WIDTH },
19789  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
19790  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_63_WIDTH },
19791  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
19792  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_64_WIDTH },
19793  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
19794  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_65_WIDTH },
19795  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
19796  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_66_WIDTH },
19797  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
19798  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_67_WIDTH },
19799  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
19800  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_68_WIDTH },
19801  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
19802  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_69_WIDTH },
19803  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
19804  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_70_WIDTH },
19805  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
19806  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_71_WIDTH },
19807  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
19808  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_72_WIDTH },
19809  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
19810  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_73_WIDTH },
19811  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
19812  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_74_WIDTH },
19813  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
19814  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_75_WIDTH },
19815  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
19816  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_76_WIDTH },
19817  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
19818  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_77_WIDTH },
19819  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
19820  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_78_WIDTH },
19821  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
19822  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_79_WIDTH },
19823  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
19824  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_80_WIDTH },
19825  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
19826  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_81_WIDTH },
19827  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
19828  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_82_WIDTH },
19829  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
19830  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_83_WIDTH },
19831  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
19832  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_84_WIDTH },
19833  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
19834  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_85_WIDTH },
19835  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
19836  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_86_WIDTH },
19837  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
19838  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_87_WIDTH },
19839  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
19840  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_88_WIDTH },
19841  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
19842  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_89_WIDTH },
19843  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
19844  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_90_WIDTH },
19845  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
19846  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_91_WIDTH },
19847  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
19848  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_92_WIDTH },
19849  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
19850  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_93_WIDTH },
19851  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
19852  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_94_WIDTH },
19853  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
19854  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_95_WIDTH },
19855  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
19856  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_96_WIDTH },
19857  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
19858  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_97_WIDTH },
19859  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
19860  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_98_WIDTH },
19861  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
19862  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_99_WIDTH },
19863  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
19864  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_100_WIDTH },
19865  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
19866  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_101_WIDTH },
19867  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
19868  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_102_WIDTH },
19869  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
19870  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_103_WIDTH },
19871  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
19872  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_104_WIDTH },
19873  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
19874  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_105_WIDTH },
19875  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
19876  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_106_WIDTH },
19877  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
19878  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_107_WIDTH },
19879  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
19880  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_108_WIDTH },
19881  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
19882  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_109_WIDTH },
19883  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
19884  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_110_WIDTH },
19885  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
19886  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_111_WIDTH },
19887  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
19888  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_112_WIDTH },
19889  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
19890  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_113_WIDTH },
19891  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
19892  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_114_WIDTH },
19893  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
19894  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_115_WIDTH },
19895  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
19896  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_116_WIDTH },
19897  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
19898  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_117_WIDTH },
19899  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
19900  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_118_WIDTH },
19901  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
19902  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_119_WIDTH },
19903  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
19904  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_120_WIDTH },
19905  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
19906  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_121_WIDTH },
19907  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
19908  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_122_WIDTH },
19909  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
19910  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_123_WIDTH },
19911  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
19912  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_124_WIDTH },
19913  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
19914  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_125_WIDTH },
19915  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
19916  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_126_WIDTH },
19917  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
19918  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_127_WIDTH },
19919  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
19920  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_128_WIDTH },
19921  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
19922  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_129_WIDTH },
19923  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
19924  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_130_WIDTH },
19925  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
19926  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_131_WIDTH },
19927  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
19928  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_132_WIDTH },
19929  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_133_CHECKER_TYPE,
19930  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_133_WIDTH },
19931  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_134_CHECKER_TYPE,
19932  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_134_WIDTH },
19933  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_135_CHECKER_TYPE,
19934  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_135_WIDTH },
19935  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_136_CHECKER_TYPE,
19936  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_136_WIDTH },
19937  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_137_CHECKER_TYPE,
19938  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_137_WIDTH },
19939  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_138_CHECKER_TYPE,
19940  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_138_WIDTH },
19941  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_139_CHECKER_TYPE,
19942  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_139_WIDTH },
19943  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_140_CHECKER_TYPE,
19944  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_140_WIDTH },
19945  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_141_CHECKER_TYPE,
19946  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_141_WIDTH },
19947  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_142_CHECKER_TYPE,
19948  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_142_WIDTH },
19949  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_143_CHECKER_TYPE,
19950  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_143_WIDTH },
19951  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_144_CHECKER_TYPE,
19952  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_144_WIDTH },
19953  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_145_CHECKER_TYPE,
19954  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_145_WIDTH },
19955  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_146_CHECKER_TYPE,
19956  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_146_WIDTH },
19957  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_147_CHECKER_TYPE,
19958  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_147_WIDTH },
19959  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_148_CHECKER_TYPE,
19960  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_148_WIDTH },
19961  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_149_CHECKER_TYPE,
19962  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_149_WIDTH },
19963  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_150_CHECKER_TYPE,
19964  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_150_WIDTH },
19965  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_151_CHECKER_TYPE,
19966  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_151_WIDTH },
19967  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_152_CHECKER_TYPE,
19968  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_152_WIDTH },
19969  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_153_CHECKER_TYPE,
19970  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_153_WIDTH },
19971  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_154_CHECKER_TYPE,
19972  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_154_WIDTH },
19973  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_155_CHECKER_TYPE,
19974  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_155_WIDTH },
19975  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_156_CHECKER_TYPE,
19976  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_156_WIDTH },
19977  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_157_CHECKER_TYPE,
19978  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_157_WIDTH },
19979  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_158_CHECKER_TYPE,
19980  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_158_WIDTH },
19981  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_159_CHECKER_TYPE,
19982  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_159_WIDTH },
19983  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_160_CHECKER_TYPE,
19984  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_160_WIDTH },
19985  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_161_CHECKER_TYPE,
19986  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_161_WIDTH },
19987  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_162_CHECKER_TYPE,
19988  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_162_WIDTH },
19989  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_163_CHECKER_TYPE,
19990  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_163_WIDTH },
19991  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_164_CHECKER_TYPE,
19992  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_164_WIDTH },
19993  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_165_CHECKER_TYPE,
19994  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_165_WIDTH },
19995  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_166_CHECKER_TYPE,
19996  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_166_WIDTH },
19997  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_167_CHECKER_TYPE,
19998  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_167_WIDTH },
19999 };
20000 
20006 static const SDL_GrpChkConfig_t SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_groupEntries[SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS] =
20007 {
20008  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
20009  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_0_WIDTH },
20010  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
20011  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_1_WIDTH },
20012  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
20013  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_2_WIDTH },
20014  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
20015  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_3_WIDTH },
20016 };
20017 
20023 static const SDL_GrpChkConfig_t SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_groupEntries[SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS] =
20024 {
20025  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
20026  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_GROUP_0_WIDTH },
20027 };
20028 
20034 static const SDL_GrpChkConfig_t SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_groupEntries[SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_MAX_NUM_CHECKERS] =
20035 {
20036  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
20037  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_GROUP_0_WIDTH },
20038 };
20039 
20045 static const SDL_GrpChkConfig_t SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_groupEntries[SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_MAX_NUM_CHECKERS] =
20046 {
20047  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_0_CHECKER_TYPE,
20048  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_0_WIDTH },
20049  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_1_CHECKER_TYPE,
20050  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_1_WIDTH },
20051  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_2_CHECKER_TYPE,
20052  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_2_WIDTH },
20053  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_3_CHECKER_TYPE,
20054  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_3_WIDTH },
20055  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_4_CHECKER_TYPE,
20056  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_4_WIDTH },
20057  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_5_CHECKER_TYPE,
20058  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_5_WIDTH },
20059  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_6_CHECKER_TYPE,
20060  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_6_WIDTH },
20061  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_7_CHECKER_TYPE,
20062  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_7_WIDTH },
20063  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_8_CHECKER_TYPE,
20064  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_8_WIDTH },
20065  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_9_CHECKER_TYPE,
20066  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_9_WIDTH },
20067  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_10_CHECKER_TYPE,
20068  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_10_WIDTH },
20069  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_11_CHECKER_TYPE,
20070  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_11_WIDTH },
20071  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_12_CHECKER_TYPE,
20072  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_12_WIDTH },
20073  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_13_CHECKER_TYPE,
20074  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_13_WIDTH },
20075  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_14_CHECKER_TYPE,
20076  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_14_WIDTH },
20077  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_15_CHECKER_TYPE,
20078  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_15_WIDTH },
20079 };
20080 
20085 static const SDL_MemConfig_t SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_MemEntries[SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
20086 {
20087  { SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID, 0u,
20088  SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_SIZE, 9u,
20089  SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ROW_WIDTH, ((bool)false) },
20090  { SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_RAM_ID, 0u,
20091  SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_RAM_SIZE, 8u,
20092  SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_ROW_WIDTH, ((bool)false) },
20093 };
20094 
20099 static const SDL_MemConfig_t SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_MemEntries[SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
20100 {
20101  { SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID, 0u,
20102  SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_SIZE, 9u,
20103  SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ROW_WIDTH, ((bool)false) },
20104  { SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_RAM_ID, 0u,
20105  SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_RAM_SIZE, 8u,
20106  SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_ROW_WIDTH, ((bool)false) },
20107 };
20108 
20113 static const SDL_MemConfig_t SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_MemEntries[SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
20114 {
20115  { SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_PSRAM8KX32E_PSRAM0_ECC_RAM_ID, 0x0041880000u,
20116  SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_PSRAM8KX32E_PSRAM0_ECC_RAM_SIZE, 4u,
20117  SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_PSRAM8KX32E_PSRAM0_ECC_ROW_WIDTH, ((bool)true) },
20118 };
20119 
20124 static const SDL_MemConfig_t SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_MemEntries[SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_RAM_IDS_TOTAL_ENTRIES] =
20125 {
20126  { SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_TF0_F0_TPRAM_60X128_SBW_SR_RAM_ID, 0u,
20127  SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_TF0_F0_TPRAM_60X128_SBW_SR_RAM_SIZE, 16u,
20128  SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_TF0_F0_TPRAM_60X128_SBW_SR_ROW_WIDTH, ((bool)false) },
20129  { SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_TF0_F1_TPRAM_60X128_SBW_SR_RAM_ID, 0u,
20130  SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_TF0_F1_TPRAM_60X128_SBW_SR_RAM_SIZE, 16u,
20131  SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_TF0_F1_TPRAM_60X128_SBW_SR_ROW_WIDTH, ((bool)false) },
20132  { SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_RF0_F0_TPRAM_60X144_SBW_SR_RAM_ID, 0u,
20133  SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_RF0_F0_TPRAM_60X144_SBW_SR_RAM_SIZE, 18u,
20134  SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_RF0_F0_TPRAM_60X144_SBW_SR_ROW_WIDTH, ((bool)false) },
20135  { SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_RF0_F1_TPRAM_60X144_SBW_SR_RAM_ID, 0u,
20136  SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_RF0_F1_TPRAM_60X144_SBW_SR_RAM_SIZE, 18u,
20137  SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_RF0_F1_TPRAM_60X144_SBW_SR_ROW_WIDTH, ((bool)false) },
20138 };
20139 
20145 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_MAX_NUM_CHECKERS] =
20146 {
20147  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_0_CHECKER_TYPE,
20148  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_0_WIDTH },
20149  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_1_CHECKER_TYPE,
20150  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_1_WIDTH },
20151  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_2_CHECKER_TYPE,
20152  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_2_WIDTH },
20153  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_3_CHECKER_TYPE,
20154  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_3_WIDTH },
20155  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_4_CHECKER_TYPE,
20156  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_4_WIDTH },
20157  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_5_CHECKER_TYPE,
20158  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_5_WIDTH },
20159  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_6_CHECKER_TYPE,
20160  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_6_WIDTH },
20161  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_7_CHECKER_TYPE,
20162  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_7_WIDTH },
20163  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_8_CHECKER_TYPE,
20164  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_8_WIDTH },
20165  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_9_CHECKER_TYPE,
20166  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_9_WIDTH },
20167  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_10_CHECKER_TYPE,
20168  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_10_WIDTH },
20169  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_11_CHECKER_TYPE,
20170  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_11_WIDTH },
20171  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_12_CHECKER_TYPE,
20172  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_12_WIDTH },
20173  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_13_CHECKER_TYPE,
20174  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_13_WIDTH },
20175  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_14_CHECKER_TYPE,
20176  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_14_WIDTH },
20177  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_15_CHECKER_TYPE,
20178  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_15_WIDTH },
20179  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_16_CHECKER_TYPE,
20180  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_16_WIDTH },
20181  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_17_CHECKER_TYPE,
20182  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_17_WIDTH },
20183  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_18_CHECKER_TYPE,
20184  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_18_WIDTH },
20185  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_19_CHECKER_TYPE,
20186  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_19_WIDTH },
20187  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_20_CHECKER_TYPE,
20188  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_20_WIDTH },
20189  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_21_CHECKER_TYPE,
20190  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_21_WIDTH },
20191  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_22_CHECKER_TYPE,
20192  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_22_WIDTH },
20193  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_23_CHECKER_TYPE,
20194  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_23_WIDTH },
20195  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_24_CHECKER_TYPE,
20196  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_24_WIDTH },
20197  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_25_CHECKER_TYPE,
20198  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_25_WIDTH },
20199  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_26_CHECKER_TYPE,
20200  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_26_WIDTH },
20201  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_27_CHECKER_TYPE,
20202  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_27_WIDTH },
20203  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_28_CHECKER_TYPE,
20204  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_28_WIDTH },
20205  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_29_CHECKER_TYPE,
20206  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_29_WIDTH },
20207  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_30_CHECKER_TYPE,
20208  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_30_WIDTH },
20209  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_31_CHECKER_TYPE,
20210  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_31_WIDTH },
20211  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_32_CHECKER_TYPE,
20212  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_32_WIDTH },
20213  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_33_CHECKER_TYPE,
20214  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_33_WIDTH },
20215  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_34_CHECKER_TYPE,
20216  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_34_WIDTH },
20217  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_35_CHECKER_TYPE,
20218  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_35_WIDTH },
20219  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_36_CHECKER_TYPE,
20220  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_36_WIDTH },
20221  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_37_CHECKER_TYPE,
20222  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_37_WIDTH },
20223  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_38_CHECKER_TYPE,
20224  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_38_WIDTH },
20225  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_39_CHECKER_TYPE,
20226  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_39_WIDTH },
20227  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_40_CHECKER_TYPE,
20228  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_40_WIDTH },
20229  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_41_CHECKER_TYPE,
20230  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_41_WIDTH },
20231  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_42_CHECKER_TYPE,
20232  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_42_WIDTH },
20233  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_43_CHECKER_TYPE,
20234  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_43_WIDTH },
20235  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_44_CHECKER_TYPE,
20236  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_44_WIDTH },
20237  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_45_CHECKER_TYPE,
20238  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_45_WIDTH },
20239  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_46_CHECKER_TYPE,
20240  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_46_WIDTH },
20241  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_47_CHECKER_TYPE,
20242  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_47_WIDTH },
20243  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_48_CHECKER_TYPE,
20244  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_48_WIDTH },
20245  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_49_CHECKER_TYPE,
20246  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_49_WIDTH },
20247  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_50_CHECKER_TYPE,
20248  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_50_WIDTH },
20249  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_51_CHECKER_TYPE,
20250  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_51_WIDTH },
20251  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_52_CHECKER_TYPE,
20252  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_52_WIDTH },
20253  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_53_CHECKER_TYPE,
20254  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_53_WIDTH },
20255  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_54_CHECKER_TYPE,
20256  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_54_WIDTH },
20257  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_55_CHECKER_TYPE,
20258  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_55_WIDTH },
20259  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_56_CHECKER_TYPE,
20260  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_56_WIDTH },
20261  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_57_CHECKER_TYPE,
20262  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_57_WIDTH },
20263  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_58_CHECKER_TYPE,
20264  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_58_WIDTH },
20265  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_59_CHECKER_TYPE,
20266  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_59_WIDTH },
20267  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_60_CHECKER_TYPE,
20268  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_60_WIDTH },
20269  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_61_CHECKER_TYPE,
20270  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_61_WIDTH },
20271  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_62_CHECKER_TYPE,
20272  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_62_WIDTH },
20273  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_63_CHECKER_TYPE,
20274  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_63_WIDTH },
20275  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_64_CHECKER_TYPE,
20276  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_64_WIDTH },
20277  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_65_CHECKER_TYPE,
20278  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_65_WIDTH },
20279  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_66_CHECKER_TYPE,
20280  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_66_WIDTH },
20281  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_67_CHECKER_TYPE,
20282  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_67_WIDTH },
20283  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_68_CHECKER_TYPE,
20284  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_68_WIDTH },
20285  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_69_CHECKER_TYPE,
20286  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_69_WIDTH },
20287  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_70_CHECKER_TYPE,
20288  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_70_WIDTH },
20289  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_71_CHECKER_TYPE,
20290  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_71_WIDTH },
20291  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_72_CHECKER_TYPE,
20292  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_72_WIDTH },
20293  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_73_CHECKER_TYPE,
20294  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_73_WIDTH },
20295  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_74_CHECKER_TYPE,
20296  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_74_WIDTH },
20297  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_75_CHECKER_TYPE,
20298  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_75_WIDTH },
20299  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_76_CHECKER_TYPE,
20300  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_76_WIDTH },
20301  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_77_CHECKER_TYPE,
20302  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_77_WIDTH },
20303 };
20304 
20310 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_MAX_NUM_CHECKERS] =
20311 {
20312  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_0_CHECKER_TYPE,
20313  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_0_WIDTH },
20314  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_1_CHECKER_TYPE,
20315  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_1_WIDTH },
20316  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_2_CHECKER_TYPE,
20317  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_2_WIDTH },
20318  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_3_CHECKER_TYPE,
20319  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_3_WIDTH },
20320  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_4_CHECKER_TYPE,
20321  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_4_WIDTH },
20322  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_5_CHECKER_TYPE,
20323  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_5_WIDTH },
20324  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_6_CHECKER_TYPE,
20325  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_6_WIDTH },
20326  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_7_CHECKER_TYPE,
20327  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_7_WIDTH },
20328  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_8_CHECKER_TYPE,
20329  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_8_WIDTH },
20330  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_9_CHECKER_TYPE,
20331  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_9_WIDTH },
20332  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_10_CHECKER_TYPE,
20333  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_10_WIDTH },
20334  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_11_CHECKER_TYPE,
20335  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_11_WIDTH },
20336  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_12_CHECKER_TYPE,
20337  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_12_WIDTH },
20338  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_13_CHECKER_TYPE,
20339  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_13_WIDTH },
20340  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_14_CHECKER_TYPE,
20341  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_14_WIDTH },
20342  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_15_CHECKER_TYPE,
20343  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_15_WIDTH },
20344  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_16_CHECKER_TYPE,
20345  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_16_WIDTH },
20346  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_17_CHECKER_TYPE,
20347  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_17_WIDTH },
20348  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_18_CHECKER_TYPE,
20349  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_18_WIDTH },
20350  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_19_CHECKER_TYPE,
20351  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_19_WIDTH },
20352  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_20_CHECKER_TYPE,
20353  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_20_WIDTH },
20354  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_21_CHECKER_TYPE,
20355  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_21_WIDTH },
20356  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_22_CHECKER_TYPE,
20357  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_22_WIDTH },
20358  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_23_CHECKER_TYPE,
20359  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_23_WIDTH },
20360  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_24_CHECKER_TYPE,
20361  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_24_WIDTH },
20362  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_25_CHECKER_TYPE,
20363  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_25_WIDTH },
20364  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_26_CHECKER_TYPE,
20365  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_26_WIDTH },
20366  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_27_CHECKER_TYPE,
20367  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_27_WIDTH },
20368  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_28_CHECKER_TYPE,
20369  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_28_WIDTH },
20370  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_29_CHECKER_TYPE,
20371  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_29_WIDTH },
20372  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_30_CHECKER_TYPE,
20373  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_30_WIDTH },
20374  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_31_CHECKER_TYPE,
20375  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_31_WIDTH },
20376  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_32_CHECKER_TYPE,
20377  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_32_WIDTH },
20378 };
20379 
20385 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
20386 {
20387  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
20388  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_0_WIDTH },
20389  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
20390  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_1_WIDTH },
20391  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
20392  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_2_WIDTH },
20393  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
20394  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_3_WIDTH },
20395  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
20396  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_4_WIDTH },
20397  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
20398  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_5_WIDTH },
20399  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
20400  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_6_WIDTH },
20401  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
20402  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_7_WIDTH },
20403  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
20404  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_8_WIDTH },
20405  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
20406  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_9_WIDTH },
20407  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
20408  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_10_WIDTH },
20409  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
20410  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_11_WIDTH },
20411  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
20412  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_12_WIDTH },
20413 };
20414 
20420 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
20421 {
20422  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
20423  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
20424  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
20425  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
20426  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
20427  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
20428  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
20429  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
20430  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
20431  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
20432  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
20433  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
20434  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
20435  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
20436  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
20437  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
20438  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
20439  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
20440  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
20441  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
20442  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
20443  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
20444  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
20445  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
20446  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
20447  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
20448  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
20449  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
20450  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
20451  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
20452  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
20453  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
20454  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
20455  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
20456  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
20457  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
20458  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
20459  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
20460  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
20461  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
20462  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
20463  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
20464  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
20465  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
20466  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
20467  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
20468  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
20469  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
20470  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
20471  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
20472  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
20473  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
20474  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
20475  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
20476  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
20477  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
20478  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
20479  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
20480  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
20481  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
20482  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
20483  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
20484  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
20485  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
20486  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
20487  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
20488  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
20489  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
20490  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
20491  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
20492  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
20493  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
20494  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
20495  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
20496  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
20497  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
20498  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
20499  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
20500  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
20501  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
20502  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
20503  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
20504  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
20505  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
20506  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
20507  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
20508  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
20509  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
20510  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
20511  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
20512  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
20513  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
20514  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
20515  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
20516  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
20517  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
20518  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
20519  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
20520  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
20521  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
20522  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
20523  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
20524  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
20525  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
20526  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
20527  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
20528  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
20529  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
20530  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
20531  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
20532  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
20533  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
20534  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
20535  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
20536  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
20537  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
20538  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
20539  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
20540  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
20541  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
20542  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
20543  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
20544  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
20545  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
20546  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
20547  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
20548  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
20549  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
20550  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
20551  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
20552  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
20553  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
20554  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
20555  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
20556  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
20557  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
20558  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
20559  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
20560  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_69_CHECKER_TYPE,
20561  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
20562  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_70_CHECKER_TYPE,
20563  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_70_WIDTH },
20564  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_71_CHECKER_TYPE,
20565  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_71_WIDTH },
20566  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_72_CHECKER_TYPE,
20567  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_72_WIDTH },
20568 };
20569 
20575 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
20576 {
20577  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
20578  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
20579  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
20580  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
20581  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
20582  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
20583  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
20584  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
20585  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
20586  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
20587  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
20588  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
20589  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
20590  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
20591  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
20592  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
20593  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
20594  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
20595  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
20596  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
20597  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
20598  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
20599  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
20600  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
20601  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
20602  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
20603  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
20604  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
20605  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
20606  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
20607  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
20608  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
20609  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
20610  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
20611  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
20612  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
20613  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
20614  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
20615  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
20616  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
20617  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
20618  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
20619  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
20620  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
20621  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
20622  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
20623  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
20624  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
20625  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
20626  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
20627  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
20628  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
20629  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
20630  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
20631  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
20632  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
20633  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
20634  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
20635  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
20636  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
20637  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
20638  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
20639  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
20640  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
20641  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
20642  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
20643  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
20644  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
20645  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
20646  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
20647  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
20648  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
20649  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
20650  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
20651  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
20652  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
20653  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
20654  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
20655  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
20656  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
20657  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
20658  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
20659  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
20660  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
20661  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
20662  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
20663  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
20664  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
20665  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
20666  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
20667  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
20668  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
20669  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
20670  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
20671  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
20672  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
20673  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
20674  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
20675  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
20676  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
20677  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
20678  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
20679  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
20680  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
20681  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
20682  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
20683  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
20684  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
20685  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
20686  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
20687  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
20688  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
20689  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
20690  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
20691  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
20692  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
20693  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
20694  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
20695  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
20696  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
20697  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
20698  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
20699  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
20700  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
20701  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
20702  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
20703  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
20704  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
20705  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
20706  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
20707  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
20708  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
20709  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
20710  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
20711  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
20712  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
20713  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
20714  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
20715  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_69_CHECKER_TYPE,
20716  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
20717  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_70_CHECKER_TYPE,
20718  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_70_WIDTH },
20719  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_71_CHECKER_TYPE,
20720  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_71_WIDTH },
20721 };
20722 
20728 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
20729 {
20730  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
20731  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
20732  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
20733  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
20734  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
20735  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
20736  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
20737  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
20738  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_4_CHECKER_TYPE,
20739  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_4_WIDTH },
20740  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_5_CHECKER_TYPE,
20741  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_5_WIDTH },
20742  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_6_CHECKER_TYPE,
20743  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_6_WIDTH },
20744 };
20745 
20751 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
20752 {
20753  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
20754  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
20755  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
20756  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
20757  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
20758  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
20759  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
20760  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
20761  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
20762  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
20763  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
20764  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
20765  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
20766  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
20767  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
20768  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
20769  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
20770  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
20771  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
20772  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
20773  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
20774  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
20775  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
20776  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
20777  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
20778  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
20779  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
20780  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
20781  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
20782  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
20783  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_15_CHECKER_TYPE,
20784  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_15_WIDTH },
20785  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_16_CHECKER_TYPE,
20786  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_16_WIDTH },
20787 };
20788 
20794 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
20795 {
20796  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
20797  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
20798  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
20799  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
20800  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
20801  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
20802  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
20803  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
20804  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
20805  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
20806  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
20807  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
20808  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
20809  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
20810  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
20811  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
20812  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
20813  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
20814  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
20815  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
20816  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
20817  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
20818  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
20819  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
20820  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
20821  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
20822  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
20823  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
20824  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
20825  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
20826  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_15_CHECKER_TYPE,
20827  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_15_WIDTH },
20828  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_16_CHECKER_TYPE,
20829  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_GROUP_16_WIDTH },
20830 };
20831 
20837 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
20838 {
20839  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
20840  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
20841  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
20842  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
20843  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
20844  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
20845  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
20846  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
20847  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
20848  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
20849  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
20850  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
20851  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
20852  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
20853  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
20854  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
20855  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
20856  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
20857  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
20858  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
20859  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
20860  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
20861  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
20862  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
20863  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
20864  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
20865  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
20866  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
20867  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
20868  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
20869  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
20870  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
20871  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
20872  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
20873  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
20874  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
20875  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
20876  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
20877  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
20878  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
20879  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
20880  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
20881  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
20882  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
20883  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
20884  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
20885  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
20886  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
20887  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
20888  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
20889  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
20890  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
20891  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
20892  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
20893  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
20894  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
20895  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
20896  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
20897  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
20898  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
20899  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
20900  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
20901  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
20902  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
20903  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
20904  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
20905  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
20906  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
20907  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
20908  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
20909  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
20910  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
20911  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
20912  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
20913  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
20914  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
20915  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
20916  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
20917  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
20918  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
20919  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
20920  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
20921  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
20922  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
20923  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
20924  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
20925  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
20926  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
20927  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
20928  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
20929  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
20930  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
20931  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
20932  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
20933  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
20934  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
20935  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
20936  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
20937  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
20938  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
20939  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
20940  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
20941  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
20942  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
20943  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
20944  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
20945  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
20946  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
20947  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
20948  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
20949  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
20950  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
20951  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
20952  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
20953  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
20954  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
20955  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
20956  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
20957  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
20958  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
20959  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
20960  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
20961  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
20962  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
20963  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
20964  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
20965  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
20966  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
20967  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
20968  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
20969  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
20970  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
20971  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
20972  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
20973  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
20974  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
20975  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
20976  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
20977  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_69_CHECKER_TYPE,
20978  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
20979 };
20980 
20986 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
20987 {
20988  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
20989  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
20990  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
20991  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
20992  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
20993  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
20994  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
20995  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
20996  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
20997  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
20998  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
20999  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
21000  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
21001  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
21002  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
21003  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
21004  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
21005  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
21006  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
21007  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
21008  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
21009  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
21010  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
21011  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
21012  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
21013  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
21014  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
21015  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
21016  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
21017  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
21018  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
21019  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
21020  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
21021  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
21022  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
21023  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
21024  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
21025  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
21026  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
21027  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
21028  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
21029  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
21030  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
21031  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
21032  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
21033  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
21034  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
21035  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
21036  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
21037  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
21038  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
21039  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
21040  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
21041  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
21042  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
21043  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
21044  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
21045  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
21046  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
21047  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
21048  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
21049  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
21050  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
21051  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
21052  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
21053  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
21054  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
21055  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
21056  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
21057  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
21058  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
21059  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
21060  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
21061  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
21062  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
21063  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
21064  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
21065  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
21066  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
21067  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
21068  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
21069  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
21070  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
21071  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
21072  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
21073  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
21074  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
21075  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
21076  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
21077  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
21078  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
21079  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
21080  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
21081  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
21082  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
21083  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
21084  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
21085  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
21086  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
21087  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
21088  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
21089  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
21090  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
21091  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
21092  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
21093  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
21094  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
21095  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
21096  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
21097  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
21098  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
21099  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
21100  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
21101  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
21102  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
21103  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
21104  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
21105  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
21106  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
21107  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
21108  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
21109  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
21110  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
21111  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
21112  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
21113  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
21114  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
21115  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
21116  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
21117  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
21118  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
21119  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
21120 };
21121 
21127 static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_SAM62A_DM_DM_ECC_AGGR_EDC_CTRL_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_SAM62A_DM_DM_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
21128 {
21129  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_SAM62A_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
21130  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_SAM62A_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
21131  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_SAM62A_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
21132  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_SAM62A_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
21133  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_SAM62A_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
21134  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_SAM62A_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
21135  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_SAM62A_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
21136  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_SAM62A_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
21137  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_SAM62A_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
21138  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_SAM62A_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
21139  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_SAM62A_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
21140  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_SAM62A_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
21141 };
21142 
21147 static const SDL_MemConfig_t SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_MemEntries[SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RAM_IDS_TOTAL_ENTRIES] =
21148 {
21149  { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F0_TPRAM_28X128_SBW_SR_RAM_ID, 0u,
21150  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F0_TPRAM_28X128_SBW_SR_RAM_SIZE, 16u,
21151  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F0_TPRAM_28X128_SBW_SR_ROW_WIDTH, ((bool)false) },
21152  { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F1_TPRAM_28X128_SBW_SR_RAM_ID, 0u,
21153  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F1_TPRAM_28X128_SBW_SR_RAM_SIZE, 16u,
21154  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F1_TPRAM_28X128_SBW_SR_ROW_WIDTH, ((bool)false) },
21155  { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F0_TPRAM_28X144_SBW_SR_RAM_ID, 0u,
21156  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F0_TPRAM_28X144_SBW_SR_RAM_SIZE, 18u,
21157  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F0_TPRAM_28X144_SBW_SR_ROW_WIDTH, ((bool)false) },
21158  { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F1_TPRAM_28X144_SBW_SR_RAM_ID, 0u,
21159  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F1_TPRAM_28X144_SBW_SR_RAM_SIZE, 18u,
21160  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F1_TPRAM_28X144_SBW_SR_ROW_WIDTH, ((bool)false) },
21161 };
21162 
21167 static const SDL_MemConfig_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
21168 {
21169  { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x0020708000u,
21170  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
21171  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
21172 };
21173 
21179 static const SDL_GrpChkConfig_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS] =
21180 {
21181  { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
21182  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
21183 };
21184 
21189 static const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_MemEntries[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RAM_IDS_TOTAL_ENTRIES] =
21190 {
21191  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_ID, 0u,
21192  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_SIZE, 6u,
21193  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21194  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_ID, 0u,
21195  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_SIZE, 6u,
21196  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21197  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_ID, 0u,
21198  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_SIZE, 6u,
21199  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21200  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_ID, 0u,
21201  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_SIZE, 6u,
21202  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21203  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_ID, 0u,
21204  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_SIZE, 4u,
21205  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21206  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_ID, 0u,
21207  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_SIZE, 4u,
21208  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21209  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
21210  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 5u,
21211  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21212  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
21213  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 5u,
21214  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21215  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
21216  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 5u,
21217  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21218  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
21219  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 5u,
21220  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21221  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID, 0u,
21222  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_SIZE, 5u,
21223  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21224  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID, 0u,
21225  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_SIZE, 5u,
21226  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21227  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_ID, 0u,
21228  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_SIZE, 5u,
21229  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21230  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_ID, 0u,
21231  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_SIZE, 5u,
21232  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21233  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
21234  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
21235  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21236  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
21237  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
21238  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21239  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
21240  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
21241  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21242  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
21243  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
21244  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21245  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_ID, 0u,
21246  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_SIZE, 4u,
21247  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21248  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
21249  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 15u,
21250  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21251  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
21252  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 15u,
21253  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21254  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
21255  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 15u,
21256  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21257  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
21258  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 15u,
21259  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21260  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID, 0u,
21261  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_SIZE, 5u,
21262  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21263  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID, 0u,
21264  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_SIZE, 5u,
21265  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21266  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID, 0u,
21267  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_SIZE, 5u,
21268  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21269  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID, 0u,
21270  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_SIZE, 5u,
21271  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21272 };
21273 
21278 static const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_MemEntries[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RAM_IDS_TOTAL_ENTRIES] =
21279 {
21280  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_ID, 0u,
21281  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_SIZE, 6u,
21282  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21283  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_ID, 0u,
21284  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_SIZE, 6u,
21285  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21286  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_ID, 0u,
21287  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_SIZE, 6u,
21288  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21289  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_ID, 0u,
21290  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_SIZE, 6u,
21291  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21292  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_ID, 0u,
21293  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_SIZE, 4u,
21294  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21295  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_ID, 0u,
21296  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_SIZE, 4u,
21297  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21298  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
21299  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 5u,
21300  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21301  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
21302  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 5u,
21303  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21304  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
21305  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 5u,
21306  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21307  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
21308  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 5u,
21309  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21310  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID, 0u,
21311  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_SIZE, 5u,
21312  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21313  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID, 0u,
21314  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_SIZE, 5u,
21315  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21316  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_ID, 0u,
21317  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_SIZE, 5u,
21318  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21319  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_ID, 0u,
21320  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_SIZE, 5u,
21321  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21322  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
21323  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
21324  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21325  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
21326  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
21327  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21328  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
21329  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
21330  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21331  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
21332  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
21333  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21334  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_ID, 0u,
21335  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_SIZE, 4u,
21336  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21337  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
21338  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 15u,
21339  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21340  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
21341  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 15u,
21342  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21343  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
21344  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 15u,
21345  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21346  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
21347  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 15u,
21348  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21349  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID, 0u,
21350  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_SIZE, 5u,
21351  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21352  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID, 0u,
21353  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_SIZE, 5u,
21354  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21355  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID, 0u,
21356  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_SIZE, 5u,
21357  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21358  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID, 0u,
21359  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_SIZE, 5u,
21360  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21361 };
21362 
21367 static const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_MemEntries[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_RAM_IDS_TOTAL_ENTRIES] =
21368 {
21369  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_ID, 0u,
21370  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_SIZE, 6u,
21371  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21372  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_ID, 0u,
21373  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_SIZE, 6u,
21374  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21375  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_ID, 0u,
21376  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_SIZE, 6u,
21377  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21378  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_ID, 0u,
21379  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_SIZE, 6u,
21380  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21381  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_ID, 0u,
21382  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_SIZE, 4u,
21383  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21384  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_ID, 0u,
21385  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_SIZE, 4u,
21386  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21387  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
21388  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 5u,
21389  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21390  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
21391  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 5u,
21392  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21393  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
21394  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 5u,
21395  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21396  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
21397  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 5u,
21398  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21399  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID, 0u,
21400  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_SIZE, 5u,
21401  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21402  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID, 0u,
21403  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_SIZE, 5u,
21404  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21405  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_ID, 0u,
21406  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_SIZE, 5u,
21407  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21408  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_ID, 0u,
21409  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_SIZE, 5u,
21410  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21411  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
21412  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
21413  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21414  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
21415  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
21416  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21417  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
21418  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
21419  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21420  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
21421  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
21422  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21423  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_ID, 0u,
21424  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_SIZE, 4u,
21425  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21426  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
21427  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 15u,
21428  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21429  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
21430  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 15u,
21431  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21432  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
21433  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 15u,
21434  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21435  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
21436  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 15u,
21437  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21438  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID, 0u,
21439  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_SIZE, 5u,
21440  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21441  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID, 0u,
21442  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_SIZE, 5u,
21443  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21444  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID, 0u,
21445  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_SIZE, 5u,
21446  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21447  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID, 0u,
21448  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_SIZE, 5u,
21449  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21450 };
21451 
21456 static const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_MemEntries[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_RAM_IDS_TOTAL_ENTRIES] =
21457 {
21458  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_ID, 0u,
21459  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_SIZE, 6u,
21460  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21461  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_ID, 0u,
21462  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_SIZE, 6u,
21463  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21464  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_ID, 0u,
21465  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_SIZE, 6u,
21466  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21467  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_ID, 0u,
21468  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_SIZE, 6u,
21469  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21470  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_ID, 0u,
21471  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_SIZE, 4u,
21472  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21473  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_ID, 0u,
21474  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_SIZE, 4u,
21475  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21476  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
21477  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 5u,
21478  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21479  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
21480  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 5u,
21481  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21482  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
21483  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 5u,
21484  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21485  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
21486  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 5u,
21487  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21488  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID, 0u,
21489  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_SIZE, 5u,
21490  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21491  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID, 0u,
21492  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_SIZE, 5u,
21493  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21494  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_ID, 0u,
21495  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_SIZE, 5u,
21496  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21497  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_ID, 0u,
21498  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_SIZE, 5u,
21499  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21500  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
21501  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
21502  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21503  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
21504  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
21505  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21506  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
21507  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
21508  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21509  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
21510  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
21511  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21512  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_ID, 0u,
21513  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_SIZE, 4u,
21514  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21515  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
21516  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 15u,
21517  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21518  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
21519  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 15u,
21520  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21521  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
21522  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 15u,
21523  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21524  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
21525  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 15u,
21526  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21527  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID, 0u,
21528  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_SIZE, 5u,
21529  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21530  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID, 0u,
21531  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_SIZE, 5u,
21532  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21533  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID, 0u,
21534  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_SIZE, 5u,
21535  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21536  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID, 0u,
21537  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_SIZE, 5u,
21538  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21539 };
21540 
21545 static const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_MemEntries[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RAM_IDS_TOTAL_ENTRIES] =
21546 {
21547  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID, 0u,
21548  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_SIZE, 5u,
21549  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21550  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID, 0u,
21551  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_SIZE, 5u,
21552  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21553  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID, 0u,
21554  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_SIZE, 5u,
21555  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21556  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID, 0u,
21557  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_SIZE, 5u,
21558  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21559  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_RAM_ID, 0u,
21560  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_RAM_SIZE, 5u,
21561  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21562  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_RAM_ID, 0u,
21563  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_RAM_SIZE, 5u,
21564  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21565  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_RAM_ID, 0u,
21566  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_RAM_SIZE, 5u,
21567  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21568  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_RAM_ID, 0u,
21569  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_RAM_SIZE, 5u,
21570  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21571  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_RAM_ID, 0u,
21572  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_RAM_SIZE, 5u,
21573  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21574  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_RAM_ID, 0u,
21575  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_RAM_SIZE, 5u,
21576  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21577  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_RAM_ID, 0u,
21578  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_RAM_SIZE, 5u,
21579  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21580  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_RAM_ID, 0u,
21581  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_RAM_SIZE, 5u,
21582  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21583  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_RAM_ID, 0u,
21584  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_RAM_SIZE, 5u,
21585  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21586  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_RAM_ID, 0u,
21587  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_RAM_SIZE, 5u,
21588  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21589  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_RAM_ID, 0u,
21590  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_RAM_SIZE, 5u,
21591  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21592  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_RAM_ID, 0u,
21593  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_RAM_SIZE, 5u,
21594  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21595  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_RAM_ID, 0u,
21596  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_RAM_SIZE, 9u,
21597  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21598  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_RAM_ID, 0u,
21599  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_RAM_SIZE, 9u,
21600  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21601  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_RAM_ID, 0u,
21602  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_RAM_SIZE, 9u,
21603  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21604  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_RAM_ID, 0u,
21605  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_RAM_SIZE, 9u,
21606  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21607  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_RAM_ID, 0u,
21608  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_RAM_SIZE, 9u,
21609  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21610  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_RAM_ID, 0u,
21611  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_RAM_SIZE, 9u,
21612  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21613  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_RAM_ID, 0u,
21614  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_RAM_SIZE, 9u,
21615  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21616  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_RAM_ID, 0u,
21617  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_RAM_SIZE, 9u,
21618  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
21619 };
21620 
21625 static const SDL_MemConfig_t SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
21626 {
21627  { SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x0004E00000u,
21628  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
21629  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
21630 };
21631 
21637 static const SDL_GrpChkConfig_t SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS] =
21638 {
21639  { SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
21640  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
21641 };
21642 
21647 static const SDL_MemConfig_t SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
21648 {
21649  { SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x0004E10000u,
21650  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
21651  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
21652 };
21653 
21659 static const SDL_GrpChkConfig_t SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS] =
21660 {
21661  { SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
21662  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
21663 };
21664 
21669 static const SDL_MemConfig_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_MemEntries[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
21670 {
21671  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_IMAILBOX4_MAIN_0_RAMECC_RAM_ID, 0u,
21672  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_IMAILBOX4_MAIN_0_RAMECC_RAM_SIZE, 4u,
21673  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_IMAILBOX4_MAIN_0_RAMECC_ROW_WIDTH, ((bool)false) },
21674 };
21675 
21681 static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_MAX_NUM_CHECKERS] =
21682 {
21683  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_0_CHECKER_TYPE,
21684  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_0_WIDTH },
21685  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_1_CHECKER_TYPE,
21686  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_1_WIDTH },
21687  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_2_CHECKER_TYPE,
21688  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_2_WIDTH },
21689  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_3_CHECKER_TYPE,
21690  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_3_WIDTH },
21691  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_4_CHECKER_TYPE,
21692  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_4_WIDTH },
21693  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_5_CHECKER_TYPE,
21694  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_5_WIDTH },
21695  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_6_CHECKER_TYPE,
21696  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_6_WIDTH },
21697  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_7_CHECKER_TYPE,
21698  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_7_WIDTH },
21699  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_8_CHECKER_TYPE,
21700  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_8_WIDTH },
21701  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_9_CHECKER_TYPE,
21702  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_9_WIDTH },
21703  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_10_CHECKER_TYPE,
21704  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_10_WIDTH },
21705  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_11_CHECKER_TYPE,
21706  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_11_WIDTH },
21707  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_12_CHECKER_TYPE,
21708  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_12_WIDTH },
21709  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_13_CHECKER_TYPE,
21710  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_13_WIDTH },
21711  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_14_CHECKER_TYPE,
21712  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_14_WIDTH },
21713  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_15_CHECKER_TYPE,
21714  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_15_WIDTH },
21715  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_16_CHECKER_TYPE,
21716  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_16_WIDTH },
21717  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_17_CHECKER_TYPE,
21718  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_17_WIDTH },
21719  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_18_CHECKER_TYPE,
21720  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_18_WIDTH },
21721  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_19_CHECKER_TYPE,
21722  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_19_WIDTH },
21723  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_20_CHECKER_TYPE,
21724  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_20_WIDTH },
21725  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_21_CHECKER_TYPE,
21726  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_21_WIDTH },
21727  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_22_CHECKER_TYPE,
21728  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_22_WIDTH },
21729  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_23_CHECKER_TYPE,
21730  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_23_WIDTH },
21731  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_24_CHECKER_TYPE,
21732  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_24_WIDTH },
21733  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_25_CHECKER_TYPE,
21734  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_25_WIDTH },
21735  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_26_CHECKER_TYPE,
21736  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_26_WIDTH },
21737  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_27_CHECKER_TYPE,
21738  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_27_WIDTH },
21739  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_28_CHECKER_TYPE,
21740  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_28_WIDTH },
21741  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_29_CHECKER_TYPE,
21742  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_29_WIDTH },
21743  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_30_CHECKER_TYPE,
21744  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_30_WIDTH },
21745  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_31_CHECKER_TYPE,
21746  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_31_WIDTH },
21747  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_32_CHECKER_TYPE,
21748  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_32_WIDTH },
21749  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_33_CHECKER_TYPE,
21750  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_33_WIDTH },
21751  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_34_CHECKER_TYPE,
21752  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_34_WIDTH },
21753  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_35_CHECKER_TYPE,
21754  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_35_WIDTH },
21755  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_36_CHECKER_TYPE,
21756  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_36_WIDTH },
21757  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_37_CHECKER_TYPE,
21758  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_37_WIDTH },
21759  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_38_CHECKER_TYPE,
21760  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_38_WIDTH },
21761  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_39_CHECKER_TYPE,
21762  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_39_WIDTH },
21763  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_40_CHECKER_TYPE,
21764  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_40_WIDTH },
21765  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_41_CHECKER_TYPE,
21766  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_41_WIDTH },
21767  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_42_CHECKER_TYPE,
21768  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_42_WIDTH },
21769  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_43_CHECKER_TYPE,
21770  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_43_WIDTH },
21771  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_44_CHECKER_TYPE,
21772  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_44_WIDTH },
21773  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_45_CHECKER_TYPE,
21774  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_45_WIDTH },
21775  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_46_CHECKER_TYPE,
21776  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_46_WIDTH },
21777  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_47_CHECKER_TYPE,
21778  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_47_WIDTH },
21779  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_48_CHECKER_TYPE,
21780  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_48_WIDTH },
21781  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_49_CHECKER_TYPE,
21782  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_49_WIDTH },
21783  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_50_CHECKER_TYPE,
21784  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_50_WIDTH },
21785  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_51_CHECKER_TYPE,
21786  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_51_WIDTH },
21787  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_52_CHECKER_TYPE,
21788  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_52_WIDTH },
21789  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_53_CHECKER_TYPE,
21790  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_53_WIDTH },
21791  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_54_CHECKER_TYPE,
21792  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_54_WIDTH },
21793  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_55_CHECKER_TYPE,
21794  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_55_WIDTH },
21795  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_56_CHECKER_TYPE,
21796  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_56_WIDTH },
21797  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_57_CHECKER_TYPE,
21798  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_57_WIDTH },
21799  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_58_CHECKER_TYPE,
21800  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_58_WIDTH },
21801  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_59_CHECKER_TYPE,
21802  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_59_WIDTH },
21803  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_60_CHECKER_TYPE,
21804  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_60_WIDTH },
21805  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_61_CHECKER_TYPE,
21806  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_61_WIDTH },
21807 };
21808 
21814 static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
21815 {
21816  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
21817  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_0_WIDTH },
21818  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
21819  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_1_WIDTH },
21820  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
21821  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_2_WIDTH },
21822  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
21823  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_3_WIDTH },
21824  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
21825  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_4_WIDTH },
21826  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
21827  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_5_WIDTH },
21828  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
21829  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_6_WIDTH },
21830  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
21831  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_7_WIDTH },
21832  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
21833  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_8_WIDTH },
21834  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
21835  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_9_WIDTH },
21836  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
21837  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_10_WIDTH },
21838  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
21839  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_11_WIDTH },
21840  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
21841  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_GROUP_12_WIDTH },
21842 };
21843 
21849 static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
21850 {
21851  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
21852  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_0_WIDTH },
21853  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
21854  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_1_WIDTH },
21855  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
21856  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_2_WIDTH },
21857  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
21858  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_3_WIDTH },
21859  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
21860  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_4_WIDTH },
21861  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
21862  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_5_WIDTH },
21863  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
21864  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_6_WIDTH },
21865  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
21866  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_7_WIDTH },
21867  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
21868  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_8_WIDTH },
21869  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
21870  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_9_WIDTH },
21871  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
21872  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_10_WIDTH },
21873  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
21874  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_11_WIDTH },
21875  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
21876  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_GROUP_12_WIDTH },
21877 };
21878 
21884 static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_MAX_NUM_CHECKERS] =
21885 {
21886  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_0_CHECKER_TYPE,
21887  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_0_WIDTH },
21888  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_1_CHECKER_TYPE,
21889  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_1_WIDTH },
21890  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_2_CHECKER_TYPE,
21891  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_2_WIDTH },
21892  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_3_CHECKER_TYPE,
21893  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_3_WIDTH },
21894  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_4_CHECKER_TYPE,
21895  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_4_WIDTH },
21896  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_5_CHECKER_TYPE,
21897  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_5_WIDTH },
21898  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_6_CHECKER_TYPE,
21899  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_6_WIDTH },
21900  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_7_CHECKER_TYPE,
21901  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_7_WIDTH },
21902  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_8_CHECKER_TYPE,
21903  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_8_WIDTH },
21904  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_9_CHECKER_TYPE,
21905  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_9_WIDTH },
21906  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_10_CHECKER_TYPE,
21907  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_10_WIDTH },
21908  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_11_CHECKER_TYPE,
21909  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_11_WIDTH },
21910  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_12_CHECKER_TYPE,
21911  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_12_WIDTH },
21912  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_13_CHECKER_TYPE,
21913  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_13_WIDTH },
21914  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_14_CHECKER_TYPE,
21915  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_14_WIDTH },
21916  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_15_CHECKER_TYPE,
21917  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_15_WIDTH },
21918  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_16_CHECKER_TYPE,
21919  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_16_WIDTH },
21920  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_17_CHECKER_TYPE,
21921  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_17_WIDTH },
21922  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_18_CHECKER_TYPE,
21923  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_18_WIDTH },
21924  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_19_CHECKER_TYPE,
21925  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_19_WIDTH },
21926  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_20_CHECKER_TYPE,
21927  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_20_WIDTH },
21928  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_21_CHECKER_TYPE,
21929  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_21_WIDTH },
21930  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_22_CHECKER_TYPE,
21931  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_22_WIDTH },
21932  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_23_CHECKER_TYPE,
21933  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_23_WIDTH },
21934  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_24_CHECKER_TYPE,
21935  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_24_WIDTH },
21936  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_25_CHECKER_TYPE,
21937  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_25_WIDTH },
21938 };
21939 
21945 static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_MAX_NUM_CHECKERS] =
21946 {
21947  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_0_CHECKER_TYPE,
21948  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_0_WIDTH },
21949  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_1_CHECKER_TYPE,
21950  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_1_WIDTH },
21951  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_2_CHECKER_TYPE,
21952  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_2_WIDTH },
21953  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_3_CHECKER_TYPE,
21954  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_3_WIDTH },
21955  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_4_CHECKER_TYPE,
21956  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_4_WIDTH },
21957  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_5_CHECKER_TYPE,
21958  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_5_WIDTH },
21959  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_6_CHECKER_TYPE,
21960  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_6_WIDTH },
21961  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_7_CHECKER_TYPE,
21962  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_7_WIDTH },
21963  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_8_CHECKER_TYPE,
21964  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_8_WIDTH },
21965  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_9_CHECKER_TYPE,
21966  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_9_WIDTH },
21967  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_10_CHECKER_TYPE,
21968  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_10_WIDTH },
21969  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_11_CHECKER_TYPE,
21970  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_11_WIDTH },
21971  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_12_CHECKER_TYPE,
21972  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_12_WIDTH },
21973  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_13_CHECKER_TYPE,
21974  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_13_WIDTH },
21975  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_14_CHECKER_TYPE,
21976  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_14_WIDTH },
21977 };
21978 
21984 static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
21985 {
21986  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
21987  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
21988  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
21989  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
21990  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
21991  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
21992  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
21993  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
21994  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
21995  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
21996  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
21997  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
21998  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
21999  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
22000  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
22001  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
22002  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
22003  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
22004  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
22005  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
22006  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
22007  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
22008  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
22009  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
22010  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
22011  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
22012  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
22013  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
22014  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
22015  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
22016 };
22017 
22023 static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
22024 {
22025  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
22026  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
22027  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
22028  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
22029  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
22030  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
22031  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
22032  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
22033 };
22034 
22040 static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
22041 {
22042  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
22043  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
22044  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
22045  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
22046  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
22047  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
22048  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
22049  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
22050  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
22051  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
22052  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
22053  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
22054  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
22055  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
22056  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
22057  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
22058  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
22059  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
22060  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
22061  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
22062  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
22063  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
22064  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
22065  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
22066  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
22067  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
22068  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
22069  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
22070  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
22071  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
22072 };
22073 
22079 static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_MAX_NUM_CHECKERS] =
22080 {
22081  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_GROUP_0_CHECKER_TYPE,
22082  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_GROUP_0_WIDTH },
22083  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_GROUP_1_CHECKER_TYPE,
22084  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_GROUP_1_WIDTH },
22085  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_GROUP_2_CHECKER_TYPE,
22086  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_GROUP_2_WIDTH },
22087  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_GROUP_3_CHECKER_TYPE,
22088  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_GROUP_3_WIDTH },
22089 };
22090 
22096 static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_MAX_NUM_CHECKERS] =
22097 {
22098  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
22099  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_0_WIDTH },
22100  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
22101  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_1_WIDTH },
22102  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
22103  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_2_WIDTH },
22104  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
22105  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_3_WIDTH },
22106  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
22107  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_4_WIDTH },
22108  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
22109  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_5_WIDTH },
22110  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
22111  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_6_WIDTH },
22112  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
22113  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_7_WIDTH },
22114  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
22115  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_8_WIDTH },
22116  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
22117  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_9_WIDTH },
22118  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
22119  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_10_WIDTH },
22120  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
22121  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_11_WIDTH },
22122  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
22123  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_12_WIDTH },
22124  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
22125  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_13_WIDTH },
22126  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
22127  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_GROUP_14_WIDTH },
22128 };
22129 
22135 static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_MAX_NUM_CHECKERS] =
22136 {
22137  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_GROUP_0_CHECKER_TYPE,
22138  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_GROUP_0_WIDTH },
22139  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_GROUP_1_CHECKER_TYPE,
22140  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_GROUP_1_WIDTH },
22141  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_GROUP_2_CHECKER_TYPE,
22142  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_GROUP_2_WIDTH },
22143  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_GROUP_3_CHECKER_TYPE,
22144  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_GROUP_3_WIDTH },
22145 };
22146 
22152 static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_MAX_NUM_CHECKERS] =
22153 {
22154  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
22155  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_0_WIDTH },
22156  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
22157  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_1_WIDTH },
22158  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
22159  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_2_WIDTH },
22160  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
22161  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_3_WIDTH },
22162  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
22163  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_4_WIDTH },
22164  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
22165  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_5_WIDTH },
22166  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
22167  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_6_WIDTH },
22168  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
22169  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_7_WIDTH },
22170  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
22171  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_8_WIDTH },
22172  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
22173  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_9_WIDTH },
22174  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
22175  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_10_WIDTH },
22176  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
22177  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_11_WIDTH },
22178  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
22179  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_12_WIDTH },
22180  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
22181  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_13_WIDTH },
22182  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
22183  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_GROUP_14_WIDTH },
22184 };
22189 static const SDL_RAMIdEntry_t SDL_PSCSS0_SAM62A_MAIN_PSC_WRAP_ECC_AGGR_RamIdTable[SDL_PSCSS0_SAM62A_MAIN_PSC_WRAP_ECC_AGGR_NUM_RAMS] =
22190 {
22191  { SDL_PSCSS0_SAM62A_MAIN_PSC_WRAP_ECC_AGGR_AM62A_PSC_CHFW_CBASS_DST_FW_CH_VBUSP_TABLE_RAM_ID,
22192  SDL_PSCSS0_SAM62A_MAIN_PSC_WRAP_ECC_AGGR_AM62A_PSC_CHFW_CBASS_DST_FW_CH_VBUSP_TABLE_INJECT_TYPE,
22193  SDL_PSCSS0_SAM62A_MAIN_PSC_WRAP_ECC_AGGR_AM62A_PSC_CHFW_CBASS_DST_FW_CH_VBUSP_TABLE_ECC_TYPE,
22194  0u,
22195  NULL },
22196 };
22197 
22202 static const SDL_RAMIdEntry_t SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RamIdTable[SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_NUM_RAMS] =
22203 {
22204  { SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_RAM_ID,
22205  SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_INJECT_TYPE,
22206  SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_ECC_TYPE,
22207  0u,
22208  NULL },
22209 };
22210 
22215 static const SDL_RAMIdEntry_t SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_RamIdTable[SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_NUM_RAMS] =
22216 {
22217  { SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_RAM_ID,
22218  SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_INJECT_TYPE,
22219  SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_ECC_TYPE,
22220  0u,
22221  NULL },
22222 };
22223 
22228 static const SDL_RAMIdEntry_t SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_RamIdTable[SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_NUM_RAMS] =
22229 {
22230  { SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_MSRAM2KX256E_MSRAM0_ECC0_RAM_ID,
22231  SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_MSRAM2KX256E_MSRAM0_ECC0_INJECT_TYPE,
22232  SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_MSRAM2KX256E_MSRAM0_ECC0_ECC_TYPE,
22233  0u,
22234  NULL },
22235 };
22236 
22241 static const SDL_RAMIdEntry_t SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_RamIdTable[SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_NUM_RAMS] =
22242 {
22243  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_RAM_ID,
22244  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_INJECT_TYPE,
22245  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_ECC_TYPE,
22246  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
22247  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_groupEntries },
22248 { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_RAM_ID,
22249  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
22250  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ECC_TYPE,
22251  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
22252  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries },
22253  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_RAM_ID,
22254  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
22255  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ECC_TYPE,
22256  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
22257  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries },
22258  { SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_SAM62A_DM_MCU_ECC_AGGR_EDC_CTRL_RAM_ID,
22259  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_SAM62A_DM_MCU_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
22260  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_SAM62A_DM_MCU_ECC_AGGR_EDC_CTRL_ECC_TYPE,
22261  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_SAM62A_DM_MCU_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
22262  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_SAM62A_DM_MCU_ECC_AGGR_EDC_CTRL_groupEntries },
22263 };
22264 
22269 static const SDL_RAMIdEntry_t SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_RamIdTable[SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_NUM_RAMS] =
22270 {
22271  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_CFG_CONFIG_RAM_ID,
22272  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_CFG_CONFIG_INJECT_TYPE,
22273  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_CFG_CONFIG_ECC_TYPE,
22274  0u,
22275  NULL },
22276  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_CFG_STATE_RAM_ID,
22277  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_CFG_STATE_INJECT_TYPE,
22278  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_CFG_STATE_ECC_TYPE,
22279  0u,
22280  NULL },
22281  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_F0_RAM_ID,
22282  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_F0_INJECT_TYPE,
22283  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_F0_ECC_TYPE,
22284  0u,
22285  NULL },
22286  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_F1_RAM_ID,
22287  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_F1_INJECT_TYPE,
22288  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_F1_ECC_TYPE,
22289  0u,
22290  NULL },
22291  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_WC_RAM_ID,
22292  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_WC_INJECT_TYPE,
22293  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RPCFIFO_WC_ECC_TYPE,
22294  0u,
22295  NULL },
22296  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_STATS_STSR0_RAM_ID,
22297  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_STATS_STSR0_INJECT_TYPE,
22298  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_STATS_STSR0_ECC_TYPE,
22299  0u,
22300  NULL },
22301  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RINGOCC_CNTR_RAM_ID,
22302  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RINGOCC_CNTR_INJECT_TYPE,
22303  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_BCDMA_RINGOCC_CNTR_ECC_TYPE,
22304  0u,
22305  NULL },
22306  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_RAM_ID,
22307  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_INJECT_TYPE,
22308  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_ECC_TYPE,
22309  0u,
22310  NULL },
22311  { SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_INTAGGR_COMMON_IM_TPRAM_153X34_SWW_SR_RAM_ID,
22312  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_INTAGGR_COMMON_IM_TPRAM_153X34_SWW_SR_INJECT_TYPE,
22313  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_DMSS_CSI_AM62A_INTAGGR_COMMON_IM_TPRAM_153X34_SWW_SR_ECC_TYPE,
22314  0u,
22315  NULL },
22316 };
22317 
22322 static const SDL_RAMIdEntry_t SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_RamIdTable[SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_NUM_RAMS] =
22323 {
22324  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_ID,
22325  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_INJECT_TYPE,
22326  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_ECC_TYPE,
22327  0u,
22328  NULL },
22329  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_RAM_ID,
22330  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_INJECT_TYPE,
22331  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_ECC_TYPE,
22332  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS,
22333  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_groupEntries },
22334  { SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_RAM_ID,
22335  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
22336  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_ECC_TYPE,
22337  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
22338  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_groupEntries },
22339 };
22340 
22345 static const SDL_RAMIdEntry_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_RamIdTable[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_NUM_RAMS] =
22346 {
22347  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_RAM_ID,
22348  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_INJECT_TYPE,
22349  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_ECC_TYPE,
22350  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_MAX_NUM_CHECKERS,
22351  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_groupEntries },
22352  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_RAM_ID,
22353  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_INJECT_TYPE,
22354  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_ECC_TYPE,
22355  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_MAX_NUM_CHECKERS,
22356  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_groupEntries },
22357  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_RAM_ID,
22358  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_INJECT_TYPE,
22359  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_ECC_TYPE,
22360  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS,
22361  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_groupEntries },
22362  { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_RAM_ID,
22363  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_INJECT_TYPE,
22364  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_ECC_TYPE,
22365  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
22366  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries },
22367 };
22368 
22373 static const SDL_RAMIdEntry_t SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RamIdTable[SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_NUM_RAMS] =
22374 {
22375  { SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_RAM_ID,
22376  SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_INJECT_TYPE,
22377  SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_ECC_TYPE,
22378  0u,
22379  NULL },
22380 };
22381 
22386 static const SDL_RAMIdEntry_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_RamIdTable[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_NUM_RAMS] =
22387 {
22388  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID,
22389  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_INJECT_TYPE,
22390  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_ECC_TYPE,
22391  0u,
22392  NULL },
22393  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID,
22394  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_INJECT_TYPE,
22395  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_ECC_TYPE,
22396  0u,
22397  NULL },
22398  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID,
22399  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_INJECT_TYPE,
22400  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_ECC_TYPE,
22401  0u,
22402  NULL },
22403  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID,
22404  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_INJECT_TYPE,
22405  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_ECC_TYPE,
22406  0u,
22407  NULL },
22408  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID,
22409  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_INJECT_TYPE,
22410  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_ECC_TYPE,
22411  0u,
22412  NULL },
22413  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID,
22414  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_INJECT_TYPE,
22415  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_ECC_TYPE,
22416  0u,
22417  NULL },
22418  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID,
22419  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_INJECT_TYPE,
22420  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_ECC_TYPE,
22421  0u,
22422  NULL },
22423  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID,
22424  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_INJECT_TYPE,
22425  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_ECC_TYPE,
22426  0u,
22427  NULL },
22428  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID,
22429  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_INJECT_TYPE,
22430  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_ECC_TYPE,
22431  0u,
22432  NULL },
22433  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID,
22434  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_INJECT_TYPE,
22435  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_ECC_TYPE,
22436  0u,
22437  NULL },
22438  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID,
22439  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_INJECT_TYPE,
22440  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_ECC_TYPE,
22441  0u,
22442  NULL },
22443  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID,
22444  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_INJECT_TYPE,
22445  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_ECC_TYPE,
22446  0u,
22447  NULL },
22448  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID,
22449  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_INJECT_TYPE,
22450  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_ECC_TYPE,
22451  0u,
22452  NULL },
22453  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID,
22454  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_INJECT_TYPE,
22455  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_ECC_TYPE,
22456  0u,
22457  NULL },
22458  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID,
22459  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_INJECT_TYPE,
22460  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_ECC_TYPE,
22461  0u,
22462  NULL },
22463  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID,
22464  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_INJECT_TYPE,
22465  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_ECC_TYPE,
22466  0u,
22467  NULL },
22468  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID,
22469  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_INJECT_TYPE,
22470  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_ECC_TYPE,
22471  0u,
22472  NULL },
22473  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID,
22474  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_INJECT_TYPE,
22475  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_ECC_TYPE,
22476  0u,
22477  NULL },
22478  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID,
22479  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_INJECT_TYPE,
22480  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_ECC_TYPE,
22481  0u,
22482  NULL },
22483  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID,
22484  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_INJECT_TYPE,
22485  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_ECC_TYPE,
22486  0u,
22487  NULL },
22488  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID,
22489  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_INJECT_TYPE,
22490  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_ECC_TYPE,
22491  0u,
22492  NULL },
22493  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_ATCM0_BANK0_RAM_ID,
22494  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_ATCM0_BANK0_INJECT_TYPE,
22495  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_ATCM0_BANK0_ECC_TYPE,
22496  0u,
22497  NULL },
22498  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_ATCM0_BANK1_RAM_ID,
22499  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_ATCM0_BANK1_INJECT_TYPE,
22500  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_ATCM0_BANK1_ECC_TYPE,
22501  0u,
22502  NULL },
22503  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B0TCM0_BANK0_RAM_ID,
22504  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B0TCM0_BANK0_INJECT_TYPE,
22505  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B0TCM0_BANK0_ECC_TYPE,
22506  0u,
22507  NULL },
22508  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B0TCM0_BANK1_RAM_ID,
22509  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B0TCM0_BANK1_INJECT_TYPE,
22510  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B0TCM0_BANK1_ECC_TYPE,
22511  0u,
22512  NULL },
22513  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B1TCM0_BANK0_RAM_ID,
22514  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B1TCM0_BANK0_INJECT_TYPE,
22515  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B1TCM0_BANK0_ECC_TYPE,
22516  0u,
22517  NULL },
22518  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B1TCM0_BANK1_RAM_ID,
22519  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B1TCM0_BANK1_INJECT_TYPE,
22520  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_B1TCM0_BANK1_ECC_TYPE,
22521  0u,
22522  NULL },
22523  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID,
22524  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_INJECT_TYPE,
22525  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ECC_TYPE,
22526  0u,
22527  NULL },
22528  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_RAM_ID,
22529  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_INJECT_TYPE,
22530  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_ECC_TYPE,
22531  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_MAX_NUM_CHECKERS,
22532  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_groupEntries },
22533  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_MEM_MST_RAMECC_RAM_ID,
22534  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_MEM_MST_RAMECC_INJECT_TYPE,
22535  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_MEM_MST_RAMECC_ECC_TYPE,
22536  0u,
22537  NULL },
22538  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_RAM_ID,
22539  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_INJECT_TYPE,
22540  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_ECC_TYPE,
22541  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_MAX_NUM_CHECKERS,
22542  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_groupEntries },
22543  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_RAM_ID,
22544  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_INJECT_TYPE,
22545  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_ECC_TYPE,
22546  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_MAX_NUM_CHECKERS,
22547  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_groupEntries },
22548  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_RAM_ID,
22549  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_INJECT_TYPE,
22550  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_ECC_TYPE,
22551  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_MAX_NUM_CHECKERS,
22552  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_groupEntries },
22553  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_RAM_ID,
22554  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
22555  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
22556  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
22557  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_groupEntries },
22558  { SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_RAM_ID,
22559  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
22560  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_ECC_TYPE,
22561  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
22562  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_groupEntries },
22563 };
22564 
22569 static const SDL_RAMIdEntry_t SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_RamIdTable[SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_NUM_RAMS] =
22570 {
22571  { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_ALE_RAM_RAM_ID,
22572  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_ALE_RAM_INJECT_TYPE,
22573  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_ALE_RAM_ECC_TYPE,
22574  0u,
22575  NULL },
22576  { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL1_RAM_ID,
22577  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL1_INJECT_TYPE,
22578  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL1_ECC_TYPE,
22579  0u,
22580  NULL },
22581  { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL2_RAM_ID,
22582  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL2_INJECT_TYPE,
22583  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL2_ECC_TYPE,
22584  0u,
22585  NULL },
22586  { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL3_RAM_ID,
22587  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL3_INJECT_TYPE,
22588  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL3_ECC_TYPE,
22589  0u,
22590  NULL },
22591  { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL4_RAM_ID,
22592  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL4_INJECT_TYPE,
22593  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL4_ECC_TYPE,
22594  0u,
22595  NULL },
22596  { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL5_RAM_ID,
22597  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL5_INJECT_TYPE,
22598  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL5_ECC_TYPE,
22599  0u,
22600  NULL },
22601  { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL6_RAM_ID,
22602  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL6_INJECT_TYPE,
22603  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_CORE_ECC_ECC_CTRL6_ECC_TYPE,
22604  0u,
22605  NULL },
22606  { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_EST_RAM_RAM_ID,
22607  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_EST_RAM_INJECT_TYPE,
22608  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_EST_RAM_ECC_TYPE,
22609  0u,
22610  NULL },
22611 };
22612 
22617 static const SDL_RAMIdEntry_t SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_RamIdTable[SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_NUM_RAMS] =
22618 {
22619  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_ID,
22620  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_INJECT_TYPE,
22621  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_ECC_TYPE,
22622  0u,
22623  NULL },
22624  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_RAM_ID,
22625  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_INJECT_TYPE,
22626  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_ECC_TYPE,
22627  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS,
22628  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_groupEntries },
22629  { SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_RAM_ID,
22630  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
22631  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_ECC_TYPE,
22632  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
22633  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_groupEntries },
22634 };
22635 
22640 static const SDL_RAMIdEntry_t SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_RamIdTable[SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_NUM_RAMS] =
22641 {
22642  { SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ICB_RAMECC_RAM_ID,
22643  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ICB_RAMECC_INJECT_TYPE,
22644  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ICB_RAMECC_ECC_TYPE,
22645  0u,
22646  NULL },
22647  { SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ITE_RAMECC_RAM_ID,
22648  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ITE_RAMECC_INJECT_TYPE,
22649  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_ITE_RAMECC_ECC_TYPE,
22650  0u,
22651  NULL },
22652  { SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_LPI_RAMECC_RAM_ID,
22653  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_LPI_RAMECC_INJECT_TYPE,
22654  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_LPI_RAMECC_ECC_TYPE,
22655  0u,
22656  NULL },
22657 };
22658 
22663 static const SDL_RAMIdEntry_t SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_RamIdTable[SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_NUM_RAMS] =
22664 {
22665  { SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_RAM_ID,
22666  SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_INJECT_TYPE,
22667  SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_ECC_TYPE,
22668  SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
22669  SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries },
22670 };
22671 
22676 static const SDL_RAMIdEntry_t SDL_DMASS0_DMSS_AM62A_ECCAGGR_RamIdTable[SDL_DMASS0_DMSS_AM62A_ECCAGGR_NUM_RAMS] =
22677 {
22678  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_CFG_CONFIG_RAM_ID,
22679  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_CFG_CONFIG_INJECT_TYPE,
22680  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_CFG_CONFIG_ECC_TYPE,
22681  0u,
22682  NULL },
22683  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_CFG_STATE_RAM_ID,
22684  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_CFG_STATE_INJECT_TYPE,
22685  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_CFG_STATE_ECC_TYPE,
22686  0u,
22687  NULL },
22688  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_TPCFIFO_F0_RAM_ID,
22689  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_TPCFIFO_F0_INJECT_TYPE,
22690  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_TPCFIFO_F0_ECC_TYPE,
22691  0u,
22692  NULL },
22693  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_TPCFIFO_F1_RAM_ID,
22694  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_TPCFIFO_F1_INJECT_TYPE,
22695  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_TPCFIFO_F1_ECC_TYPE,
22696  0u,
22697  NULL },
22698  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_RPCFIFO_F0_RAM_ID,
22699  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_RPCFIFO_F0_INJECT_TYPE,
22700  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_RPCFIFO_F0_ECC_TYPE,
22701  0u,
22702  NULL },
22703  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_RPCFIFO_F1_RAM_ID,
22704  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_RPCFIFO_F1_INJECT_TYPE,
22705  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_RPCFIFO_F1_ECC_TYPE,
22706  0u,
22707  NULL },
22708  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_RPCFIFO_WC_RAM_ID,
22709  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_RPCFIFO_WC_INJECT_TYPE,
22710  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_RPCFIFO_WC_ECC_TYPE,
22711  0u,
22712  NULL },
22713  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_STATS_STST0_RAM_ID,
22714  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_STATS_STST0_INJECT_TYPE,
22715  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_STATS_STST0_ECC_TYPE,
22716  0u,
22717  NULL },
22718  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_STATS_STSR0_RAM_ID,
22719  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_STATS_STSR0_INJECT_TYPE,
22720  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_STATS_STSR0_ECC_TYPE,
22721  0u,
22722  NULL },
22723  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_RINGOCC_CNTR_RAM_ID,
22724  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_RINGOCC_CNTR_INJECT_TYPE,
22725  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_PKTDMA_RINGOCC_CNTR_ECC_TYPE,
22726  0u,
22727  NULL },
22728  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_CFG_CONFIG_RAM_ID,
22729  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_CFG_CONFIG_INJECT_TYPE,
22730  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_CFG_CONFIG_ECC_TYPE,
22731  0u,
22732  NULL },
22733  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_CFG_STATE_RAM_ID,
22734  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_CFG_STATE_INJECT_TYPE,
22735  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_CFG_STATE_ECC_TYPE,
22736  0u,
22737  NULL },
22738  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_PCFIFO_DFIFO_F0_RAM_ID,
22739  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_PCFIFO_DFIFO_F0_INJECT_TYPE,
22740  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_PCFIFO_DFIFO_F0_ECC_TYPE,
22741  0u,
22742  NULL },
22743  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_PCFIFO_DFIFO_F1_RAM_ID,
22744  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_PCFIFO_DFIFO_F1_INJECT_TYPE,
22745  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_PCFIFO_DFIFO_F1_ECC_TYPE,
22746  0u,
22747  NULL },
22748  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_TPCFIFO_F0_RAM_ID,
22749  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_TPCFIFO_F0_INJECT_TYPE,
22750  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_TPCFIFO_F0_ECC_TYPE,
22751  0u,
22752  NULL },
22753  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_TPCFIFO_F1_RAM_ID,
22754  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_TPCFIFO_F1_INJECT_TYPE,
22755  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_TPCFIFO_F1_ECC_TYPE,
22756  0u,
22757  NULL },
22758  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_RPCFIFO_F0_RAM_ID,
22759  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_RPCFIFO_F0_INJECT_TYPE,
22760  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_RPCFIFO_F0_ECC_TYPE,
22761  0u,
22762  NULL },
22763  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_RPCFIFO_F1_RAM_ID,
22764  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_RPCFIFO_F1_INJECT_TYPE,
22765  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_RPCFIFO_F1_ECC_TYPE,
22766  0u,
22767  NULL },
22768  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_RPCFIFO_WC_RAM_ID,
22769  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_RPCFIFO_WC_INJECT_TYPE,
22770  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_RPCFIFO_WC_ECC_TYPE,
22771  0u,
22772  NULL },
22773  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_STATS_STST0_RAM_ID,
22774  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_STATS_STST0_INJECT_TYPE,
22775  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_STATS_STST0_ECC_TYPE,
22776  0u,
22777  NULL },
22778  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_STATS_STSR0_RAM_ID,
22779  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_STATS_STSR0_INJECT_TYPE,
22780  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_STATS_STSR0_ECC_TYPE,
22781  0u,
22782  NULL },
22783  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_RINGOCC_CNTR_RAM_ID,
22784  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_RINGOCC_CNTR_INJECT_TYPE,
22785  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_BCDMA_RINGOCC_CNTR_ECC_TYPE,
22786  0u,
22787  NULL },
22788  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_INTAGGR_STATREG_SR_SPRAM_184X128_SWW_SR_RAM_ID,
22789  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_INTAGGR_STATREG_SR_SPRAM_184X128_SWW_SR_INJECT_TYPE,
22790  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_INTAGGR_STATREG_SR_SPRAM_184X128_SWW_SR_ECC_TYPE,
22791  0u,
22792  NULL },
22793  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_INTAGGR_COMMON_IM_TPRAM_1531X34_SWW_SR_RAM_ID,
22794  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_INTAGGR_COMMON_IM_TPRAM_1531X34_SWW_SR_INJECT_TYPE,
22795  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_INTAGGR_COMMON_IM_TPRAM_1531X34_SWW_SR_ECC_TYPE,
22796  0u,
22797  NULL },
22798  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_IPCSS_RINGACC_STRAM_RAM_ID,
22799  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_IPCSS_RINGACC_STRAM_INJECT_TYPE,
22800  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_IPCSS_RINGACC_STRAM_ECC_TYPE,
22801  0u,
22802  NULL },
22803  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_IPCSS_SEC_PROXY_BUF_STRAM_RAM_ID,
22804  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_IPCSS_SEC_PROXY_BUF_STRAM_INJECT_TYPE,
22805  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_IPCSS_SEC_PROXY_BUF_STRAM_ECC_TYPE,
22806  0u,
22807  NULL },
22808  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_IPCSS_SEC_PROXY_BUF_BUFRAM_RAM_ID,
22809  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_IPCSS_SEC_PROXY_BUF_BUFRAM_INJECT_TYPE,
22810  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_IPCSS_SEC_PROXY_BUF_BUFRAM_ECC_TYPE,
22811  0u,
22812  NULL },
22813  { SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_IPCSS_MSRAM_ECC0_RAM_ID,
22814  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_IPCSS_MSRAM_ECC0_INJECT_TYPE,
22815  SDL_DMASS0_DMSS_AM62A_ECCAGGR_DMSS_AM62A_IPCSS_MSRAM_ECC0_ECC_TYPE,
22816  0u,
22817  NULL },
22818 };
22819 
22824 static const SDL_RAMIdEntry_t SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RamIdTable[SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_NUM_RAMS] =
22825 {
22826  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_RAM_ID,
22827  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_INJECT_TYPE,
22828  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_ECC_TYPE,
22829  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_MAX_NUM_CHECKERS,
22830  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_groupEntries },
22831  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_RAM_ID,
22832  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_INJECT_TYPE,
22833  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_ECC_TYPE,
22834  0u,
22835  NULL },
22836  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_RAM_ID,
22837  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_INJECT_TYPE,
22838  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_ECC_TYPE,
22839  0u,
22840  NULL },
22841  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_RAM_ID,
22842  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_INJECT_TYPE,
22843  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_ECC_TYPE,
22844  0u,
22845  NULL },
22846  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_RAM_ID,
22847  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_INJECT_TYPE,
22848  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_ECC_TYPE,
22849  0u,
22850  NULL },
22851  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_RAM_ID,
22852  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_INJECT_TYPE,
22853  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_ECC_TYPE,
22854  0u,
22855  NULL },
22856  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_RAM_ID,
22857  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_INJECT_TYPE,
22858  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_ECC_TYPE,
22859  0u,
22860  NULL },
22861  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_RAM_ID,
22862  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_INJECT_TYPE,
22863  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_ECC_TYPE,
22864  0u,
22865  NULL },
22866 };
22867 
22872 static const SDL_RAMIdEntry_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_NUM_RAMS] =
22873 {
22874  { SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_ID,
22875  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_INJECT_TYPE,
22876  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_ECC_TYPE,
22877  0u,
22878  NULL },
22879 };
22880 
22885 static const SDL_RAMIdEntry_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_NUM_RAMS] =
22886 {
22887  { SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_ID,
22888  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_INJECT_TYPE,
22889  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_ECC_TYPE,
22890  0u,
22891  NULL },
22892 };
22893 
22898 static const SDL_RAMIdEntry_t SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable[SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_NUM_RAMS] =
22899 {
22900  { SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_ID,
22901  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_INJECT_TYPE,
22902  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_ECC_TYPE,
22903  0u,
22904  NULL },
22905 };
22906 
22911 static const SDL_RAMIdEntry_t SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable[SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_NUM_RAMS] =
22912 {
22913  { SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_ID,
22914  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_INJECT_TYPE,
22915  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_ECC_TYPE,
22916  0u,
22917  NULL },
22918 };
22919 
22924 static const SDL_RAMIdEntry_t SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_RamIdTable[SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_NUM_RAMS] =
22925 {
22926  { SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_EMMCSD8SS_SDHC_WRAP_TXMEM_RAM_ID,
22927  SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_EMMCSD8SS_SDHC_WRAP_TXMEM_INJECT_TYPE,
22928  SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_EMMCSD8SS_SDHC_WRAP_TXMEM_ECC_TYPE,
22929  0u,
22930  NULL },
22931 };
22932 
22937 static const SDL_RAMIdEntry_t SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_RamIdTable[SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_NUM_RAMS] =
22938 {
22939  { SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_EMMCSD8SS_SDHC_WRAP_RXMEM_RAM_ID,
22940  SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_EMMCSD8SS_SDHC_WRAP_RXMEM_INJECT_TYPE,
22941  SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_EMMCSD8SS_SDHC_WRAP_RXMEM_ECC_TYPE,
22942  0u,
22943  NULL },
22944 };
22945 
22950 static const SDL_RAMIdEntry_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_RamIdTable[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_NUM_RAMS] =
22951 {
22952  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_RAM_ID,
22953  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_INJECT_TYPE,
22954  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_ECC_TYPE,
22955  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_MAX_NUM_CHECKERS,
22956  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_groupEntries },
22957  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_RAM_ID,
22958  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_INJECT_TYPE,
22959  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_ECC_TYPE,
22960  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_MAX_NUM_CHECKERS,
22961  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_groupEntries },
22962  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_RAM_ID,
22963  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_INJECT_TYPE,
22964  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_ECC_TYPE,
22965  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_MAX_NUM_CHECKERS,
22966  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_groupEntries },
22967  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_RAM_ID,
22968  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_INJECT_TYPE,
22969  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_ECC_TYPE,
22970  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_MAX_NUM_CHECKERS,
22971  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_groupEntries },
22972  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_RAM_ID,
22973  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_INJECT_TYPE,
22974  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_ECC_TYPE,
22975  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_MAX_NUM_CHECKERS,
22976  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_groupEntries },
22977  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_RAM_ID,
22978  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_INJECT_TYPE,
22979  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_ECC_TYPE,
22980  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_MAX_NUM_CHECKERS,
22981  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_groupEntries },
22982  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_DM2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_RAM_ID,
22983  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_DM2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_INJECT_TYPE,
22984  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_DM2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_ECC_TYPE,
22985  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_DM2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_MAX_NUM_CHECKERS,
22986  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_DM2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_groupEntries },
22987  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_RAM_ID,
22988  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_INJECT_TYPE,
22989  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_ECC_TYPE,
22990  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_MAX_NUM_CHECKERS,
22991  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_groupEntries },
22992  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_RD_RAMECC_RAM_ID,
22993  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_RD_RAMECC_INJECT_TYPE,
22994  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_RD_RAMECC_ECC_TYPE,
22995  0u,
22996  NULL },
22997  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_WR_RAMECC_RAM_ID,
22998  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_WR_RAMECC_INJECT_TYPE,
22999  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_WR_RAMECC_ECC_TYPE,
23000  0u,
23001  NULL },
23002  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_RAM_ID,
23003  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_INJECT_TYPE,
23004  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_ECC_TYPE,
23005  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
23006  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries },
23007  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_RAM_ID,
23008  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_INJECT_TYPE,
23009  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_ECC_TYPE,
23010  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
23011  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries },
23012  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_RAM_ID,
23013  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_INJECT_TYPE,
23014  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_ECC_TYPE,
23015  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
23016  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_groupEntries },
23017  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_RAM_ID,
23018  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_INJECT_TYPE,
23019  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_ECC_TYPE,
23020  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
23021  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_groupEntries },
23022  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_RAM_ID,
23023  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_INJECT_TYPE,
23024  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_ECC_TYPE,
23025  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
23026  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_groupEntries },
23027  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_RAM_ID,
23028  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_INJECT_TYPE,
23029  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_ECC_TYPE,
23030  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
23031  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_groupEntries },
23032  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_RAM_ID,
23033  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_INJECT_TYPE,
23034  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_ECC_TYPE,
23035  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
23036  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_groupEntries },
23037  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_RAM_ID,
23038  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_INJECT_TYPE,
23039  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_ECC_TYPE,
23040  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
23041  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_groupEntries },
23042  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_RAM_ID,
23043  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_INJECT_TYPE,
23044  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_ECC_TYPE,
23045  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
23046  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_groupEntries },
23047  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_RAM_ID,
23048  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_INJECT_TYPE,
23049  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_ECC_TYPE,
23050  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_MAX_NUM_CHECKERS,
23051  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_groupEntries },
23052  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_RAM_ID,
23053  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_INJECT_TYPE,
23054  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_ECC_TYPE,
23055  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_MAX_NUM_CHECKERS,
23056  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_groupEntries },
23057  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_RAM_ID,
23058  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_INJECT_TYPE,
23059  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_ECC_TYPE,
23060  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS,
23061  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_groupEntries },
23062  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_RAM_ID,
23063  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_INJECT_TYPE,
23064  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_ECC_TYPE,
23065  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
23066  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_groupEntries },
23067  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_RAM_ID,
23068  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_INJECT_TYPE,
23069  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_ECC_TYPE,
23070  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
23071  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_groupEntries },
23072  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_RAM_ID,
23073  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_INJECT_TYPE,
23074  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_ECC_TYPE,
23075  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
23076  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_groupEntries },
23077  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_RAM_ID,
23078  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_INJECT_TYPE,
23079  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_ECC_TYPE,
23080  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
23081  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_groupEntries },
23082  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_RAM_ID,
23083  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_INJECT_TYPE,
23084  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_ECC_TYPE,
23085  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
23086  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_groupEntries },
23087  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_RAM_ID,
23088  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_INJECT_TYPE,
23089  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_ECC_TYPE,
23090  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
23091  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_groupEntries },
23092  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_RAM_ID,
23093  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_INJECT_TYPE,
23094  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_ECC_TYPE,
23095  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
23096  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_groupEntries },
23097  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_RAM_ID,
23098  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_INJECT_TYPE,
23099  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_ECC_TYPE,
23100  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
23101  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_groupEntries },
23102  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_RAM_ID,
23103  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_INJECT_TYPE,
23104  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_ECC_TYPE,
23105  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
23106  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_groupEntries },
23107  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_RAM_ID,
23108  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_INJECT_TYPE,
23109  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_ECC_TYPE,
23110  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
23111  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_groupEntries },
23112  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_RAM_ID,
23113  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_INJECT_TYPE,
23114  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_ECC_TYPE,
23115  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
23116  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_groupEntries },
23117  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_RAM_ID,
23118  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_INJECT_TYPE,
23119  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_ECC_TYPE,
23120  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
23121  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_groupEntries },
23122  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_RAM_ID,
23123  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_INJECT_TYPE,
23124  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ECC_TYPE,
23125  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23126  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries },
23127  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_RAM_ID,
23128  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_INJECT_TYPE,
23129  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ECC_TYPE,
23130  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23131  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries },
23132  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_RAM_ID,
23133  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
23134  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
23135  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23136  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries },
23137  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_RAM_ID,
23138  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_INJECT_TYPE,
23139  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ECC_TYPE,
23140  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
23141  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries },
23142  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_RAM_ID,
23143  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
23144  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
23145  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23146  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries },
23147  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_RAM_ID,
23148  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_INJECT_TYPE,
23149  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ECC_TYPE,
23150  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
23151  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries },
23152  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_RAM_ID,
23153  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_INJECT_TYPE,
23154  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_ECC_TYPE,
23155  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
23156  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_groupEntries },
23157  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_RAM_ID,
23158  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_INJECT_TYPE,
23159  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_ECC_TYPE,
23160  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
23161  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_groupEntries },
23162  { SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_SAM62A_MCU_MCU_ECC_AGGR_EDC_CTRL_RAM_ID,
23163  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_SAM62A_MCU_MCU_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
23164  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_SAM62A_MCU_MCU_ECC_AGGR_EDC_CTRL_ECC_TYPE,
23165  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_SAM62A_MCU_MCU_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
23166  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_SAM62A_MCU_MCU_ECC_AGGR_EDC_CTRL_groupEntries },
23167 };
23168 
23173 static const SDL_RAMIdEntry_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_RamIdTable[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_NUM_RAMS] =
23174 {
23175  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_RAM_ID,
23176  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_INJECT_TYPE,
23177  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_ECC_TYPE,
23178  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_MAX_NUM_CHECKERS,
23179  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_groupEntries },
23180  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_CONFIG_RAM_ID,
23181  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_CONFIG_INJECT_TYPE,
23182  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_CONFIG_ECC_TYPE,
23183  0u,
23184  NULL },
23185  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_STATE_RAM_ID,
23186  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_STATE_INJECT_TYPE,
23187  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_STATE_ECC_TYPE,
23188  0u,
23189  NULL },
23190  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F0_RAM_ID,
23191  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F0_INJECT_TYPE,
23192  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F0_ECC_TYPE,
23193  0u,
23194  NULL },
23195  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F1_RAM_ID,
23196  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F1_INJECT_TYPE,
23197  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F1_ECC_TYPE,
23198  0u,
23199  NULL },
23200  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F0_RAM_ID,
23201  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F0_INJECT_TYPE,
23202  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F0_ECC_TYPE,
23203  0u,
23204  NULL },
23205  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F1_RAM_ID,
23206  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F1_INJECT_TYPE,
23207  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F1_ECC_TYPE,
23208  0u,
23209  NULL },
23210  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_WC_RAM_ID,
23211  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_WC_INJECT_TYPE,
23212  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_WC_ECC_TYPE,
23213  0u,
23214  NULL },
23215  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STST0_RAM_ID,
23216  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STST0_INJECT_TYPE,
23217  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STST0_ECC_TYPE,
23218  0u,
23219  NULL },
23220  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STSR0_RAM_ID,
23221  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STSR0_INJECT_TYPE,
23222  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STSR0_ECC_TYPE,
23223  0u,
23224  NULL },
23225  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RINGOCC_CNTR_RAM_ID,
23226  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RINGOCC_CNTR_INJECT_TYPE,
23227  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RINGOCC_CNTR_ECC_TYPE,
23228  0u,
23229  NULL },
23230  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_RAM_ID,
23231  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_INJECT_TYPE,
23232  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_ECC_TYPE,
23233  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_MAX_NUM_CHECKERS,
23234  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_groupEntries },
23235  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_RAM_ID,
23236  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_INJECT_TYPE,
23237  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_ECC_TYPE,
23238  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_MAX_NUM_CHECKERS,
23239  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_groupEntries },
23240  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_RAM_ID,
23241  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_INJECT_TYPE,
23242  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_ECC_TYPE,
23243  0u,
23244  NULL },
23245  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_COMMON_IM_TPRAM_158X34_SWW_SR_RAM_ID,
23246  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_COMMON_IM_TPRAM_158X34_SWW_SR_INJECT_TYPE,
23247  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_COMMON_IM_TPRAM_158X34_SWW_SR_ECC_TYPE,
23248  0u,
23249  NULL },
23250  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_RAM_ID,
23251  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_INJECT_TYPE,
23252  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_ECC_TYPE,
23253  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_MAX_NUM_CHECKERS,
23254  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_groupEntries },
23255  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_RAM_ID,
23256  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_INJECT_TYPE,
23257  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_ECC_TYPE,
23258  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_MAX_NUM_CHECKERS,
23259  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_groupEntries },
23260  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_STRAM_RAM_ID,
23261  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_STRAM_INJECT_TYPE,
23262  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_STRAM_ECC_TYPE,
23263  0u,
23264  NULL },
23265  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_STRAM_RAM_ID,
23266  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_STRAM_INJECT_TYPE,
23267  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_STRAM_ECC_TYPE,
23268  0u,
23269  NULL },
23270  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_BUFRAM_RAM_ID,
23271  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_BUFRAM_INJECT_TYPE,
23272  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_BUFRAM_ECC_TYPE,
23273  0u,
23274  NULL },
23275  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_RAM_ID,
23276  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_INJECT_TYPE,
23277  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_ECC_TYPE,
23278  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_MAX_NUM_CHECKERS,
23279  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_groupEntries },
23280  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
23281  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
23282  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
23283  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
23284  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
23285  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_RAM_ID,
23286  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_INJECT_TYPE,
23287  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_ECC_TYPE,
23288  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
23289  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries },
23290  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_RAM_ID,
23291  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_INJECT_TYPE,
23292  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_ECC_TYPE,
23293  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS,
23294  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries },
23295  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_ECC0_RAM_ID,
23296  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_ECC0_INJECT_TYPE,
23297  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_ECC0_ECC_TYPE,
23298  0u,
23299  NULL },
23300  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_RAM_ID,
23301  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_INJECT_TYPE,
23302  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_ECC_TYPE,
23303  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_MAX_NUM_CHECKERS,
23304  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_groupEntries },
23305  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_RAM_ID,
23306  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_INJECT_TYPE,
23307  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_ECC_TYPE,
23308  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS,
23309  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_groupEntries },
23310  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_RAM_ID,
23311  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_INJECT_TYPE,
23312  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_ECC_TYPE,
23313  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS,
23314  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_groupEntries },
23315  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_RAM_ID,
23316  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_INJECT_TYPE,
23317  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_ECC_TYPE,
23318  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS,
23319  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries },
23320  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_RAM_ID,
23321  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_INJECT_TYPE,
23322  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_ECC_TYPE,
23323  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS,
23324  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries },
23325  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_RAM_ID,
23326  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_INJECT_TYPE,
23327  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_ECC_TYPE,
23328  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS,
23329  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries },
23330  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_RAM_ID,
23331  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_INJECT_TYPE,
23332  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_ECC_TYPE,
23333  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS,
23334  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries },
23335  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_RAM_ID,
23336  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_INJECT_TYPE,
23337  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_ECC_TYPE,
23338  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS,
23339  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_groupEntries },
23340  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_RAM_ID,
23341  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_INJECT_TYPE,
23342  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_ECC_TYPE,
23343  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_MAX_NUM_CHECKERS,
23344  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_groupEntries },
23345  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_RAM_ID,
23346  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_INJECT_TYPE,
23347  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_ECC_TYPE,
23348  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS,
23349  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_groupEntries },
23350  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_RAM_ID,
23351  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_INJECT_TYPE,
23352  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_ECC_TYPE,
23353  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_MAX_NUM_CHECKERS,
23354  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_groupEntries },
23355  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_RAM_ID,
23356  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_INJECT_TYPE,
23357  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_ECC_TYPE,
23358  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_MAX_NUM_CHECKERS,
23359  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_groupEntries },
23360  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_RAM_ID,
23361  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_INJECT_TYPE,
23362  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_ECC_TYPE,
23363  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_MAX_NUM_CHECKERS,
23364  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_groupEntries },
23365  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_RAM_ID,
23366  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_INJECT_TYPE,
23367  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_ECC_TYPE,
23368  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS,
23369  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_groupEntries },
23370  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_RAM_ID,
23371  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_INJECT_TYPE,
23372  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_ECC_TYPE,
23373  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_MAX_NUM_CHECKERS,
23374  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_groupEntries },
23375  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_RAM_ID,
23376  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_INJECT_TYPE,
23377  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_ECC_TYPE,
23378  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
23379  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_groupEntries },
23380  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_RAM_ID,
23381  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_INJECT_TYPE,
23382  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_ECC_TYPE,
23383  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
23384  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_groupEntries },
23385  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_RAM_ID,
23386  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_INJECT_TYPE,
23387  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_ECC_TYPE,
23388  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
23389  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_groupEntries },
23390  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_RAM_ID,
23391  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_INJECT_TYPE,
23392  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_ECC_TYPE,
23393  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS,
23394  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_groupEntries },
23395  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_RAM_ID,
23396  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_INJECT_TYPE,
23397  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_ECC_TYPE,
23398  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS,
23399  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries },
23400  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_RAM_ID,
23401  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_INJECT_TYPE,
23402  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_ECC_TYPE,
23403  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
23404  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries },
23405  { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_RAM_ID,
23406  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_INJECT_TYPE,
23407  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_ECC_TYPE,
23408  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS,
23409  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries },
23410 };
23411 
23416 static const SDL_RAMIdEntry_t SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_RamIdTable[SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_NUM_RAMS] =
23417 {
23418  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM0_ECC_RAM_ID,
23419  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM0_ECC_INJECT_TYPE,
23420  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM0_ECC_ECC_TYPE,
23421  0u,
23422  NULL },
23423  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM1_ECC_RAM_ID,
23424  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM1_ECC_INJECT_TYPE,
23425  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM1_ECC_ECC_TYPE,
23426  0u,
23427  NULL },
23428  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKA_PROG_RAM_ECC_RAM_ID,
23429  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKA_PROG_RAM_ECC_INJECT_TYPE,
23430  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKA_PROG_RAM_ECC_ECC_TYPE,
23431  0u,
23432  NULL },
23433  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK01_ECC_RAM_ID,
23434  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK01_ECC_INJECT_TYPE,
23435  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK01_ECC_ECC_TYPE,
23436  0u,
23437  NULL },
23438  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK23_ECC_RAM_ID,
23439  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK23_ECC_INJECT_TYPE,
23440  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK23_ECC_ECC_TYPE,
23441  0u,
23442  NULL },
23443  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK4_ECC_RAM_ID,
23444  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK4_ECC_INJECT_TYPE,
23445  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK4_ECC_ECC_TYPE,
23446  0u,
23447  NULL },
23448  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK01_ECC_RAM_ID,
23449  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK01_ECC_INJECT_TYPE,
23450  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK01_ECC_ECC_TYPE,
23451  0u,
23452  NULL },
23453  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK23_ECC_RAM_ID,
23454  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK23_ECC_INJECT_TYPE,
23455  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK23_ECC_ECC_TYPE,
23456  0u,
23457  NULL },
23458  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK45_ECC_RAM_ID,
23459  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK45_ECC_INJECT_TYPE,
23460  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK45_ECC_ECC_TYPE,
23461  0u,
23462  NULL },
23463  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK67_ECC_RAM_ID,
23464  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK67_ECC_INJECT_TYPE,
23465  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK67_ECC_ECC_TYPE,
23466  0u,
23467  NULL },
23468  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK89_ECC_RAM_ID,
23469  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK89_ECC_INJECT_TYPE,
23470  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK89_ECC_ECC_TYPE,
23471  0u,
23472  NULL },
23473  { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK10_ECC_RAM_ID,
23474  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK10_ECC_INJECT_TYPE,
23475  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK10_ECC_ECC_TYPE,
23476  0u,
23477  NULL },
23478 };
23479 
23484 static const SDL_RAMIdEntry_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_RamIdTable[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_NUM_RAMS] =
23485 {
23486  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_RAM_ID,
23487  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_INJECT_TYPE,
23488  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_ECC_TYPE,
23489  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
23490  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries },
23491  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_RAM_ID,
23492  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_INJECT_TYPE,
23493  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_ECC_TYPE,
23494  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
23495  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries },
23496  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_RAM_ID,
23497  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_INJECT_TYPE,
23498  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_ECC_TYPE,
23499  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23500  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_groupEntries },
23501  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_RAM_ID,
23502  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_INJECT_TYPE,
23503  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_ECC_TYPE,
23504  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
23505  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries },
23506  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_RAM_ID,
23507  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_INJECT_TYPE,
23508  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_ECC_TYPE,
23509  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
23510  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries },
23511  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_RAM_ID,
23512  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_INJECT_TYPE,
23513  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_ECC_TYPE,
23514  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS,
23515  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_groupEntries },
23516  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_ISAM62A_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_RAM_ID,
23517  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_ISAM62A_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_INJECT_TYPE,
23518  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_ISAM62A_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_ECC_TYPE,
23519  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_ISAM62A_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_MAX_NUM_CHECKERS,
23520  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_ISAM62A_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_groupEntries },
23521  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_RAM_ID,
23522  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_INJECT_TYPE,
23523  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_ECC_TYPE,
23524  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
23525  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries },
23526  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_RAM_ID,
23527  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_INJECT_TYPE,
23528  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_ECC_TYPE,
23529  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
23530  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_groupEntries },
23531  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_RAM_ID,
23532  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_INJECT_TYPE,
23533  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_ECC_TYPE,
23534  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS,
23535  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_groupEntries },
23536  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_RAM_ID,
23537  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_INJECT_TYPE,
23538  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_ECC_TYPE,
23539  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
23540  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_groupEntries },
23541  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_RAM_ID,
23542  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_INJECT_TYPE,
23543  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_ECC_TYPE,
23544  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
23545  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_groupEntries },
23546  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_RAM_ID,
23547  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_INJECT_TYPE,
23548  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ECC_TYPE,
23549  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23550  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries },
23551  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_RAM_ID,
23552  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
23553  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
23554  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23555  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries },
23556  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_RAM_ID,
23557  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_INJECT_TYPE,
23558  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ECC_TYPE,
23559  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
23560  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries },
23561  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_RAM_ID,
23562  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_INJECT_TYPE,
23563  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_ECC_TYPE,
23564  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
23565  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_groupEntries },
23566  { SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_SAM62A_WKUP_SAFE_ECC_AGGR_EDC_CTRL_RAM_ID,
23567  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_SAM62A_WKUP_SAFE_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
23568  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_SAM62A_WKUP_SAFE_ECC_AGGR_EDC_CTRL_ECC_TYPE,
23569  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_SAM62A_WKUP_SAFE_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
23570  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_SAM62A_WKUP_SAFE_ECC_AGGR_EDC_CTRL_groupEntries },
23571 };
23572 
23577 static const SDL_RAMIdEntry_t SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RamIdTable[SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_NUM_RAMS] =
23578 {
23579  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID,
23580  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_INJECT_TYPE,
23581  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_ECC_TYPE,
23582  0u,
23583  NULL },
23584  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID,
23585  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_INJECT_TYPE,
23586  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_ECC_TYPE,
23587  0u,
23588  NULL },
23589  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID,
23590  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_INJECT_TYPE,
23591  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_ECC_TYPE,
23592  0u,
23593  NULL },
23594  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID,
23595  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_INJECT_TYPE,
23596  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_ECC_TYPE,
23597  0u,
23598  NULL },
23599  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID,
23600  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_INJECT_TYPE,
23601  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_ECC_TYPE,
23602  0u,
23603  NULL },
23604  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID,
23605  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_INJECT_TYPE,
23606  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_ECC_TYPE,
23607  0u,
23608  NULL },
23609  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID,
23610  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_INJECT_TYPE,
23611  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_ECC_TYPE,
23612  0u,
23613  NULL },
23614  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID,
23615  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_INJECT_TYPE,
23616  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_ECC_TYPE,
23617  0u,
23618  NULL },
23619  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID,
23620  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_INJECT_TYPE,
23621  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_ECC_TYPE,
23622  0u,
23623  NULL },
23624  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID,
23625  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_INJECT_TYPE,
23626  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_ECC_TYPE,
23627  0u,
23628  NULL },
23629  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID,
23630  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_INJECT_TYPE,
23631  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_ECC_TYPE,
23632  0u,
23633  NULL },
23634  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID,
23635  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_INJECT_TYPE,
23636  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_ECC_TYPE,
23637  0u,
23638  NULL },
23639  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID,
23640  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_INJECT_TYPE,
23641  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_ECC_TYPE,
23642  0u,
23643  NULL },
23644  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID,
23645  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_INJECT_TYPE,
23646  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_ECC_TYPE,
23647  0u,
23648  NULL },
23649  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID,
23650  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_INJECT_TYPE,
23651  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_ECC_TYPE,
23652  0u,
23653  NULL },
23654  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID,
23655  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_INJECT_TYPE,
23656  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_ECC_TYPE,
23657  0u,
23658  NULL },
23659  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID,
23660  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_INJECT_TYPE,
23661  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_ECC_TYPE,
23662  0u,
23663  NULL },
23664  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID,
23665  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_INJECT_TYPE,
23666  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_ECC_TYPE,
23667  0u,
23668  NULL },
23669  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID,
23670  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_INJECT_TYPE,
23671  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_ECC_TYPE,
23672  0u,
23673  NULL },
23674  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID,
23675  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_INJECT_TYPE,
23676  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_ECC_TYPE,
23677  0u,
23678  NULL },
23679  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID,
23680  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_INJECT_TYPE,
23681  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_ECC_TYPE,
23682  0u,
23683  NULL },
23684  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK0_RAM_ID,
23685  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK0_INJECT_TYPE,
23686  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK0_ECC_TYPE,
23687  0u,
23688  NULL },
23689  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK1_RAM_ID,
23690  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK1_INJECT_TYPE,
23691  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK1_ECC_TYPE,
23692  0u,
23693  NULL },
23694  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK0_RAM_ID,
23695  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK0_INJECT_TYPE,
23696  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK0_ECC_TYPE,
23697  0u,
23698  NULL },
23699  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK1_RAM_ID,
23700  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK1_INJECT_TYPE,
23701  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK1_ECC_TYPE,
23702  0u,
23703  NULL },
23704  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK0_RAM_ID,
23705  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK0_INJECT_TYPE,
23706  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK0_ECC_TYPE,
23707  0u,
23708  NULL },
23709  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK1_RAM_ID,
23710  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK1_INJECT_TYPE,
23711  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK1_ECC_TYPE,
23712  0u,
23713  NULL },
23714  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_PULSAR_KS_VIM_COMMON_CORE0_RAM_RAM_ID,
23715  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_PULSAR_KS_VIM_COMMON_CORE0_RAM_INJECT_TYPE,
23716  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_PULSAR_KS_VIM_COMMON_CORE0_RAM_ECC_TYPE,
23717  0u,
23718  NULL },
23719  { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_MEM_MST0_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID,
23720  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_MEM_MST0_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_INJECT_TYPE,
23721  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_MEM_MST0_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ECC_TYPE,
23722  0u,
23723  NULL },
23724 };
23725 
23730 static const SDL_RAMIdEntry_t SDL_SMS0_SMS_HSM_ECC_RamIdTable[SDL_SMS0_SMS_HSM_ECC_NUM_RAMS] =
23731 {
23732  { SDL_SMS0_SMS_HSM_ECC_ISRAM0_RAMECC_RAM_ID,
23733  SDL_SMS0_SMS_HSM_ECC_ISRAM0_RAMECC_INJECT_TYPE,
23734  SDL_SMS0_SMS_HSM_ECC_ISRAM0_RAMECC_ECC_TYPE,
23735  0u,
23736  NULL },
23737  { SDL_SMS0_SMS_HSM_ECC_ISRAM1_RAMECC_RAM_ID,
23738  SDL_SMS0_SMS_HSM_ECC_ISRAM1_RAMECC_INJECT_TYPE,
23739  SDL_SMS0_SMS_HSM_ECC_ISRAM1_RAMECC_ECC_TYPE,
23740  0u,
23741  NULL },
23742  { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_RAM_ID,
23743  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_INJECT_TYPE,
23744  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_ECC_TYPE,
23745  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_MAX_NUM_CHECKERS,
23746  SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_groupEntries },
23747  { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_RAM_ID,
23748  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_INJECT_TYPE,
23749  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_ECC_TYPE,
23750  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_MAX_NUM_CHECKERS,
23751  SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_groupEntries },
23752  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_RAM_ID,
23753  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_INJECT_TYPE,
23754  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_ECC_TYPE,
23755  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_MAX_NUM_CHECKERS,
23756  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_groupEntries },
23757  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_RAM_ID,
23758  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_INJECT_TYPE,
23759  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_ECC_TYPE,
23760  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
23761  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_groupEntries },
23762  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_RAM_ID,
23763  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
23764  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
23765  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23766  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_groupEntries },
23767  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_RAM_ID,
23768  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_INJECT_TYPE,
23769  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_ECC_TYPE,
23770  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23771  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_groupEntries },
23772  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_RAM_ID,
23773  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_INJECT_TYPE,
23774  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ECC_TYPE,
23775  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23776  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries },
23777  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_RAM_ID,
23778  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
23779  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
23780  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23781  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries },
23782  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_RAM_ID,
23783  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_INJECT_TYPE,
23784  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ECC_TYPE,
23785  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
23786  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries },
23787  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_RAM_ID,
23788  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_INJECT_TYPE,
23789  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_ECC_TYPE,
23790  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23791  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_groupEntries },
23792  { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_RAM_ID,
23793  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_INJECT_TYPE,
23794  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_ECC_TYPE,
23795  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_MAX_NUM_CHECKERS,
23796  SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_groupEntries },
23797 };
23798 
23803 static const SDL_RAMIdEntry_t SDL_SMS0_SMS_TIFS_ECC_RamIdTable[SDL_SMS0_SMS_TIFS_ECC_NUM_RAMS] =
23804 {
23805  { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_RAMECC_RAM_ID,
23806  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_RAMECC_INJECT_TYPE,
23807  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_RAMECC_ECC_TYPE,
23808  0u,
23809  NULL },
23810  { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_RAMECC_RAM_ID,
23811  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_RAMECC_INJECT_TYPE,
23812  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_RAMECC_ECC_TYPE,
23813  0u,
23814  NULL },
23815  { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_RAM_ID,
23816  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_INJECT_TYPE,
23817  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_ECC_TYPE,
23818  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_MAX_NUM_CHECKERS,
23819  SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_groupEntries },
23820  { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_RAM_ID,
23821  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_INJECT_TYPE,
23822  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_ECC_TYPE,
23823  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_MAX_NUM_CHECKERS,
23824  SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_groupEntries },
23825  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_RAM_ID,
23826  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_INJECT_TYPE,
23827  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_ECC_TYPE,
23828  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_MAX_NUM_CHECKERS,
23829  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_groupEntries },
23830  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_RAM_ID,
23831  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_INJECT_TYPE,
23832  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_ECC_TYPE,
23833  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_MAX_NUM_CHECKERS,
23834  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_groupEntries },
23835  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_RAM_ID,
23836  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_INJECT_TYPE,
23837  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_ECC_TYPE,
23838  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_MAX_NUM_CHECKERS,
23839  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_groupEntries },
23840  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_RAM_ID,
23841  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_INJECT_TYPE,
23842  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_ECC_TYPE,
23843  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
23844  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_groupEntries },
23845  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_RAM_ID,
23846  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_INJECT_TYPE,
23847  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_ECC_TYPE,
23848  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
23849  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_groupEntries },
23850  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_RAM_ID,
23851  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_INJECT_TYPE,
23852  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_ECC_TYPE,
23853  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
23854  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_groupEntries },
23855  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_RAM_ID,
23856  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_INJECT_TYPE,
23857  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_ECC_TYPE,
23858  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
23859  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_groupEntries },
23860  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_RAM_ID,
23861  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_INJECT_TYPE,
23862  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_ECC_TYPE,
23863  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23864  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_groupEntries },
23865  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_RAM_ID,
23866  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_INJECT_TYPE,
23867  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ECC_TYPE,
23868  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23869  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries },
23870  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_RAM_ID,
23871  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
23872  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
23873  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23874  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries },
23875  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_RAM_ID,
23876  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_INJECT_TYPE,
23877  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ECC_TYPE,
23878  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
23879  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries },
23880  { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_RAM_ID,
23881  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
23882  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
23883  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23884  SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_groupEntries },
23885  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_RAM_ID,
23886  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_INJECT_TYPE,
23887  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_ECC_TYPE,
23888  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
23889  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_groupEntries },
23890  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_RAM_ID,
23891  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_INJECT_TYPE,
23892  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_ECC_TYPE,
23893  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23894  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_groupEntries },
23895  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_RAM_ID,
23896  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_INJECT_TYPE,
23897  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_ECC_TYPE,
23898  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23899  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_groupEntries },
23900  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_RAM_ID,
23901  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_INJECT_TYPE,
23902  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_ECC_TYPE,
23903  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23904  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_groupEntries },
23905  { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_RAM_ID,
23906  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_INJECT_TYPE,
23907  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_ECC_TYPE,
23908  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_MAX_NUM_CHECKERS,
23909  SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_groupEntries },
23910 };
23911 
23916 static const SDL_RAMIdEntry_t SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_RamIdTable[SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_NUM_RAMS] =
23917 {
23918  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_RESPONSE_BUFFER0_RAM_ID,
23919  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_RESPONSE_BUFFER0_INJECT_TYPE,
23920  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_RESPONSE_BUFFER0_ECC_TYPE,
23921  0u,
23922  NULL },
23923  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_QUEUE_BUFFER0_RAM_ID,
23924  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_QUEUE_BUFFER0_INJECT_TYPE,
23925  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_QUEUE_BUFFER0_ECC_TYPE,
23926  0u,
23927  NULL },
23928  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_QUEUE_BUFFER1_RAM_ID,
23929  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_QUEUE_BUFFER1_INJECT_TYPE,
23930  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_QUEUE_BUFFER1_ECC_TYPE,
23931  0u,
23932  NULL },
23933  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_QUEUE_BUFFER2_RAM_ID,
23934  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_QUEUE_BUFFER2_INJECT_TYPE,
23935  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_QUEUE_BUFFER2_ECC_TYPE,
23936  0u,
23937  NULL },
23938  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_STATE_BUFFER0_RAM_ID,
23939  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_STATE_BUFFER0_INJECT_TYPE,
23940  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_STATE_BUFFER0_ECC_TYPE,
23941  0u,
23942  NULL },
23943  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_RING_MEMORY_RAM_ID,
23944  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_RING_MEMORY_INJECT_TYPE,
23945  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_DRU_R30_UTCL_64CH_WRAP_TPRAM_DRU_RING_MEMORY_ECC_TYPE,
23946  0u,
23947  NULL },
23948 };
23949 
23954 static const SDL_RAMIdEntry_t SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_RamIdTable[SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_NUM_RAMS] =
23955 {
23956  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALY_LUT_B0_MEMECC_RAM_ID,
23957  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALY_LUT_B0_MEMECC_INJECT_TYPE,
23958  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALY_LUT_B0_MEMECC_ECC_TYPE,
23959  0u,
23960  NULL },
23961  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALY_LUT_B1_MEMECC_RAM_ID,
23962  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALY_LUT_B1_MEMECC_INJECT_TYPE,
23963  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALY_LUT_B1_MEMECC_ECC_TYPE,
23964  0u,
23965  NULL },
23966  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALC_LUT_B0_MEMECC_RAM_ID,
23967  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALC_LUT_B0_MEMECC_INJECT_TYPE,
23968  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALC_LUT_B0_MEMECC_ECC_TYPE,
23969  0u,
23970  NULL },
23971  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALC_LUT_B1_MEMECC_RAM_ID,
23972  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALC_LUT_B1_MEMECC_INJECT_TYPE,
23973  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALC_LUT_B1_MEMECC_ECC_TYPE,
23974  0u,
23975  NULL },
23976  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B0_P0_MEMECC_RAM_ID,
23977  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B0_P0_MEMECC_INJECT_TYPE,
23978  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B0_P0_MEMECC_ECC_TYPE,
23979  0u,
23980  NULL },
23981  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B1_P0_MEMECC_RAM_ID,
23982  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B1_P0_MEMECC_INJECT_TYPE,
23983  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B1_P0_MEMECC_ECC_TYPE,
23984  0u,
23985  NULL },
23986  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B2_P0_MEMECC_RAM_ID,
23987  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B2_P0_MEMECC_INJECT_TYPE,
23988  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B2_P0_MEMECC_ECC_TYPE,
23989  0u,
23990  NULL },
23991  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B3_P0_MEMECC_RAM_ID,
23992  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B3_P0_MEMECC_INJECT_TYPE,
23993  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B3_P0_MEMECC_ECC_TYPE,
23994  0u,
23995  NULL },
23996  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B0_P1_MEMECC_RAM_ID,
23997  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B0_P1_MEMECC_INJECT_TYPE,
23998  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B0_P1_MEMECC_ECC_TYPE,
23999  0u,
24000  NULL },
24001  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B1_P1_MEMECC_RAM_ID,
24002  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B1_P1_MEMECC_INJECT_TYPE,
24003  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B1_P1_MEMECC_ECC_TYPE,
24004  0u,
24005  NULL },
24006  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B2_P1_MEMECC_RAM_ID,
24007  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B2_P1_MEMECC_INJECT_TYPE,
24008  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B2_P1_MEMECC_ECC_TYPE,
24009  0u,
24010  NULL },
24011  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B3_P1_MEMECC_RAM_ID,
24012  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B3_P1_MEMECC_INJECT_TYPE,
24013  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B3_P1_MEMECC_ECC_TYPE,
24014  0u,
24015  NULL },
24016 };
24017 
24022 static const SDL_RAMIdEntry_t SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_RamIdTable[SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_NUM_RAMS] =
24023 {
24024  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT1_RAM_INTF_RAM0_RAM_ID,
24025  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT1_RAM_INTF_RAM0_INJECT_TYPE,
24026  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT1_RAM_INTF_RAM0_ECC_TYPE,
24027  0u,
24028  NULL },
24029  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT1_RAM_INTF_RAM1_RAM_ID,
24030  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT1_RAM_INTF_RAM1_INJECT_TYPE,
24031  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT1_RAM_INTF_RAM1_ECC_TYPE,
24032  0u,
24033  NULL },
24034  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT2_RAM_INTF_RAM0_RAM_ID,
24035  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT2_RAM_INTF_RAM0_INJECT_TYPE,
24036  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT2_RAM_INTF_RAM0_ECC_TYPE,
24037  0u,
24038  NULL },
24039  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT2_RAM_INTF_RAM1_RAM_ID,
24040  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT2_RAM_INTF_RAM1_INJECT_TYPE,
24041  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT2_RAM_INTF_RAM1_ECC_TYPE,
24042  0u,
24043  NULL },
24044  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT3_RAM_INTF_RAM0_RAM_ID,
24045  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT3_RAM_INTF_RAM0_INJECT_TYPE,
24046  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT3_RAM_INTF_RAM0_ECC_TYPE,
24047  0u,
24048  NULL },
24049  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT3_RAM_INTF_RAM1_RAM_ID,
24050  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT3_RAM_INTF_RAM1_INJECT_TYPE,
24051  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LUT3_RAM_INTF_RAM1_ECC_TYPE,
24052  0u,
24053  NULL },
24054  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_WDR_LUT_RAM_INTF_RAM0_RAM_ID,
24055  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_WDR_LUT_RAM_INTF_RAM0_INJECT_TYPE,
24056  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_WDR_LUT_RAM_INTF_RAM0_ECC_TYPE,
24057  0u,
24058  NULL },
24059  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_WDR_LUT_RAM_INTF_RAM1_RAM_ID,
24060  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_WDR_LUT_RAM_INTF_RAM1_INJECT_TYPE,
24061  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_WDR_LUT_RAM_INTF_RAM1_ECC_TYPE,
24062  0u,
24063  NULL },
24064  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_DPC_DPC_LUT_RAM_INTF_RAM0_RAM_ID,
24065  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_DPC_DPC_LUT_RAM_INTF_RAM0_INJECT_TYPE,
24066  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_DPC_DPC_LUT_RAM_INTF_RAM0_ECC_TYPE,
24067  0u,
24068  NULL },
24069  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LSC_RAM_INTF_RAM0_RAM_ID,
24070  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LSC_RAM_INTF_RAM0_INJECT_TYPE,
24071  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_LSC_RAM_INTF_RAM0_ECC_TYPE,
24072  0u,
24073  NULL },
24074  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_H3A_LUT_RAM_INTF_RAM0_RAM_ID,
24075  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_H3A_LUT_RAM_INTF_RAM0_INJECT_TYPE,
24076  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_H3A_LUT_RAM_INTF_RAM0_ECC_TYPE,
24077  0u,
24078  NULL },
24079  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_H3A_LUT_RAM_INTF_RAM1_RAM_ID,
24080  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_H3A_LUT_RAM_INTF_RAM1_INJECT_TYPE,
24081  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_H3A_LUT_RAM_INTF_RAM1_ECC_TYPE,
24082  0u,
24083  NULL },
24084  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_DPC_STATS_RAM0_RAM_ID,
24085  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_DPC_STATS_RAM0_INJECT_TYPE,
24086  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_RAWFE_DPC_STATS_RAM0_ECC_TYPE,
24087  0u,
24088  NULL },
24089  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM0_RAMECC_RAM_ID,
24090  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM0_RAMECC_INJECT_TYPE,
24091  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM0_RAMECC_ECC_TYPE,
24092  0u,
24093  NULL },
24094  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM1_RAMECC_RAM_ID,
24095  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM1_RAMECC_INJECT_TYPE,
24096  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM1_RAMECC_ECC_TYPE,
24097  0u,
24098  NULL },
24099  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM2_RAMECC_RAM_ID,
24100  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM2_RAMECC_INJECT_TYPE,
24101  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM2_RAMECC_ECC_TYPE,
24102  0u,
24103  NULL },
24104  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM3_RAMECC_RAM_ID,
24105  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM3_RAMECC_INJECT_TYPE,
24106  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM3_RAMECC_ECC_TYPE,
24107  0u,
24108  NULL },
24109  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM4_RAMECC_RAM_ID,
24110  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM4_RAMECC_INJECT_TYPE,
24111  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM4_RAMECC_ECC_TYPE,
24112  0u,
24113  NULL },
24114  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM5_RAMECC_RAM_ID,
24115  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM5_RAMECC_INJECT_TYPE,
24116  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM5_RAMECC_ECC_TYPE,
24117  0u,
24118  NULL },
24119  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM6_RAMECC_RAM_ID,
24120  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM6_RAMECC_INJECT_TYPE,
24121  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM6_RAMECC_ECC_TYPE,
24122  0u,
24123  NULL },
24124  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM7_RAMECC_RAM_ID,
24125  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM7_RAMECC_INJECT_TYPE,
24126  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM7_RAMECC_ECC_TYPE,
24127  0u,
24128  NULL },
24129  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_HIST_BANK0_MEMECC_RAM_ID,
24130  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_HIST_BANK0_MEMECC_INJECT_TYPE,
24131  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_HIST_BANK0_MEMECC_ECC_TYPE,
24132  0u,
24133  NULL },
24134  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_HIST_BANK1_MEMECC_RAM_ID,
24135  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_HIST_BANK1_MEMECC_INJECT_TYPE,
24136  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_HIST_BANK1_MEMECC_ECC_TYPE,
24137  0u,
24138  NULL },
24139  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX0_BANK0_MEMECC_RAM_ID,
24140  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX0_BANK0_MEMECC_INJECT_TYPE,
24141  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX0_BANK0_MEMECC_ECC_TYPE,
24142  0u,
24143  NULL },
24144  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX0_BANK1_MEMECC_RAM_ID,
24145  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX0_BANK1_MEMECC_INJECT_TYPE,
24146  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX0_BANK1_MEMECC_ECC_TYPE,
24147  0u,
24148  NULL },
24149  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX1_BANK0_MEMECC_RAM_ID,
24150  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX1_BANK0_MEMECC_INJECT_TYPE,
24151  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX1_BANK0_MEMECC_ECC_TYPE,
24152  0u,
24153  NULL },
24154  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX1_BANK1_MEMECC_RAM_ID,
24155  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX1_BANK1_MEMECC_INJECT_TYPE,
24156  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX1_BANK1_MEMECC_ECC_TYPE,
24157  0u,
24158  NULL },
24159  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX2_BANK0_MEMECC_RAM_ID,
24160  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX2_BANK0_MEMECC_INJECT_TYPE,
24161  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX2_BANK0_MEMECC_ECC_TYPE,
24162  0u,
24163  NULL },
24164  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX2_BANK1_MEMECC_RAM_ID,
24165  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX2_BANK1_MEMECC_INJECT_TYPE,
24166  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX2_BANK1_MEMECC_ECC_TYPE,
24167  0u,
24168  NULL },
24169  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_Y8R8_BANK0_MEMECC_RAM_ID,
24170  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_Y8R8_BANK0_MEMECC_INJECT_TYPE,
24171  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_Y8R8_BANK0_MEMECC_ECC_TYPE,
24172  0u,
24173  NULL },
24174  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_Y8R8_BANK1_MEMECC_RAM_ID,
24175  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_Y8R8_BANK1_MEMECC_INJECT_TYPE,
24176  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_Y8R8_BANK1_MEMECC_ECC_TYPE,
24177  0u,
24178  NULL },
24179  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_UV8G8_BANK0_MEMECC_RAM_ID,
24180  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_UV8G8_BANK0_MEMECC_INJECT_TYPE,
24181  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_UV8G8_BANK0_MEMECC_ECC_TYPE,
24182  0u,
24183  NULL },
24184  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_UV8G8_BANK1_MEMECC_RAM_ID,
24185  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_UV8G8_BANK1_MEMECC_INJECT_TYPE,
24186  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_UV8G8_BANK1_MEMECC_ECC_TYPE,
24187  0u,
24188  NULL },
24189  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_S8B8_BANK0_MEMECC_RAM_ID,
24190  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_S8B8_BANK0_MEMECC_INJECT_TYPE,
24191  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_S8B8_BANK0_MEMECC_ECC_TYPE,
24192  0u,
24193  NULL },
24194  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_S8B8_BANK1_MEMECC_RAM_ID,
24195  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_S8B8_BANK1_MEMECC_INJECT_TYPE,
24196  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FLEXCC_MEMWRAP_S8B8_BANK1_MEMECC_ECC_TYPE,
24197  0u,
24198  NULL },
24199  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_LUT_0_RAMECC_RAM_ID,
24200  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_LUT_0_RAMECC_INJECT_TYPE,
24201  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_LUT_0_RAMECC_ECC_TYPE,
24202  0u,
24203  NULL },
24204  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_LUT_1_RAMECC_RAM_ID,
24205  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_LUT_1_RAMECC_INJECT_TYPE,
24206  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_LUT_1_RAMECC_ECC_TYPE,
24207  0u,
24208  NULL },
24209  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_EELUT_0_RAMECC_RAM_ID,
24210  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_EELUT_0_RAMECC_INJECT_TYPE,
24211  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_EELUT_0_RAMECC_ECC_TYPE,
24212  0u,
24213  NULL },
24214  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_EELUT_1_RAMECC_RAM_ID,
24215  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_EELUT_1_RAMECC_INJECT_TYPE,
24216  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_EELUT_1_RAMECC_ECC_TYPE,
24217  0u,
24218  NULL },
24219  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_NSF4V_RAWHIST_MEMWRAP_HIST_LUT_B0_MEMECC_RAM_ID,
24220  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_NSF4V_RAWHIST_MEMWRAP_HIST_LUT_B0_MEMECC_INJECT_TYPE,
24221  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_NSF4V_RAWHIST_MEMWRAP_HIST_LUT_B0_MEMECC_ECC_TYPE,
24222  0u,
24223  NULL },
24224  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_NSF4V_RAWHIST_MEMWRAP_HIST_LUT_B1_MEMECC_RAM_ID,
24225  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_NSF4V_RAWHIST_MEMWRAP_HIST_LUT_B1_MEMECC_INJECT_TYPE,
24226  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_NSF4V_RAWHIST_MEMWRAP_HIST_LUT_B1_MEMECC_ECC_TYPE,
24227  0u,
24228  NULL },
24229  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_NSF4V_RAWHIST_MEMWRAP_HIST_DATA_B0_MEMECC_RAM_ID,
24230  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_NSF4V_RAWHIST_MEMWRAP_HIST_DATA_B0_MEMECC_INJECT_TYPE,
24231  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_NSF4V_RAWHIST_MEMWRAP_HIST_DATA_B0_MEMECC_ECC_TYPE,
24232  0u,
24233  NULL },
24234  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_NSF4V_RAWHIST_MEMWRAP_HIST_DATA_B1_MEMECC_RAM_ID,
24235  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_NSF4V_RAWHIST_MEMWRAP_HIST_DATA_B1_MEMECC_INJECT_TYPE,
24236  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_NSF4V_RAWHIST_MEMWRAP_HIST_DATA_B1_MEMECC_ECC_TYPE,
24237  0u,
24238  NULL },
24239  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT0_0_RAMECC_RAM_ID,
24240  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT0_0_RAMECC_INJECT_TYPE,
24241  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT0_0_RAMECC_ECC_TYPE,
24242  0u,
24243  NULL },
24244  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT0_1_RAMECC_RAM_ID,
24245  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT0_1_RAMECC_INJECT_TYPE,
24246  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT0_1_RAMECC_ECC_TYPE,
24247  0u,
24248  NULL },
24249  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT1_0_RAMECC_RAM_ID,
24250  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT1_0_RAMECC_INJECT_TYPE,
24251  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT1_0_RAMECC_ECC_TYPE,
24252  0u,
24253  NULL },
24254  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT1_1_RAMECC_RAM_ID,
24255  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT1_1_RAMECC_INJECT_TYPE,
24256  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT1_1_RAMECC_ECC_TYPE,
24257  0u,
24258  NULL },
24259  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT2_0_RAMECC_RAM_ID,
24260  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT2_0_RAMECC_INJECT_TYPE,
24261  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT2_0_RAMECC_ECC_TYPE,
24262  0u,
24263  NULL },
24264  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT2_1_RAMECC_RAM_ID,
24265  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT2_1_RAMECC_INJECT_TYPE,
24266  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT2_1_RAMECC_ECC_TYPE,
24267  0u,
24268  NULL },
24269  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT3_0_RAMECC_RAM_ID,
24270  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT3_0_RAMECC_INJECT_TYPE,
24271  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT3_0_RAMECC_ECC_TYPE,
24272  0u,
24273  NULL },
24274  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT3_1_RAMECC_RAM_ID,
24275  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT3_1_RAMECC_INJECT_TYPE,
24276  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_CLUT3_1_RAMECC_ECC_TYPE,
24277  0u,
24278  NULL },
24279  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT0_0_RAMECC_RAM_ID,
24280  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT0_0_RAMECC_INJECT_TYPE,
24281  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT0_0_RAMECC_ECC_TYPE,
24282  0u,
24283  NULL },
24284  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT0_1_RAMECC_RAM_ID,
24285  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT0_1_RAMECC_INJECT_TYPE,
24286  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT0_1_RAMECC_ECC_TYPE,
24287  0u,
24288  NULL },
24289  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT1_0_RAMECC_RAM_ID,
24290  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT1_0_RAMECC_INJECT_TYPE,
24291  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT1_0_RAMECC_ECC_TYPE,
24292  0u,
24293  NULL },
24294  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT1_1_RAMECC_RAM_ID,
24295  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT1_1_RAMECC_INJECT_TYPE,
24296  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT1_1_RAMECC_ECC_TYPE,
24297  0u,
24298  NULL },
24299  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT2_0_RAMECC_RAM_ID,
24300  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT2_0_RAMECC_INJECT_TYPE,
24301  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT2_0_RAMECC_ECC_TYPE,
24302  0u,
24303  NULL },
24304  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT2_1_RAMECC_RAM_ID,
24305  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT2_1_RAMECC_INJECT_TYPE,
24306  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT2_1_RAMECC_ECC_TYPE,
24307  0u,
24308  NULL },
24309  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT3_0_RAMECC_RAM_ID,
24310  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT3_0_RAMECC_INJECT_TYPE,
24311  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT3_0_RAMECC_ECC_TYPE,
24312  0u,
24313  NULL },
24314  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT3_1_RAMECC_RAM_ID,
24315  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT3_1_RAMECC_INJECT_TYPE,
24316  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_FCP_DLUT3_1_RAMECC_ECC_TYPE,
24317  0u,
24318  NULL },
24319  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_CAC_MEMWRAP_MESHLUT_MEMECC_RAM_ID,
24320  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_CAC_MEMWRAP_MESHLUT_MEMECC_INJECT_TYPE,
24321  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_CAC_MEMWRAP_MESHLUT_MEMECC_ECC_TYPE,
24322  0u,
24323  NULL },
24324  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_PCID_MEMWRAP_REMAPLUT_MEMECC_B0_RAM_ID,
24325  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_PCID_MEMWRAP_REMAPLUT_MEMECC_B0_INJECT_TYPE,
24326  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_PCID_MEMWRAP_REMAPLUT_MEMECC_B0_ECC_TYPE,
24327  0u,
24328  NULL },
24329  { SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_PCID_MEMWRAP_REMAPLUT_MEMECC_B1_RAM_ID,
24330  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_PCID_MEMWRAP_REMAPLUT_MEMECC_B1_INJECT_TYPE,
24331  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_VISS_PCID_MEMWRAP_REMAPLUT_MEMECC_B1_ECC_TYPE,
24332  0u,
24333  NULL },
24334 };
24335 
24340 static const SDL_RAMIdEntry_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_RamIdTable[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_NUM_RAMS] =
24341 {
24342  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_RAM_ID,
24343  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_INJECT_TYPE,
24344  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_ECC_TYPE,
24345  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_MAX_NUM_CHECKERS,
24346  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_groupEntries },
24347  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_RAM_ID,
24348  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_INJECT_TYPE,
24349  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_ECC_TYPE,
24350  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_MAX_NUM_CHECKERS,
24351  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_groupEntries },
24352  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_RAM_ID,
24353  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_INJECT_TYPE,
24354  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_ECC_TYPE,
24355  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_MAX_NUM_CHECKERS,
24356  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_groupEntries },
24357  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_RAM_ID,
24358  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_INJECT_TYPE,
24359  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_ECC_TYPE,
24360  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_MAX_NUM_CHECKERS,
24361  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_groupEntries },
24362  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_RAM_ID,
24363  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_INJECT_TYPE,
24364  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_ECC_TYPE,
24365  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_MAX_NUM_CHECKERS,
24366  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_groupEntries },
24367  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_RAM_ID,
24368  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_INJECT_TYPE,
24369  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_ECC_TYPE,
24370  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_MAX_NUM_CHECKERS,
24371  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_groupEntries },
24372  { SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_RAM_ID,
24373  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
24374  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_ECC_TYPE,
24375  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
24376  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_groupEntries },
24377 };
24378 
24383 static const SDL_RAMIdEntry_t SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_RamIdTable[SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_NUM_RAMS] =
24384 {
24385  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_RAM_ID,
24386  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_INJECT_TYPE,
24387  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_ECC_TYPE,
24388  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_MAX_NUM_CHECKERS,
24389  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_groupEntries },
24390  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_RAM_ID,
24391  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_INJECT_TYPE,
24392  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_ECC_TYPE,
24393  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_MAX_NUM_CHECKERS,
24394  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_groupEntries },
24395  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_RAM_ID,
24396  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_INJECT_TYPE,
24397  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_ECC_TYPE,
24398  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_MAX_NUM_CHECKERS,
24399  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_groupEntries },
24400  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_RAM_ID,
24401  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_INJECT_TYPE,
24402  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_ECC_TYPE,
24403  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS,
24404  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_groupEntries },
24405  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_RAM_ID,
24406  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_INJECT_TYPE,
24407  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_ECC_TYPE,
24408  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS,
24409  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_groupEntries },
24410  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_RAM_ID,
24411  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_INJECT_TYPE,
24412  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_ECC_TYPE,
24413  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_MAX_NUM_CHECKERS,
24414  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_groupEntries },
24415  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_SAM62A_C7XV_CLEC_CLEC_SRAM_RAM_ID,
24416  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_SAM62A_C7XV_CLEC_CLEC_SRAM_INJECT_TYPE,
24417  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_SAM62A_C7XV_CLEC_CLEC_SRAM_ECC_TYPE,
24418  0u,
24419  NULL },
24420  { SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_RAM_ID,
24421  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_INJECT_TYPE,
24422  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_ECC_TYPE,
24423  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_MAX_NUM_CHECKERS,
24424  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_groupEntries },
24425 };
24426 
24431 static const SDL_RAMIdEntry_t SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RamIdTable[SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_NUM_RAMS] =
24432 {
24433  { SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID,
24434  SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_INJECT_TYPE,
24435  SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ECC_TYPE,
24436  0u,
24437  NULL },
24438  { SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_RAM_ID,
24439  SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_INJECT_TYPE,
24440  SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_ECC_TYPE,
24441  0u,
24442  NULL },
24443 };
24444 
24449 static const SDL_RAMIdEntry_t SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RamIdTable[SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_NUM_RAMS] =
24450 {
24451  { SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID,
24452  SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_INJECT_TYPE,
24453  SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ECC_TYPE,
24454  0u,
24455  NULL },
24456  { SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_RAM_ID,
24457  SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_INJECT_TYPE,
24458  SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_ECC_TYPE,
24459  0u,
24460  NULL },
24461 };
24462 
24467 static const SDL_RAMIdEntry_t SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_RamIdTable[SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_NUM_RAMS] =
24468 {
24469  { SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_PSRAM8KX32E_PSRAM0_ECC_RAM_ID,
24470  SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_PSRAM8KX32E_PSRAM0_ECC_INJECT_TYPE,
24471  SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_PSRAM8KX32E_PSRAM0_ECC_ECC_TYPE,
24472  0u,
24473  NULL },
24474 };
24475 
24480 static const SDL_RAMIdEntry_t SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_RamIdTable[SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_NUM_RAMS] =
24481 {
24482  { SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_TF0_F0_TPRAM_60X128_SBW_SR_RAM_ID,
24483  SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_TF0_F0_TPRAM_60X128_SBW_SR_INJECT_TYPE,
24484  SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_TF0_F0_TPRAM_60X128_SBW_SR_ECC_TYPE,
24485  0u,
24486  NULL },
24487  { SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_TF0_F1_TPRAM_60X128_SBW_SR_RAM_ID,
24488  SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_TF0_F1_TPRAM_60X128_SBW_SR_INJECT_TYPE,
24489  SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_TF0_F1_TPRAM_60X128_SBW_SR_ECC_TYPE,
24490  0u,
24491  NULL },
24492  { SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_RF0_F0_TPRAM_60X144_SBW_SR_RAM_ID,
24493  SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_RF0_F0_TPRAM_60X144_SBW_SR_INJECT_TYPE,
24494  SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_RF0_F0_TPRAM_60X144_SBW_SR_ECC_TYPE,
24495  0u,
24496  NULL },
24497  { SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_RF0_F1_TPRAM_60X144_SBW_SR_RAM_ID,
24498  SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_RF0_F1_TPRAM_60X144_SBW_SR_INJECT_TYPE,
24499  SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_SAM62_PDMA_SPI_PDMA_CORE_RF0_F1_TPRAM_60X144_SBW_SR_ECC_TYPE,
24500  0u,
24501  NULL },
24502 };
24503 
24508 static const SDL_RAMIdEntry_t SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_RamIdTable[SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_NUM_RAMS] =
24509 {
24510  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_RAM_ID,
24511  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_INJECT_TYPE,
24512  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_ECC_TYPE,
24513  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_MAX_NUM_CHECKERS,
24514  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_groupEntries },
24515  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_RAM_ID,
24516  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_INJECT_TYPE,
24517  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_ECC_TYPE,
24518  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_MAX_NUM_CHECKERS,
24519  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_groupEntries },
24520  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_RAM_ID,
24521  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_INJECT_TYPE,
24522  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_ECC_TYPE,
24523  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
24524  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_groupEntries },
24525  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_RAM_ID,
24526  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
24527  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ECC_TYPE,
24528  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
24529  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries },
24530  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
24531  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
24532  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
24533  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
24534  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
24535  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_RAM_ID,
24536  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_INJECT_TYPE,
24537  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_ECC_TYPE,
24538  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
24539  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_groupEntries },
24540  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_RAM_ID,
24541  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_INJECT_TYPE,
24542  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_ECC_TYPE,
24543  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
24544  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_groupEntries },
24545  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_RAM_ID,
24546  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_INJECT_TYPE,
24547  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_ECC_TYPE,
24548  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
24549  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_groupEntries },
24550  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
24551  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
24552  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
24553  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
24554  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
24555  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
24556  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
24557  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
24558  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
24559  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
24560  { SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_SAM62A_DM_DM_ECC_AGGR_EDC_CTRL_RAM_ID,
24561  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_SAM62A_DM_DM_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
24562  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_SAM62A_DM_DM_ECC_AGGR_EDC_CTRL_ECC_TYPE,
24563  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_SAM62A_DM_DM_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
24564  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_SAM62A_DM_DM_ECC_AGGR_EDC_CTRL_groupEntries },
24565 };
24566 
24571 static const SDL_RAMIdEntry_t SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RamIdTable[SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_NUM_RAMS] =
24572 {
24573  { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F0_TPRAM_28X128_SBW_SR_RAM_ID,
24574  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F0_TPRAM_28X128_SBW_SR_INJECT_TYPE,
24575  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F0_TPRAM_28X128_SBW_SR_ECC_TYPE,
24576  0u,
24577  NULL },
24578  { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F1_TPRAM_28X128_SBW_SR_RAM_ID,
24579  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F1_TPRAM_28X128_SBW_SR_INJECT_TYPE,
24580  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F1_TPRAM_28X128_SBW_SR_ECC_TYPE,
24581  0u,
24582  NULL },
24583  { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F0_TPRAM_28X144_SBW_SR_RAM_ID,
24584  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F0_TPRAM_28X144_SBW_SR_INJECT_TYPE,
24585  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F0_TPRAM_28X144_SBW_SR_ECC_TYPE,
24586  0u,
24587  NULL },
24588  { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F1_TPRAM_28X144_SBW_SR_RAM_ID,
24589  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F1_TPRAM_28X144_SBW_SR_INJECT_TYPE,
24590  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F1_TPRAM_28X144_SBW_SR_ECC_TYPE,
24591  0u,
24592  NULL },
24593 };
24594 
24599 static const SDL_RAMIdEntry_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] =
24600 {
24601  { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
24602  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
24603  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
24604  0u,
24605  NULL },
24606  { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
24607  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
24608  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
24609  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
24610  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
24611 };
24612 
24617 static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RamIdTable[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_NUM_RAMS] =
24618 {
24619  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_ID,
24620  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_INJECT_TYPE,
24621  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ECC_TYPE,
24622  0u,
24623  NULL },
24624  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_ID,
24625  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_INJECT_TYPE,
24626  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ECC_TYPE,
24627  0u,
24628  NULL },
24629  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_ID,
24630  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_INJECT_TYPE,
24631  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ECC_TYPE,
24632  0u,
24633  NULL },
24634  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_ID,
24635  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_INJECT_TYPE,
24636  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ECC_TYPE,
24637  0u,
24638  NULL },
24639  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_ID,
24640  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_INJECT_TYPE,
24641  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ECC_TYPE,
24642  0u,
24643  NULL },
24644  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_ID,
24645  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_INJECT_TYPE,
24646  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ECC_TYPE,
24647  0u,
24648  NULL },
24649  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
24650  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
24651  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
24652  0u,
24653  NULL },
24654  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
24655  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
24656  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
24657  0u,
24658  NULL },
24659  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
24660  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
24661  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
24662  0u,
24663  NULL },
24664  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
24665  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
24666  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
24667  0u,
24668  NULL },
24669  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID,
24670  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_INJECT_TYPE,
24671  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ECC_TYPE,
24672  0u,
24673  NULL },
24674  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID,
24675  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_INJECT_TYPE,
24676  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ECC_TYPE,
24677  0u,
24678  NULL },
24679  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_ID,
24680  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_INJECT_TYPE,
24681  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ECC_TYPE,
24682  0u,
24683  NULL },
24684  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_ID,
24685  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_INJECT_TYPE,
24686  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ECC_TYPE,
24687  0u,
24688  NULL },
24689  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
24690  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
24691  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
24692  0u,
24693  NULL },
24694  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
24695  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
24696  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
24697  0u,
24698  NULL },
24699  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
24700  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
24701  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
24702  0u,
24703  NULL },
24704  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
24705  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
24706  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
24707  0u,
24708  NULL },
24709  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_ID,
24710  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_INJECT_TYPE,
24711  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ECC_TYPE,
24712  0u,
24713  NULL },
24714  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
24715  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
24716  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
24717  0u,
24718  NULL },
24719  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
24720  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
24721  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
24722  0u,
24723  NULL },
24724  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
24725  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
24726  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
24727  0u,
24728  NULL },
24729  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
24730  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
24731  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
24732  0u,
24733  NULL },
24734  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID,
24735  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_INJECT_TYPE,
24736  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ECC_TYPE,
24737  0u,
24738  NULL },
24739  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID,
24740  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_INJECT_TYPE,
24741  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ECC_TYPE,
24742  0u,
24743  NULL },
24744  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID,
24745  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_INJECT_TYPE,
24746  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ECC_TYPE,
24747  0u,
24748  NULL },
24749  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID,
24750  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_INJECT_TYPE,
24751  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ECC_TYPE,
24752  0u,
24753  NULL },
24754 };
24755 
24760 static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RamIdTable[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_NUM_RAMS] =
24761 {
24762  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_ID,
24763  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_INJECT_TYPE,
24764  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ECC_TYPE,
24765  0u,
24766  NULL },
24767  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_ID,
24768  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_INJECT_TYPE,
24769  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ECC_TYPE,
24770  0u,
24771  NULL },
24772  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_ID,
24773  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_INJECT_TYPE,
24774  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ECC_TYPE,
24775  0u,
24776  NULL },
24777  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_ID,
24778  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_INJECT_TYPE,
24779  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ECC_TYPE,
24780  0u,
24781  NULL },
24782  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_ID,
24783  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_INJECT_TYPE,
24784  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ECC_TYPE,
24785  0u,
24786  NULL },
24787  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_ID,
24788  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_INJECT_TYPE,
24789  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ECC_TYPE,
24790  0u,
24791  NULL },
24792  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
24793  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
24794  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
24795  0u,
24796  NULL },
24797  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
24798  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
24799  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
24800  0u,
24801  NULL },
24802  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
24803  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
24804  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
24805  0u,
24806  NULL },
24807  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
24808  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
24809  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
24810  0u,
24811  NULL },
24812  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID,
24813  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_INJECT_TYPE,
24814  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ECC_TYPE,
24815  0u,
24816  NULL },
24817  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID,
24818  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_INJECT_TYPE,
24819  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ECC_TYPE,
24820  0u,
24821  NULL },
24822  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_ID,
24823  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_INJECT_TYPE,
24824  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ECC_TYPE,
24825  0u,
24826  NULL },
24827  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_ID,
24828  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_INJECT_TYPE,
24829  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ECC_TYPE,
24830  0u,
24831  NULL },
24832  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
24833  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
24834  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
24835  0u,
24836  NULL },
24837  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
24838  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
24839  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
24840  0u,
24841  NULL },
24842  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
24843  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
24844  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
24845  0u,
24846  NULL },
24847  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
24848  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
24849  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
24850  0u,
24851  NULL },
24852  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_ID,
24853  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_INJECT_TYPE,
24854  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ECC_TYPE,
24855  0u,
24856  NULL },
24857  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
24858  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
24859  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
24860  0u,
24861  NULL },
24862  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
24863  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
24864  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
24865  0u,
24866  NULL },
24867  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
24868  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
24869  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
24870  0u,
24871  NULL },
24872  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
24873  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
24874  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
24875  0u,
24876  NULL },
24877  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID,
24878  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_INJECT_TYPE,
24879  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ECC_TYPE,
24880  0u,
24881  NULL },
24882  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID,
24883  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_INJECT_TYPE,
24884  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ECC_TYPE,
24885  0u,
24886  NULL },
24887  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID,
24888  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_INJECT_TYPE,
24889  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ECC_TYPE,
24890  0u,
24891  NULL },
24892  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID,
24893  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_INJECT_TYPE,
24894  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ECC_TYPE,
24895  0u,
24896  NULL },
24897 };
24898 
24903 static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_RamIdTable[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_NUM_RAMS] =
24904 {
24905  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_ID,
24906  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_INJECT_TYPE,
24907  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ECC_TYPE,
24908  0u,
24909  NULL },
24910  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_ID,
24911  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_INJECT_TYPE,
24912  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ECC_TYPE,
24913  0u,
24914  NULL },
24915  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_ID,
24916  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_INJECT_TYPE,
24917  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ECC_TYPE,
24918  0u,
24919  NULL },
24920  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_ID,
24921  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_INJECT_TYPE,
24922  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ECC_TYPE,
24923  0u,
24924  NULL },
24925  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_ID,
24926  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_INJECT_TYPE,
24927  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ECC_TYPE,
24928  0u,
24929  NULL },
24930  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_ID,
24931  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_INJECT_TYPE,
24932  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ECC_TYPE,
24933  0u,
24934  NULL },
24935  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
24936  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
24937  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
24938  0u,
24939  NULL },
24940  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
24941  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
24942  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
24943  0u,
24944  NULL },
24945  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
24946  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
24947  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
24948  0u,
24949  NULL },
24950  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
24951  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
24952  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
24953  0u,
24954  NULL },
24955  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID,
24956  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_INJECT_TYPE,
24957  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ECC_TYPE,
24958  0u,
24959  NULL },
24960  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID,
24961  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_INJECT_TYPE,
24962  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ECC_TYPE,
24963  0u,
24964  NULL },
24965  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_ID,
24966  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_INJECT_TYPE,
24967  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ECC_TYPE,
24968  0u,
24969  NULL },
24970  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_ID,
24971  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_INJECT_TYPE,
24972  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ECC_TYPE,
24973  0u,
24974  NULL },
24975  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
24976  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
24977  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
24978  0u,
24979  NULL },
24980  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
24981  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
24982  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
24983  0u,
24984  NULL },
24985  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
24986  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
24987  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
24988  0u,
24989  NULL },
24990  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
24991  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
24992  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
24993  0u,
24994  NULL },
24995  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_ID,
24996  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_INJECT_TYPE,
24997  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ECC_TYPE,
24998  0u,
24999  NULL },
25000  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
25001  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
25002  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
25003  0u,
25004  NULL },
25005  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
25006  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
25007  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
25008  0u,
25009  NULL },
25010  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
25011  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
25012  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
25013  0u,
25014  NULL },
25015  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
25016  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
25017  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
25018  0u,
25019  NULL },
25020  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID,
25021  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_INJECT_TYPE,
25022  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ECC_TYPE,
25023  0u,
25024  NULL },
25025  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID,
25026  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_INJECT_TYPE,
25027  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ECC_TYPE,
25028  0u,
25029  NULL },
25030  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID,
25031  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_INJECT_TYPE,
25032  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ECC_TYPE,
25033  0u,
25034  NULL },
25035  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID,
25036  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_INJECT_TYPE,
25037  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ECC_TYPE,
25038  0u,
25039  NULL },
25040 };
25041 
25046 static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_RamIdTable[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_NUM_RAMS] =
25047 {
25048  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_ID,
25049  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_INJECT_TYPE,
25050  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ECC_TYPE,
25051  0u,
25052  NULL },
25053  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_ID,
25054  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_INJECT_TYPE,
25055  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ECC_TYPE,
25056  0u,
25057  NULL },
25058  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_ID,
25059  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_INJECT_TYPE,
25060  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ECC_TYPE,
25061  0u,
25062  NULL },
25063  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_ID,
25064  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_INJECT_TYPE,
25065  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ECC_TYPE,
25066  0u,
25067  NULL },
25068  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_ID,
25069  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_INJECT_TYPE,
25070  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ECC_TYPE,
25071  0u,
25072  NULL },
25073  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_ID,
25074  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_INJECT_TYPE,
25075  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ECC_TYPE,
25076  0u,
25077  NULL },
25078  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
25079  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
25080  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
25081  0u,
25082  NULL },
25083  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
25084  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
25085  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
25086  0u,
25087  NULL },
25088  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
25089  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
25090  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
25091  0u,
25092  NULL },
25093  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
25094  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
25095  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
25096  0u,
25097  NULL },
25098  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID,
25099  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_INJECT_TYPE,
25100  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ECC_TYPE,
25101  0u,
25102  NULL },
25103  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID,
25104  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_INJECT_TYPE,
25105  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ECC_TYPE,
25106  0u,
25107  NULL },
25108  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_ID,
25109  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_INJECT_TYPE,
25110  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ECC_TYPE,
25111  0u,
25112  NULL },
25113  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_ID,
25114  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_INJECT_TYPE,
25115  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ECC_TYPE,
25116  0u,
25117  NULL },
25118  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
25119  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
25120  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
25121  0u,
25122  NULL },
25123  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
25124  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
25125  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
25126  0u,
25127  NULL },
25128  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
25129  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
25130  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
25131  0u,
25132  NULL },
25133  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
25134  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
25135  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
25136  0u,
25137  NULL },
25138  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_ID,
25139  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_INJECT_TYPE,
25140  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ECC_TYPE,
25141  0u,
25142  NULL },
25143  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
25144  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
25145  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
25146  0u,
25147  NULL },
25148  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
25149  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
25150  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
25151  0u,
25152  NULL },
25153  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
25154  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
25155  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
25156  0u,
25157  NULL },
25158  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
25159  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
25160  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
25161  0u,
25162  NULL },
25163  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID,
25164  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_INJECT_TYPE,
25165  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ECC_TYPE,
25166  0u,
25167  NULL },
25168  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID,
25169  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_INJECT_TYPE,
25170  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ECC_TYPE,
25171  0u,
25172  NULL },
25173  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID,
25174  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_INJECT_TYPE,
25175  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ECC_TYPE,
25176  0u,
25177  NULL },
25178  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID,
25179  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_INJECT_TYPE,
25180  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ECC_TYPE,
25181  0u,
25182  NULL },
25183 };
25184 
25189 static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RamIdTable[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_NUM_RAMS] =
25190 {
25191  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID,
25192  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_INJECT_TYPE,
25193  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ECC_TYPE,
25194  0u,
25195  NULL },
25196  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID,
25197  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_INJECT_TYPE,
25198  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ECC_TYPE,
25199  0u,
25200  NULL },
25201  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID,
25202  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_INJECT_TYPE,
25203  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ECC_TYPE,
25204  0u,
25205  NULL },
25206  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID,
25207  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_INJECT_TYPE,
25208  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ECC_TYPE,
25209  0u,
25210  NULL },
25211  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_RAM_ID,
25212  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_INJECT_TYPE,
25213  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_ECC_TYPE,
25214  0u,
25215  NULL },
25216  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_RAM_ID,
25217  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_INJECT_TYPE,
25218  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_ECC_TYPE,
25219  0u,
25220  NULL },
25221  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_RAM_ID,
25222  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_INJECT_TYPE,
25223  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_ECC_TYPE,
25224  0u,
25225  NULL },
25226  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_RAM_ID,
25227  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_INJECT_TYPE,
25228  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_ECC_TYPE,
25229  0u,
25230  NULL },
25231  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_RAM_ID,
25232  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_INJECT_TYPE,
25233  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_ECC_TYPE,
25234  0u,
25235  NULL },
25236  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_RAM_ID,
25237  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_INJECT_TYPE,
25238  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_ECC_TYPE,
25239  0u,
25240  NULL },
25241  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_RAM_ID,
25242  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_INJECT_TYPE,
25243  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_ECC_TYPE,
25244  0u,
25245  NULL },
25246  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_RAM_ID,
25247  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_INJECT_TYPE,
25248  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_ECC_TYPE,
25249  0u,
25250  NULL },
25251  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_RAM_ID,
25252  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_INJECT_TYPE,
25253  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_ECC_TYPE,
25254  0u,
25255  NULL },
25256  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_RAM_ID,
25257  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_INJECT_TYPE,
25258  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_ECC_TYPE,
25259  0u,
25260  NULL },
25261  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_RAM_ID,
25262  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_INJECT_TYPE,
25263  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_ECC_TYPE,
25264  0u,
25265  NULL },
25266  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_RAM_ID,
25267  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_INJECT_TYPE,
25268  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_ECC_TYPE,
25269  0u,
25270  NULL },
25271  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_RAM_ID,
25272  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_INJECT_TYPE,
25273  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_ECC_TYPE,
25274  0u,
25275  NULL },
25276  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_RAM_ID,
25277  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_INJECT_TYPE,
25278  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_ECC_TYPE,
25279  0u,
25280  NULL },
25281  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_RAM_ID,
25282  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_INJECT_TYPE,
25283  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_ECC_TYPE,
25284  0u,
25285  NULL },
25286  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_RAM_ID,
25287  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_INJECT_TYPE,
25288  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_ECC_TYPE,
25289  0u,
25290  NULL },
25291  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_RAM_ID,
25292  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_INJECT_TYPE,
25293  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_ECC_TYPE,
25294  0u,
25295  NULL },
25296  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_RAM_ID,
25297  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_INJECT_TYPE,
25298  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_ECC_TYPE,
25299  0u,
25300  NULL },
25301  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_RAM_ID,
25302  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_INJECT_TYPE,
25303  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_ECC_TYPE,
25304  0u,
25305  NULL },
25306  { SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_RAM_ID,
25307  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_INJECT_TYPE,
25308  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_ECC_TYPE,
25309  0u,
25310  NULL },
25311 };
25312 
25317 static const SDL_RAMIdEntry_t SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] =
25318 {
25319  { SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
25320  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
25321  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
25322  0u,
25323  NULL },
25324  { SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
25325  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
25326  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
25327  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
25328  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
25329 };
25330 
25335 static const SDL_RAMIdEntry_t SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] =
25336 {
25337  { SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
25338  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
25339  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
25340  0u,
25341  NULL },
25342  { SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
25343  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
25344  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
25345  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
25346  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
25347 };
25348 
25353 static const SDL_RAMIdEntry_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_RamIdTable[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_NUM_RAMS] =
25354 {
25355  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_IMAILBOX4_MAIN_0_RAMECC_RAM_ID,
25356  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_IMAILBOX4_MAIN_0_RAMECC_INJECT_TYPE,
25357  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_IMAILBOX4_MAIN_0_RAMECC_ECC_TYPE,
25358  0u,
25359  NULL },
25360  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_RAM_ID,
25361  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_INJECT_TYPE,
25362  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_ECC_TYPE,
25363  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_MAX_NUM_CHECKERS,
25364  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_groupEntries },
25365  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_RAM_ID,
25366  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_INJECT_TYPE,
25367  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_ECC_TYPE,
25368  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
25369  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_groupEntries },
25370  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_RAM_ID,
25371  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_INJECT_TYPE,
25372  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_ECC_TYPE,
25373  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
25374  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_groupEntries },
25375  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_RAM_ID,
25376  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_INJECT_TYPE,
25377  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_ECC_TYPE,
25378  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_MAX_NUM_CHECKERS,
25379  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_groupEntries },
25380  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_RAM_ID,
25381  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_INJECT_TYPE,
25382  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_ECC_TYPE,
25383  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_MAX_NUM_CHECKERS,
25384  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_groupEntries },
25385  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_RAM_ID,
25386  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_INJECT_TYPE,
25387  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_ECC_TYPE,
25388  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
25389  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries },
25390  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_RAM_ID,
25391  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_INJECT_TYPE,
25392  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_ECC_TYPE,
25393  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
25394  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_groupEntries },
25395  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_RAM_ID,
25396  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_INJECT_TYPE,
25397  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_ECC_TYPE,
25398  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
25399  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_groupEntries },
25400  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_RAM_ID,
25401  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_INJECT_TYPE,
25402  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_ECC_TYPE,
25403  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_MAX_NUM_CHECKERS,
25404  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_groupEntries },
25405  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_RAM_ID,
25406  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_INJECT_TYPE,
25407  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_ECC_TYPE,
25408  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_MAX_NUM_CHECKERS,
25409  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_groupEntries },
25410  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_RAM_ID,
25411  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_INJECT_TYPE,
25412  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_ECC_TYPE,
25413  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_MAX_NUM_CHECKERS,
25414  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_groupEntries },
25415  { SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_RAM_ID,
25416  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_INJECT_TYPE,
25417  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_ECC_TYPE,
25418  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_MAX_NUM_CHECKERS,
25419  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_groupEntries },
25420 };
25421 
25422 static SDL_ecc_aggrRegs * const SDL_ECC_aggrBaseAddressTable[SDL_ECC_Base_Address_TOTAL_ENTRIES] =
25423 {
25424  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_WKUP_PSC0_BASE)),
25425  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_PSRAMECC0_ECC_AGGR_BASE)),
25426  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_PSRAMECC1_ECC_AGGR_BASE)),
25427  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MSRAM_64K0_ECC_AGGR_REGS_BASE)),
25428  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_WKUP_ECC_AGGR1_ECC_AGGR_BASE)),
25429  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_DMASS1_ECCAGGR_BASE)),
25430  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_MSRAM_256K1_ECC_AGGR_REGS_BASE)),
25431  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_WKUP_VTM0_ECCAGGR_CFG_BASE)),
25432  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_FSS0_OSPI0_ECC_AGGR_BASE)),
25433  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_R5FSS0_CORE0_ECC_AGGR_BASE)),
25434  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_CPSW0_ECC_BASE)),
25435  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_MSRAM_256K0_ECC_AGGR_REGS_BASE )),
25436  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_GICSS0_REGS_BASE)),
25437  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_ECC_AGGR1_ECC_AGGR_BASE)),
25438  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_DMASS0_ECCAGGR_BASE)),
25439  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_CSI_RX_IF0_ECC_AGGR_CFG_BASE)),
25440  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MMCSD1_ECC_AGGR_RXMEM_BASE)),
25441  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MMCSD1_ECC_AGGR_TXMEM_BASE)),
25442  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MMCSD2_ECC_AGGR_RXMEM_BASE)),
25443  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MMCSD2_ECC_AGGR_TXMEM_BASE )),
25444  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MMCSD0_ECC_AGGR_TXMEM_BASE)),
25445  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MMCSD0_ECC_AGGR_RXMEM_BASE)),
25446  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_ECC_AGGR0_ECC_AGGR_BASE )),
25447  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_CFG_BASE )),
25448  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECCAGGR_CFG_BASE)),
25449  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_WKUP_ECC_AGGR2_ECC_AGGR_BASE )),
25450  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_R5FSS0_CORE0_ECC_AGGR_BASE)),
25451  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_SMS0_HSM_ECC_BASE)),
25452  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_SMS0_TIFS_DMSS_HSM_ECC_BASE)),
25453  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_VPAC0_IVPAC_TOP_0_CFG_SLV_KSDW_ECC_AGGR_CFG_BASE)),
25454  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_VPAC0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_LDC0_S_VBUSP_KSDW_ECC_AGGR_CFG_BASE)),
25455  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_VPAC0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_VISS0_S_VBUSP_KSDW_ECC_AGGR_CFG_BASE)),
25456  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_ECC_AGGR1_ECC_AGGR_BASE)),
25457  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_C7X256V0_ECC_AGGR_BASE)),
25458  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_USB1_ECC_AGGR_BASE )),
25459  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_USB0_ECC_AGGR_BASE)),
25460  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_WKUP_PSRAMECC_8K0_REGS_BASE)),
25461  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_PDMA0_BASE)),
25462  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_WKUP_ECC_AGGR0_ECC_AGGR_BASE)),
25463  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_PDMA1_BASE )),
25464  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCAN0_ECC_AGGR_BASE )),
25465  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_COMPUTE_CLUSTER0_CORE0_ECC_AGGR_BASE)),
25466  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_COMPUTE_CLUSTER0_CORE1_ECC_AGGR_BASE )),
25467  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_COMPUTE_CLUSTER0_CORE2_ECC_AGGR_BASE )),
25468  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_COMPUTE_CLUSTER0_CORE3_ECC_AGGR_BASE)),
25469  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_COMPUTE_CLUSTER0_SS_ECC_AGGR_BASE)),
25470  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_MCAN0_ECC_AGGR_BASE )),
25471  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_MCAN1_ECC_AGGR_BASE )),
25472  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_ECC_AGGR0_ECC_AGGR_BASE)),
25473 };
25474 
25475 SDL_ecc_aggrRegs * SDL_ECC_aggrTransBaseAddressTable[SDL_ECC_MEMTYPE_MAX];
25480 static const SDL_EccAggrEntry_t SDL_ECC_aggrTable[SDL_ECC_MEMTYPE_MAX] =
25481 {
25482 
25483  /* SDL_PSCSS0_SAM62A_MAIN_PSC_WRAP_ECC_AGGR (0) */
25484  {
25485  SDL_PSCSS0_SAM62A_MAIN_PSC_WRAP_ECC_AGGR_NUM_RAMS,
25486  SDL_PSCSS0_SAM62A_MAIN_PSC_WRAP_ECC_AGGR_RamIdTable,
25487  SDL_PSCSS0_SAM62A_MAIN_PSC_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
25488  SDL_PSCSS0_SAM62A_MAIN_PSC_WRAP_ECC_AGGR_MemEntries,
25489  SDL_ESM_INST_MAIN_ESM0,
25490  SDLR_ESM0_ESM_LVL_EVENT_PSC0_ECC_AGGR_0_FW_CH_BR_ECC_AGGR_CORR_LEVEL_0,
25491  SDLR_ESM0_ESM_LVL_EVENT_PSC0_ECC_AGGR_0_FW_CH_BR_ECC_AGGR_UNCORR_LEVEL_0
25492  },
25493  /* Index: SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR (1) */
25494  {
25495  SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_NUM_RAMS,
25496  SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RamIdTable,
25497  SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
25498  SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_MemEntries,
25499  SDL_ESM_INST_MAIN_ESM0,
25500  SDLR_ESM0_ESM_LVL_EVENT_PSRAMECC0_ECC_CORR_LEVEL_0,
25501  SDLR_ESM0_ESM_LVL_EVENT_PSRAMECC0_ECC_UNCORR_LEVEL_0
25502  },
25503  /* Index: SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR (2) */
25504  {
25505  SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_NUM_RAMS,
25506  SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_RamIdTable,
25507  SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
25508  SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_MemEntries,
25509  SDL_ESM_INST_MAIN_ESM0,
25510  SDLR_ESM0_ESM_LVL_EVENT_PSRAMECC1_ECC_CORR_LEVEL_0,
25511  SDLR_ESM0_ESM_LVL_EVENT_PSRAMECC1_ECC_UNCORR_LEVEL_0
25512  },
25513  /* Index: SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR (3u) */
25514  {
25515  SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_NUM_RAMS,
25516  SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_RamIdTable,
25517  SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
25518  SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_MemEntries,
25519  SDL_ESM_INST_MAIN_ESM0,
25520  SDLR_ESM0_ESM_LVL_EVENT_MSRAM_64K0_ECC_CORR_LEVEL_0,
25521  SDLR_ESM0_ESM_LVL_EVENT_MSRAM_64K0_ECC_UNCORR_LEVEL_0
25522  },
25523  /* Index: SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR (4u) */
25524  {
25525  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_NUM_RAMS,
25526  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_RamIdTable,
25527  SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
25528  NULL,
25529  SDL_ESM_INST_MAIN_ESM0,
25530  SDLR_ESM0_ESM_LVL_EVENT_WKUP_ECC_AGGR1_CORR_LEVEL_0,
25531  SDLR_ESM0_ESM_LVL_EVENT_WKUP_ECC_AGGR1_UNCORR_LEVEL_0
25532  },
25533  /* Index: SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR (5u) */
25534  {
25535  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_NUM_RAMS,
25536  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_RamIdTable,
25537  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_RAM_IDS_TOTAL_ENTRIES,
25538  SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_MemEntries,
25539  SDL_ESM_INST_MAIN_ESM0,
25540  SDLR_ESM0_ESM_LVL_EVENT_DMASS1_ECC_AGGR_0_ECC_CORRECTED_ERR_LEVEL_0,
25541  SDLR_ESM0_ESM_LVL_EVENT_DMASS1_ECC_AGGR_0_ECC_UNCORRECTED_ERR_LEVEL_0
25542  },
25543  /* Index: SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR (6u) */
25544  {
25545  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_NUM_RAMS,
25546  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_RamIdTable,
25547  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
25548  SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MemEntries,
25549  SDL_ESM_INST_WKUP_ESM0,
25550  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_MSRAM_256K1_ECC_CORR_LEVEL_0,
25551  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_MSRAM_256K1_ECC_UNCORR_LEVEL_0
25552  },
25553  /*Index: SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR (7u) */
25554  {
25555  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_NUM_RAMS,
25556  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_RamIdTable,
25557  SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_RAM_IDS_TOTAL_ENTRIES,
25558  NULL,
25559  SDL_ESM_INST_MAIN_ESM0,
25560  SDLR_ESM0_ESM_LVL_EVENT_WKUP_VTM0_CORR_LEVEL_0,
25561  SDLR_ESM0_ESM_LVL_EVENT_WKUP_VTM0_UNCORR_LEVEL_0
25562  },
25563  /* Index: SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR (8) */
25564  {
25565  SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_NUM_RAMS,
25566  SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RamIdTable,
25567  SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
25568  SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_MemEntries,
25569  SDL_ESM_INST_MAIN_ESM0,
25570  SDLR_ESM0_ESM_LVL_EVENT_FSS0_OSPI_0_OSPI_ECC_CORR_LVL_INTR_0,
25571  SDLR_ESM0_ESM_LVL_EVENT_FSS0_OSPI_0_OSPI_ECC_UNCORR_LVL_INTR_0
25572  },
25573  /* Index: SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR (9u) */
25574  {
25575  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_NUM_RAMS,
25576  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_RamIdTable,
25577  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
25578  SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_MemEntries,
25579  SDL_ESM_INST_WKUP_ESM0,
25580  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_R5FSS0_CPU0_ECC_AGGR_0_CPU0_ECC_CORRECTED_LEVEL_0,
25581  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_R5FSS0_CPU0_ECC_AGGR_0_CPU0_ECC_UNCORRECTED_LEVEL_0
25582  },
25583  /* Index: SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR (10u) */
25584  {
25585  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_NUM_RAMS,
25586  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_RamIdTable,
25587  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
25588  SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_MemEntries,
25589  SDL_ESM_INST_MAIN_ESM0,
25590  SDLR_ESM0_ESM_LVL_EVENT_CPSW0_ECC_SEC_PEND_0,
25591  SDLR_ESM0_ESM_LVL_EVENT_CPSW0_ECC_DED_PEND_0
25592  },
25593  /* Index: SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR (11u) */
25594  {
25595  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_NUM_RAMS,
25596  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_RamIdTable,
25597  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
25598  SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MemEntries,
25599  SDL_ESM_INST_WKUP_ESM0,
25600  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_MSRAM_256K0_ECC_CORR_LEVEL_0,
25601  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_MSRAM_256K0_ECC_UNCORR_LEVEL_0
25602  },
25603  /* Index: SDL_GICSS0_GIC500SS_1_4_ECC_AGGR (12u) */
25604  {
25605  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_NUM_RAMS,
25606  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_RamIdTable,
25607  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
25608  SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_MemEntries,
25609  SDL_ESM_INST_MAIN_ESM0,
25610  SDLR_ESM0_ESM_LVL_EVENT_GICSS0_ECC_AGGR_CORR_LEVEL_0,
25611  SDLR_ESM0_ESM_LVL_EVENT_GICSS0_ECC_AGGR_UNCORR_LEVEL_0
25612  },
25613  /* Index: SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR (13u) */
25614  {
25615  SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_NUM_RAMS,
25616  SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_RamIdTable,
25617  SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
25618  NULL,
25619  SDL_ESM_INST_MAIN_ESM0,
25620  SDLR_ESM0_ESM_LVL_EVENT_ECC_AGGR1_CORR_LEVEL_0,
25621  SDLR_ESM0_ESM_LVL_EVENT_ECC_AGGR1_UNCORR_LEVEL_0
25622  },
25623  /* Index: SDL_DMASS0_DMSS_AM62A_ECCAGGR (14u) */
25624  {
25625  SDL_DMASS0_DMSS_AM62A_ECCAGGR_NUM_RAMS,
25626  SDL_DMASS0_DMSS_AM62A_ECCAGGR_RamIdTable,
25627  SDL_DMASS0_DMSS_AM62A_ECCAGGR_RAM_IDS_TOTAL_ENTRIES,
25628  SDL_DMASS0_DMSS_AM62A_ECCAGGR_MemEntries,
25629  SDL_ESM_INST_MAIN_ESM0,
25630  SDLR_ESM0_ESM_LVL_EVENT_DMASS0_ECC_AGGR_0_ECC_CORRECTED_ERR_LEVEL_0,
25631  SDLR_ESM0_ESM_LVL_EVENT_DMASS0_ECC_AGGR_0_ECC_UNCORRECTED_ERR_LEVEL_0
25632  },
25633  /* Index: SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR (15u) */
25634  {
25635  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_NUM_RAMS,
25636  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RamIdTable,
25637  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
25638  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_MemEntries,
25639  SDL_ESM_INST_MAIN_ESM0,
25640  SDLR_ESM0_ESM_LVL_EVENT_CSI_RX_IF0_CORR_LEVEL_0,
25641  SDLR_ESM0_ESM_LVL_EVENT_CSI_RX_IF0_UNCORR_LEVEL_0
25642  },
25643  /* Index: SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM (16u) */
25644  {
25645  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_NUM_RAMS,
25646  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable,
25647  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES,
25648  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries,
25649  SDL_ESM_INST_MAIN_ESM0,
25650  SDLR_ESM0_ESM_LVL_EVENT_MMCSD1_EMMCSDSS_RXMEM_CORR_ERR_LVL_0,
25651  SDLR_ESM0_ESM_LVL_EVENT_MMCSD1_EMMCSDSS_RXMEM_UNCORR_ERR_LVL_0
25652  },
25653  /* Index: SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM (17u) */
25654  {
25655  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_NUM_RAMS,
25656  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable,
25657  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES,
25658  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries,
25659  SDL_ESM_INST_MAIN_ESM0,
25660  SDLR_ESM0_ESM_LVL_EVENT_MMCSD1_EMMCSDSS_TXMEM_CORR_ERR_LVL_0,
25661  SDLR_ESM0_ESM_LVL_EVENT_MMCSD1_EMMCSDSS_TXMEM_UNCORR_ERR_LVL_0
25662  },
25663 
25664  /* Index: SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM (18u) */
25665  {
25666  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_NUM_RAMS,
25667  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable,
25668  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES,
25669  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries,
25670  SDL_ESM_INST_MAIN_ESM0,
25671  SDLR_ESM0_ESM_LVL_EVENT_MMCSD2_EMMCSDSS_RXMEM_CORR_ERR_LVL_0,
25672  SDLR_ESM0_ESM_LVL_EVENT_MMCSD2_EMMCSDSS_RXMEM_UNCORR_ERR_LVL_0
25673  },
25674 
25675  /* Index: SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM (19u) */
25676  {
25677  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_NUM_RAMS,
25678  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable,
25679  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES,
25680  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries,
25681  SDL_ESM_INST_MAIN_ESM0,
25682  SDLR_ESM0_ESM_LVL_EVENT_MMCSD2_EMMCSDSS_TXMEM_CORR_ERR_LVL_0,
25683  SDLR_ESM0_ESM_LVL_EVENT_MMCSD2_EMMCSDSS_TXMEM_UNCORR_ERR_LVL_0
25684  },
25685 
25686  /* Index: SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM (20u) */
25687  {
25688  SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_NUM_RAMS,
25689  SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_RamIdTable,
25690  SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES,
25691  SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_MemEntries,
25692  SDL_ESM_INST_MAIN_ESM0,
25693  SDLR_ESM0_ESM_LVL_EVENT_MMCSD0_EMMCSDSS_TXMEM_CORR_ERR_LVL_0,
25694  SDLR_ESM0_ESM_LVL_EVENT_MMCSD0_EMMCSDSS_TXMEM_UNCORR_ERR_LVL_0
25695  },
25696 
25697  /* Index: SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM (21u) */
25698  {
25699  SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_NUM_RAMS,
25700  SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_RamIdTable,
25701  SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES,
25702  SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_MemEntries,
25703  SDL_ESM_INST_MAIN_ESM0,
25704  SDLR_ESM0_ESM_LVL_EVENT_MMCSD0_EMMCSDSS_RXMEM_CORR_ERR_LVL_0,
25705  SDLR_ESM0_ESM_LVL_EVENT_MMCSD0_EMMCSDSS_RXMEM_UNCORR_ERR_LVL_0
25706  },
25707 
25708  /* Index: SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR (22u) */
25709  {
25710  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_NUM_RAMS,
25711  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_RamIdTable,
25712  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
25713  SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_MemEntries,
25714  SDL_ESM_INST_WKUP_ESM0,
25715  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_ECC_AGGR0_CORR_LEVEL_0,
25716  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_ECC_AGGR0_UNCORR_LEVEL_0
25717  },
25718 
25719  /* Index: SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR (23u) */
25720  {
25721  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_NUM_RAMS,
25722  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_RamIdTable,
25723  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_RAM_IDS_TOTAL_ENTRIES,
25724  SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_MemEntries,
25725  SDL_ESM_INST_MAIN_ESM0,
25726  SDLR_ESM0_ESM_LVL_EVENT_SA3_SS0_DMSS_ECCAGGR_0_DMSS_ECC_DED_PEND_0,
25727  SDLR_ESM0_ESM_LVL_EVENT_SA3_SS0_DMSS_ECCAGGR_0_DMSS_ECC_SEC_PEND_0
25728  },
25729  /* Index: SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR (24u) */
25730  {
25731  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_NUM_RAMS,
25732  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_RamIdTable,
25733  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
25734  SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_MemEntries,
25735  SDL_ESM_INST_MAIN_ESM0,
25736  SDLR_ESM0_ESM_LVL_EVENT_SA3_SS0_SA_UL_0_SA_UL_ECC_CORR_LEVEL_0,
25737  SDLR_ESM0_ESM_LVL_EVENT_SA3_SS0_SA_UL_0_SA_UL_ECC_UNCORR_LEVEL_0
25738  },
25739  /* Index: SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR (25u) */
25740  {
25741  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_NUM_RAMS,
25742  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_RamIdTable,
25743  SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
25744  NULL,
25745  SDL_ESM_INST_WKUP_ESM0,
25746  SDLR_WKUP_ESM0_ESM_LVL_EVENT_WKUP_ECC_AGGR2_CORR_LEVEL_0,
25747  SDLR_WKUP_ESM0_ESM_LVL_EVENT_WKUP_ECC_AGGR2_UNCORR_LEVEL_0
25748  },
25749  /* Index: SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR (26u) */
25750  {
25751  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_NUM_RAMS,
25752  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RamIdTable,
25753  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
25754  SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_MemEntries,
25755  SDL_ESM_INST_MAIN_ESM0,
25756  SDLR_ESM0_ESM_LVL_EVENT_WKUP_R5FSS0_CORE0_ECC_CORRECTED_LEVEL_0,
25757  SDLR_ESM0_ESM_LVL_EVENT_WKUP_R5FSS0_CORE0_ECC_UNCORRECTED_LEVEL_0
25758  },
25759  /* Index: SDL_SMS0_SMS_HSM_ECC (27u) */
25760  {
25761  SDL_SMS0_SMS_HSM_ECC_NUM_RAMS,
25762  SDL_SMS0_SMS_HSM_ECC_RamIdTable,
25763  SDL_SMS0_SMS_HSM_ECC_RAM_IDS_TOTAL_ENTRIES,
25764  SDL_SMS0_SMS_HSM_ECC_MemEntries,
25765  SDL_ESM_INST_MAIN_ESM0,
25766  SDLR_ESM0_ESM_LVL_EVENT_SMS0_HSM_ECC_AGGR_0_ECC_CORRECTED_LEVEL_0,
25767  SDLR_ESM0_ESM_LVL_EVENT_SMS0_HSM_ECC_AGGR_0_ECC_UNCORRECTED_LEVEL_0
25768  },
25769  /* Index: SDL_SMS0_SMS_TIFS_ECC (28u) */
25770  {
25771  SDL_SMS0_SMS_TIFS_ECC_NUM_RAMS,
25772  SDL_SMS0_SMS_TIFS_ECC_RamIdTable,
25773  SDL_SMS0_SMS_TIFS_ECC_RAM_IDS_TOTAL_ENTRIES,
25774  SDL_SMS0_SMS_TIFS_ECC_MemEntries,
25775  SDL_ESM_INST_MAIN_ESM0,
25776  SDLR_ESM0_ESM_LVL_EVENT_SMS0_TIFS_ECC_AGGR_0_ECC_CORRECTED_LEVEL_0,
25777  SDLR_ESM0_ESM_LVL_EVENT_SMS0_TIFS_ECC_AGGR_0_ECC_UNCORRECTED_LEVEL_0
25778  },
25779  /* Index: SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR (29u) */
25780  {
25781  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_NUM_RAMS,
25782  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_RamIdTable,
25783  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
25784  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_MemEntries,
25785  SDL_ESM_INST_MAIN_ESM0,
25786  SDLR_ESM0_ESM_LVL_EVENT_VPAC0_ECC_AGGR_0_ECC_INTR0_CORR_LEVEL_0,
25787  SDLR_ESM0_ESM_LVL_EVENT_VPAC0_ECC_AGGR_0_ECC_INTR0_UNCORR_LEVEL_0
25788  },
25789  /* Index: SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR (30u) */
25790  {
25791  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_NUM_RAMS,
25792  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_RamIdTable,
25793  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
25794  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_MemEntries,
25795  SDL_ESM_INST_MAIN_ESM0,
25796  SDLR_ESM0_ESM_LVL_EVENT_VPAC0_LDC0_ECC_AGGR_0_ECC_INTR1_CORR_LEVEL_0,
25797  SDLR_ESM0_ESM_LVL_EVENT_VPAC0_LDC0_ECC_AGGR_0_ECC_INTR1_UNCORR_LEVEL_0
25798  },
25799  /* Index: SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR (31u) */
25800  {
25801  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_NUM_RAMS,
25802  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_RamIdTable,
25803  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
25804  SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_MemEntries,
25805  SDL_ESM_INST_MAIN_ESM0,
25806  SDLR_ESM0_ESM_LVL_EVENT_VPAC0_VISS0_ECC_AGGR_0_ECC_INTR3_CORR_LEVEL_0,
25807  SDLR_ESM0_ESM_LVL_EVENT_VPAC0_VISS0_ECC_AGGR_0_ECC_INTR3_UNCORR_LEVEL_0
25808 
25809  },
25810  /* SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR (32u) */
25811  {
25812  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_NUM_RAMS,
25813  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_RamIdTable,
25814  SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
25815  NULL,
25816  SDL_ESM_INST_WKUP_ESM0,
25817  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_ECC_AGGR1_CORR_LEVEL_0,
25818  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_ECC_AGGR1_UNCORR_LEVEL_0
25819  },
25820  /* SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR (33u) */
25821  {
25822  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_NUM_RAMS,
25823  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_RamIdTable,
25824  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
25825  SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_MemEntries,
25826  SDL_ESM_INST_MAIN_ESM0,
25827  SDLR_ESM0_ESM_LVL_EVENT_C7X256V0_CLEC_ESM_EVENTS_OUT_LEVEL_0,
25828  SDLR_ESM0_ESM_LVL_EVENT_C7X256V0_CLEC_ESM_EVENTS_OUT_LEVEL_1
25829  },
25830  /* SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR (34u) */
25831  {
25832  SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_NUM_RAMS,
25833  SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RamIdTable,
25834  SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
25835  SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_MemEntries,
25836  SDL_ESM_INST_MAIN_ESM0,
25837  SDLR_ESM0_ESM_LVL_EVENT_USB1_A_ECC_AGGR_CORRECTED_ERR_LEVEL_0,
25838  SDLR_ESM0_ESM_LVL_EVENT_USB1_A_ECC_AGGR_UNCORRECTED_ERR_LEVEL_0
25839  },
25840  /* SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR (35u) */
25841  {
25842  SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_NUM_RAMS,
25843  SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RamIdTable,
25844  SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
25845  SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_MemEntries,
25846  SDL_ESM_INST_MAIN_ESM0,
25847  SDLR_ESM0_ESM_LVL_EVENT_USB0_A_ECC_AGGR_CORRECTED_ERR_LEVEL_0,
25848  SDLR_ESM0_ESM_LVL_EVENT_USB0_A_ECC_AGGR_UNCORRECTED_ERR_LEVEL_0
25849  },
25850  /* SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR (36u) */
25851  {
25852  SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_NUM_RAMS,
25853  SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_RamIdTable,
25854  SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
25855  SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_MemEntries,
25856  SDL_ESM_INST_MAIN_ESM0,
25857  SDLR_ESM0_ESM_LVL_EVENT_WKUP_PSRAMECC_8K0_ECC_CORR_LEVEL_0,
25858  SDLR_ESM0_ESM_LVL_EVENT_WKUP_PSRAMECC_8K0_ECC_UNCORR_LEVEL_0
25859  },
25860  /* SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR (37u) */
25861  {
25862  SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_NUM_RAMS,
25863  SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_RamIdTable,
25864  SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_RAM_IDS_TOTAL_ENTRIES,
25865  SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_MemEntries,
25866  SDL_ESM_INST_MAIN_ESM0,
25867  SDLR_ESM0_ESM_LVL_EVENT_PDMA0_ECC_SEC_PEND_0,
25868  SDLR_ESM0_ESM_LVL_EVENT_PDMA0_ECC_DED_PEND_0
25869  },
25870  /* SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR (38u) */
25871  {
25872  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_NUM_RAMS,
25873  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_RamIdTable,
25874  SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
25875  NULL,
25876  SDL_ESM_INST_MAIN_ESM0,
25877  SDLR_ESM0_ESM_LVL_EVENT_WKUP_ECC_AGGR0_CORR_LEVEL_0,
25878  SDLR_ESM0_ESM_LVL_EVENT_WKUP_ECC_AGGR0_UNCORR_LEVEL_0
25879  },
25880  /* SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR (39u) */
25881  {
25882  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_NUM_RAMS,
25883  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RamIdTable,
25884  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RAM_IDS_TOTAL_ENTRIES,
25885  SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_MemEntries,
25886  SDL_ESM_INST_MAIN_ESM0,
25887  SDLR_ESM0_ESM_LVL_EVENT_PDMA1_ECC_SEC_PEND_0,
25888  SDLR_ESM0_ESM_LVL_EVENT_PDMA1_ECC_DED_PEND_0
25889  },
25890  /* SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR (40u) */
25891  {
25892  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
25893  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable,
25894  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
25895  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries,
25896  SDL_ESM_INST_MAIN_ESM0,
25897  SDLR_ESM0_ESM_LVL_EVENT_MCAN0_MCANSS_ECC_CORR_LVL_INT_0,
25898  SDLR_ESM0_ESM_LVL_EVENT_MCAN0_MCANSS_ECC_UNCORR_LVL_INT_0
25899  },
25900  /* SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0 (41u) */
25901  {
25902  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_NUM_RAMS,
25903  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RamIdTable,
25904  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RAM_IDS_TOTAL_ENTRIES,
25905  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_MemEntries,
25906  SDL_ESM_INST_MAIN_ESM0,
25907  SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR0_CORRECTED_ERR_LEVEL_0,
25908  SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR0_UNCORRECTED_ERR_LEVEL_0
25909  },
25910  /* SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1 (42u) */
25911  {
25912  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_NUM_RAMS,
25913  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RamIdTable,
25914  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RAM_IDS_TOTAL_ENTRIES,
25915  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_MemEntries,
25916  SDL_ESM_INST_MAIN_ESM0,
25917  SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR1_CORRECTED_ERR_LEVEL_0,
25918  SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR1_UNCORRECTED_ERR_LEVEL_0
25919  },
25920  /* SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2 (43u) */
25921  {
25922  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_NUM_RAMS,
25923  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_RamIdTable,
25924  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_RAM_IDS_TOTAL_ENTRIES,
25925  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_MemEntries,
25926  SDL_ESM_INST_MAIN_ESM0,
25927  SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR2_CORRECTED_ERR_LEVEL_0,
25928  SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR2_UNCORRECTED_ERR_LEVEL_0
25929  },
25930  /* SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3 (44u) */
25931  {
25932  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_NUM_RAMS,
25933  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_RamIdTable,
25934  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_RAM_IDS_TOTAL_ENTRIES,
25935  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_MemEntries,
25936  SDL_ESM_INST_MAIN_ESM0,
25937  SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR3_CORRECTED_ERR_LEVEL_0,
25938  SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR3_CORRECTED_ERR_LEVEL_0
25939  },
25940  /* SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC (45u) */
25941  {
25942  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_NUM_RAMS,
25943  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RamIdTable,
25944  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RAM_IDS_TOTAL_ENTRIES,
25945  SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_MemEntries,
25946  SDL_ESM_INST_MAIN_ESM0,
25947  SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR_COREPAC_CORRECTED_ERR_LEVEL_0,
25948  SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR_COREPAC_UNCORRECTED_ERR_LEVEL_0
25949  },
25950  /* SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR (46u) */
25951  {
25952  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
25953  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable,
25954  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
25955  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries,
25956  SDL_ESM_INST_WKUP_ESM0,
25957  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_MCAN0_MCANSS_ECC_CORR_LVL_INT_0,
25958  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_MCAN0_MCANSS_ECC_UNCORR_LVL_INT_0
25959  },
25960  /* SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR (47u) */
25961  {
25962  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
25963  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable,
25964  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
25965  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries,
25966  SDL_ESM_INST_WKUP_ESM0,
25967  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_MCAN1_MCANSS_ECC_CORR_LVL_INT_0,
25968  SDLR_WKUP_ESM0_ESM_LVL_EVENT_MCU_MCAN1_MCANSS_ECC_UNCORR_LVL_INT_0
25969  },
25970  /* SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR (48u) */
25971  {
25972  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_NUM_RAMS,
25973  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_RamIdTable,
25974  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
25975  SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_MemEntries,
25976  SDL_ESM_INST_MAIN_ESM0,
25977  SDLR_ESM0_ESM_LVL_EVENT_ECC_AGGR0_CORR_LEVEL_0,
25978  SDLR_ESM0_ESM_LVL_EVENT_ECC_AGGR0_UNCORR_LEVEL_0
25979  },
25980 };
25981 
25982  #endif /* INCLUDE_SDL_ECC_SOC_H_ */
SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:90
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_P2P_BRIDGE_IPULSAR_ULS_MCU_0_CPU0_CFG_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:3041
SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:20728
SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:89
SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_MemEntries
static const SDL_MemConfig_t SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_MemEntries[SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:20124
SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:18282
SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_MemEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:1224
SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_MemEntries[SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:1767
SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES
#define SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:85
SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:102
SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:100
SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:96
SDL_ESM_INST_MAIN_ESM0
@ SDL_ESM_INST_MAIN_ESM0
Definition: sdl_esm_soc.h:63
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:2928
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_RamIdTable
static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_RamIdTable[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_NUM_RAMS]
Definition: sdl_ecc_soc.h:25046
SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RamIdTable[SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:23577
SDL_SMS0_SMS_HSM_ECC_RamIdTable
static const SDL_RAMIdEntry_t SDL_SMS0_SMS_HSM_ECC_RamIdTable[SDL_SMS0_SMS_HSM_ECC_NUM_RAMS]
Definition: sdl_ecc_soc.h:23730
SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_MemEntries[SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:18828
SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_MemEntries
static const SDL_MemConfig_t SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_MemEntries[SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:511
SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES
#define SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:82
SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:20145
SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_RamIdTable[SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:23916
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:7543
SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:16044
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:2652
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:10051
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_AM62A_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:7085
SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_TIFS_VBUSP_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:21849
SDL_ECC_aggrTable
static const SDL_EccAggrEntry_t SDL_ECC_aggrTable[SDL_ECC_MEMTYPE_MAX]
Definition: sdl_ecc_soc.h:25480
SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:77
SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable
static const SDL_RAMIdEntry_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_NUM_RAMS]
Definition: sdl_ecc_soc.h:22885
SDL_PSCSS0_SAM62A_MAIN_PSC_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_PSCSS0_SAM62A_MAIN_PSC_WRAP_ECC_AGGR_RamIdTable[SDL_PSCSS0_SAM62A_MAIN_PSC_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:22189
SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_groupEntries[SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:19661
SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:17531
SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:19093
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:7402
SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:15543
SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_RamIdTable[SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:22322
SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:79
SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_MemEntries
static const SDL_MemConfig_t SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_MemEntries[SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:21147
SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_RamIdTable[SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:22241
SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:98
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:10620
SDL_DMASS0_DMSS_AM62A_ECCAGGR_MemEntries
static const SDL_MemConfig_t SDL_DMASS0_DMSS_AM62A_ECCAGGR_MemEntries[SDL_DMASS0_DMSS_AM62A_ECCAGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:2004
SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM62A_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:14669
SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_RamIdTable[SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:24508
SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_MemEntries[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:21669
SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:72
sdl_esm_soc.h
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RamIdTable
static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RamIdTable[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_NUM_RAMS]
Definition: sdl_ecc_soc.h:25189
SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RamIdTable[SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:24571
SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:22096
SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:13545
SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:1950
SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable
static const SDL_RAMIdEntry_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_NUM_RAMS]
Definition: sdl_ecc_soc.h:22872
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_RAM_IDS_TOTAL_ENTRIES
#define SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:108
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6998
SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:18400
SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:18307
SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:104
SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:16184
SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES
#define SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:83
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_SAM62A_MCU_MCU_ECC_AGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_SAM62A_MCU_MCU_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_SAM62A_MCU_MCU_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:7445
SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:11311
SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:65
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:9603
SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:97
SDL_ecc_aggrRegs
Definition: V0/sdlr_ecc.h:53
SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RamIdTable[SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:22202
SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_MemEntries[SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:130
SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_SAM62A_DM_DM_ECC_AGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_SAM62A_DM_DM_ECC_AGGR_EDC_CTRL_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_SAM62A_DM_DM_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:21127
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6384
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_MCU_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:3142
SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:164
SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_MemEntries
static const SDL_MemConfig_t SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_MemEntries[SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:2182
SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:103
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:7741
SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_groupEntries[SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:19648
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_DM2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_DM2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_DM2MCU_VBUSM_GASKET_MCU_0_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:2747
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_ISAM62A_MCU_PULSAR_UL_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:3177
SDL_SMS0_SMS_TIFS_ECC_RAM_IDS_TOTAL_ENTRIES
#define SDL_SMS0_SMS_TIFS_ECC_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:92
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:2366
SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:14352
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:10405
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:8262
SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RamIdTable[SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:24449
SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_RamIdTable[SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:22228
SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_RamIdTable[SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:24480
SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:14828
SDL_PSCSS0_SAM62A_MAIN_PSC_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_PSCSS0_SAM62A_MAIN_PSC_WRAP_ECC_AGGR_MemEntries[SDL_PSCSS0_SAM62A_MAIN_PSC_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:119
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_AM62A_MCU_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:7041
SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_PAC_BASE_KSDW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:93
SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable
static const SDL_RAMIdEntry_t SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable[SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_NUM_RAMS]
Definition: sdl_ecc_soc.h:22898
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:7696
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6905
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:10943
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:8681
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:3099
SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_MemEntries[SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:141
SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:13510
SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:21659
SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_RamIdTable[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:22345
SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_MemEntries[SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:18898
SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:336
SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_RamIdTable[SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:22663
SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_PULSAR_ULS_CPU0_CFG_SCRP_P_SCR1_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:1584
SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_groupEntries
static const SDL_GrpChkConfig_t SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_groupEntries[SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:19631
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:2708
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_MemEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:2204
SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:20385
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:3872
SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:25317
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_RMST_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:2219
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:10090
SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:68
SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:21167
SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_groupEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:1484
SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_RamIdTable[SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:24383
SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_AM62A_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:14688
SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_MemEntries[SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:2096
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_1_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_1_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:3006
SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_MemEntries[SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:20113
SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_RamIdTable[SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:22640
SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:22023
SDL_ECC_aggrTransBaseAddressTable
SDL_ecc_aggrRegs * SDL_ECC_aggrTransBaseAddressTable[SDL_ECC_MEMTYPE_MAX]
Definition: sdl_ecc_soc.h:25475
SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:76
SDL_PSCSS0_SAM62A_MAIN_PSC_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_PSCSS0_SAM62A_MAIN_PSC_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:64
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RamIdTable
static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RamIdTable[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_NUM_RAMS]
Definition: sdl_ecc_soc.h:24617
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:4754
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_MemEntries
static const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_MemEntries[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:21189
SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:12625
SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_BRIDGE_ISMS_MAIN_0_HSM_VBUSP_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:21814
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RAM_IDS_TOTAL_ENTRIES
#define SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:105
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:8969
SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_SAM62A_WKUP_SAFE_ECC_AGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_SAM62A_WKUP_SAFE_ECC_AGGR_EDC_CTRL_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_SAM62A_WKUP_SAFE_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:14899
SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:73
SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:16879
SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RamIdTable[SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:24431
SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_MemEntries[SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:20099
SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_PLL_MMR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:11989
SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_groupEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_SCRP_EDC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:1523
SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:18725
SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_RamIdTable[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:24340
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RAM_IDS_TOTAL_ENTRIES
#define SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:109
SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_RamIdTable[SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:22569
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SCR_AM62A_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:7225
SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:17496
SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_MemEntries[SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:14919
SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_groupEntries[SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:558
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:10064
SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:18447
SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:20420
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:2905
SDL_SMS0_SMS_TIFS_ECC_RamIdTable
static const SDL_RAMIdEntry_t SDL_SMS0_SMS_TIFS_ECC_RamIdTable[SDL_SMS0_SMS_TIFS_ECC_NUM_RAMS]
Definition: sdl_ecc_soc.h:23803
SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:22152
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_MemEntries
static const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_MemEntries[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:21278
SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:17400
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:5031
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RAM_IDS_TOTAL_ENTRIES
#define SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:106
SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_RamIdTable[SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:23954
SDL_DMASS0_DMSS_AM62A_ECCAGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_DMASS0_DMSS_AM62A_ECCAGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:78
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_RAM_IDS_TOTAL_ENTRIES
#define SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:107
SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:16137
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:8528
SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:16309
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:10920
SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_MemEntries[SDL_GICSS0_GIC500SS_1_4_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:1970
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:9972
SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:74
SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_SAM62A_MCU_PULSAR_UL_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:19599
SDL_SMS0_SMS_TIFS_ECC_MemEntries
static const SDL_MemConfig_t SDL_SMS0_SMS_TIFS_ECC_MemEntries[SDL_SMS0_SMS_TIFS_ECC_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:16245
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:7522
SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:16019
SDL_MemConfig_t
Definition: sdl_ecc_priv.h:71
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_AM62A_MCU_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:7060
SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_RamIdTable[SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:24467
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:7318
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_MemEntries
static const SDL_MemConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_MemEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:7465
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_MemEntries
static const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_MemEntries[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:21456
SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable
static const SDL_RAMIdEntry_t SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable[SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_NUM_RAMS]
Definition: sdl_ecc_soc.h:22911
SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_AM62A_WKUP_SAFE_CBASS_SCRP_SAFE_CLK4_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:13831
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:87
SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_RamIdTable[SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:24022
SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_groupEntries[SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:20045
SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries
static const SDL_MemConfig_t SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries[SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:2171
SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_groupEntries[SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:20023
SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:13580
SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries
static const SDL_MemConfig_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:2138
SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_MemEntries[SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:18854
SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:75
SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:69
SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RamIdTable[SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:22373
SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_PKTDMA_CRED_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:22135
SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:19379
sdl_ecc.h
Header file contains enumerations, structure definitions and function.
SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:21945
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_RamIdTable[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:22950
SDL_SMS0_SMS_HSM_ECC_RAM_IDS_TOTAL_ENTRIES
#define SDL_SMS0_SMS_HSM_ECC_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:91
SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_RamIdTable
static const SDL_RAMIdEntry_t SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_RamIdTable[SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_NUM_RAMS]
Definition: sdl_ecc_soc.h:22924
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_P2P_BRIDGE_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:3076
SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_ECC_AGGR1_SAM62A_SEC_MCU_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:1988
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6825
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_AM62A_MCU_CBASS_SCRM_64B_CLK1_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:4233
SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_P2P_BRIDGE_ISAM62A_DM_MCU_ECC_AGGR_WKUP_1_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:20794
SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:697
SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:111
SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_CFG_SLV_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:19526
SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_RamIdTable[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:22386
SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:15508
SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:15029
SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES
#define SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:81
SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MemEntries[SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:546
SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:16358
SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:12104
SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:21647
SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:19543
SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_groupEntries[SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:2126
SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_VISS0_KSDW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:95
SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:15127
SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:187
SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_VPAC0_SAM62A_VPAC_WRAP_IVPAC_TOP_0_VPAC_LDC0_KSDW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:94
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:9323
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_MemEntries
static const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_MemEntries[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:21545
SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_RamIdTable[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:25353
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:7178
SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:21884
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:9893
SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:18623
SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:18588
SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries
static const SDL_MemConfig_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:2149
SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RamIdTable[SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:22824
SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:18147
SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:20310
SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_RamIdTable
static const SDL_RAMIdEntry_t SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_RamIdTable[SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_NUM_RAMS]
Definition: sdl_ecc_soc.h:22937
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:9814
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:9254
SDL_SMS0_SMS_HSM_ECC_MemEntries
static const SDL_MemConfig_t SDL_SMS0_SMS_HSM_ECC_MemEntries[SDL_SMS0_SMS_HSM_ECC_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:15014
SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:20575
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:11134
SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:22040
SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MemEntries[SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:1799
SDL_ECC_aggrBaseAddressTable
static SDL_ecc_aggrRegs *const SDL_ECC_aggrBaseAddressTable[SDL_ECC_Base_Address_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:25422
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK2_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:5552
SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:21681
SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:21179
SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_MCU_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:20837
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_RamIdTable
static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_RamIdTable[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_NUM_RAMS]
Definition: sdl_ecc_soc.h:24903
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:9179
SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_MemEntries
static const SDL_MemConfig_t SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_MemEntries[SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:2193
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_M2P_BRIDGE_BR_SCRM_64B_CLK1_TO_SCRP_32B_CLK2_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6862
SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_RamIdTable[SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:22617
SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_MemEntries[SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:11266
SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_RamIdTable[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:23484
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_P2P_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRP_32B_CLK4_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6979
SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__IECC_AGGR_CFG_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:19582
SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES
#define SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:80
SDL_RAMIdEntry_t
Definition: sdl_ecc_priv.h:46
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_RamIdTable[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:23173
SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_SAM62A_DM_MCU_ECC_AGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_SAM62A_DM_MCU_ECC_AGGR_EDC_CTRL_groupEntries[SDL_WKUP_ECC_AGGR1_SAM62A_DM_MCU_ECC_AGGR_SAM62A_DM_MCU_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:491
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:8954
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:9104
SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:71
SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:67
SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_RamIdTable[SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:23416
SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_groupEntries[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:718
SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:88
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_MemEntries
static const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_MemEntries[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:21367
SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:21637
SDL_ECC_Base_Address_TOTAL_ENTRIES
#define SDL_ECC_Base_Address_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:113
SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_groupEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_MEM_MST0_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:1401
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:8385
SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_RamIdTable[SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:22215
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:86
SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_ISAM62A_SEC_BR_MAIN_0_IP2P_SA3_DMSS_CFG_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:22079
SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:15078
SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR1_SAM62A_MCU_PULSAR_UL_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_SLV_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:19240
SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:16260
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU2DM_VBUSM_GASKET_MCU_1_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:2758
SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_groupEntries[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:739
SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:16225
SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_PSRAMECC1_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:66
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM62A_MCU_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:7365
SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM62A_WKUP_DM_CBASS_EXPORT_AM62A_WKUP_DM_CBASS_TO_AM62A_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:20986
SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_RamIdTable[SDL_DMASS1_DMSS_CSI_AM62A_ECCAGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:22269
SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_groupEntries[SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:20034
SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:110
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:10891
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_P2P_CPU0_PMST_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:2691
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_AM62A_MCU_CBASS_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:5863
SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:24599
SDL_EccAggrEntry_t
Definition: sdl_ecc_priv.h:87
SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_MemEntries[SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:1213
SDL_DMASS0_DMSS_AM62A_ECCAGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_DMASS0_DMSS_AM62A_ECCAGGR_RamIdTable[SDL_DMASS0_DMSS_AM62A_ECCAGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:22676
SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES
#define SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:84
SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:15884
SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_SAM62A_DM_DM_ECC_AGGR_AM62A_WKUP_DM_CBASS_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_ISAM62A_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:20751
SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries
static const SDL_MemConfig_t SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries[SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:2160
SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:18808
SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_groupEntries[SDL_MCU_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:1811
SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:18644
SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_groupEntries[SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_DRU_R30_C_R_CORE_QUEUE_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:20006
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_1_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:3212
SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_MemEntries[SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:20085
SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_groupEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_CPU0_VBUSM2AXI_EDC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:1320
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:10077
SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_MemEntries[SDL_C7X256V0_SAM62A_C7XV_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:19619
SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:11832
SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:112
SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_MemEntries[SDL_MSRAM_64K0_MSRAM2KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:152
SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_PULSAR_ULS_CPU0_ECC_AGGR_PULSAR_ULS_CPU0_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:1747
SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RamIdTable
static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RamIdTable[SDL_COMPUTE_CLUSTER0_SAM62A_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_NUM_RAMS]
Definition: sdl_ecc_soc.h:24760
SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:1090
sdl_ecc_priv.h
SDL_ESM_INST_WKUP_ESM0
@ SDL_ESM_INST_WKUP_ESM0
Definition: sdl_esm_soc.h:61
SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62AXX_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:13146
SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:70
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:10184
SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:101
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_MCU_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_2_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:3653
SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_AM62A_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:14781
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_P2M_BRIDGE_BR_SCRP_32B_CLK2_TO_SCRM_64B_CLK1_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6936
SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:1105
SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:18052
SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:99
SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:21625
SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:25335
SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:17461
SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_ISAM62A_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_ISAM62A_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_groupEntries[SDL_WKUP_ECC_AGGR2_SAM62A_WKUP_SAFE_ECC_AGGR_ISAM62A_DM2WS_VBUSM_GASKET_MCU_0_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:13499
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_AM62A_MCU_CBASS_IMSRAM32KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM32KX64E_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:2971
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:9392
SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:10169
SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_ECC_AGGR0_SAM62A_SEC_HSM_ECC_AGGR_AM62A_MAIN_FW_CBASS_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM62A_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:21984
SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_groupEntries[SDL_MCU_ECC_AGGR0_SAM62A_MCU_MCU_ECC_AGGR_ISAM62A_MCU_PULSAR_UL_BR__ICPU0_M2M_CPU0_WMST_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:2505