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AM62Ax MCU+ SDK
09.00.00
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51 #ifndef SOC_AM62AX_CLOCKS_H
52 #define SOC_AM62AX_CLOCKS_H
60 #define TISCI_DEV_DPHY_RX0_IO_RX_CL_L_M 2
61 #define TISCI_DEV_DPHY_RX0_IO_RX_CL_L_M 2
62 #define TISCI_DEV_DPHY_RX0_IO_RX_CL_L_P 3
63 #define TISCI_DEV_DPHY_RX0_IO_RX_CL_L_P 3
64 #define TISCI_DEV_DPHY_RX0_JTAG_TCK 4
65 #define TISCI_DEV_DPHY_RX0_MAIN_CLK_CLK 5
66 #define TISCI_DEV_DPHY_RX0_PPI_RX_BYTE_CLK 6
68 #define TISCI_DEV_CMP_EVENT_INTROUTER0_INTR_CLK 0
70 #define TISCI_DEV_DBGSUSPENDROUTER0_INTR_CLK 0
72 #define TISCI_DEV_MAIN_GPIOMUX_INTROUTER0_INTR_CLK 0
74 #define TISCI_DEV_WKUP_MCU_GPIOMUX_INTROUTER0_INTR_CLK 0
76 #define TISCI_DEV_TIMESYNC_EVENT_ROUTER0_INTR_CLK 0
78 #define TISCI_DEV_CPSW0_CPPI_CLK_CLK 0
79 #define TISCI_DEV_CPSW0_CPTS_GENF0 1
80 #define TISCI_DEV_CPSW0_CPTS_GENF1 2
81 #define TISCI_DEV_CPSW0_CPTS_RFT_CLK 3
82 #define TISCI_DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK 4
83 #define TISCI_DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK 5
84 #define TISCI_DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT 6
85 #define TISCI_DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 8
86 #define TISCI_DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 9
87 #define TISCI_DEV_CPSW0_CPTS_RFT_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK 10
88 #define TISCI_DEV_CPSW0_CPTS_RFT_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK 11
89 #define TISCI_DEV_CPSW0_GMII1_MR_CLK 13
90 #define TISCI_DEV_CPSW0_GMII1_MT_CLK 14
91 #define TISCI_DEV_CPSW0_GMII2_MR_CLK 15
92 #define TISCI_DEV_CPSW0_GMII2_MT_CLK 16
93 #define TISCI_DEV_CPSW0_GMII_RFT_CLK 17
94 #define TISCI_DEV_CPSW0_MDIO_MDCLK_O 18
95 #define TISCI_DEV_CPSW0_RGMII1_RXC_I 19
96 #define TISCI_DEV_CPSW0_RGMII1_TXC_I 20
97 #define TISCI_DEV_CPSW0_RGMII1_TXC_O 21
98 #define TISCI_DEV_CPSW0_RGMII2_RXC_I 22
99 #define TISCI_DEV_CPSW0_RGMII2_TXC_I 23
100 #define TISCI_DEV_CPSW0_RGMII2_TXC_O 24
101 #define TISCI_DEV_CPSW0_RGMII_MHZ_250_CLK 25
102 #define TISCI_DEV_CPSW0_RGMII_MHZ_50_CLK 26
103 #define TISCI_DEV_CPSW0_RGMII_MHZ_5_CLK 27
104 #define TISCI_DEV_CPSW0_RMII1_MHZ_50_CLK 28
105 #define TISCI_DEV_CPSW0_RMII2_MHZ_50_CLK 29
107 #define TISCI_DEV_CPT2_AGGR1_VCLK_CLK 0
109 #define TISCI_DEV_CPT2_AGGR0_VCLK_CLK 0
111 #define TISCI_DEV_MCU_CPT2_AGGR0_VCLK_CLK 0
113 #define TISCI_DEV_CSI_RX_IF0_MAIN_CLK_CLK 0
114 #define TISCI_DEV_CSI_RX_IF0_PPI_RX_BYTE_CLK 2
115 #define TISCI_DEV_CSI_RX_IF0_VBUS_CLK_CLK 3
116 #define TISCI_DEV_CSI_RX_IF0_VP_CLK_CLK 4
118 #define TISCI_DEV_STM0_ATB_CLK 0
119 #define TISCI_DEV_STM0_CORE_CLK 1
120 #define TISCI_DEV_STM0_VBUSP_CLK 2
122 #define TISCI_DEV_DCC0_DCC_CLKSRC0_CLK 0
123 #define TISCI_DEV_DCC0_DCC_CLKSRC1_CLK 1
124 #define TISCI_DEV_DCC0_DCC_CLKSRC2_CLK 2
125 #define TISCI_DEV_DCC0_DCC_CLKSRC3_CLK 3
126 #define TISCI_DEV_DCC0_DCC_CLKSRC4_CLK 4
127 #define TISCI_DEV_DCC0_DCC_CLKSRC5_CLK 5
128 #define TISCI_DEV_DCC0_DCC_CLKSRC6_CLK 6
129 #define TISCI_DEV_DCC0_DCC_CLKSRC7_CLK 7
130 #define TISCI_DEV_DCC0_DCC_INPUT00_CLK 8
131 #define TISCI_DEV_DCC0_DCC_INPUT01_CLK 9
132 #define TISCI_DEV_DCC0_DCC_INPUT02_CLK 10
133 #define TISCI_DEV_DCC0_DCC_INPUT10_CLK 11
134 #define TISCI_DEV_DCC0_VBUS_CLK 12
136 #define TISCI_DEV_DCC1_DCC_CLKSRC0_CLK 0
137 #define TISCI_DEV_DCC1_DCC_CLKSRC1_CLK 1
138 #define TISCI_DEV_DCC1_DCC_CLKSRC2_CLK 2
139 #define TISCI_DEV_DCC1_DCC_CLKSRC3_CLK 3
140 #define TISCI_DEV_DCC1_DCC_CLKSRC4_CLK 4
141 #define TISCI_DEV_DCC1_DCC_CLKSRC5_CLK 5
142 #define TISCI_DEV_DCC1_DCC_CLKSRC6_CLK 6
143 #define TISCI_DEV_DCC1_DCC_CLKSRC7_CLK 7
144 #define TISCI_DEV_DCC1_DCC_INPUT00_CLK 8
145 #define TISCI_DEV_DCC1_DCC_INPUT01_CLK 9
146 #define TISCI_DEV_DCC1_DCC_INPUT02_CLK 10
147 #define TISCI_DEV_DCC1_DCC_INPUT10_CLK 11
148 #define TISCI_DEV_DCC1_VBUS_CLK 12
150 #define TISCI_DEV_DCC2_DCC_CLKSRC0_CLK 0
151 #define TISCI_DEV_DCC2_DCC_CLKSRC1_CLK 1
152 #define TISCI_DEV_DCC2_DCC_CLKSRC2_CLK 2
153 #define TISCI_DEV_DCC2_DCC_CLKSRC3_CLK 3
154 #define TISCI_DEV_DCC2_DCC_CLKSRC4_CLK 4
155 #define TISCI_DEV_DCC2_DCC_CLKSRC5_CLK 5
156 #define TISCI_DEV_DCC2_DCC_CLKSRC6_CLK 6
157 #define TISCI_DEV_DCC2_DCC_CLKSRC7_CLK 7
158 #define TISCI_DEV_DCC2_DCC_INPUT00_CLK 8
159 #define TISCI_DEV_DCC2_DCC_INPUT01_CLK 9
160 #define TISCI_DEV_DCC2_DCC_INPUT02_CLK 10
161 #define TISCI_DEV_DCC2_DCC_INPUT10_CLK 11
162 #define TISCI_DEV_DCC2_VBUS_CLK 12
164 #define TISCI_DEV_DCC3_DCC_CLKSRC0_CLK 0
165 #define TISCI_DEV_DCC3_DCC_CLKSRC1_CLK 1
166 #define TISCI_DEV_DCC3_DCC_CLKSRC2_CLK 2
167 #define TISCI_DEV_DCC3_DCC_CLKSRC3_CLK 3
168 #define TISCI_DEV_DCC3_DCC_CLKSRC4_CLK 4
169 #define TISCI_DEV_DCC3_DCC_CLKSRC5_CLK 5
170 #define TISCI_DEV_DCC3_DCC_CLKSRC6_CLK 6
171 #define TISCI_DEV_DCC3_DCC_CLKSRC7_CLK 7
172 #define TISCI_DEV_DCC3_DCC_INPUT00_CLK 8
173 #define TISCI_DEV_DCC3_DCC_INPUT01_CLK 9
174 #define TISCI_DEV_DCC3_DCC_INPUT02_CLK 10
175 #define TISCI_DEV_DCC3_DCC_INPUT10_CLK 11
176 #define TISCI_DEV_DCC3_VBUS_CLK 12
178 #define TISCI_DEV_DCC4_DCC_CLKSRC0_CLK 0
179 #define TISCI_DEV_DCC4_DCC_CLKSRC1_CLK 1
180 #define TISCI_DEV_DCC4_DCC_CLKSRC2_CLK 2
181 #define TISCI_DEV_DCC4_DCC_CLKSRC3_CLK 3
182 #define TISCI_DEV_DCC4_DCC_CLKSRC4_CLK 4
183 #define TISCI_DEV_DCC4_DCC_CLKSRC5_CLK 5
184 #define TISCI_DEV_DCC4_DCC_CLKSRC6_CLK 6
185 #define TISCI_DEV_DCC4_DCC_CLKSRC7_CLK 7
186 #define TISCI_DEV_DCC4_DCC_INPUT00_CLK 8
187 #define TISCI_DEV_DCC4_DCC_INPUT01_CLK 9
188 #define TISCI_DEV_DCC4_DCC_INPUT02_CLK 10
189 #define TISCI_DEV_DCC4_DCC_INPUT10_CLK 11
190 #define TISCI_DEV_DCC4_VBUS_CLK 12
192 #define TISCI_DEV_DCC5_DCC_CLKSRC0_CLK 0
193 #define TISCI_DEV_DCC5_DCC_CLKSRC2_CLK 2
194 #define TISCI_DEV_DCC5_DCC_CLKSRC3_CLK 3
195 #define TISCI_DEV_DCC5_DCC_CLKSRC4_CLK 4
196 #define TISCI_DEV_DCC5_DCC_CLKSRC5_CLK 5
197 #define TISCI_DEV_DCC5_DCC_CLKSRC6_CLK 6
198 #define TISCI_DEV_DCC5_DCC_CLKSRC7_CLK 7
199 #define TISCI_DEV_DCC5_DCC_INPUT00_CLK 8
200 #define TISCI_DEV_DCC5_DCC_INPUT01_CLK 9
201 #define TISCI_DEV_DCC5_DCC_INPUT02_CLK 10
202 #define TISCI_DEV_DCC5_DCC_INPUT10_CLK 11
203 #define TISCI_DEV_DCC5_VBUS_CLK 12
205 #define TISCI_DEV_DCC6_DCC_CLKSRC0_CLK 0
206 #define TISCI_DEV_DCC6_DCC_CLKSRC1_CLK 1
207 #define TISCI_DEV_DCC6_DCC_CLKSRC2_CLK 2
208 #define TISCI_DEV_DCC6_DCC_CLKSRC3_CLK 3
209 #define TISCI_DEV_DCC6_DCC_CLKSRC4_CLK 4
210 #define TISCI_DEV_DCC6_DCC_CLKSRC5_CLK 5
211 #define TISCI_DEV_DCC6_DCC_CLKSRC6_CLK 6
212 #define TISCI_DEV_DCC6_DCC_CLKSRC7_CLK 7
213 #define TISCI_DEV_DCC6_DCC_INPUT00_CLK 8
214 #define TISCI_DEV_DCC6_DCC_INPUT01_CLK 9
215 #define TISCI_DEV_DCC6_DCC_INPUT02_CLK 10
216 #define TISCI_DEV_DCC6_DCC_INPUT10_CLK 11
217 #define TISCI_DEV_DCC6_VBUS_CLK 12
219 #define TISCI_DEV_MCU_DCC0_DCC_CLKSRC0_CLK 0
220 #define TISCI_DEV_MCU_DCC0_DCC_CLKSRC1_CLK 1
221 #define TISCI_DEV_MCU_DCC0_DCC_CLKSRC2_CLK 2
222 #define TISCI_DEV_MCU_DCC0_DCC_CLKSRC3_CLK 3
223 #define TISCI_DEV_MCU_DCC0_DCC_CLKSRC4_CLK 4
224 #define TISCI_DEV_MCU_DCC0_DCC_CLKSRC5_CLK 5
225 #define TISCI_DEV_MCU_DCC0_DCC_CLKSRC6_CLK 6
226 #define TISCI_DEV_MCU_DCC0_DCC_CLKSRC7_CLK 7
227 #define TISCI_DEV_MCU_DCC0_DCC_INPUT00_CLK 8
228 #define TISCI_DEV_MCU_DCC0_DCC_INPUT01_CLK 9
229 #define TISCI_DEV_MCU_DCC0_DCC_INPUT02_CLK 10
230 #define TISCI_DEV_MCU_DCC0_DCC_INPUT10_CLK 11
231 #define TISCI_DEV_MCU_DCC0_VBUS_CLK 12
233 #define TISCI_DEV_MCU_DCC1_DCC_CLKSRC0_CLK 0
234 #define TISCI_DEV_MCU_DCC1_DCC_CLKSRC1_CLK 1
235 #define TISCI_DEV_MCU_DCC1_DCC_CLKSRC5_CLK 5
236 #define TISCI_DEV_MCU_DCC1_DCC_CLKSRC6_CLK 6
237 #define TISCI_DEV_MCU_DCC1_DCC_CLKSRC7_CLK 7
238 #define TISCI_DEV_MCU_DCC1_DCC_INPUT00_CLK 8
239 #define TISCI_DEV_MCU_DCC1_DCC_INPUT01_CLK 9
240 #define TISCI_DEV_MCU_DCC1_DCC_INPUT02_CLK 10
241 #define TISCI_DEV_MCU_DCC1_DCC_INPUT10_CLK 11
242 #define TISCI_DEV_MCU_DCC1_VBUS_CLK 12
244 #define TISCI_DEV_DEBUGSS_WRAP0_ATB_CLK 0
245 #define TISCI_DEV_DEBUGSS_WRAP0_CORE_CLK 1
246 #define TISCI_DEV_DEBUGSS_WRAP0_CSTPIU_TRACECLK 2
247 #define TISCI_DEV_DEBUGSS_WRAP0_JTAG_TCK 20
248 #define TISCI_DEV_DEBUGSS_WRAP0_P1500_WRCK 21
249 #define TISCI_DEV_DEBUGSS_WRAP0_TREXPT_CLK 22
251 #define TISCI_DEV_DMASS0_BCDMA_0_CLK 0
253 #define TISCI_DEV_DMASS0_CBASS_0_CLK 0
255 #define TISCI_DEV_DMASS0_INTAGGR_0_CLK 0
257 #define TISCI_DEV_DMASS0_IPCSS_0_CLK 0
259 #define TISCI_DEV_DMASS0_PKTDMA_0_CLK 0
261 #define TISCI_DEV_DMASS0_RINGACC_0_CLK 0
263 #define TISCI_DEV_DMASS1_BCDMA_0_CLK 0
265 #define TISCI_DEV_DMASS1_INTAGGR_0_CLK 0
267 #define TISCI_DEV_TIMER0_TIMER_HCLK_CLK 0
268 #define TISCI_DEV_TIMER0_TIMER_PWM 1
269 #define TISCI_DEV_TIMER0_TIMER_TCLK_CLK 2
270 #define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 3
271 #define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0 4
272 #define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK 5
273 #define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 6
274 #define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 7
275 #define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 8
276 #define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT 10
277 #define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK 11
278 #define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK 12
279 #define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0 13
280 #define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1 14
281 #define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_5_HSDIVOUT1_CLK 15
283 #define TISCI_DEV_TIMER1_TIMER_HCLK_CLK 0
284 #define TISCI_DEV_TIMER1_TIMER_PWM 1
285 #define TISCI_DEV_TIMER1_TIMER_TCLK_CLK 2
286 #define TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_MAIN_TIMERCLKN_SEL_OUT1 3
287 #define TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_0_TIMER_PWM 4
289 #define TISCI_DEV_TIMER2_TIMER_HCLK_CLK 0
290 #define TISCI_DEV_TIMER2_TIMER_PWM 1
291 #define TISCI_DEV_TIMER2_TIMER_TCLK_CLK 2
292 #define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 3
293 #define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0 4
294 #define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK 5
295 #define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 6
296 #define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 7
297 #define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 8
298 #define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT 10
299 #define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK 11
300 #define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK 12
301 #define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0 13
302 #define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1 14
303 #define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_5_HSDIVOUT1_CLK 15
305 #define TISCI_DEV_TIMER3_TIMER_HCLK_CLK 0
306 #define TISCI_DEV_TIMER3_TIMER_PWM 1
307 #define TISCI_DEV_TIMER3_TIMER_TCLK_CLK 2
308 #define TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_MAIN_TIMERCLKN_SEL_OUT3 3
309 #define TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_2_TIMER_PWM 4
311 #define TISCI_DEV_TIMER4_TIMER_HCLK_CLK 0
312 #define TISCI_DEV_TIMER4_TIMER_PWM 1
313 #define TISCI_DEV_TIMER4_TIMER_TCLK_CLK 2
314 #define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 3
315 #define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0 4
316 #define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK 5
317 #define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 6
318 #define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 7
319 #define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 8
320 #define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT 10
321 #define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK 11
322 #define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK 12
323 #define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0 13
324 #define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1 14
325 #define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_5_HSDIVOUT1_CLK 15
327 #define TISCI_DEV_TIMER5_TIMER_HCLK_CLK 0
328 #define TISCI_DEV_TIMER5_TIMER_PWM 1
329 #define TISCI_DEV_TIMER5_TIMER_TCLK_CLK 2
330 #define TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_MAIN_TIMERCLKN_SEL_OUT5 3
331 #define TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_4_TIMER_PWM 4
333 #define TISCI_DEV_TIMER6_TIMER_HCLK_CLK 0
334 #define TISCI_DEV_TIMER6_TIMER_PWM 1
335 #define TISCI_DEV_TIMER6_TIMER_TCLK_CLK 2
336 #define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 3
337 #define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0 4
338 #define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK 5
339 #define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 6
340 #define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 7
341 #define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 8
342 #define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT 10
343 #define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK 11
344 #define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK 12
345 #define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0 13
346 #define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1 14
347 #define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_5_HSDIVOUT1_CLK 15
349 #define TISCI_DEV_TIMER7_TIMER_HCLK_CLK 0
350 #define TISCI_DEV_TIMER7_TIMER_PWM 1
351 #define TISCI_DEV_TIMER7_TIMER_TCLK_CLK 2
352 #define TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_MAIN_TIMERCLKN_SEL_OUT7 3
353 #define TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_6_TIMER_PWM 4
355 #define TISCI_DEV_MCU_TIMER0_TIMER_HCLK_CLK 0
356 #define TISCI_DEV_MCU_TIMER0_TIMER_PWM 1
357 #define TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK 2
358 #define TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 3
359 #define TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4 4
360 #define TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 5
361 #define TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV1_16FFT_MCU_0_HSDIVOUT5_CLK 6
362 #define TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 7
363 #define TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0 8
364 #define TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0 9
365 #define TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 10
367 #define TISCI_DEV_MCU_TIMER1_TIMER_HCLK_CLK 0
368 #define TISCI_DEV_MCU_TIMER1_TIMER_PWM 1
369 #define TISCI_DEV_MCU_TIMER1_TIMER_TCLK_CLK 2
370 #define TISCI_DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_MCU_TIMERCLKN_SEL_OUT1 3
371 #define TISCI_DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_0_TIMER_PWM 4
373 #define TISCI_DEV_MCU_TIMER2_TIMER_HCLK_CLK 0
374 #define TISCI_DEV_MCU_TIMER2_TIMER_PWM 1
375 #define TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK 2
376 #define TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 3
377 #define TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4 4
378 #define TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 5
379 #define TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV1_16FFT_MCU_0_HSDIVOUT5_CLK 6
380 #define TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 7
381 #define TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0 8
382 #define TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0 9
383 #define TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 10
385 #define TISCI_DEV_MCU_TIMER3_TIMER_HCLK_CLK 0
386 #define TISCI_DEV_MCU_TIMER3_TIMER_PWM 1
387 #define TISCI_DEV_MCU_TIMER3_TIMER_TCLK_CLK 2
388 #define TISCI_DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_MCU_TIMERCLKN_SEL_OUT3 3
389 #define TISCI_DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_2_TIMER_PWM 4
391 #define TISCI_DEV_WKUP_TIMER0_TIMER_HCLK_CLK 0
392 #define TISCI_DEV_WKUP_TIMER0_TIMER_HCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_15_HSDIVOUT0_CLK 1
393 #define TISCI_DEV_WKUP_TIMER0_TIMER_HCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK 2
394 #define TISCI_DEV_WKUP_TIMER0_TIMER_PWM 3
395 #define TISCI_DEV_WKUP_TIMER0_TIMER_TCLK_CLK 4
396 #define TISCI_DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 5
397 #define TISCI_DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_WKUP_CLKSEL_OUT04 6
398 #define TISCI_DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 7
399 #define TISCI_DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV1_16FFT_MCU_0_HSDIVOUT5_CLK 8
400 #define TISCI_DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 9
401 #define TISCI_DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0 10
402 #define TISCI_DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0 11
403 #define TISCI_DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 12
405 #define TISCI_DEV_WKUP_TIMER1_TIMER_HCLK_CLK 0
406 #define TISCI_DEV_WKUP_TIMER1_TIMER_HCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_15_HSDIVOUT0_CLK 1
407 #define TISCI_DEV_WKUP_TIMER1_TIMER_HCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK 2
408 #define TISCI_DEV_WKUP_TIMER1_TIMER_TCLK_CLK 4
409 #define TISCI_DEV_WKUP_TIMER1_TIMER_TCLK_CLK_PARENT_WKUP_TIMERCLKN_SEL_OUT1 5
410 #define TISCI_DEV_WKUP_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_WKUP_0_TIMER_PWM 6
412 #define TISCI_DEV_ECAP0_VBUS_CLK 0
414 #define TISCI_DEV_ECAP1_VBUS_CLK 0
416 #define TISCI_DEV_ECAP2_VBUS_CLK 0
418 #define TISCI_DEV_ELM0_VBUSP_CLK 0
420 #define TISCI_DEV_MMCSD1_EMMCSDSS_IO_CLK_I 0
421 #define TISCI_DEV_MMCSD1_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC1_CLKLB_OUT 1
422 #define TISCI_DEV_MMCSD1_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC1_CLK_OUT 2
423 #define TISCI_DEV_MMCSD1_EMMCSDSS_IO_CLK_O 3
424 #define TISCI_DEV_MMCSD1_EMMCSDSS_VBUS_CLK 5
425 #define TISCI_DEV_MMCSD1_EMMCSDSS_XIN_CLK 6
426 #define TISCI_DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT5_CLK 7
427 #define TISCI_DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK 8
429 #define TISCI_DEV_MMCSD2_EMMCSDSS_IO_CLK_I 0
430 #define TISCI_DEV_MMCSD2_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC2_CLKLB_OUT 1
431 #define TISCI_DEV_MMCSD2_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC2_CLK_OUT 2
432 #define TISCI_DEV_MMCSD2_EMMCSDSS_IO_CLK_O 3
433 #define TISCI_DEV_MMCSD2_EMMCSDSS_VBUS_CLK 5
434 #define TISCI_DEV_MMCSD2_EMMCSDSS_XIN_CLK 6
435 #define TISCI_DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT5_CLK 7
436 #define TISCI_DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK 8
438 #define TISCI_DEV_MMCSD0_EMMCSDSS_IO_CLK_I 0
439 #define TISCI_DEV_MMCSD0_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC0_CLKLB_OUT 1
440 #define TISCI_DEV_MMCSD0_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC0_CLK_OUT 2
441 #define TISCI_DEV_MMCSD0_EMMCSDSS_IO_CLK_O 3
442 #define TISCI_DEV_MMCSD0_EMMCSDSS_VBUS_CLK 5
443 #define TISCI_DEV_MMCSD0_EMMCSDSS_XIN_CLK 6
444 #define TISCI_DEV_MMCSD0_EMMCSDSS_XIN_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT5_CLK 7
445 #define TISCI_DEV_MMCSD0_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK 8
447 #define TISCI_DEV_EQEP0_VBUS_CLK 0
449 #define TISCI_DEV_EQEP1_VBUS_CLK 0
451 #define TISCI_DEV_EQEP2_VBUS_CLK 0
453 #define TISCI_DEV_ESM0_CLK 0
455 #define TISCI_DEV_WKUP_ESM0_CLK 0
457 #define TISCI_DEV_FSS0_FSAS_0_GCLK 0
459 #define TISCI_DEV_FSS0_OSPI_0_OSPI_DQS_CLK 0
460 #define TISCI_DEV_FSS0_OSPI_0_OSPI_HCLK_CLK 1
461 #define TISCI_DEV_FSS0_OSPI_0_OSPI_ICLK_CLK 2
462 #define TISCI_DEV_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_OSPI0_DQS_OUT 3
463 #define TISCI_DEV_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_OSPI0_LBCLKO_OUT 4
464 #define TISCI_DEV_FSS0_OSPI_0_OSPI_OCLK_CLK 5
465 #define TISCI_DEV_FSS0_OSPI_0_OSPI_PCLK_CLK 6
466 #define TISCI_DEV_FSS0_OSPI_0_OSPI_RCLK_CLK 7
467 #define TISCI_DEV_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK 8
468 #define TISCI_DEV_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT5_CLK 9
470 #define TISCI_DEV_GICSS0_VCLK_CLK 0
472 #define TISCI_DEV_GPIO0_MMR_CLK 0
474 #define TISCI_DEV_GPIO1_MMR_CLK 0
476 #define TISCI_DEV_MCU_GPIO0_MMR_CLK 0
477 #define TISCI_DEV_MCU_GPIO0_MMR_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4 1
478 #define TISCI_DEV_MCU_GPIO0_MMR_CLK_PARENT_GLUELOGIC_LFOSC0_CLKOUT 2
479 #define TISCI_DEV_MCU_GPIO0_MMR_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 3
480 #define TISCI_DEV_MCU_GPIO0_MMR_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 4
482 #define TISCI_DEV_GPMC0_FUNC_CLK 0
483 #define TISCI_DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK 1
484 #define TISCI_DEV_GPMC0_FUNC_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT7_CLK 2
485 #define TISCI_DEV_GPMC0_PI_GPMC_RET_CLK 3
486 #define TISCI_DEV_GPMC0_PO_GPMC_DEV_CLK 4
487 #define TISCI_DEV_GPMC0_VBUSM_CLK 5
489 #define TISCI_DEV_WKUP_GTC0_GTC_CLK 0
490 #define TISCI_DEV_WKUP_GTC0_GTC_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK 1
491 #define TISCI_DEV_WKUP_GTC0_GTC_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK 2
492 #define TISCI_DEV_WKUP_GTC0_GTC_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT 3
493 #define TISCI_DEV_WKUP_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 5
494 #define TISCI_DEV_WKUP_GTC0_GTC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 6
495 #define TISCI_DEV_WKUP_GTC0_GTC_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK2 7
496 #define TISCI_DEV_WKUP_GTC0_GTC_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK 8
497 #define TISCI_DEV_WKUP_GTC0_VBUSP_CLK 9
498 #define TISCI_DEV_WKUP_GTC0_VBUSP_CLK_PARENT_HSDIV2_16FFT_MAIN_15_HSDIVOUT0_CLK 10
499 #define TISCI_DEV_WKUP_GTC0_VBUSP_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK 11
501 #define TISCI_DEV_DDPA0_DDPA_CLK 0
503 #define TISCI_DEV_DSS0_DPI_0_IN_CLK 0
504 #define TISCI_DEV_DSS0_DPI_1_IN_CLK 2
505 #define TISCI_DEV_DSS0_DPI_1_IN_CLK_PARENT_HSDIV0_16FFT_MAIN_17_HSDIVOUT0_CLK 3
506 #define TISCI_DEV_DSS0_DPI_1_IN_CLK_PARENT_BOARD_0_VOUT0_EXTPCLKIN_OUT 4
507 #define TISCI_DEV_DSS0_DPI_1_OUT_CLK 5
508 #define TISCI_DEV_DSS0_DSS_FUNC_CLK 6
510 #define TISCI_DEV_EPWM0_VBUSP_CLK 0
512 #define TISCI_DEV_EPWM1_VBUSP_CLK 0
514 #define TISCI_DEV_EPWM2_VBUSP_CLK 0
516 #define TISCI_DEV_JPGENC0_CORE_CLK 0
518 #define TISCI_DEV_LED0_VBUS_CLK 1
520 #define TISCI_DEV_PBIST0_CLK8_CLK 7
521 #define TISCI_DEV_PBIST0_TCLK_CLK 9
523 #define TISCI_DEV_WKUP_PBIST0_CLK8_CLK 7
525 #define TISCI_DEV_MCU_PBIST0_CLK8_CLK 7
527 #define TISCI_DEV_CODEC0_VPU_ACLK_CLK 0
528 #define TISCI_DEV_CODEC0_VPU_BCLK_CLK 1
529 #define TISCI_DEV_CODEC0_VPU_CCLK_CLK 2
530 #define TISCI_DEV_CODEC0_VPU_PCLK_CLK 3
532 #define TISCI_DEV_WKUP_VTM0_FIX_REF2_CLK 0
533 #define TISCI_DEV_WKUP_VTM0_FIX_REF_CLK 1
534 #define TISCI_DEV_WKUP_VTM0_VBUSP_CLK 2
535 #define TISCI_DEV_WKUP_VTM0_VBUSP_CLK_PARENT_HSDIV2_16FFT_MAIN_15_HSDIVOUT0_CLK 3
536 #define TISCI_DEV_WKUP_VTM0_VBUSP_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK 4
538 #define TISCI_DEV_MCAN0_MCANSS_CCLK_CLK 1
539 #define TISCI_DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK 2
540 #define TISCI_DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 3
541 #define TISCI_DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 4
542 #define TISCI_DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 5
543 #define TISCI_DEV_MCAN0_MCANSS_HCLK_CLK 6
545 #define TISCI_DEV_MCU_MCAN0_MCANSS_CCLK_CLK 1
546 #define TISCI_DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT4_CLK 2
547 #define TISCI_DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 3
548 #define TISCI_DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 4
549 #define TISCI_DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT_DUP0 5
550 #define TISCI_DEV_MCU_MCAN0_MCANSS_HCLK_CLK 6
552 #define TISCI_DEV_MCU_MCAN1_MCANSS_CCLK_CLK 1
553 #define TISCI_DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT4_CLK 2
554 #define TISCI_DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 3
555 #define TISCI_DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 4
556 #define TISCI_DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT_DUP0 5
557 #define TISCI_DEV_MCU_MCAN1_MCANSS_HCLK_CLK 6
559 #define TISCI_DEV_MCASP0_AUX_CLK 0
560 #define TISCI_DEV_MCASP0_AUX_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK 1
561 #define TISCI_DEV_MCASP0_AUX_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK 2
562 #define TISCI_DEV_MCASP0_MCASP_ACLKR_PIN 3
563 #define TISCI_DEV_MCASP0_MCASP_ACLKR_POUT 4
564 #define TISCI_DEV_MCASP0_MCASP_ACLKX_PIN 5
565 #define TISCI_DEV_MCASP0_MCASP_ACLKX_POUT 6
566 #define TISCI_DEV_MCASP0_MCASP_AFSR_POUT 7
567 #define TISCI_DEV_MCASP0_MCASP_AFSX_POUT 8
568 #define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN 9
569 #define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT 10
570 #define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT 11
571 #define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 12
572 #define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 13
573 #define TISCI_DEV_MCASP0_MCASP_AHCLKR_POUT 14
574 #define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN 15
575 #define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT 16
576 #define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT 17
577 #define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 18
578 #define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 19
579 #define TISCI_DEV_MCASP0_MCASP_AHCLKX_POUT 20
580 #define TISCI_DEV_MCASP0_VBUSP_CLK 21
582 #define TISCI_DEV_MCASP1_AUX_CLK 0
583 #define TISCI_DEV_MCASP1_AUX_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK 1
584 #define TISCI_DEV_MCASP1_AUX_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK 2
585 #define TISCI_DEV_MCASP1_MCASP_ACLKR_PIN 3
586 #define TISCI_DEV_MCASP1_MCASP_ACLKR_POUT 4
587 #define TISCI_DEV_MCASP1_MCASP_ACLKX_PIN 5
588 #define TISCI_DEV_MCASP1_MCASP_ACLKX_POUT 6
589 #define TISCI_DEV_MCASP1_MCASP_AFSR_POUT 7
590 #define TISCI_DEV_MCASP1_MCASP_AFSX_POUT 8
591 #define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN 9
592 #define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT 10
593 #define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT 11
594 #define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 12
595 #define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 13
596 #define TISCI_DEV_MCASP1_MCASP_AHCLKR_POUT 14
597 #define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN 15
598 #define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT 16
599 #define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT 17
600 #define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 18
601 #define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 19
602 #define TISCI_DEV_MCASP1_MCASP_AHCLKX_POUT 20
603 #define TISCI_DEV_MCASP1_VBUSP_CLK 21
605 #define TISCI_DEV_MCASP2_AUX_CLK 0
606 #define TISCI_DEV_MCASP2_AUX_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK 1
607 #define TISCI_DEV_MCASP2_AUX_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK 2
608 #define TISCI_DEV_MCASP2_MCASP_ACLKR_PIN 3
609 #define TISCI_DEV_MCASP2_MCASP_ACLKR_POUT 4
610 #define TISCI_DEV_MCASP2_MCASP_ACLKX_PIN 5
611 #define TISCI_DEV_MCASP2_MCASP_ACLKX_POUT 6
612 #define TISCI_DEV_MCASP2_MCASP_AFSR_POUT 7
613 #define TISCI_DEV_MCASP2_MCASP_AFSX_POUT 8
614 #define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN 9
615 #define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT 10
616 #define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT 11
617 #define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 12
618 #define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 13
619 #define TISCI_DEV_MCASP2_MCASP_AHCLKR_POUT 14
620 #define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN 15
621 #define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT 16
622 #define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT 17
623 #define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 18
624 #define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 19
625 #define TISCI_DEV_MCASP2_MCASP_AHCLKX_POUT 20
626 #define TISCI_DEV_MCASP2_VBUSP_CLK 21
628 #define TISCI_DEV_MCRC64_0_CLK 0
630 #define TISCI_DEV_MCU_MCRC64_0_CLK 0
632 #define TISCI_DEV_I2C0_CLK 0
633 #define TISCI_DEV_I2C0_PISCL 1
634 #define TISCI_DEV_I2C0_PISYS_CLK 2
635 #define TISCI_DEV_I2C0_PORSCL 3
637 #define TISCI_DEV_I2C1_CLK 0
638 #define TISCI_DEV_I2C1_PISCL 1
639 #define TISCI_DEV_I2C1_PISYS_CLK 2
640 #define TISCI_DEV_I2C1_PORSCL 3
642 #define TISCI_DEV_I2C2_CLK 0
643 #define TISCI_DEV_I2C2_PISCL 1
644 #define TISCI_DEV_I2C2_PISYS_CLK 2
645 #define TISCI_DEV_I2C2_PORSCL 3
647 #define TISCI_DEV_I2C3_CLK 0
648 #define TISCI_DEV_I2C3_PISCL 1
649 #define TISCI_DEV_I2C3_PISYS_CLK 2
650 #define TISCI_DEV_I2C3_PORSCL 3
652 #define TISCI_DEV_MCU_I2C0_CLK 0
653 #define TISCI_DEV_MCU_I2C0_PISCL 1
654 #define TISCI_DEV_MCU_I2C0_PISYS_CLK 2
655 #define TISCI_DEV_MCU_I2C0_PORSCL 3
657 #define TISCI_DEV_WKUP_I2C0_CLK 0
658 #define TISCI_DEV_WKUP_I2C0_CLK_PARENT_HSDIV2_16FFT_MAIN_15_HSDIVOUT0_CLK 1
659 #define TISCI_DEV_WKUP_I2C0_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK 2
660 #define TISCI_DEV_WKUP_I2C0_PISYS_CLK 4
661 #define TISCI_DEV_WKUP_I2C0_PORSCL 5
663 #define TISCI_DEV_WKUP_R5FSS0_CORE0_CPU_CLK 0
664 #define TISCI_DEV_WKUP_R5FSS0_CORE0_CPU_CLK_PARENT_HSDIV2_16FFT_MAIN_15_HSDIVOUT2_CLK 1
665 #define TISCI_DEV_WKUP_R5FSS0_CORE0_CPU_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK 2
666 #define TISCI_DEV_WKUP_R5FSS0_CORE0_INTERFACE_CLK 5
668 #define TISCI_DEV_MCU_R5FSS0_CORE0_CPU0_CLK 0
669 #define TISCI_DEV_MCU_R5FSS0_CORE0_INTERFACE0_CLK 1
671 #define TISCI_DEV_WKUP_RTCSS0_ANA_OSC32K_CLK 0
672 #define TISCI_DEV_WKUP_RTCSS0_ANA_OSC32K_CLK_PARENT_CLK_32K_RC_SEL_OUT0 1
673 #define TISCI_DEV_WKUP_RTCSS0_ANA_OSC32K_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 2
674 #define TISCI_DEV_WKUP_RTCSS0_JTAG_WRCK 4
675 #define TISCI_DEV_WKUP_RTCSS0_VCLK_CLK 6
676 #define TISCI_DEV_WKUP_RTCSS0_VCLK_CLK_PARENT_HSDIV2_16FFT_MAIN_15_HSDIVOUT0_CLK 7
677 #define TISCI_DEV_WKUP_RTCSS0_VCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK 8
679 #define TISCI_DEV_RTI4_RTI_CLK 0
680 #define TISCI_DEV_RTI4_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 1
681 #define TISCI_DEV_RTI4_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0 2
682 #define TISCI_DEV_RTI4_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 3
683 #define TISCI_DEV_RTI4_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 4
684 #define TISCI_DEV_RTI4_VBUSP_CLK 5
686 #define TISCI_DEV_RTI0_RTI_CLK 0
687 #define TISCI_DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 1
688 #define TISCI_DEV_RTI0_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0 2
689 #define TISCI_DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 3
690 #define TISCI_DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 4
691 #define TISCI_DEV_RTI0_VBUSP_CLK 5
693 #define TISCI_DEV_RTI1_RTI_CLK 0
694 #define TISCI_DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 1
695 #define TISCI_DEV_RTI1_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0 2
696 #define TISCI_DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 3
697 #define TISCI_DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 4
698 #define TISCI_DEV_RTI1_VBUSP_CLK 5
700 #define TISCI_DEV_RTI2_RTI_CLK 0
701 #define TISCI_DEV_RTI2_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 1
702 #define TISCI_DEV_RTI2_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0 2
703 #define TISCI_DEV_RTI2_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 3
704 #define TISCI_DEV_RTI2_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 4
705 #define TISCI_DEV_RTI2_VBUSP_CLK 5
707 #define TISCI_DEV_RTI3_RTI_CLK 0
708 #define TISCI_DEV_RTI3_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 1
709 #define TISCI_DEV_RTI3_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0 2
710 #define TISCI_DEV_RTI3_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 3
711 #define TISCI_DEV_RTI3_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 4
712 #define TISCI_DEV_RTI3_VBUSP_CLK 5
714 #define TISCI_DEV_MCU_RTI0_RTI_CLK 0
715 #define TISCI_DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 1
716 #define TISCI_DEV_MCU_RTI0_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0 2
717 #define TISCI_DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 3
718 #define TISCI_DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 4
719 #define TISCI_DEV_MCU_RTI0_VBUSP_CLK 5
721 #define TISCI_DEV_WKUP_RTI0_RTI_CLK 0
722 #define TISCI_DEV_WKUP_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 1
723 #define TISCI_DEV_WKUP_RTI0_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0 2
724 #define TISCI_DEV_WKUP_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 3
725 #define TISCI_DEV_WKUP_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 4
726 #define TISCI_DEV_WKUP_RTI0_VBUSP_CLK 5
727 #define TISCI_DEV_WKUP_RTI0_VBUSP_CLK_PARENT_HSDIV2_16FFT_MAIN_15_HSDIVOUT0_CLK 6
728 #define TISCI_DEV_WKUP_RTI0_VBUSP_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK 7
730 #define TISCI_DEV_WKUP_DEEPSLEEP_SOURCES0_CLK_12M_RC_CLK 0
732 #define TISCI_DEV_A53SS0_CORE_0_A53_CORE0_ARM_CLK_CLK 0
734 #define TISCI_DEV_A53SS0_CORE_1_A53_CORE1_ARM_CLK_CLK 0
736 #define TISCI_DEV_A53SS0_CORE_2_A53_CORE2_ARM_CLK_CLK 0
738 #define TISCI_DEV_A53SS0_CORE_3_A53_CORE3_ARM_CLK_CLK 0
740 #define TISCI_DEV_A53SS0_A53_DIVH_CLK4_OBSCLK_OUT_CLK 2
741 #define TISCI_DEV_A53SS0_COREPAC_ARM_CLK_CLK 3
742 #define TISCI_DEV_A53SS0_PLL_CTRL_CLK 5
744 #define TISCI_DEV_A53_RS_BW_LIMITER0_CLK_CLK 0
746 #define TISCI_DEV_A53_WS_BW_LIMITER1_CLK_CLK 0
748 #define TISCI_DEV_C7XV_RSWS_BS_LIMITER6_CLK_CLK 0
750 #define TISCI_DEV_C7X256V0_C7XV_CORE_0_C7XV_CLK 0
752 #define TISCI_DEV_C7X256V0_CORE0_DIVH_CLK2_SOC_GCLK 0
753 #define TISCI_DEV_C7X256V0_CORE0_DIVH_CLK4_GCLK 1
754 #define TISCI_DEV_C7X256V0_CORE0_DIVH_CLK4_SOC_GCLK 2
755 #define TISCI_DEV_C7X256V0_CORE0_DIVP_CLK1_GCLK 3
756 #define TISCI_DEV_C7X256V0_CORE0_DIVP_CLK1_SOC_GCLK 4
758 #define TISCI_DEV_C7X256V0_CLK_C7XV_CLK 0
759 #define TISCI_DEV_C7X256V0_CLK_C7XV_DIVH_CLK4_OBSCLK_OUT_CLK 1
760 #define TISCI_DEV_C7X256V0_CLK_DIVH_CLK2_SOC_GCLK 2
761 #define TISCI_DEV_C7X256V0_CLK_DIVH_CLK4_GCLK 3
762 #define TISCI_DEV_C7X256V0_CLK_DIVH_CLK4_SOC_GCLK 4
763 #define TISCI_DEV_C7X256V0_CLK_DIVP_CLK1_GCLK 5
764 #define TISCI_DEV_C7X256V0_CLK_DIVP_CLK1_SOC_GCLK 6
765 #define TISCI_DEV_C7X256V0_CLK_PLL_CTRL_CLK 7
767 #define TISCI_DEV_DDR32SS0_DDR_PLL_DIVH_CLK4_OBSCLK_OUT_CLK 0
768 #define TISCI_DEV_DDR32SS0_DDRSS_DDR_PLL_CLK 1
769 #define TISCI_DEV_DDR32SS0_DDRSS_TCK 2
770 #define TISCI_DEV_DDR32SS0_PLL_CTRL_CLK 3
772 #define TISCI_DEV_DEBUGSS0_CFG_CLK 0
773 #define TISCI_DEV_DEBUGSS0_DBG_CLK 1
774 #define TISCI_DEV_DEBUGSS0_SYS_CLK 2
776 #define TISCI_DEV_JPGENC_RS_BW_LIMITER4_CLK_CLK 0
778 #define TISCI_DEV_JPGENC_WS_BW_LIMITER5_CLK_CLK 0
780 #define TISCI_DEV_PSC0_FW_0_CLK 0
782 #define TISCI_DEV_PSC0_CLK 0
783 #define TISCI_DEV_PSC0_SLOW_CLK 1
785 #define TISCI_DEV_MCU_MCU_16FF0_PLL_CTRL_MCU_CLK24_CLK 3
787 #define TISCI_DEV_WKUP_PSC0_CLK 0
788 #define TISCI_DEV_WKUP_PSC0_SLOW_CLK 1
790 #define TISCI_DEV_VPAC_RSWS_BW_LIMITER8_CLK_CLK 0
792 #define TISCI_DEV_VPAC_RSWS_BW_LIMITER7_CLK_CLK 0
794 #define TISCI_DEV_VPAC0_PLL_CTRL_CLK 1
795 #define TISCI_DEV_VPAC0_VPAC_PLL_CFG_CLK 3
796 #define TISCI_DEV_VPAC0_VPAC_PLL_CLK 4
798 #define TISCI_DEV_PBIST3_CLK8_CLK 1
800 #define TISCI_DEV_CODEC_RS_BW_LIMITER2_CLK_CLK 0
802 #define TISCI_DEV_CODEC_WS_BW_LIMITER3_CLK_CLK 0
804 #define TISCI_DEV_HSM0_DAP_CLK 0
806 #define TISCI_DEV_MCSPI0_CLKSPIREF_CLK 0
807 #define TISCI_DEV_MCSPI0_IO_CLKSPIO_CLK 2
808 #define TISCI_DEV_MCSPI0_VBUSP_CLK 3
809 #define TISCI_DEV_MCSPI0_IO_CLKSPII_CLK 4
810 #define TISCI_DEV_MCSPI0_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI0_CLK_OUT 5
811 #define TISCI_DEV_MCSPI0_IO_CLKSPII_CLK_PARENT_SPI_MAIN_0_IO_CLKSPIO_CLK 6
813 #define TISCI_DEV_MCSPI1_CLKSPIREF_CLK 0
814 #define TISCI_DEV_MCSPI1_IO_CLKSPIO_CLK 2
815 #define TISCI_DEV_MCSPI1_VBUSP_CLK 3
816 #define TISCI_DEV_MCSPI1_IO_CLKSPII_CLK 4
817 #define TISCI_DEV_MCSPI1_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI1_CLK_OUT 5
818 #define TISCI_DEV_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MAIN_1_IO_CLKSPIO_CLK 6
820 #define TISCI_DEV_MCSPI2_CLKSPIREF_CLK 0
821 #define TISCI_DEV_MCSPI2_IO_CLKSPIO_CLK 2
822 #define TISCI_DEV_MCSPI2_VBUSP_CLK 3
823 #define TISCI_DEV_MCSPI2_IO_CLKSPII_CLK 4
824 #define TISCI_DEV_MCSPI2_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI2_CLK_OUT 5
825 #define TISCI_DEV_MCSPI2_IO_CLKSPII_CLK_PARENT_SPI_MAIN_2_IO_CLKSPIO_CLK 6
827 #define TISCI_DEV_MCU_MCSPI0_CLKSPIREF_CLK 0
828 #define TISCI_DEV_MCU_MCSPI0_IO_CLKSPIO_CLK 2
829 #define TISCI_DEV_MCU_MCSPI0_VBUSP_CLK 3
830 #define TISCI_DEV_MCU_MCSPI0_IO_CLKSPII_CLK 4
831 #define TISCI_DEV_MCU_MCSPI0_IO_CLKSPII_CLK_PARENT_BOARD_0_MCU_SPI0_CLK_OUT 5
832 #define TISCI_DEV_MCU_MCSPI0_IO_CLKSPII_CLK_PARENT_SPI_MCU_0_IO_CLKSPIO_CLK 6
834 #define TISCI_DEV_MCU_MCSPI1_CLKSPIREF_CLK 0
835 #define TISCI_DEV_MCU_MCSPI1_IO_CLKSPIO_CLK 2
836 #define TISCI_DEV_MCU_MCSPI1_VBUSP_CLK 3
837 #define TISCI_DEV_MCU_MCSPI1_IO_CLKSPII_CLK 4
838 #define TISCI_DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_BOARD_0_MCU_SPI1_CLK_OUT 5
839 #define TISCI_DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MCU_1_IO_CLKSPIO_CLK 6
841 #define TISCI_DEV_SPINLOCK0_VCLK_CLK 0
843 #define TISCI_DEV_UART0_FCLK_CLK 0
844 #define TISCI_DEV_UART0_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT0 1
845 #define TISCI_DEV_UART0_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK 2
846 #define TISCI_DEV_UART0_VBUSP_CLK 5
848 #define TISCI_DEV_UART1_FCLK_CLK 0
849 #define TISCI_DEV_UART1_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT1 1
850 #define TISCI_DEV_UART1_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK 2
851 #define TISCI_DEV_UART1_VBUSP_CLK 5
853 #define TISCI_DEV_UART2_FCLK_CLK 0
854 #define TISCI_DEV_UART2_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT2 1
855 #define TISCI_DEV_UART2_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK 2
856 #define TISCI_DEV_UART2_VBUSP_CLK 5
858 #define TISCI_DEV_UART3_FCLK_CLK 0
859 #define TISCI_DEV_UART3_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT3 1
860 #define TISCI_DEV_UART3_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK 2
861 #define TISCI_DEV_UART3_VBUSP_CLK 5
863 #define TISCI_DEV_UART4_FCLK_CLK 0
864 #define TISCI_DEV_UART4_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT4 1
865 #define TISCI_DEV_UART4_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK 2
866 #define TISCI_DEV_UART4_VBUSP_CLK 5
868 #define TISCI_DEV_UART5_FCLK_CLK 0
869 #define TISCI_DEV_UART5_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT5 1
870 #define TISCI_DEV_UART5_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK 2
871 #define TISCI_DEV_UART5_VBUSP_CLK 5
873 #define TISCI_DEV_UART6_FCLK_CLK 0
874 #define TISCI_DEV_UART6_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT6 1
875 #define TISCI_DEV_UART6_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK 2
876 #define TISCI_DEV_UART6_VBUSP_CLK 5
878 #define TISCI_DEV_MCU_UART0_FCLK_CLK 0
879 #define TISCI_DEV_MCU_UART0_VBUSP_CLK 3
881 #define TISCI_DEV_WKUP_UART0_FCLK_CLK 0
882 #define TISCI_DEV_WKUP_UART0_VBUSP_CLK 3
883 #define TISCI_DEV_WKUP_UART0_VBUSP_CLK_PARENT_HSDIV2_16FFT_MAIN_15_HSDIVOUT0_CLK 4
884 #define TISCI_DEV_WKUP_UART0_VBUSP_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK 5
886 #define TISCI_DEV_USB0_BUS_CLK 0
887 #define TISCI_DEV_USB0_CFG_CLK 1
888 #define TISCI_DEV_USB0_USB2_APB_PCLK_CLK 2
889 #define TISCI_DEV_USB0_USB2_REFCLOCK_CLK 3
890 #define TISCI_DEV_USB0_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 4
891 #define TISCI_DEV_USB0_USB2_REFCLOCK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT8_CLK 5
892 #define TISCI_DEV_USB0_USB2_TAP_TCK 10
894 #define TISCI_DEV_USB1_BUS_CLK 0
895 #define TISCI_DEV_USB1_CFG_CLK 1
896 #define TISCI_DEV_USB1_USB2_APB_PCLK_CLK 2
897 #define TISCI_DEV_USB1_USB2_REFCLOCK_CLK 3
898 #define TISCI_DEV_USB1_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 4
899 #define TISCI_DEV_USB1_USB2_REFCLOCK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT8_CLK 5
900 #define TISCI_DEV_USB1_USB2_TAP_TCK 10
902 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN 0
903 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT 1
904 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT 2
905 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT 3
906 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT 4
907 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT 5
908 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT 6
909 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK 7
910 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK 8
911 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_OUT 9
912 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN 10
913 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT 11
914 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT 12
915 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT 13
916 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT 14
917 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT 15
918 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT 16
919 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK 17
920 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK 18
921 #define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT 19
922 #define TISCI_DEV_BOARD0_CLKOUT0_IN 20
923 #define TISCI_DEV_BOARD0_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK5 21
924 #define TISCI_DEV_BOARD0_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK10 22
925 #define TISCI_DEV_BOARD0_CP_GEMAC_CPTS0_RFT_CLK_OUT 23
926 #define TISCI_DEV_BOARD0_DDR0_CK0_IN 24
927 #define TISCI_DEV_BOARD0_DDR0_CK0_N_IN 25
928 #define TISCI_DEV_BOARD0_DDR0_CK0_OUT 27
929 #define TISCI_DEV_BOARD0_EXT_REFCLK1_OUT 33
930 #define TISCI_DEV_BOARD0_GPMC0_CLKLB_IN 34
931 #define TISCI_DEV_BOARD0_GPMC0_CLKLB_OUT 35
932 #define TISCI_DEV_BOARD0_GPMC0_CLK_IN 36
933 #define TISCI_DEV_BOARD0_GPMC0_FCLK_MUX_IN 37
934 #define TISCI_DEV_BOARD0_GPMC0_FCLK_MUX_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK 38
935 #define TISCI_DEV_BOARD0_GPMC0_FCLK_MUX_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT7_CLK 39
936 #define TISCI_DEV_BOARD0_I2C0_SCL_IN 40
937 #define TISCI_DEV_BOARD0_I2C0_SCL_OUT 41
938 #define TISCI_DEV_BOARD0_I2C1_SCL_IN 42
939 #define TISCI_DEV_BOARD0_I2C1_SCL_OUT 43
940 #define TISCI_DEV_BOARD0_I2C2_SCL_IN 44
941 #define TISCI_DEV_BOARD0_I2C2_SCL_OUT 45
942 #define TISCI_DEV_BOARD0_I2C3_SCL_IN 46
943 #define TISCI_DEV_BOARD0_I2C3_SCL_OUT 47
944 #define TISCI_DEV_BOARD0_MCASP0_ACLKR_IN 49
945 #define TISCI_DEV_BOARD0_MCASP0_ACLKR_OUT 50
946 #define TISCI_DEV_BOARD0_MCASP0_ACLKX_IN 51
947 #define TISCI_DEV_BOARD0_MCASP0_ACLKX_OUT 52
948 #define TISCI_DEV_BOARD0_MCASP0_AFSR_IN 53
949 #define TISCI_DEV_BOARD0_MCASP0_AFSX_IN 54
950 #define TISCI_DEV_BOARD0_MCASP1_ACLKR_IN 55
951 #define TISCI_DEV_BOARD0_MCASP1_ACLKR_OUT 56
952 #define TISCI_DEV_BOARD0_MCASP1_ACLKX_IN 57
953 #define TISCI_DEV_BOARD0_MCASP1_ACLKX_OUT 58
954 #define TISCI_DEV_BOARD0_MCASP1_AFSR_IN 59
955 #define TISCI_DEV_BOARD0_MCASP1_AFSX_IN 60
956 #define TISCI_DEV_BOARD0_MCASP2_ACLKR_IN 61
957 #define TISCI_DEV_BOARD0_MCASP2_ACLKR_OUT 62
958 #define TISCI_DEV_BOARD0_MCASP2_ACLKX_IN 63
959 #define TISCI_DEV_BOARD0_MCASP2_ACLKX_OUT 64
960 #define TISCI_DEV_BOARD0_MCASP2_AFSR_IN 65
961 #define TISCI_DEV_BOARD0_MCASP2_AFSX_IN 66
962 #define TISCI_DEV_BOARD0_MCU_EXT_REFCLK0_OUT 67
963 #define TISCI_DEV_BOARD0_MCU_I2C0_SCL_OUT 69
964 #define TISCI_DEV_BOARD0_MCU_OBSCLK0_IN 70
965 #define TISCI_DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_MCU_OBSCLK_DIV_OUT0 71
966 #define TISCI_DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT 72
967 #define TISCI_DEV_BOARD0_MCU_SPI0_CLK_IN 73
968 #define TISCI_DEV_BOARD0_MCU_SPI0_CLK_OUT 74
969 #define TISCI_DEV_BOARD0_MCU_SPI1_CLK_IN 75
970 #define TISCI_DEV_BOARD0_MCU_SPI1_CLK_OUT 76
971 #define TISCI_DEV_BOARD0_MCU_SYSCLKOUT0_IN 77
972 #define TISCI_DEV_BOARD0_MCU_TIMER_IO0_IN 78
973 #define TISCI_DEV_BOARD0_MCU_TIMER_IO1_IN 79
974 #define TISCI_DEV_BOARD0_MCU_TIMER_IO2_IN 80
975 #define TISCI_DEV_BOARD0_MCU_TIMER_IO3_IN 81
976 #define TISCI_DEV_BOARD0_MDIO0_MDC_IN 82
977 #define TISCI_DEV_BOARD0_MMC0_CLKLB_IN 83
978 #define TISCI_DEV_BOARD0_MMC0_CLKLB_OUT 84
979 #define TISCI_DEV_BOARD0_MMC0_CLK_IN 85
980 #define TISCI_DEV_BOARD0_MMC0_CLK_OUT 86
981 #define TISCI_DEV_BOARD0_MMC1_CLKLB_IN 87
982 #define TISCI_DEV_BOARD0_MMC1_CLKLB_OUT 88
983 #define TISCI_DEV_BOARD0_MMC1_CLK_IN 89
984 #define TISCI_DEV_BOARD0_MMC1_CLK_OUT 90
985 #define TISCI_DEV_BOARD0_MMC2_CLKLB_IN 91
986 #define TISCI_DEV_BOARD0_MMC2_CLKLB_OUT 92
987 #define TISCI_DEV_BOARD0_MMC2_CLK_IN 93
988 #define TISCI_DEV_BOARD0_MMC2_CLK_OUT 94
989 #define TISCI_DEV_BOARD0_OBSCLK0_IN 95
990 #define TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_MAIN_OBSCLK_DIV_OUT0 96
991 #define TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT 97
992 #define TISCI_DEV_BOARD0_OBSCLK1_IN 128
993 #define TISCI_DEV_BOARD0_OSPI0_DQS_OUT 129
994 #define TISCI_DEV_BOARD0_OSPI0_LBCLKO_IN 130
995 #define TISCI_DEV_BOARD0_OSPI0_LBCLKO_OUT 131
996 #define TISCI_DEV_BOARD0_RGMII1_RXC_OUT 132
997 #define TISCI_DEV_BOARD0_RGMII1_TXC_IN 133
998 #define TISCI_DEV_BOARD0_RGMII1_TXC_OUT 134
999 #define TISCI_DEV_BOARD0_RGMII2_RXC_OUT 135
1000 #define TISCI_DEV_BOARD0_RGMII2_TXC_IN 136
1001 #define TISCI_DEV_BOARD0_RGMII2_TXC_OUT 137
1002 #define TISCI_DEV_BOARD0_RMII1_REF_CLK_OUT 138
1003 #define TISCI_DEV_BOARD0_RMII2_REF_CLK_OUT 139
1004 #define TISCI_DEV_BOARD0_SPI0_CLK_IN 140
1005 #define TISCI_DEV_BOARD0_SPI0_CLK_OUT 141
1006 #define TISCI_DEV_BOARD0_SPI1_CLK_IN 142
1007 #define TISCI_DEV_BOARD0_SPI1_CLK_OUT 143
1008 #define TISCI_DEV_BOARD0_SPI2_CLK_IN 144
1009 #define TISCI_DEV_BOARD0_SPI2_CLK_OUT 145
1010 #define TISCI_DEV_BOARD0_SYSCLKOUT0_IN 146
1011 #define TISCI_DEV_BOARD0_TCK_OUT 147
1012 #define TISCI_DEV_BOARD0_TIMER_IO0_IN 148
1013 #define TISCI_DEV_BOARD0_TIMER_IO1_IN 149
1014 #define TISCI_DEV_BOARD0_TIMER_IO2_IN 150
1015 #define TISCI_DEV_BOARD0_TIMER_IO3_IN 151
1016 #define TISCI_DEV_BOARD0_TIMER_IO4_IN 152
1017 #define TISCI_DEV_BOARD0_TIMER_IO5_IN 153
1018 #define TISCI_DEV_BOARD0_TIMER_IO6_IN 154
1019 #define TISCI_DEV_BOARD0_TIMER_IO7_IN 155
1020 #define TISCI_DEV_BOARD0_TRC_CLK_IN 156
1021 #define TISCI_DEV_BOARD0_VOUT0_EXTPCLKIN_OUT 157
1022 #define TISCI_DEV_BOARD0_VOUT0_PCLK_IN 158
1023 #define TISCI_DEV_BOARD0_WKUP_CLKOUT0_IN 159
1024 #define TISCI_DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_WKUP_CLKOUT_SEL_OUT0 160
1025 #define TISCI_DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT 161
1027 #define TISCI_DEV_CLK_32K_RC_SEL_DEV_VD_CLK 0
1028 #define TISCI_DEV_CLK_32K_RC_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 1
1029 #define TISCI_DEV_CLK_32K_RC_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT8 2
1030 #define TISCI_DEV_CLK_32K_RC_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3_DUP0 3
1031 #define TISCI_DEV_CLK_32K_RC_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_LFOSC0_CLKOUT 4
1033 #define TISCI_DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK 0
1034 #define TISCI_DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_LFOSC0_CLKOUT 1
1035 #define TISCI_DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK 2
1036 #define TISCI_DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK 3
1037 #define TISCI_DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT9_CLK 4
1038 #define TISCI_DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_CLK_32K_RC_SEL_OUT0 5
1039 #define TISCI_DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 6
1040 #define TISCI_DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 7
1042 #define TISCI_DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK 0
1043 #define TISCI_DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 1
1044 #define TISCI_DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK 2
1045 #define TISCI_DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT4_CLK 3
1046 #define TISCI_DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK_DUP0 4
1047 #define TISCI_DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 5
1048 #define TISCI_DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 6
1049 #define TISCI_DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT8 7
1050 #define TISCI_DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK 8
1051 #define TISCI_DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_CLK_32K_RC_SEL_OUT0 9
1053 #define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK 0
1054 #define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK 1
1055 #define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK 2
1056 #define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0 3
1057 #define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1 4
1058 #define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK 5
1059 #define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_15_HSDIVOUT0_CLK 6
1060 #define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV0_16FFT_MAIN_17_HSDIVOUT0_CLK 7
1061 #define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK 8
1062 #define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_CLK_32K_RC_SEL_OUT0 9
1063 #define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV2_16FFT_MAIN_5_HSDIVOUT0_CLK 10
1064 #define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_SAM62A_C7XV_WRAP_MAIN_0_CLOCK_CONTROL_0_C7XV_DIVH_CLK4_OBSCLK_OUT_CLK 11
1065 #define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK 12
1066 #define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_SAM62A_A53_512KB_WRAP_MAIN_0_ARM_COREPACK_0_A53_DIVH_CLK4_OBSCLK_OUT_CLK 13
1067 #define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_SAM62A_DDR_WRAP_MAIN_0_DDR_PLL_DIVH_CLK4_OBSCLK_OUT_CLK 14
1068 #define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 15
1069 #define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT8 16
1070 #define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0 17
1071 #define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT 18
1072 #define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 19