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AM62Ax MCU+ SDK
09.00.00
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Go to the documentation of this file.
41 #ifndef SCICLIENT_FMWMSGPARAMS_H_
42 #define SCICLIENT_FMWMSGPARAMS_H_
59 #define TISCI_PARAM_UNDEF (0xFFFFFFFFU)
69 #define SCICLIENT_FIRMWARE_ABI_MAJOR (3U)
74 #define SCICLIENT_FIRMWARE_ABI_MINOR (5U)
78 #define SCICLIENT_CONTEXT_C7X_NONSEC_0 (10U)
79 #define SCICLIENT_CONTEXT_C7X_SEC_0 (9U)
81 #define SCICLIENT_C7X_NON_SECURE_INTERRUPT_NUM (9U)
82 #define SCICLIENT_C7X_SECURE_INTERRUPT_NUM (10U)
90 #define SCICLIENT_CONTEXT_R5_SEC_0 (0U)
92 #define SCICLIENT_CONTEXT_R5_NONSEC_0 (1U)
94 #define SCICLIENT_CONTEXT_R5_SEC_1 (2U)
96 #define SCICLIENT_CONTEXT_R5_NONSEC_1 (3U)
98 #define SCICLIENT_CONTEXT_A53_SEC_0 (4U)
100 #define SCICLIENT_CONTEXT_A53_SEC_1 (5U)
102 #define SCICLIENT_CONTEXT_A53_NONSEC_1 (6U)
104 #define SCICLIENT_CONTEXT_A53_NONSEC_2 (7U)
106 #define SCICLIENT_CONTEXT_MCU_R5_0_NONSEC_0 (8U)
108 #define SCICLIENT_CONTEXT_A53_NONSEC_3 (9U)
110 #define SCICLIENT_CONTEXT_C7_NONSEC_0 (10U)
113 #define SCICLIENT_CONTEXT_MAX_NUM (11U)
126 #define SCICLIENT_PROC_ID_A53SS0_CORE_0 (0x20U)
131 #define SCICLIENT_PROC_ID_A53SS0_CORE_1 (0x21U)
136 #define SCICLIENT_PROC_ID_A53SS0_CORE_2 (0x22U)
141 #define SCICLIENT_PROC_ID_A53SS0_CORE_3 (0x23U)
146 #define SCICLIENT_PROC_ID_C7X256V0_C7XV_CORE_0 (0x04U)
151 #define SCICLIENT_PROC_ID_MCU_R5FSS0_CORE0 (0x03U)
156 #define SCICLIENT_PROC_ID_R5FSS0_CORE0 (0x01U)
161 #define SCICLIENT_PROC_ID_HSM_M4FSS0_CORE0 (0x80U)
166 #define SOC_NUM_SCICLIENT_PROCESSORS (0x08U)
172 #define TISCI_MSG_VALUE_RM_NULL_RING_TYPE (0xFFFFu)
173 #define TISCI_MSG_VALUE_RM_NULL_RING_INDEX (0xFFFFFFFFu)
174 #define TISCI_MSG_VALUE_RM_NULL_RING_ADDR (0xFFFFFFFFu)
175 #define TISCI_MSG_VALUE_RM_NULL_RING_COUNT (0xFFFFFFFFu)
181 #define TISCI_MSG_VALUE_RM_NULL_RING_MODE (0xFFu)
182 #define TISCI_MSG_VALUE_RM_NULL_RING_SIZE (0xFFu)
183 #define TISCI_MSG_VALUE_RM_NULL_ORDER_ID (0xFFu)
184 #define TISCI_MSG_VALUE_RM_UDMAP_NULL_CH_TYPE (0xFFu)
185 #define TISCI_MSG_VALUE_RM_UDMAP_NULL_CH_INDEX (0xFFFFFFFFu)
213 #define SCICLIENT_DEV_MCU_R5FSS0_CORE0 (TISCI_DEV_WKUP_R5FSS0_CORE0)
214 #define SCICLIENT_DEV_MCU_R5FSS0_CORE1 (TISCI_DEV_WKUP_R5FSS0_CORE0)
220 #define TISCI_ISC_CC_ID (160U)
229 #define TISCI_RINGACC0_OES_IRQ_SRC_IDX_START (0U)
230 #define TISCI_RINGACC0_MON_IRQ_SRC_IDX_START (1024U)
231 #define TISCI_RINGACC0_EOES_IRQ_SRC_IDX_START (2048U)
232 #define TISCI_UDMAP0_TX_OES_IRQ_SRC_IDX_START (0U)
233 #define TISCI_UDMAP0_TX_EOES_IRQ_SRC_IDX_START (512U)
234 #define TISCI_UDMAP0_RX_OES_IRQ_SRC_IDX_START (1024U)
235 #define TISCI_UDMAP0_RX_EOES_IRQ_SRC_IDX_START (1280U)
236 #define TISCI_UDMAP0_RX_FLOW_EOES_IRQ_SRC_IDX_START (1536U)
237 #define TISCI_BCDMA0_BC_RC_OES_IRQ_SRC_IDX_START (9216U)
238 #define TISCI_BCDMA0_TX_RC_OES_IRQ_SRC_IDX_START (10752U)
239 #define TISCI_BCDMA0_RX_RC_OES_IRQ_SRC_IDX_START (12288U)
240 #define TISCI_BCDMA0_BC_DC_OES_IRQ_SRC_IDX_START (8704U)
241 #define TISCI_BCDMA0_TX_DC_OES_IRQ_SRC_IDX_START (10240U)
242 #define TISCI_BCDMA0_RX_DC_OES_IRQ_SRC_IDX_START (11776U)
243 #define TISCI_PKTDMA0_TX_FLOW_OES_IRQ_SRC_IDX_START (4608U)
244 #define TISCI_PKTDMA0_RX_FLOW_OES_IRQ_SRC_IDX_START (5632U)
253 #define SCICLIENT_DEV_MCU_R5FSS0_CORE0_PROCID \
254 (SCICLIENT_PROC_ID_R5FSS0_CORE0)
255 #define SCICLIENT_DEV_MCU_R5FSS0_CORE1_PROCID \
256 (SCICLIENT_PROC_ID_R5FSS0_CORE0)
260 #define SCICLIENT_ALLOWED_BOARDCFG_BASE_START 1
262 #define SCICLIENT_ALLOWED_BOARDCFG_BASE_END 0xFFFFFFFF