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AM62Ax MCU+ SDK
08.06.00
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Go to the documentation of this file.
44 #if defined (SOC_AM62AX)
45 #include <sdl/include/am62ax/sdlr_soc_baseaddress.h>
50 #define SDL_VTM_TS_MAX_NUM (8U)
67 volatile uint8_t Resv_32[12];
73 volatile uint8_t Resv_8[4];
76 volatile uint32_t
TH2;
77 volatile uint8_t Resv_32[12];
82 volatile uint32_t
PID;
84 volatile uint8_t Resv_256[248];
86 volatile uint8_t Resv_516[4];
89 volatile uint8_t Resv_532[8];
92 volatile uint8_t Resv_548[8];
95 volatile uint8_t Resv_564[8];
98 volatile uint8_t Resv_580[8];
101 volatile uint8_t Resv_596[8];
104 volatile uint8_t Resv_768[164];
113 #define SDL_VTM_CFG1_PID (0x00000000U)
114 #define SDL_VTM_CFG1_DEVINFO_PWR0 (0x00000004U)
115 #define SDL_VTM_CFG1_VD_DEVINFO(VTM_VD) (0x00000100U+((VTM_VD)*0x20U))
116 #define SDL_VTM_CFG1_VD_OPPVID(VTM_VD) (0x00000104U+((VTM_VD)*0x20U))
117 #define SDL_VTM_CFG1_VD_EVT_STAT(VTM_VD) (0x00000108U+((VTM_VD)*0x20U))
118 #define SDL_VTM_CFG1_VD_EVT_SET(VTM_VD) (0x0000010CU+((VTM_VD)*0x20U))
119 #define SDL_VTM_CFG1_VD_EVT_CLR(VTM_VD) (0x00000110U+((VTM_VD)*0x20U))
120 #define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET (0x00000204U)
121 #define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR (0x00000208U)
122 #define SDL_VTM_CFG1_GT_TH1_INT_EN_SET (0x00000214U)
123 #define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR (0x00000218U)
124 #define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET (0x00000224U)
125 #define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR (0x00000228U)
126 #define SDL_VTM_CFG1_GT_TH2_INT_EN_SET (0x00000234U)
127 #define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR (0x00000238U)
128 #define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET (0x00000244U)
129 #define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR (0x00000248U)
130 #define SDL_VTM_CFG1_LT_TH0_INT_EN_SET (0x00000254U)
131 #define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR (0x00000258U)
132 #define SDL_VTM_CFG1_TMPSENS_CTRL(TMPSENS) (0x00000300U+((TMPSENS)*0x20U))
133 #define SDL_VTM_CFG1_TMPSENS_STAT(TMPSENS) (0x00000308U+((TMPSENS)*0x20U))
134 #define SDL_VTM_CFG1_TMPSENS_TH(TMPSENS) (0x0000030CU+((TMPSENS)*0x20U))
135 #define SDL_VTM_CFG1_TMPSENS_TH2(TMPSENS) (0x00000310U+((TMPSENS)*0x20U))
144 #define SDL_VTM_CFG1_DEVINFO_VD_MAP_MASK (0x00000F00U)
145 #define SDL_VTM_CFG1_DEVINFO_VD_MAP_SHIFT (0x00000008U)
146 #define SDL_VTM_CFG1_DEVINFO_VD_MAP_MAX (0x0000000FU)
148 #define SDL_VTM_CFG1_DEVINFO_AVS0_SUP_MASK (0x00001000U)
149 #define SDL_VTM_CFG1_DEVINFO_AVS0_SUP_SHIFT (0x0000000CU)
150 #define SDL_VTM_CFG1_DEVINFO_AVS0_SUP_MAX (0x00000001U)
154 #define SDL_VTM_CFG1_VTM_VD_OPPVID_OPP_0_MASK (0x000000FFU)
155 #define SDL_VTM_CFG1_VTM_VD_OPPVID_OPP_0_SHIFT (0x00000000U)
156 #define SDL_VTM_CFG1_VTM_VD_OPPVID_OPP_0_MAX (0x000000FFU)
158 #define SDL_VTM_CFG1_VTM_VD_OPPVID_OPP_1_MASK (0x0000FF00U)
159 #define SDL_VTM_CFG1_VTM_VD_OPPVID_OPP_1_SHIFT (0x00000008U)
160 #define SDL_VTM_CFG1_VTM_VD_OPPVID_OPP_1_MAX (0x000000FFU)
162 #define SDL_VTM_CFG1_VTM_VD_OPPVID_OPP_2_MASK (0x00FF0000U)
163 #define SDL_VTM_CFG1_VTM_VD_OPPVID_OPP_2_SHIFT (0x00000010U)
164 #define SDL_VTM_CFG1_VTM_VD_OPPVID_OPP_2_MAX (0x000000FFU)
166 #define SDL_VTM_CFG1_VTM_VD_OPPVID_OPP_3_MASK (0xFF000000U)
167 #define SDL_VTM_CFG1_VTM_VD_OPPVID_OPP_3_SHIFT (0x00000018U)
168 #define SDL_VTM_CFG1_VTM_VD_OPPVID_OPP_3_MAX (0x000000FFU)
172 #define SDL_VTM_CFG1_OPPVID_OPP_LOW_DFLT_MASK (0x000000FFU)
173 #define SDL_VTM_CFG1_OPPVID_OPP_LOW_DFLT_SHIFT (0x00000000U)
174 #define SDL_VTM_CFG1_OPPVID_OPP_LOW_DFLT_MAX (0x000000FFU)
176 #define SDL_VTM_CFG1_OPPVID_OPP_NOM_DFLT_MASK (0x0000FF00U)
177 #define SDL_VTM_CFG1_OPPVID_OPP_NOM_DFLT_SHIFT (0x00000008U)
178 #define SDL_VTM_CFG1_OPPVID_OPP_NOM_DFLT_MAX (0x000000FFU)
180 #define SDL_VTM_CFG1_OPPVID_OPP_ODR_DFLT_MASK (0x00FF0000U)
181 #define SDL_VTM_CFG1_OPPVID_OPP_ODR_DFLT_SHIFT (0x00000010U)
182 #define SDL_VTM_CFG1_OPPVID_OPP_ODR_DFLT_MAX (0x000000FFU)
184 #define SDL_VTM_CFG1_OPPVID_OPP_TRB_DFLT_MASK (0xFF000000U)
185 #define SDL_VTM_CFG1_OPPVID_OPP_TRB_DFLT_SHIFT (0x00000018U)
186 #define SDL_VTM_CFG1_OPPVID_OPP_TRB_DFLT_MAX (0x000000FFU)
190 #define SDL_VTM_CFG1_EVT_STAT_GT_TH1_ALERT_MASK (0x00000001U)
191 #define SDL_VTM_CFG1_EVT_STAT_GT_TH1_ALERT_SHIFT (0x00000000U)
192 #define SDL_VTM_CFG1_EVT_STAT_GT_TH1_ALERT_MAX (0x00000001U)
194 #define SDL_VTM_CFG1_EVT_STAT_GT_TH2_ALERT_MASK (0x00000002U)
195 #define SDL_VTM_CFG1_EVT_STAT_GT_TH2_ALERT_SHIFT (0x00000001U)
196 #define SDL_VTM_CFG1_EVT_STAT_GT_TH2_ALERT_MAX (0x00000001U)
198 #define SDL_VTM_CFG1_EVT_STAT_LT_TH0_ALERT_MASK (0x00000004U)
199 #define SDL_VTM_CFG1_EVT_STAT_LT_TH0_ALERT_SHIFT (0x00000002U)
200 #define SDL_VTM_CFG1_EVT_STAT_LT_TH0_ALERT_MAX (0x00000001U)
204 #define SDL_VTM_CFG1_EVT_SET_TSENS_EVT_SEL_MASK (0x00FF0000U)
205 #define SDL_VTM_CFG1_EVT_SET_TSENS_EVT_SEL_SHIFT (0x00000010U)
206 #define SDL_VTM_CFG1_EVT_SET_TSENS_EVT_SEL_MAX (0x000000FFU)
210 #define SDL_VTM_CFG1_EVT_CLR_TSENS_EVT_SEL_MASK (0x00FF0000U)
211 #define SDL_VTM_CFG1_EVT_CLR_TSENS_EVT_SEL_SHIFT (0x00000010U)
212 #define SDL_VTM_CFG1_EVT_CLR_TSENS_EVT_SEL_MAX (0x000000FFU)
216 #define SDL_VTM_CFG1_TMPSENS_CTRL_GT_TH1_EN_MASK (0x00000100U)
217 #define SDL_VTM_CFG1_TMPSENS_CTRL_GT_TH1_EN_SHIFT (0x00000008U)
218 #define SDL_VTM_CFG1_TMPSENS_CTRL_GT_TH1_EN_MAX (0x00000001U)
220 #define SDL_VTM_CFG1_TMPSENS_CTRL_GT_TH2_EN_MASK (0x00000200U)
221 #define SDL_VTM_CFG1_TMPSENS_CTRL_GT_TH2_EN_SHIFT (0x00000009U)
222 #define SDL_VTM_CFG1_TMPSENS_CTRL_GT_TH2_EN_MAX (0x00000001U)
224 #define SDL_VTM_CFG1_TMPSENS_CTRL_LT_TH0_EN_MASK (0x00000400U)
225 #define SDL_VTM_CFG1_TMPSENS_CTRL_LT_TH0_EN_SHIFT (0x0000000AU)
226 #define SDL_VTM_CFG1_TMPSENS_CTRL_LT_TH0_EN_MAX (0x00000001U)
230 #define SDL_VTM_CFG1_TMPSENS_STAT_DATA_OUT_MASK (0x000003FFU)
231 #define SDL_VTM_CFG1_TMPSENS_STAT_DATA_OUT_SHIFT (0x00000000U)
232 #define SDL_VTM_CFG1_TMPSENS_STAT_DATA_OUT_MAX (0x000003FFU)
234 #define SDL_VTM_CFG1_TMPSENS_STAT_DATA_VALID_MASK (0x00000400U)
235 #define SDL_VTM_CFG1_TMPSENS_STAT_DATA_VALID_SHIFT (0x0000000AU)
236 #define SDL_VTM_CFG1_TMPSENS_STAT_DATA_VALID_MAX (0x00000001U)
238 #define SDL_VTM_CFG1_TMPSENS_STAT_EOC_FC_UPDATE_MASK (0x00000800U)
239 #define SDL_VTM_CFG1_TMPSENS_STAT_EOC_FC_UPDATE_SHIFT (0x0000000BU)
240 #define SDL_VTM_CFG1_TMPSENS_STAT_EOC_FC_UPDATE_MAX (0x00000001U)
242 #define SDL_VTM_CFG1_TMPSENS_STAT_GT_TH1_ALERT_MASK (0x00001000U)
243 #define SDL_VTM_CFG1_TMPSENS_STAT_GT_TH1_ALERT_SHIFT (0x0000000CU)
244 #define SDL_VTM_CFG1_TMPSENS_STAT_GT_TH1_ALERT_MAX (0x00000001U)
246 #define SDL_VTM_CFG1_TMPSENS_STAT_GT_TH2_ALERT_MASK (0x00002000U)
247 #define SDL_VTM_CFG1_TMPSENS_STAT_GT_TH2_ALERT_SHIFT (0x0000000DU)
248 #define SDL_VTM_CFG1_TMPSENS_STAT_GT_TH2_ALERT_MAX (0x00000001U)
250 #define SDL_VTM_CFG1_TMPSENS_STAT_LT_TH0_ALERT_MASK (0x00004000U)
251 #define SDL_VTM_CFG1_TMPSENS_STAT_LT_TH0_ALERT_SHIFT (0x0000000EU)
252 #define SDL_VTM_CFG1_TMPSENS_STAT_LT_TH0_ALERT_MAX (0x00000001U)
254 #define SDL_VTM_CFG1_TMPSENS_STAT_MAXT_OUTRG_ALERT_MASK (0x00008000U)
255 #define SDL_VTM_CFG1_TMPSENS_STAT_MAXT_OUTRG_ALERT_SHIFT (0x0000000FU)
256 #define SDL_VTM_CFG1_TMPSENS_STAT_MAXT_OUTRG_ALERT_MAX (0x00000001U)
258 #define SDL_VTM_CFG1_TMPSENS_STAT_VD_MAP_MASK (0x000F0000U)
259 #define SDL_VTM_CFG1_TMPSENS_STAT_VD_MAP_SHIFT (0x00000010U)
260 #define SDL_VTM_CFG1_TMPSENS_STAT_VD_MAP_MAX (0x0000000FU)
264 #define SDL_VTM_CFG1_TMPSENS_STAT_DTEMP_MASK (0x000003FFU)
265 #define SDL_VTM_CFG1_TMPSENS_STAT_DTEMP_SHIFT (0x00000000U)
266 #define SDL_VTM_CFG1_TMPSENS_STAT_DTEMP_MAX (0x000003FFU)
268 #define SDL_VTM_CFG1_TMPSENS_STAT_EOCZ_MASK (0x00000400U)
269 #define SDL_VTM_CFG1_TMPSENS_STAT_EOCZ_SHIFT (0x0000000AU)
270 #define SDL_VTM_CFG1_TMPSENS_STAT_EOCZ_MAX (0x00000001U)
274 #define SDL_VTM_CFG1_TMPSENS_TH_TH0_VAL_MASK (0x000003FFU)
275 #define SDL_VTM_CFG1_TMPSENS_TH_TH0_VAL_SHIFT (0x00000000U)
276 #define SDL_VTM_CFG1_TMPSENS_TH_TH0_VAL_MAX (0x000003FFU)
278 #define SDL_VTM_CFG1_TMPSENS_TH_TH1_VAL_MASK (0x03FF0000U)
279 #define SDL_VTM_CFG1_TMPSENS_TH_TH1_VAL_SHIFT (0x00000010U)
280 #define SDL_VTM_CFG1_TMPSENS_TH_TH1_VAL_MAX (0x000003FFU)
284 #define SDL_VTM_CFG1_TMPSENS_TH2_TH2_VAL_MASK (0x000003FFU)
285 #define SDL_VTM_CFG1_TMPSENS_TH2_TH2_VAL_SHIFT (0x00000000U)
286 #define SDL_VTM_CFG1_TMPSENS_TH2_TH2_VAL_MAX (0x000003FFU)
290 #define SDL_VTM_CFG1_PID_Y_MINOR_MASK (0x0000003FU)
291 #define SDL_VTM_CFG1_PID_Y_MINOR_SHIFT (0x00000000U)
292 #define SDL_VTM_CFG1_PID_Y_MINOR_MAX (0x0000003FU)
294 #define SDL_VTM_CFG1_PID_CUSTOM_MASK (0x000000C0U)
295 #define SDL_VTM_CFG1_PID_CUSTOM_SHIFT (0x00000006U)
296 #define SDL_VTM_CFG1_PID_CUSTOM_MAX (0x00000003U)
298 #define SDL_VTM_CFG1_PID_X_MAJOR_MASK (0x00000700U)
299 #define SDL_VTM_CFG1_PID_X_MAJOR_SHIFT (0x00000008U)
300 #define SDL_VTM_CFG1_PID_X_MAJOR_MAX (0x00000007U)
302 #define SDL_VTM_CFG1_PID_R_RTL_MASK (0x0000F800U)
303 #define SDL_VTM_CFG1_PID_R_RTL_SHIFT (0x0000000BU)
304 #define SDL_VTM_CFG1_PID_R_RTL_MAX (0x0000001FU)
306 #define SDL_VTM_CFG1_PID_FUNC_MASK (0x0FFF0000U)
307 #define SDL_VTM_CFG1_PID_FUNC_SHIFT (0x00000010U)
308 #define SDL_VTM_CFG1_PID_FUNC_MAX (0x00000FFFU)
310 #define SDL_VTM_CFG1_PID_BU_MASK (0x30000000U)
311 #define SDL_VTM_CFG1_PID_BU_SHIFT (0x0000001CU)
312 #define SDL_VTM_CFG1_PID_BU_MAX (0x00000003U)
314 #define SDL_VTM_CFG1_PID_SCHEME_MASK (0xC0000000U)
315 #define SDL_VTM_CFG1_PID_SCHEME_SHIFT (0x0000001EU)
316 #define SDL_VTM_CFG1_PID_SCHEME_MAX (0x00000003U)
320 #define SDL_VTM_CFG1_DEVINFO_PWR0_CVD_CT_MASK (0x0000000FU)
321 #define SDL_VTM_CFG1_DEVINFO_PWR0_CVD_CT_SHIFT (0x00000000U)
322 #define SDL_VTM_CFG1_DEVINFO_PWR0_CVD_CT_MAX (0x0000000FU)
324 #define SDL_VTM_CFG1_DEVINFO_PWR0_TMPSENS_CT_MASK (0x000000F0U)
325 #define SDL_VTM_CFG1_DEVINFO_PWR0_TMPSENS_CT_SHIFT (0x00000004U)
326 #define SDL_VTM_CFG1_DEVINFO_PWR0_TMPSENS_CT_MAX (0x0000000FU)
328 #define SDL_VTM_CFG1_DEVINFO_PWR0_VDD_RTC_MASK (0x00001000U)
329 #define SDL_VTM_CFG1_DEVINFO_PWR0_VDD_RTC_SHIFT (0x0000000CU)
330 #define SDL_VTM_CFG1_DEVINFO_PWR0_VDD_RTC_MAX (0x00000001U)
332 #define SDL_VTM_CFG1_DEVINFO_PWR0_VTM_VD_MAP_MASK (0x000F0000U)
333 #define SDL_VTM_CFG1_DEVINFO_PWR0_VTM_VD_MAP_SHIFT (0x00000010U)
334 #define SDL_VTM_CFG1_DEVINFO_PWR0_VTM_VD_MAP_MAX (0x0000000FU)
338 #define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD_MASK (0x000000FFU)
339 #define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD_SHIFT (0x00000000U)
340 #define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD_MAX (0x000000FFU)
344 #define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD_MASK (0x000000FFU)
345 #define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD_SHIFT (0x00000000U)
346 #define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD_MAX (0x000000FFU)
350 #define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD_MASK (0x000000FFU)
351 #define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD_SHIFT (0x00000000U)
352 #define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD_MAX (0x000000FFU)
356 #define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD_MASK (0x000000FFU)
357 #define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD_SHIFT (0x00000000U)
358 #define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD_MAX (0x000000FFU)
362 #define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD_MASK (0x000000FFU)
363 #define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD_SHIFT (0x00000000U)
364 #define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD_MAX (0x000000FFU)
368 #define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD_MASK (0x000000FFU)
369 #define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD_SHIFT (0x00000000U)
370 #define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD_MAX (0x000000FFU)
374 #define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD_MASK (0x000000FFU)
375 #define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD_SHIFT (0x00000000U)
376 #define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD_MAX (0x000000FFU)
380 #define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD_MASK (0x000000FFU)
381 #define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD_SHIFT (0x00000000U)
382 #define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD_MAX (0x000000FFU)
386 #define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD_MASK (0x000000FFU)
387 #define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD_SHIFT (0x00000000U)
388 #define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD_MAX (0x000000FFU)
392 #define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD_MASK (0x000000FFU)
393 #define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD_SHIFT (0x00000000U)
394 #define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD_MAX (0x000000FFU)
398 #define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD_MASK (0x000000FFU)
399 #define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD_SHIFT (0x00000000U)
400 #define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD_MAX (0x000000FFU)
404 #define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD_MASK (0x000000FFU)
405 #define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD_SHIFT (0x00000000U)
406 #define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD_MAX (0x000000FFU)
412 #define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD0_MASK (0x00000001U)
413 #define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD0_SHIFT (0x00000000U)
414 #define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD0_MAX (0x00000001U)
416 #define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD1_MASK (0x00000002U)
417 #define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD1_SHIFT (0x00000001U)
418 #define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD1_MAX (0x00000001U)
420 #define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD2_MASK (0x00000004U)
421 #define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD2_SHIFT (0x00000002U)
422 #define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD2_MAX (0x00000001U)
424 #define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD3_MASK (0x00000008U)
425 #define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD3_SHIFT (0x00000003U)
426 #define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD3_MAX (0x00000001U)
428 #define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD4_MASK (0x00000010U)
429 #define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD4_SHIFT (0x00000004U)
430 #define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD4_MAX (0x00000001U)
432 #define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD5_MASK (0x00000020U)
433 #define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD5_SHIFT (0x00000005U)
434 #define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD5_MAX (0x00000001U)
436 #define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD6_MASK (0x00000040U)
437 #define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD6_SHIFT (0x00000006U)
438 #define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD6_MAX (0x00000001U)
440 #define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD7_MASK (0x00000080U)
441 #define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD7_SHIFT (0x00000007U)
442 #define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD7_MAX (0x00000001U)
446 #define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD0_MASK (0x00000001U)
447 #define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD0_SHIFT (0x00000000U)
448 #define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD0_MAX (0x00000001U)
450 #define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD1_MASK (0x00000002U)
451 #define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD1_SHIFT (0x00000001U)
452 #define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD1_MAX (0x00000001U)
454 #define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD2_MASK (0x00000004U)
455 #define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD2_SHIFT (0x00000002U)
456 #define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD2_MAX (0x00000001U)
458 #define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD3_MASK (0x00000008U)
459 #define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD3_SHIFT (0x00000003U)
460 #define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD3_MAX (0x00000001U)
462 #define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD4_MASK (0x00000010U)
463 #define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD4_SHIFT (0x00000004U)
464 #define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD4_MAX (0x00000001U)
466 #define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD5_MASK (0x00000020U)
467 #define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD5_SHIFT (0x00000005U)
468 #define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD5_MAX (0x00000001U)
470 #define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD6_MASK (0x00000040U)
471 #define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD6_SHIFT (0x00000006U)
472 #define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD6_MAX (0x00000001U)
474 #define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD7_MASK (0x00000080U)
475 #define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD7_SHIFT (0x00000007U)
476 #define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD7_MAX (0x00000001U)
480 #define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD0_MASK (0x00000001U)
481 #define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD0_SHIFT (0x00000000U)
482 #define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD0_MAX (0x00000001U)
484 #define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD1_MASK (0x00000002U)
485 #define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD1_SHIFT (0x00000001U)
486 #define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD1_MAX (0x00000001U)
488 #define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD2_MASK (0x00000004U)
489 #define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD2_SHIFT (0x00000002U)
490 #define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD2_MAX (0x00000001U)
492 #define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD3_MASK (0x00000008U)
493 #define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD3_SHIFT (0x00000003U)
494 #define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD3_MAX (0x00000001U)
496 #define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD4_MASK (0x00000010U)
497 #define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD4_SHIFT (0x00000004U)
498 #define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD4_MAX (0x00000001U)
500 #define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD5_MASK (0x00000020U)
501 #define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD5_SHIFT (0x00000005U)
502 #define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD5_MAX (0x00000001U)
504 #define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD6_MASK (0x00000040U)
505 #define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD6_SHIFT (0x00000006U)
506 #define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD6_MAX (0x00000001U)
508 #define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD7_MASK (0x00000080U)
509 #define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD7_SHIFT (0x00000007U)
510 #define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD7_MAX (0x00000001U)
514 #define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD0_MASK (0x00000001U)
515 #define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD0_SHIFT (0x00000000U)
516 #define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD0_MAX (0x00000001U)
518 #define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD1_MASK (0x00000002U)
519 #define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD1_SHIFT (0x00000001U)
520 #define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD1_MAX (0x00000001U)
522 #define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD2_MASK (0x00000004U)
523 #define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD2_SHIFT (0x00000002U)
524 #define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD2_MAX (0x00000001U)
526 #define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD3_MASK (0x00000008U)
527 #define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD3_SHIFT (0x00000003U)
528 #define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD3_MAX (0x00000001U)
530 #define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD4_MASK (0x00000010U)
531 #define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD4_SHIFT (0x00000004U)
532 #define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD4_MAX (0x00000001U)
534 #define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD5_MASK (0x00000020U)
535 #define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD5_SHIFT (0x00000005U)
536 #define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD5_MAX (0x00000001U)
538 #define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD6_MASK (0x00000040U)
539 #define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD6_SHIFT (0x00000006U)
540 #define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD6_MAX (0x00000001U)
542 #define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD7_MASK (0x00000080U)
543 #define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD7_SHIFT (0x00000007U)
544 #define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD7_MAX (0x00000001U)
548 #define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD0_MASK (0x00000001U)
549 #define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD0_SHIFT (0x00000000U)
550 #define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD0_MAX (0x00000001U)
552 #define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD1_MASK (0x00000002U)
553 #define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD1_SHIFT (0x00000001U)
554 #define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD1_MAX (0x00000001U)
556 #define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD2_MASK (0x00000004U)
557 #define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD2_SHIFT (0x00000002U)
558 #define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD2_MAX (0x00000001U)
560 #define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD3_MASK (0x00000008U)
561 #define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD3_SHIFT (0x00000003U)
562 #define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD3_MAX (0x00000001U)
564 #define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD4_MASK (0x00000010U)
565 #define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD4_SHIFT (0x00000004U)
566 #define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD4_MAX (0x00000001U)
568 #define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD5_MASK (0x00000020U)
569 #define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD5_SHIFT (0x00000005U)
570 #define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD5_MAX (0x00000001U)
572 #define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD6_MASK (0x00000040U)
573 #define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD6_SHIFT (0x00000006U)
574 #define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD6_MAX (0x00000001U)
576 #define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD7_MASK (0x00000080U)
577 #define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD7_SHIFT (0x00000007U)
578 #define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD7_MAX (0x00000001U)
582 #define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD0_MASK (0x00000001U)
583 #define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD0_SHIFT (0x00000000U)
584 #define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD0_MAX (0x00000001U)
586 #define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD1_MASK (0x00000002U)
587 #define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD1_SHIFT (0x00000001U)
588 #define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD1_MAX (0x00000001U)
590 #define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD2_MASK (0x00000004U)
591 #define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD2_SHIFT (0x00000002U)
592 #define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD2_MAX (0x00000001U)
594 #define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD3_MASK (0x00000008U)
595 #define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD3_SHIFT (0x00000003U)
596 #define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD3_MAX (0x00000001U)
598 #define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD4_MASK (0x00000010U)
599 #define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD4_SHIFT (0x00000004U)
600 #define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD4_MAX (0x00000001U)
602 #define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD5_MASK (0x00000020U)
603 #define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD5_SHIFT (0x00000005U)
604 #define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD5_MAX (0x00000001U)
606 #define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD6_MASK (0x00000040U)
607 #define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD6_SHIFT (0x00000006U)
608 #define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD6_MAX (0x00000001U)
610 #define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD7_MASK (0x00000080U)
611 #define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD7_SHIFT (0x00000007U)
612 #define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD7_MAX (0x00000001U)
616 #define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD0_MASK (0x00000001U)
617 #define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD0_SHIFT (0x00000000U)
618 #define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD0_MAX (0x00000001U)
620 #define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD1_MASK (0x00000002U)
621 #define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD1_SHIFT (0x00000001U)
622 #define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD1_MAX (0x00000001U)
624 #define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD2_MASK (0x00000004U)
625 #define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD2_SHIFT (0x00000002U)
626 #define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD2_MAX (0x00000001U)
628 #define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD3_MASK (0x00000008U)
629 #define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD3_SHIFT (0x00000003U)
630 #define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD3_MAX (0x00000001U)
632 #define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD4_MASK (0x00000010U)
633 #define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD4_SHIFT (0x00000004U)
634 #define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD4_MAX (0x00000001U)
636 #define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD5_MASK (0x00000020U)
637 #define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD5_SHIFT (0x00000005U)
638 #define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD5_MAX (0x00000001U)
640 #define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD6_MASK (0x00000040U)
641 #define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD6_SHIFT (0x00000006U)
642 #define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD6_MAX (0x00000001U)
644 #define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD7_MASK (0x00000080U)
645 #define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD7_SHIFT (0x00000007U)
646 #define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD7_MAX (0x00000001U)
650 #define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD0_MASK (0x00000001U)
651 #define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD0_SHIFT (0x00000000U)
652 #define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD0_MAX (0x00000001U)
654 #define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD1_MASK (0x00000002U)
655 #define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD1_SHIFT (0x00000001U)
656 #define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD1_MAX (0x00000001U)
658 #define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD2_MASK (0x00000004U)
659 #define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD2_SHIFT (0x00000002U)
660 #define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD2_MAX (0x00000001U)
662 #define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD3_MASK (0x00000008U)
663 #define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD3_SHIFT (0x00000003U)
664 #define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD3_MAX (0x00000001U)
666 #define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD4_MASK (0x00000010U)
667 #define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD4_SHIFT (0x00000004U)
668 #define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD4_MAX (0x00000001U)
670 #define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD5_MASK (0x00000020U)
671 #define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD5_SHIFT (0x00000005U)
672 #define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD5_MAX (0x00000001U)
674 #define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD6_MASK (0x00000040U)
675 #define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD6_SHIFT (0x00000006U)
676 #define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD6_MAX (0x00000001U)
678 #define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD7_MASK (0x00000080U)
679 #define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD7_SHIFT (0x00000007U)
680 #define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD7_MAX (0x00000001U)
684 #define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD0_MASK (0x00000001U)
685 #define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD0_SHIFT (0x00000000U)
686 #define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD0_MAX (0x00000001U)
688 #define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD1_MASK (0x00000002U)
689 #define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD1_SHIFT (0x00000001U)
690 #define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD1_MAX (0x00000001U)
692 #define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD2_MASK (0x00000004U)
693 #define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD2_SHIFT (0x00000002U)
694 #define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD2_MAX (0x00000001U)
696 #define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD3_MASK (0x00000008U)
697 #define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD3_SHIFT (0x00000003U)
698 #define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD3_MAX (0x00000001U)
700 #define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD4_MASK (0x00000010U)
701 #define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD4_SHIFT (0x00000004U)
702 #define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD4_MAX (0x00000001U)
704 #define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD5_MASK (0x00000020U)
705 #define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD5_SHIFT (0x00000005U)
706 #define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD5_MAX (0x00000001U)
708 #define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD6_MASK (0x00000040U)
709 #define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD6_SHIFT (0x00000006U)
710 #define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD6_MAX (0x00000001U)
712 #define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD7_MASK (0x00000080U)
713 #define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD7_SHIFT (0x00000007U)
714 #define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD7_MAX (0x00000001U)
718 #define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD0_MASK (0x00000001U)
719 #define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD0_SHIFT (0x00000000U)
720 #define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD0_MAX (0x00000001U)
722 #define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD1_MASK (0x00000002U)
723 #define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD1_SHIFT (0x00000001U)
724 #define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD1_MAX (0x00000001U)
726 #define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD2_MASK (0x00000004U)
727 #define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD2_SHIFT (0x00000002U)
728 #define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD2_MAX (0x00000001U)
730 #define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD3_MASK (0x00000008U)
731 #define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD3_SHIFT (0x00000003U)
732 #define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD3_MAX (0x00000001U)
734 #define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD4_MASK (0x00000010U)
735 #define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD4_SHIFT (0x00000004U)
736 #define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD4_MAX (0x00000001U)
738 #define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD5_MASK (0x00000020U)
739 #define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD5_SHIFT (0x00000005U)
740 #define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD5_MAX (0x00000001U)
742 #define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD6_MASK (0x00000040U)
743 #define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD6_SHIFT (0x00000006U)
744 #define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD6_MAX (0x00000001U)
746 #define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD7_MASK (0x00000080U)
747 #define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD7_SHIFT (0x00000007U)
748 #define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD7_MAX (0x00000001U)
752 #define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD0_MASK (0x00000001U)
753 #define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD0_SHIFT (0x00000000U)
754 #define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD0_MAX (0x00000001U)
756 #define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD1_MASK (0x00000002U)
757 #define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD1_SHIFT (0x00000001U)
758 #define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD1_MAX (0x00000001U)
760 #define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD2_MASK (0x00000004U)
761 #define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD2_SHIFT (0x00000002U)
762 #define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD2_MAX (0x00000001U)
764 #define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD3_MASK (0x00000008U)
765 #define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD3_SHIFT (0x00000003U)
766 #define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD3_MAX (0x00000001U)
768 #define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD4_MASK (0x00000010U)
769 #define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD4_SHIFT (0x00000004U)
770 #define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD4_MAX (0x00000001U)
772 #define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD5_MASK (0x00000020U)
773 #define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD5_SHIFT (0x00000005U)
774 #define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD5_MAX (0x00000001U)
776 #define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD6_MASK (0x00000040U)
777 #define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD6_SHIFT (0x00000006U)
778 #define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD6_MAX (0x00000001U)
780 #define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD7_MASK (0x00000080U)
781 #define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD7_SHIFT (0x00000007U)
782 #define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD7_MAX (0x00000001U)
786 #define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD0_MASK (0x00000001U)
787 #define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD0_SHIFT (0x00000000U)
788 #define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD0_MAX (0x00000001U)
790 #define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD1_MASK (0x00000002U)
791 #define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD1_SHIFT (0x00000001U)
792 #define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD1_MAX (0x00000001U)
794 #define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD2_MASK (0x00000004U)
795 #define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD2_SHIFT (0x00000002U)
796 #define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD2_MAX (0x00000001U)
798 #define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD3_MASK (0x00000008U)
799 #define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD3_SHIFT (0x00000003U)
800 #define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD3_MAX (0x00000001U)
802 #define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD4_MASK (0x00000010U)
803 #define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD4_SHIFT (0x00000004U)
804 #define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD4_MAX (0x00000001U)
806 #define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD5_MASK (0x00000020U)
807 #define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD5_SHIFT (0x00000005U)
808 #define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD5_MAX (0x00000001U)
810 #define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD6_MASK (0x00000040U)
811 #define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD6_SHIFT (0x00000006U)
812 #define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD6_MAX (0x00000001U)
814 #define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD7_MASK (0x00000080U)
815 #define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD7_SHIFT (0x00000007U)
816 #define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD7_MAX (0x00000001U)
830 volatile uint8_t Resv_32[24];
835 volatile uint8_t Resv_8[8];
839 volatile uint8_t Resv_32[12];
841 volatile uint8_t Resv_768[732];
850 #define SDL_VTM_CFG2_CLK_CTRL (0x00000008U)
851 #define SDL_VTM_CFG2_MISC_CTRL (0x0000000CU)
852 #define SDL_VTM_CFG2_MISC_CTRL2 (0x00000010U)
853 #define SDL_VTM_CFG2_SAMPLE_CTRL (0x00000020U)
854 #define SDL_VTM_CFG2_TMPSENS_CTRL(TMPSENS) (0x00000300U+((TMPSENS)*0x20U))
855 #define SDL_VTM_CFG2_TMPSENS_TRIM(TMPSENS) (0x00000304U+((TMPSENS)*0x20U))
864 #define SDL_VTM_CFG2_TMPSENS_CTRL_CONT_MASK (0x00000010U)
865 #define SDL_VTM_CFG2_TMPSENS_CTRL_CONT_SHIFT (0x00000004U)
866 #define SDL_VTM_CFG2_TMPSENS_CTRL_CONT_MAX (0x00000001U)
868 #define SDL_VTM_CFG2_TMPSENS_CTRL_SOC_MASK (0x00000020U)
869 #define SDL_VTM_CFG2_TMPSENS_CTRL_SOC_SHIFT (0x00000005U)
870 #define SDL_VTM_CFG2_TMPSENS_CTRL_SOC_MAX (0x00000001U)
872 #define SDL_VTM_CFG2_TMPSENS_CTRL_CLRZ_MASK (0x00000040U)
873 #define SDL_VTM_CFG2_TMPSENS_CTRL_CLRZ_SHIFT (0x00000006U)
874 #define SDL_VTM_CFG2_TMPSENS_CTRL_CLRZ_MAX (0x00000001U)
876 #define SDL_VTM_CFG2_TMPSENS_CTRL_MAXT_OUTRG_EN_MASK (0x00000800U)
877 #define SDL_VTM_CFG2_TMPSENS_CTRL_MAXT_OUTRG_EN_SHIFT (0x0000000BU)
878 #define SDL_VTM_CFG2_TMPSENS_CTRL_MAXT_OUTRG_EN_MAX (0x00000001U)
882 #define SDL_VTM_CFG2_TMPSENS_TRIM_TRIMG_MASK (0x0000001FU)
883 #define SDL_VTM_CFG2_TMPSENS_TRIM_TRIMG_SHIFT (0x00000000U)
884 #define SDL_VTM_CFG2_TMPSENS_TRIM_TRIMG_MAX (0x0000001FU)
886 #define SDL_VTM_CFG2_TMPSENS_TRIM_TRIMO_MASK (0x00003F00U)
887 #define SDL_VTM_CFG2_TMPSENS_TRIM_TRIMO_SHIFT (0x00000008U)
888 #define SDL_VTM_CFG2_TMPSENS_TRIM_TRIMO_MAX (0x0000003FU)
892 #define SDL_VTM_CFG2_CLK_CTRL_TSENS_CLK_SEL_MASK (0x80000000U)
893 #define SDL_VTM_CFG2_CLK_CTRL_TSENS_CLK_SEL_SHIFT (0x0000001FU)
894 #define SDL_VTM_CFG2_CLK_CTRL_TSENS_CLK_SEL_MAX (0x00000001U)
896 #define SDL_VTM_CFG2_CLK_CTRL_TSENS_CLK_DIV_MASK (0x0000001FU)
897 #define SDL_VTM_CFG2_CLK_CTRL_TSENS_CLK_DIV_SHIFT (0x00000000U)
898 #define SDL_VTM_CFG2_CLK_CTRL_TSENS_CLK_DIV_MAX (0x0000001FU)
902 #define SDL_VTM_CFG2_MISC_CTRL_ANY_MAXT_OUTRG_ALERT_EN_MASK (0x00000001U)
903 #define SDL_VTM_CFG2_MISC_CTRL_ANY_MAXT_OUTRG_ALERT_EN_SHIFT (0x00000000U)
904 #define SDL_VTM_CFG2_MISC_CTRL_ANY_MAXT_OUTRG_ALERT_EN_MAX (0x00000001U)
908 #define SDL_VTM_CFG2_MISC_CTRL2_MAXT_OUTRG_ALERT_THR0_MASK (0x03FF0000U)
909 #define SDL_VTM_CFG2_MISC_CTRL2_MAXT_OUTRG_ALERT_THR0_SHIFT (0x00000010U)
910 #define SDL_VTM_CFG2_MISC_CTRL2_MAXT_OUTRG_ALERT_THR0_MAX (0x000003FFU)
912 #define SDL_VTM_CFG2_MISC_CTRL2_MAXT_OUTRG_ALERT_THR_MASK (0x000003FFU)
913 #define SDL_VTM_CFG2_MISC_CTRL2_MAXT_OUTRG_ALERT_THR_SHIFT (0x00000000U)
914 #define SDL_VTM_CFG2_MISC_CTRL2_MAXT_OUTRG_ALERT_THR_MAX (0x000003FFU)
918 #define SDL_VTM_CFG2_SAMPLE_CTRL_SAMPLE_PER_CNT_MASK (0x0000FFFFU)
919 #define SDL_VTM_CFG2_SAMPLE_CTRL_SAMPLE_PER_CNT_SHIFT (0x00000000U)
920 #define SDL_VTM_CFG2_SAMPLE_CTRL_SAMPLE_PER_CNT_MAX (0x0000FFFFU)
Definition: sdlr_vtm.h:61
volatile uint32_t LT_TH0_INT_EN_STAT_CLR
Definition: sdlr_vtm.h:100
volatile uint32_t GT_TH2_INT_EN_SET
Definition: sdlr_vtm.h:96
Definition: sdlr_vtm.h:81
volatile uint32_t TH2
Definition: sdlr_vtm.h:76
volatile uint32_t GT_TH1_INT_RAW_STAT_SET
Definition: sdlr_vtm.h:87
volatile uint32_t DEVINFO_PWR0
Definition: sdlr_vtm.h:83
volatile uint32_t CTRL
Definition: sdlr_vtm.h:72
volatile uint32_t GT_TH2_INT_RAW_STAT_SET
Definition: sdlr_vtm.h:93
volatile uint32_t MISC_CTRL
Definition: sdlr_vtm.h:837
volatile uint32_t CLK_CTRL
Definition: sdlr_vtm.h:836
volatile uint32_t MISC_CTRL2
Definition: sdlr_vtm.h:838
volatile uint32_t GT_TH1_INT_EN_SET
Definition: sdlr_vtm.h:90
volatile uint32_t DEVINFO
Definition: sdlr_vtm.h:62
Definition: sdlr_vtm.h:827
Definition: sdlr_vtm.h:834
volatile uint32_t TH
Definition: sdlr_vtm.h:75
volatile uint32_t GT_TH2_INT_EN_STAT_CLR
Definition: sdlr_vtm.h:94
volatile uint32_t GT_TH1_INT_EN_CLR
Definition: sdlr_vtm.h:91
volatile uint32_t SAMPLE_CTRL
Definition: sdlr_vtm.h:840
volatile uint32_t GT_TH2_INT_EN_CLR
Definition: sdlr_vtm.h:97
volatile uint32_t TRIM
Definition: sdlr_vtm.h:829
volatile uint32_t PID
Definition: sdlr_vtm.h:82
volatile uint32_t STAT
Definition: sdlr_vtm.h:74
volatile uint32_t EVT_SEL_SET
Definition: sdlr_vtm.h:65
volatile uint32_t LT_TH0_INT_EN_SET
Definition: sdlr_vtm.h:102
volatile uint32_t OPPVID
Definition: sdlr_vtm.h:63
volatile uint32_t GT_TH1_INT_EN_STAT_CLR
Definition: sdlr_vtm.h:88
volatile uint32_t EVT_STAT
Definition: sdlr_vtm.h:64
volatile uint32_t LT_TH0_INT_EN_CLR
Definition: sdlr_vtm.h:103
volatile uint32_t EVT_SEL_CLR
Definition: sdlr_vtm.h:66
volatile uint32_t CTRL
Definition: sdlr_vtm.h:828
Definition: sdlr_vtm.h:71
volatile uint32_t LT_TH0_INT_RAW_STAT_SET
Definition: sdlr_vtm.h:99