tisci_clocks.h

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/*
 *  Copyright (C) 2017-2025 Texas Instruments Incorporated
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */
#ifndef SOC_AM275X_CLOCKS_H
#define SOC_AM275X_CLOCKS_H
 
#ifdef __cplusplus
extern "C"
{
#endif
 
 
#define TISCI_DEV_ADC0_ADC_CLK 0
#define TISCI_DEV_ADC0_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLK 1
#define TISCI_DEV_ADC0_ADC_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT 2
#define TISCI_DEV_ADC0_ADC_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT4_CLK 3
#define TISCI_DEV_ADC0_ADC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 4
#define TISCI_DEV_ADC0_SYS_CLK 5
#define TISCI_DEV_ADC0_VBUS_CLK 6
 
#define TISCI_DEV_C7X256V0_C7XV_CORE_0_C7XV_CLK 0
 
#define TISCI_DEV_C7X256V0_CORE0_DIVH_CLK2_PULSAR_GCLK 0
#define TISCI_DEV_C7X256V0_CORE0_DIVH_CLK2_SOC_GCLK 1
#define TISCI_DEV_C7X256V0_CORE0_DIVH_CLK4_GCLK 2
#define TISCI_DEV_C7X256V0_CORE0_DIVH_CLK4_SOC_GCLK 3
#define TISCI_DEV_C7X256V0_CORE0_DIVP_CLK1_GCLK 4
#define TISCI_DEV_C7X256V0_CORE0_PULSAR_PLL_CLK_CLK 6
 
#define TISCI_DEV_C7X256V0_CLK_C7XV_CLK 0
#define TISCI_DEV_C7X256V0_CLK_C7XV_DIVH_CLK4_OBSCLK_OUT_CLK 1
#define TISCI_DEV_C7X256V0_CLK_DIVH_CLK2_PULSAR_GCLK 2
#define TISCI_DEV_C7X256V0_CLK_DIVH_CLK2_SOC_GCLK 3
#define TISCI_DEV_C7X256V0_CLK_DIVH_CLK4_GCLK 4
#define TISCI_DEV_C7X256V0_CLK_DIVH_CLK4_SOC_GCLK 5
#define TISCI_DEV_C7X256V0_CLK_DIVP_CLK1_GCLK 6
#define TISCI_DEV_C7X256V0_CLK_PLL_CTRL_CLK 7
#define TISCI_DEV_C7X256V0_CLK_PULSAR_PLL_CLK_CLK 8
 
#define TISCI_DEV_C7X256V1_C7XV_CORE_0_C7XV_CLK 0
 
#define TISCI_DEV_C7X256V1_CORE0_DIVH_CLK2_PULSAR_GCLK 0
#define TISCI_DEV_C7X256V1_CORE0_DIVH_CLK2_SOC_GCLK 1
#define TISCI_DEV_C7X256V1_CORE0_DIVH_CLK4_GCLK 2
#define TISCI_DEV_C7X256V1_CORE0_DIVH_CLK4_SOC_GCLK 3
#define TISCI_DEV_C7X256V1_CORE0_DIVP_CLK1_GCLK 4
#define TISCI_DEV_C7X256V1_CORE0_PULSAR_PLL_CLK_CLK 6
 
#define TISCI_DEV_C7X256V1_CLK_C7XV_CLK 0
#define TISCI_DEV_C7X256V1_CLK_C7XV_DIVH_CLK4_OBSCLK_OUT_CLK 1
#define TISCI_DEV_C7X256V1_CLK_DIVH_CLK2_PULSAR_GCLK 2
#define TISCI_DEV_C7X256V1_CLK_DIVH_CLK2_SOC_GCLK 3
#define TISCI_DEV_C7X256V1_CLK_DIVH_CLK4_GCLK 4
#define TISCI_DEV_C7X256V1_CLK_DIVH_CLK4_SOC_GCLK 5
#define TISCI_DEV_C7X256V1_CLK_DIVP_CLK1_GCLK 6
#define TISCI_DEV_C7X256V1_CLK_PLL_CTRL_CLK 7
#define TISCI_DEV_C7X256V1_CLK_PULSAR_PLL_CLK_CLK 8
 
#define TISCI_DEV_DBG_INTROUTER0_INTR_CLK 0
 
#define TISCI_DEV_MAIN_GPIOMUX_INTROUTER0_INTR_CLK 0
 
#define TISCI_DEV_PSCSS0_CLK 0
#define TISCI_DEV_PSCSS0_SLOW_CLK 1
 
#define TISCI_DEV_MCU_MCU_16FF0_PLL_CTRL_MCU_CLK24_CLK 3
 
#define TISCI_DEV_MCU_MCU_GPIOMUX_INTROUTER0_INTR_CLK 0
 
#define TISCI_DEV_TIMESYNC_EVENT_INTROUTER0_INTR_CLK 0
 
#define TISCI_DEV_ATL0_ATL_CLK 0
#define TISCI_DEV_ATL0_ATL_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK 1
#define TISCI_DEV_ATL0_ATL_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK 2
#define TISCI_DEV_ATL0_ATL_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK 3
#define TISCI_DEV_ATL0_ATL_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT1_CLK 4
#define TISCI_DEV_ATL0_ATL_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK 5
#define TISCI_DEV_ATL0_ATL_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 6
#define TISCI_DEV_ATL0_ATL_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 7
#define TISCI_DEV_ATL0_ATL_IO_PORT_ATCLK_OUT 9
#define TISCI_DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_1 10
#define TISCI_DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_2 11
#define TISCI_DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_3 12
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS 13
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_MCASP0_AFSX_OUT 14
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_MCASP1_AFSX_OUT 15
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_MCASP2_AFSX_OUT 16
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_MCASP3_AFSX_OUT 17
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_MCASP4_AFSX_OUT 18
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0 19
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0 20
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0 21
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0 22
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0 23
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 24
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 25
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 26
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_1 30
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_MCASP0_AFSX_OUT 31
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_MCASP1_AFSX_OUT 32
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_MCASP2_AFSX_OUT 33
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_MCASP3_AFSX_OUT 34
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_MCASP4_AFSX_OUT 35
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0 36
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0 37
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0 38
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0 39
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0 40
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 41
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 42
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 43
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_2 53
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_MCASP0_AFSX_OUT 54
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_MCASP1_AFSX_OUT 55
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_MCASP2_AFSX_OUT 56
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_MCASP3_AFSX_OUT 57
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_MCASP4_AFSX_OUT 58
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0 59
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0 60
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0 61
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0 62
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0 63
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 64
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 65
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 66
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_3 70
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_MCASP0_AFSX_OUT 71
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_MCASP1_AFSX_OUT 72
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_MCASP2_AFSX_OUT 73
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_MCASP3_AFSX_OUT 74
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_MCASP4_AFSX_OUT 75
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0 76
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0 77
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0 78
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0 79
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0 80
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 81
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 82
#define TISCI_DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 83
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS 93
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_MCASP0_AFSR_OUT 94
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_MCASP1_AFSR_OUT 95
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_MCASP2_AFSR_OUT 96
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_MCASP3_AFSR_OUT 97
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_MCASP4_AFSR_OUT 98
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_MCASP0_AFSX_OUT 99
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_MCASP1_AFSX_OUT 100
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_MCASP2_AFSX_OUT 101
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_MCASP3_AFSX_OUT 102
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_MCASP4_AFSX_OUT 103
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 104
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 105
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 106
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_1 110
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_MCASP0_AFSR_OUT 111
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_MCASP1_AFSR_OUT 112
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_MCASP2_AFSR_OUT 113
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_MCASP3_AFSR_OUT 114
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_MCASP4_AFSR_OUT 115
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_MCASP0_AFSX_OUT 116
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_MCASP1_AFSX_OUT 117
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_MCASP2_AFSX_OUT 118
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_MCASP3_AFSX_OUT 119
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_MCASP4_AFSX_OUT 120
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 121
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 122
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 123
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_2 133
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_MCASP0_AFSR_OUT 134
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_MCASP1_AFSR_OUT 135
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_MCASP2_AFSR_OUT 136
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_MCASP3_AFSR_OUT 137
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_MCASP4_AFSR_OUT 138
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_MCASP0_AFSX_OUT 139
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_MCASP1_AFSX_OUT 140
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_MCASP2_AFSX_OUT 141
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_MCASP3_AFSX_OUT 142
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_MCASP4_AFSX_OUT 143
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 144
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 145
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 146
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_3 150
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_MCASP0_AFSR_OUT 151
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_MCASP1_AFSR_OUT 152
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_MCASP2_AFSR_OUT 153
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_MCASP3_AFSR_OUT 154
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_MCASP4_AFSR_OUT 155
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_MCASP0_AFSX_OUT 156
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_MCASP1_AFSX_OUT 157
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_MCASP2_AFSX_OUT 158
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_MCASP3_AFSX_OUT 159
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_MCASP4_AFSX_OUT 160
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 161
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 162
#define TISCI_DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 163
#define TISCI_DEV_ATL0_VBUS_CLK 173
 
#define TISCI_DEV_CPSW0_CPPI_CLK_CLK 0
#define TISCI_DEV_CPSW0_CPTS_GENF0 1
#define TISCI_DEV_CPSW0_CPTS_GENF1 2
#define TISCI_DEV_CPSW0_CPTS_RFT_CLK 3
#define TISCI_DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK 4
#define TISCI_DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK 5
#define TISCI_DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT 6
#define TISCI_DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 8
#define TISCI_DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 9
#define TISCI_DEV_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT1_CLK 10
#define TISCI_DEV_CPSW0_CPTS_RFT_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK 11
#define TISCI_DEV_CPSW0_GMII1_MR_CLK 12
#define TISCI_DEV_CPSW0_GMII1_MT_CLK 13
#define TISCI_DEV_CPSW0_GMII2_MR_CLK 14
#define TISCI_DEV_CPSW0_GMII2_MT_CLK 15
#define TISCI_DEV_CPSW0_GMII_RFT_CLK 16
#define TISCI_DEV_CPSW0_MDIO_MDCLK_O 17
#define TISCI_DEV_CPSW0_RGMII_MHZ_250_CLK 18
#define TISCI_DEV_CPSW0_RGMII_MHZ_50_CLK 19
#define TISCI_DEV_CPSW0_RGMII_MHZ_5_CLK 20
#define TISCI_DEV_CPSW0_RMII1_MHZ_50_CLK 21
#define TISCI_DEV_CPSW0_RMII2_MHZ_50_CLK 22
 
#define TISCI_DEV_CPT2_AGGR1_VCLK_CLK 0
 
#define TISCI_DEV_CPT2_AGGR0_VCLK_CLK 0
 
#define TISCI_DEV_CPT2_AGGR2_VCLK_CLK 0
 
#define TISCI_DEV_STM0_ATB_CLK 0
#define TISCI_DEV_STM0_CORE_CLK 1
#define TISCI_DEV_STM0_VBUSP_CLK 2
 
#define TISCI_DEV_DCC0_DCC_CLKSRC0_CLK 0
#define TISCI_DEV_DCC0_DCC_CLKSRC1_CLK 1
#define TISCI_DEV_DCC0_DCC_CLKSRC2_CLK 2
#define TISCI_DEV_DCC0_DCC_CLKSRC3_CLK 3
#define TISCI_DEV_DCC0_DCC_CLKSRC4_CLK 4
#define TISCI_DEV_DCC0_DCC_CLKSRC5_CLK 5
#define TISCI_DEV_DCC0_DCC_CLKSRC6_CLK 6
#define TISCI_DEV_DCC0_DCC_CLKSRC7_CLK 7
#define TISCI_DEV_DCC0_DCC_INPUT00_CLK 8
#define TISCI_DEV_DCC0_DCC_INPUT01_CLK 9
#define TISCI_DEV_DCC0_DCC_INPUT02_CLK 10
#define TISCI_DEV_DCC0_DCC_INPUT10_CLK 11
#define TISCI_DEV_DCC0_VBUS_CLK 12
 
#define TISCI_DEV_DCC1_DCC_CLKSRC0_CLK 0
#define TISCI_DEV_DCC1_DCC_CLKSRC1_CLK 1
#define TISCI_DEV_DCC1_DCC_CLKSRC2_CLK 2
#define TISCI_DEV_DCC1_DCC_CLKSRC3_CLK 3
#define TISCI_DEV_DCC1_DCC_CLKSRC4_CLK 4
#define TISCI_DEV_DCC1_DCC_CLKSRC5_CLK 5
#define TISCI_DEV_DCC1_DCC_CLKSRC6_CLK 6
#define TISCI_DEV_DCC1_DCC_CLKSRC7_CLK 7
#define TISCI_DEV_DCC1_DCC_INPUT00_CLK 8
#define TISCI_DEV_DCC1_DCC_INPUT01_CLK 9
#define TISCI_DEV_DCC1_DCC_INPUT02_CLK 10
#define TISCI_DEV_DCC1_DCC_INPUT10_CLK 11
#define TISCI_DEV_DCC1_VBUS_CLK 12
 
#define TISCI_DEV_DCC2_DCC_CLKSRC0_CLK 0
#define TISCI_DEV_DCC2_DCC_CLKSRC1_CLK 1
#define TISCI_DEV_DCC2_DCC_CLKSRC2_CLK 2
#define TISCI_DEV_DCC2_DCC_CLKSRC3_CLK 3
#define TISCI_DEV_DCC2_DCC_CLKSRC5_CLK 5
#define TISCI_DEV_DCC2_DCC_CLKSRC6_CLK 6
#define TISCI_DEV_DCC2_DCC_CLKSRC7_CLK 7
#define TISCI_DEV_DCC2_DCC_INPUT00_CLK 8
#define TISCI_DEV_DCC2_DCC_INPUT01_CLK 9
#define TISCI_DEV_DCC2_DCC_INPUT02_CLK 10
#define TISCI_DEV_DCC2_DCC_INPUT10_CLK 11
#define TISCI_DEV_DCC2_VBUS_CLK 12
 
#define TISCI_DEV_DCC3_DCC_CLKSRC0_CLK 0
#define TISCI_DEV_DCC3_DCC_CLKSRC1_CLK 1
#define TISCI_DEV_DCC3_DCC_CLKSRC2_CLK 2
#define TISCI_DEV_DCC3_DCC_CLKSRC3_CLK 3
#define TISCI_DEV_DCC3_DCC_CLKSRC4_CLK 4
#define TISCI_DEV_DCC3_DCC_CLKSRC5_CLK 5
#define TISCI_DEV_DCC3_DCC_INPUT00_CLK 8
#define TISCI_DEV_DCC3_DCC_INPUT01_CLK 9
#define TISCI_DEV_DCC3_DCC_INPUT02_CLK 10
#define TISCI_DEV_DCC3_DCC_INPUT10_CLK 11
#define TISCI_DEV_DCC3_VBUS_CLK 12
 
#define TISCI_DEV_DCC4_DCC_CLKSRC1_CLK 1
#define TISCI_DEV_DCC4_DCC_CLKSRC2_CLK 2
#define TISCI_DEV_DCC4_DCC_CLKSRC4_CLK 4
#define TISCI_DEV_DCC4_DCC_CLKSRC5_CLK 5
#define TISCI_DEV_DCC4_DCC_CLKSRC6_CLK 6
#define TISCI_DEV_DCC4_DCC_CLKSRC7_CLK 7
#define TISCI_DEV_DCC4_DCC_INPUT00_CLK 8
#define TISCI_DEV_DCC4_DCC_INPUT01_CLK 9
#define TISCI_DEV_DCC4_DCC_INPUT02_CLK 10
#define TISCI_DEV_DCC4_DCC_INPUT10_CLK 11
#define TISCI_DEV_DCC4_VBUS_CLK 12
 
#define TISCI_DEV_DCC5_DCC_CLKSRC0_CLK 0
#define TISCI_DEV_DCC5_DCC_CLKSRC1_CLK 1
#define TISCI_DEV_DCC5_DCC_CLKSRC2_CLK 2
#define TISCI_DEV_DCC5_DCC_CLKSRC3_CLK 3
#define TISCI_DEV_DCC5_DCC_CLKSRC4_CLK 4
#define TISCI_DEV_DCC5_DCC_CLKSRC7_CLK 7
#define TISCI_DEV_DCC5_DCC_INPUT00_CLK 8
#define TISCI_DEV_DCC5_DCC_INPUT01_CLK 9
#define TISCI_DEV_DCC5_DCC_INPUT02_CLK 10
#define TISCI_DEV_DCC5_DCC_INPUT10_CLK 11
#define TISCI_DEV_DCC5_VBUS_CLK 12
 
#define TISCI_DEV_DCC6_DCC_CLKSRC1_CLK 1
#define TISCI_DEV_DCC6_DCC_CLKSRC2_CLK 2
#define TISCI_DEV_DCC6_DCC_CLKSRC3_CLK 3
#define TISCI_DEV_DCC6_DCC_CLKSRC4_CLK 4
#define TISCI_DEV_DCC6_DCC_CLKSRC5_CLK 5
#define TISCI_DEV_DCC6_DCC_CLKSRC6_CLK 6
#define TISCI_DEV_DCC6_DCC_CLKSRC7_CLK 7
#define TISCI_DEV_DCC6_DCC_INPUT00_CLK 8
#define TISCI_DEV_DCC6_DCC_INPUT01_CLK 9
#define TISCI_DEV_DCC6_DCC_INPUT02_CLK 10
#define TISCI_DEV_DCC6_DCC_INPUT10_CLK 11
#define TISCI_DEV_DCC6_VBUS_CLK 12
 
#define TISCI_DEV_DCC7_DCC_CLKSRC0_CLK 0
#define TISCI_DEV_DCC7_DCC_CLKSRC1_CLK 1
#define TISCI_DEV_DCC7_DCC_CLKSRC3_CLK 3
#define TISCI_DEV_DCC7_DCC_CLKSRC4_CLK 4
#define TISCI_DEV_DCC7_DCC_CLKSRC5_CLK 5
#define TISCI_DEV_DCC7_DCC_CLKSRC6_CLK 6
#define TISCI_DEV_DCC7_DCC_CLKSRC7_CLK 7
#define TISCI_DEV_DCC7_DCC_INPUT00_CLK 8
#define TISCI_DEV_DCC7_DCC_INPUT01_CLK 9
#define TISCI_DEV_DCC7_DCC_INPUT02_CLK 10
#define TISCI_DEV_DCC7_DCC_INPUT10_CLK 11
#define TISCI_DEV_DCC7_VBUS_CLK 12
 
#define TISCI_DEV_DCC8_DCC_CLKSRC0_CLK 0
#define TISCI_DEV_DCC8_DCC_CLKSRC1_CLK 1
#define TISCI_DEV_DCC8_DCC_CLKSRC2_CLK 2
#define TISCI_DEV_DCC8_DCC_CLKSRC3_CLK 3
#define TISCI_DEV_DCC8_DCC_CLKSRC4_CLK 4
#define TISCI_DEV_DCC8_DCC_CLKSRC5_CLK 5
#define TISCI_DEV_DCC8_DCC_CLKSRC6_CLK 6
#define TISCI_DEV_DCC8_DCC_CLKSRC7_CLK 7
#define TISCI_DEV_DCC8_DCC_INPUT00_CLK 8
#define TISCI_DEV_DCC8_DCC_INPUT01_CLK 9
#define TISCI_DEV_DCC8_DCC_INPUT02_CLK 10
#define TISCI_DEV_DCC8_DCC_INPUT10_CLK 11
#define TISCI_DEV_DCC8_VBUS_CLK 12
 
#define TISCI_DEV_MCU_DCC0_DCC_CLKSRC0_CLK 0
#define TISCI_DEV_MCU_DCC0_DCC_CLKSRC1_CLK 1
#define TISCI_DEV_MCU_DCC0_DCC_CLKSRC2_CLK 2
#define TISCI_DEV_MCU_DCC0_DCC_CLKSRC3_CLK 3
#define TISCI_DEV_MCU_DCC0_DCC_CLKSRC4_CLK 4
#define TISCI_DEV_MCU_DCC0_DCC_CLKSRC5_CLK 5
#define TISCI_DEV_MCU_DCC0_DCC_CLKSRC6_CLK 6
#define TISCI_DEV_MCU_DCC0_DCC_CLKSRC7_CLK 7
#define TISCI_DEV_MCU_DCC0_DCC_INPUT00_CLK 8
#define TISCI_DEV_MCU_DCC0_DCC_INPUT01_CLK 9
#define TISCI_DEV_MCU_DCC0_DCC_INPUT02_CLK 10
#define TISCI_DEV_MCU_DCC0_DCC_INPUT10_CLK 11
#define TISCI_DEV_MCU_DCC0_VBUS_CLK 12
 
#define TISCI_DEV_MCU_DCC1_DCC_CLKSRC0_CLK 0
#define TISCI_DEV_MCU_DCC1_DCC_CLKSRC1_CLK 1
#define TISCI_DEV_MCU_DCC1_DCC_CLKSRC5_CLK 5
#define TISCI_DEV_MCU_DCC1_DCC_CLKSRC6_CLK 6
#define TISCI_DEV_MCU_DCC1_DCC_CLKSRC7_CLK 7
#define TISCI_DEV_MCU_DCC1_DCC_INPUT00_CLK 8
#define TISCI_DEV_MCU_DCC1_DCC_INPUT01_CLK 9
#define TISCI_DEV_MCU_DCC1_DCC_INPUT02_CLK 10
#define TISCI_DEV_MCU_DCC1_DCC_INPUT10_CLK 11
#define TISCI_DEV_MCU_DCC1_VBUS_CLK 12
 
#define TISCI_DEV_DEBUGSS_WRAP0_ATB_CLK 0
#define TISCI_DEV_DEBUGSS_WRAP0_CORE_CLK 1
#define TISCI_DEV_DEBUGSS_WRAP0_CSTPIU_TRACECLK 2
#define TISCI_DEV_DEBUGSS_WRAP0_JTAG_TCK 20
#define TISCI_DEV_DEBUGSS_WRAP0_P1500_WRCK 21
#define TISCI_DEV_DEBUGSS_WRAP0_TREXPT_CLK 22
 
#define TISCI_DEV_DMASS0_BCDMA_0_CLK 0
 
#define TISCI_DEV_DMASS0_CBASS_0_CLK 0
 
#define TISCI_DEV_DMASS0_INTAGGR_0_CLK 0
 
#define TISCI_DEV_DMASS0_IPCSS_0_CLK 0
 
#define TISCI_DEV_DMASS0_PKTDMA_0_CLK 0
 
#define TISCI_DEV_DMASS0_RINGACC_0_CLK 0
 
#define TISCI_DEV_TIMER0_TIMER_HCLK_CLK 0
#define TISCI_DEV_TIMER0_TIMER_PWM 1
#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK 2
#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLK 3
#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0 4
#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK 5
#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 6
#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 7
#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 8
#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT 10
#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK 11
#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK 12
#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 13
#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 14
#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK 15
 
#define TISCI_DEV_TIMER1_TIMER_HCLK_CLK 0
#define TISCI_DEV_TIMER1_TIMER_PWM 1
#define TISCI_DEV_TIMER1_TIMER_TCLK_CLK 2
#define TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_MAIN_TIMERCLKN_SEL_OUT1 3
#define TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_0_TIMER_PWM 4
 
#define TISCI_DEV_TIMER10_TIMER_HCLK_CLK 0
#define TISCI_DEV_TIMER10_TIMER_PWM 1
#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK 2
#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLK 3
#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0 4
#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK 5
#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 6
#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 7
#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 8
#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT 10
#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK 11
#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK 12
#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 13
#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 14
#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK 15
 
#define TISCI_DEV_TIMER11_TIMER_HCLK_CLK 0
#define TISCI_DEV_TIMER11_TIMER_TCLK_CLK 2
#define TISCI_DEV_TIMER11_TIMER_TCLK_CLK_PARENT_MAIN_TIMERCLKN_SEL_OUT11 3
#define TISCI_DEV_TIMER11_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_10_TIMER_PWM 4
 
#define TISCI_DEV_TIMER12_TIMER_HCLK_CLK 0
#define TISCI_DEV_TIMER12_TIMER_PWM 1
#define TISCI_DEV_TIMER12_TIMER_TCLK_CLK 2
#define TISCI_DEV_TIMER12_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLK 3
#define TISCI_DEV_TIMER12_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0 4
#define TISCI_DEV_TIMER12_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK 5
#define TISCI_DEV_TIMER12_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 6
#define TISCI_DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 7
#define TISCI_DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 8
#define TISCI_DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT 10
#define TISCI_DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK 11
#define TISCI_DEV_TIMER12_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK 12
#define TISCI_DEV_TIMER12_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 13
#define TISCI_DEV_TIMER12_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 14
#define TISCI_DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK 15
 
#define TISCI_DEV_TIMER13_TIMER_HCLK_CLK 0
#define TISCI_DEV_TIMER13_TIMER_TCLK_CLK 2
#define TISCI_DEV_TIMER13_TIMER_TCLK_CLK_PARENT_MAIN_TIMERCLKN_SEL_OUT13 3
#define TISCI_DEV_TIMER13_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_12_TIMER_PWM 4
 
#define TISCI_DEV_TIMER14_TIMER_HCLK_CLK 0
#define TISCI_DEV_TIMER14_TIMER_PWM 1
#define TISCI_DEV_TIMER14_TIMER_TCLK_CLK 2
#define TISCI_DEV_TIMER14_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLK 3
#define TISCI_DEV_TIMER14_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0 4
#define TISCI_DEV_TIMER14_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK 5
#define TISCI_DEV_TIMER14_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 6
#define TISCI_DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 7
#define TISCI_DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 8
#define TISCI_DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT 10
#define TISCI_DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK 11
#define TISCI_DEV_TIMER14_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK 12
#define TISCI_DEV_TIMER14_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 13
#define TISCI_DEV_TIMER14_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 14
#define TISCI_DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK 15
 
#define TISCI_DEV_TIMER15_TIMER_HCLK_CLK 0
#define TISCI_DEV_TIMER15_TIMER_TCLK_CLK 2
#define TISCI_DEV_TIMER15_TIMER_TCLK_CLK_PARENT_MAIN_TIMERCLKN_SEL_OUT15 3
#define TISCI_DEV_TIMER15_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_14_TIMER_PWM 4
 
#define TISCI_DEV_TIMER2_TIMER_HCLK_CLK 0
#define TISCI_DEV_TIMER2_TIMER_PWM 1
#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK 2
#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLK 3
#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0 4
#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK 5
#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 6
#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 7
#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 8
#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT 10
#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK 11
#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK 12
#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 13
#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 14
#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK 15
 
#define TISCI_DEV_TIMER3_TIMER_HCLK_CLK 0
#define TISCI_DEV_TIMER3_TIMER_PWM 1
#define TISCI_DEV_TIMER3_TIMER_TCLK_CLK 2
#define TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_MAIN_TIMERCLKN_SEL_OUT3 3
#define TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_2_TIMER_PWM 4
 
#define TISCI_DEV_TIMER4_TIMER_HCLK_CLK 0
#define TISCI_DEV_TIMER4_TIMER_PWM 1
#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK 2
#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLK 3
#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0 4
#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK 5
#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 6
#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 7
#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 8
#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT 10
#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK 11
#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK 12
#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 13
#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 14
#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK 15
 
#define TISCI_DEV_TIMER5_TIMER_HCLK_CLK 0
#define TISCI_DEV_TIMER5_TIMER_PWM 1
#define TISCI_DEV_TIMER5_TIMER_TCLK_CLK 2
#define TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_MAIN_TIMERCLKN_SEL_OUT5 3
#define TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_4_TIMER_PWM 4
 
#define TISCI_DEV_TIMER6_TIMER_HCLK_CLK 0
#define TISCI_DEV_TIMER6_TIMER_PWM 1
#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK 2
#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLK 3
#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0 4
#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK 5
#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 6
#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 7
#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 8
#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT 10
#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK 11
#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK 12
#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 13
#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 14
#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK 15
 
#define TISCI_DEV_TIMER7_TIMER_HCLK_CLK 0
#define TISCI_DEV_TIMER7_TIMER_PWM 1
#define TISCI_DEV_TIMER7_TIMER_TCLK_CLK 2
#define TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_MAIN_TIMERCLKN_SEL_OUT7 3
#define TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_6_TIMER_PWM 4
 
#define TISCI_DEV_TIMER8_TIMER_HCLK_CLK 0
#define TISCI_DEV_TIMER8_TIMER_PWM 1
#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK 2
#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLK 3
#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0 4
#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK 5
#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 6
#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 7
#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 8
#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT 10
#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK 11
#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK 12
#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 13
#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 14
#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK 15
 
#define TISCI_DEV_TIMER9_TIMER_HCLK_CLK 0
#define TISCI_DEV_TIMER9_TIMER_TCLK_CLK 2
#define TISCI_DEV_TIMER9_TIMER_TCLK_CLK_PARENT_MAIN_TIMERCLKN_SEL_OUT9 3
#define TISCI_DEV_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_8_TIMER_PWM 4
 
#define TISCI_DEV_WKUP_TIMER0_TIMER_HCLK_CLK 0
#define TISCI_DEV_WKUP_TIMER0_TIMER_HCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK 1
#define TISCI_DEV_WKUP_TIMER0_TIMER_HCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK 2
#define TISCI_DEV_WKUP_TIMER0_TIMER_PWM 3
#define TISCI_DEV_WKUP_TIMER0_TIMER_TCLK_CLK 4
#define TISCI_DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLK 5
#define TISCI_DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_WKUP_CLKSEL_OUT02 6
#define TISCI_DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 7
#define TISCI_DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV1_16FFT_MCU_0_HSDIVOUT5_CLK 8
#define TISCI_DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 9
#define TISCI_DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0 10
#define TISCI_DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 11
#define TISCI_DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 12
 
#define TISCI_DEV_WKUP_TIMER1_TIMER_HCLK_CLK 0
#define TISCI_DEV_WKUP_TIMER1_TIMER_HCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK 1
#define TISCI_DEV_WKUP_TIMER1_TIMER_HCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK 2
#define TISCI_DEV_WKUP_TIMER1_TIMER_TCLK_CLK 4
 
#define TISCI_DEV_ECAP0_VBUS_CLK 0
 
#define TISCI_DEV_ECAP1_VBUS_CLK 0
 
#define TISCI_DEV_ECAP2_VBUS_CLK 0
 
#define TISCI_DEV_ECAP3_VBUS_CLK 0
 
#define TISCI_DEV_ECAP4_VBUS_CLK 0
 
#define TISCI_DEV_ECAP5_VBUS_CLK 0
 
#define TISCI_DEV_MMCSD0_EMMCSDSS_IO_CLK_I 0
#define TISCI_DEV_MMCSD0_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC0_CLKLB_OUT 1
#define TISCI_DEV_MMCSD0_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC0_CLK_OUT 2
#define TISCI_DEV_MMCSD0_EMMCSDSS_IO_CLK_O 3
#define TISCI_DEV_MMCSD0_EMMCSDSS_VBUS_CLK 5
#define TISCI_DEV_MMCSD0_EMMCSDSS_XIN_CLK 6
#define TISCI_DEV_MMCSD0_EMMCSDSS_XIN_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT5_CLK 7
#define TISCI_DEV_MMCSD0_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK 8
 
#define TISCI_DEV_WKUP_ESM0_CLK 0
 
#define TISCI_DEV_ESM0_CLK 0
 
#define TISCI_DEV_FSS1_FSAS_0_GCLK 0
 
#define TISCI_DEV_FSS1_HYPERBUS1P0_0_CBA_CLK 0
#define TISCI_DEV_FSS1_HYPERBUS1P0_0_HPB_CLKX1_CLK 2
#define TISCI_DEV_FSS1_HYPERBUS1P0_0_HPB_CLKX1_INV_CLK 4
#define TISCI_DEV_FSS1_HYPERBUS1P0_0_HPB_CLKX2_CLK 6
#define TISCI_DEV_FSS1_HYPERBUS1P0_0_HPB_CLKX2_INV_CLK 8
#define TISCI_DEV_FSS1_HYPERBUS1P0_0_HPB_OUT_CLK_N 10
#define TISCI_DEV_FSS1_HYPERBUS1P0_0_HPB_OUT_CLK_P 11
 
#define TISCI_DEV_FSS1_OSPI_0_OSPI_DQS_CLK 0
#define TISCI_DEV_FSS1_OSPI_0_OSPI_HCLK_CLK 1
#define TISCI_DEV_FSS1_OSPI_0_OSPI_ICLK_CLK 2
#define TISCI_DEV_FSS1_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_OSPI1_DQS_OUT 3
#define TISCI_DEV_FSS1_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_OSPI1_LBCLKO_OUT 4
#define TISCI_DEV_FSS1_OSPI_0_OSPI_OCLK_CLK 5
#define TISCI_DEV_FSS1_OSPI_0_OSPI_PCLK_CLK 6
#define TISCI_DEV_FSS1_OSPI_0_OSPI_RCLK_CLK 7
#define TISCI_DEV_FSS1_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK 8
#define TISCI_DEV_FSS1_OSPI_0_OSPI_RCLK_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT5_CLK 9
 
#define TISCI_DEV_FSS1_OSPI_1_OSPI_HCLK_CLK 1
#define TISCI_DEV_FSS1_OSPI_1_OSPI_PCLK_CLK 6
 
#define TISCI_DEV_FSS0_M8051EW_JTAG_TCK 0
#define TISCI_DEV_FSS0_OSPI0_DQS_CLK 1
#define TISCI_DEV_FSS0_OSPI0_ICLK_CLK 2
#define TISCI_DEV_FSS0_OSPI0_ICLK_CLK_PARENT_BOARD_0_OSPI0_DQS_OUT 3
#define TISCI_DEV_FSS0_OSPI0_ICLK_CLK_PARENT_BOARD_0_OSPI0_LBCLKO_OUT 4
#define TISCI_DEV_FSS0_OSPI0_OCLK_CLK 5
#define TISCI_DEV_FSS0_OSPI0_RCLK_CLK 6
#define TISCI_DEV_FSS0_OSPI0_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK 7
#define TISCI_DEV_FSS0_OSPI0_RCLK_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT5_CLK 8
#define TISCI_DEV_FSS0_VBUS_CLK 9
 
#define TISCI_DEV_GPIO0_MMR_CLK 0
 
#define TISCI_DEV_GPIO1_MMR_CLK 0
 
#define TISCI_DEV_MCU_GPIO0_MMR_CLK 0
#define TISCI_DEV_MCU_GPIO0_MMR_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4 1
#define TISCI_DEV_MCU_GPIO0_MMR_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 3
#define TISCI_DEV_MCU_GPIO0_MMR_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 4
 
#define TISCI_DEV_WKUP_GTC0_GTC_CLK 0
#define TISCI_DEV_WKUP_GTC0_GTC_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK 1
#define TISCI_DEV_WKUP_GTC0_GTC_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK 2
#define TISCI_DEV_WKUP_GTC0_GTC_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT 3
#define TISCI_DEV_WKUP_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 5
#define TISCI_DEV_WKUP_GTC0_GTC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 6
#define TISCI_DEV_WKUP_GTC0_GTC_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK2 7
#define TISCI_DEV_WKUP_GTC0_GTC_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK 8
#define TISCI_DEV_WKUP_GTC0_VBUSP_CLK 9
#define TISCI_DEV_WKUP_GTC0_VBUSP_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK 10
#define TISCI_DEV_WKUP_GTC0_VBUSP_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK 11
 
#define TISCI_DEV_AASRC0_RX0_SYNC_CLK 8
#define TISCI_DEV_AASRC0_RX0_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSR_OUT 9
#define TISCI_DEV_AASRC0_RX0_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSR_OUT 10
#define TISCI_DEV_AASRC0_RX0_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSR_OUT 11
#define TISCI_DEV_AASRC0_RX0_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSR_OUT 12
#define TISCI_DEV_AASRC0_RX0_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSR_OUT 13
#define TISCI_DEV_AASRC0_RX0_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSX_OUT 17
#define TISCI_DEV_AASRC0_RX0_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSX_OUT 18
#define TISCI_DEV_AASRC0_RX0_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSX_OUT 19
#define TISCI_DEV_AASRC0_RX0_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSX_OUT 20
#define TISCI_DEV_AASRC0_RX0_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSX_OUT 21
#define TISCI_DEV_AASRC0_RX0_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 25
#define TISCI_DEV_AASRC0_RX0_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 26
#define TISCI_DEV_AASRC0_RX0_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 27
#define TISCI_DEV_AASRC0_RX0_SYNC_CLK_PARENT_ADC_CLK_SEL_OUT0 29
#define TISCI_DEV_AASRC0_RX0_SYNC_CLK_PARENT_BOARD_0_MLB0_MLBCLK_OUT 30
#define TISCI_DEV_AASRC0_RX0_SYNC_CLK_PARENT_ASRC_SYNC_DIV_OUT0 31
#define TISCI_DEV_AASRC0_RX0_SYNC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 33
#define TISCI_DEV_AASRC0_RX0_SYNC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 34
#define TISCI_DEV_AASRC0_RX0_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 35
#define TISCI_DEV_AASRC0_RX0_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 36
#define TISCI_DEV_AASRC0_RX1_SYNC_CLK 41
#define TISCI_DEV_AASRC0_RX1_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSR_OUT 42
#define TISCI_DEV_AASRC0_RX1_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSR_OUT 43
#define TISCI_DEV_AASRC0_RX1_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSR_OUT 44
#define TISCI_DEV_AASRC0_RX1_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSR_OUT 45
#define TISCI_DEV_AASRC0_RX1_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSR_OUT 46
#define TISCI_DEV_AASRC0_RX1_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSX_OUT 50
#define TISCI_DEV_AASRC0_RX1_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSX_OUT 51
#define TISCI_DEV_AASRC0_RX1_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSX_OUT 52
#define TISCI_DEV_AASRC0_RX1_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSX_OUT 53
#define TISCI_DEV_AASRC0_RX1_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSX_OUT 54
#define TISCI_DEV_AASRC0_RX1_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 58
#define TISCI_DEV_AASRC0_RX1_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 59
#define TISCI_DEV_AASRC0_RX1_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 60
#define TISCI_DEV_AASRC0_RX1_SYNC_CLK_PARENT_ADC_CLK_SEL_OUT0 62
#define TISCI_DEV_AASRC0_RX1_SYNC_CLK_PARENT_BOARD_0_MLB0_MLBCLK_OUT 63
#define TISCI_DEV_AASRC0_RX1_SYNC_CLK_PARENT_ASRC_SYNC_DIV_OUT0 64
#define TISCI_DEV_AASRC0_RX1_SYNC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 66
#define TISCI_DEV_AASRC0_RX1_SYNC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 67
#define TISCI_DEV_AASRC0_RX1_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 68
#define TISCI_DEV_AASRC0_RX1_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 69
#define TISCI_DEV_AASRC0_RX2_SYNC_CLK 74
#define TISCI_DEV_AASRC0_RX2_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSR_OUT 75
#define TISCI_DEV_AASRC0_RX2_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSR_OUT 76
#define TISCI_DEV_AASRC0_RX2_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSR_OUT 77
#define TISCI_DEV_AASRC0_RX2_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSR_OUT 78
#define TISCI_DEV_AASRC0_RX2_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSR_OUT 79
#define TISCI_DEV_AASRC0_RX2_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSX_OUT 83
#define TISCI_DEV_AASRC0_RX2_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSX_OUT 84
#define TISCI_DEV_AASRC0_RX2_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSX_OUT 85
#define TISCI_DEV_AASRC0_RX2_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSX_OUT 86
#define TISCI_DEV_AASRC0_RX2_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSX_OUT 87
#define TISCI_DEV_AASRC0_RX2_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 91
#define TISCI_DEV_AASRC0_RX2_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 92
#define TISCI_DEV_AASRC0_RX2_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 93
#define TISCI_DEV_AASRC0_RX2_SYNC_CLK_PARENT_ADC_CLK_SEL_OUT0 95
#define TISCI_DEV_AASRC0_RX2_SYNC_CLK_PARENT_BOARD_0_MLB0_MLBCLK_OUT 96
#define TISCI_DEV_AASRC0_RX2_SYNC_CLK_PARENT_ASRC_SYNC_DIV_OUT0 97
#define TISCI_DEV_AASRC0_RX2_SYNC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 99
#define TISCI_DEV_AASRC0_RX2_SYNC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 100
#define TISCI_DEV_AASRC0_RX2_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 101
#define TISCI_DEV_AASRC0_RX2_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 102
#define TISCI_DEV_AASRC0_RX3_SYNC_CLK 107
#define TISCI_DEV_AASRC0_RX3_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSR_OUT 108
#define TISCI_DEV_AASRC0_RX3_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSR_OUT 109
#define TISCI_DEV_AASRC0_RX3_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSR_OUT 110
#define TISCI_DEV_AASRC0_RX3_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSR_OUT 111
#define TISCI_DEV_AASRC0_RX3_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSR_OUT 112
#define TISCI_DEV_AASRC0_RX3_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSX_OUT 116
#define TISCI_DEV_AASRC0_RX3_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSX_OUT 117
#define TISCI_DEV_AASRC0_RX3_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSX_OUT 118
#define TISCI_DEV_AASRC0_RX3_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSX_OUT 119
#define TISCI_DEV_AASRC0_RX3_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSX_OUT 120
#define TISCI_DEV_AASRC0_RX3_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 124
#define TISCI_DEV_AASRC0_RX3_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 125
#define TISCI_DEV_AASRC0_RX3_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 126
#define TISCI_DEV_AASRC0_RX3_SYNC_CLK_PARENT_ADC_CLK_SEL_OUT0 128
#define TISCI_DEV_AASRC0_RX3_SYNC_CLK_PARENT_BOARD_0_MLB0_MLBCLK_OUT 129
#define TISCI_DEV_AASRC0_RX3_SYNC_CLK_PARENT_ASRC_SYNC_DIV_OUT0 130
#define TISCI_DEV_AASRC0_RX3_SYNC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 132
#define TISCI_DEV_AASRC0_RX3_SYNC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 133
#define TISCI_DEV_AASRC0_RX3_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 134
#define TISCI_DEV_AASRC0_RX3_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 135
#define TISCI_DEV_AASRC0_SYS_CLK 144
#define TISCI_DEV_AASRC0_TX0_SYNC_CLK 145
#define TISCI_DEV_AASRC0_TX0_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSX_OUT 146
#define TISCI_DEV_AASRC0_TX0_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSX_OUT 147
#define TISCI_DEV_AASRC0_TX0_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0 148
#define TISCI_DEV_AASRC0_TX0_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0 149
#define TISCI_DEV_AASRC0_TX0_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0 150
#define TISCI_DEV_AASRC0_TX0_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0 154
#define TISCI_DEV_AASRC0_TX0_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0 155
#define TISCI_DEV_AASRC0_TX0_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSX_OUT 156
#define TISCI_DEV_AASRC0_TX0_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSX_OUT 157
#define TISCI_DEV_AASRC0_TX0_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSX_OUT 158
#define TISCI_DEV_AASRC0_TX0_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 162
#define TISCI_DEV_AASRC0_TX0_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 163
#define TISCI_DEV_AASRC0_TX0_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 164
#define TISCI_DEV_AASRC0_TX0_SYNC_CLK_PARENT_ADC_CLK_SEL_OUT0 166
#define TISCI_DEV_AASRC0_TX0_SYNC_CLK_PARENT_BOARD_0_MLB0_MLBCLK_OUT 167
#define TISCI_DEV_AASRC0_TX0_SYNC_CLK_PARENT_ASRC_SYNC_DIV_OUT0 168
#define TISCI_DEV_AASRC0_TX0_SYNC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 170
#define TISCI_DEV_AASRC0_TX0_SYNC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 171
#define TISCI_DEV_AASRC0_TX0_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 172
#define TISCI_DEV_AASRC0_TX0_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 173
#define TISCI_DEV_AASRC0_TX1_SYNC_CLK 178
#define TISCI_DEV_AASRC0_TX1_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSX_OUT 179
#define TISCI_DEV_AASRC0_TX1_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSX_OUT 180
#define TISCI_DEV_AASRC0_TX1_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0 181
#define TISCI_DEV_AASRC0_TX1_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0 182
#define TISCI_DEV_AASRC0_TX1_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0 183
#define TISCI_DEV_AASRC0_TX1_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0 187
#define TISCI_DEV_AASRC0_TX1_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0 188
#define TISCI_DEV_AASRC0_TX1_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSX_OUT 189
#define TISCI_DEV_AASRC0_TX1_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSX_OUT 190
#define TISCI_DEV_AASRC0_TX1_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSX_OUT 191
#define TISCI_DEV_AASRC0_TX1_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 195
#define TISCI_DEV_AASRC0_TX1_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 196
#define TISCI_DEV_AASRC0_TX1_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 197
#define TISCI_DEV_AASRC0_TX1_SYNC_CLK_PARENT_ADC_CLK_SEL_OUT0 199
#define TISCI_DEV_AASRC0_TX1_SYNC_CLK_PARENT_BOARD_0_MLB0_MLBCLK_OUT 200
#define TISCI_DEV_AASRC0_TX1_SYNC_CLK_PARENT_ASRC_SYNC_DIV_OUT0 201
#define TISCI_DEV_AASRC0_TX1_SYNC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 203
#define TISCI_DEV_AASRC0_TX1_SYNC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 204
#define TISCI_DEV_AASRC0_TX1_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 205
#define TISCI_DEV_AASRC0_TX1_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 206
#define TISCI_DEV_AASRC0_TX2_SYNC_CLK 211
#define TISCI_DEV_AASRC0_TX2_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSX_OUT 212
#define TISCI_DEV_AASRC0_TX2_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSX_OUT 213
#define TISCI_DEV_AASRC0_TX2_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0 214
#define TISCI_DEV_AASRC0_TX2_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0 215
#define TISCI_DEV_AASRC0_TX2_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0 216
#define TISCI_DEV_AASRC0_TX2_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0 220
#define TISCI_DEV_AASRC0_TX2_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0 221
#define TISCI_DEV_AASRC0_TX2_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSX_OUT 222
#define TISCI_DEV_AASRC0_TX2_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSX_OUT 223
#define TISCI_DEV_AASRC0_TX2_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSX_OUT 224
#define TISCI_DEV_AASRC0_TX2_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 228
#define TISCI_DEV_AASRC0_TX2_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 229
#define TISCI_DEV_AASRC0_TX2_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 230
#define TISCI_DEV_AASRC0_TX2_SYNC_CLK_PARENT_ADC_CLK_SEL_OUT0 232
#define TISCI_DEV_AASRC0_TX2_SYNC_CLK_PARENT_BOARD_0_MLB0_MLBCLK_OUT 233
#define TISCI_DEV_AASRC0_TX2_SYNC_CLK_PARENT_ASRC_SYNC_DIV_OUT0 234
#define TISCI_DEV_AASRC0_TX2_SYNC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 236
#define TISCI_DEV_AASRC0_TX2_SYNC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 237
#define TISCI_DEV_AASRC0_TX2_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 238
#define TISCI_DEV_AASRC0_TX2_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 239
#define TISCI_DEV_AASRC0_TX3_SYNC_CLK 244
#define TISCI_DEV_AASRC0_TX3_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSX_OUT 245
#define TISCI_DEV_AASRC0_TX3_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSX_OUT 246
#define TISCI_DEV_AASRC0_TX3_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0 247
#define TISCI_DEV_AASRC0_TX3_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0 248
#define TISCI_DEV_AASRC0_TX3_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0 249
#define TISCI_DEV_AASRC0_TX3_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0 253
#define TISCI_DEV_AASRC0_TX3_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0 254
#define TISCI_DEV_AASRC0_TX3_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSX_OUT 255
#define TISCI_DEV_AASRC0_TX3_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSX_OUT 256
#define TISCI_DEV_AASRC0_TX3_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSX_OUT 257
#define TISCI_DEV_AASRC0_TX3_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 261
#define TISCI_DEV_AASRC0_TX3_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 262
#define TISCI_DEV_AASRC0_TX3_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 263
#define TISCI_DEV_AASRC0_TX3_SYNC_CLK_PARENT_ADC_CLK_SEL_OUT0 265
#define TISCI_DEV_AASRC0_TX3_SYNC_CLK_PARENT_BOARD_0_MLB0_MLBCLK_OUT 266
#define TISCI_DEV_AASRC0_TX3_SYNC_CLK_PARENT_ASRC_SYNC_DIV_OUT0 267
#define TISCI_DEV_AASRC0_TX3_SYNC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 269
#define TISCI_DEV_AASRC0_TX3_SYNC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 270
#define TISCI_DEV_AASRC0_TX3_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 271
#define TISCI_DEV_AASRC0_TX3_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 272
#define TISCI_DEV_AASRC0_VBUSP_CLK 281
 
#define TISCI_DEV_AASRC1_RX0_SYNC_CLK 8
#define TISCI_DEV_AASRC1_RX0_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSR_OUT 9
#define TISCI_DEV_AASRC1_RX0_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSR_OUT 10
#define TISCI_DEV_AASRC1_RX0_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSR_OUT 11
#define TISCI_DEV_AASRC1_RX0_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSR_OUT 12
#define TISCI_DEV_AASRC1_RX0_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSR_OUT 13
#define TISCI_DEV_AASRC1_RX0_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSX_OUT 17
#define TISCI_DEV_AASRC1_RX0_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSX_OUT 18
#define TISCI_DEV_AASRC1_RX0_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSX_OUT 19
#define TISCI_DEV_AASRC1_RX0_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSX_OUT 20
#define TISCI_DEV_AASRC1_RX0_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSX_OUT 21
#define TISCI_DEV_AASRC1_RX0_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 25
#define TISCI_DEV_AASRC1_RX0_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 26
#define TISCI_DEV_AASRC1_RX0_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 27
#define TISCI_DEV_AASRC1_RX0_SYNC_CLK_PARENT_ADC_CLK_SEL_OUT0 29
#define TISCI_DEV_AASRC1_RX0_SYNC_CLK_PARENT_BOARD_0_MLB0_MLBCLK_OUT 30
#define TISCI_DEV_AASRC1_RX0_SYNC_CLK_PARENT_ASRC_SYNC_DIV_OUT0 31
#define TISCI_DEV_AASRC1_RX0_SYNC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 33
#define TISCI_DEV_AASRC1_RX0_SYNC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 34
#define TISCI_DEV_AASRC1_RX0_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 35
#define TISCI_DEV_AASRC1_RX0_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 36
#define TISCI_DEV_AASRC1_RX1_SYNC_CLK 41
#define TISCI_DEV_AASRC1_RX1_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSR_OUT 42
#define TISCI_DEV_AASRC1_RX1_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSR_OUT 43
#define TISCI_DEV_AASRC1_RX1_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSR_OUT 44
#define TISCI_DEV_AASRC1_RX1_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSR_OUT 45
#define TISCI_DEV_AASRC1_RX1_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSR_OUT 46
#define TISCI_DEV_AASRC1_RX1_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSX_OUT 50
#define TISCI_DEV_AASRC1_RX1_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSX_OUT 51
#define TISCI_DEV_AASRC1_RX1_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSX_OUT 52
#define TISCI_DEV_AASRC1_RX1_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSX_OUT 53
#define TISCI_DEV_AASRC1_RX1_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSX_OUT 54
#define TISCI_DEV_AASRC1_RX1_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 58
#define TISCI_DEV_AASRC1_RX1_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 59
#define TISCI_DEV_AASRC1_RX1_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 60
#define TISCI_DEV_AASRC1_RX1_SYNC_CLK_PARENT_ADC_CLK_SEL_OUT0 62
#define TISCI_DEV_AASRC1_RX1_SYNC_CLK_PARENT_BOARD_0_MLB0_MLBCLK_OUT 63
#define TISCI_DEV_AASRC1_RX1_SYNC_CLK_PARENT_ASRC_SYNC_DIV_OUT0 64
#define TISCI_DEV_AASRC1_RX1_SYNC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 66
#define TISCI_DEV_AASRC1_RX1_SYNC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 67
#define TISCI_DEV_AASRC1_RX1_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 68
#define TISCI_DEV_AASRC1_RX1_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 69
#define TISCI_DEV_AASRC1_RX2_SYNC_CLK 74
#define TISCI_DEV_AASRC1_RX2_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSR_OUT 75
#define TISCI_DEV_AASRC1_RX2_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSR_OUT 76
#define TISCI_DEV_AASRC1_RX2_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSR_OUT 77
#define TISCI_DEV_AASRC1_RX2_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSR_OUT 78
#define TISCI_DEV_AASRC1_RX2_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSR_OUT 79
#define TISCI_DEV_AASRC1_RX2_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSX_OUT 83
#define TISCI_DEV_AASRC1_RX2_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSX_OUT 84
#define TISCI_DEV_AASRC1_RX2_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSX_OUT 85
#define TISCI_DEV_AASRC1_RX2_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSX_OUT 86
#define TISCI_DEV_AASRC1_RX2_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSX_OUT 87
#define TISCI_DEV_AASRC1_RX2_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 91
#define TISCI_DEV_AASRC1_RX2_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 92
#define TISCI_DEV_AASRC1_RX2_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 93
#define TISCI_DEV_AASRC1_RX2_SYNC_CLK_PARENT_ADC_CLK_SEL_OUT0 95
#define TISCI_DEV_AASRC1_RX2_SYNC_CLK_PARENT_BOARD_0_MLB0_MLBCLK_OUT 96
#define TISCI_DEV_AASRC1_RX2_SYNC_CLK_PARENT_ASRC_SYNC_DIV_OUT0 97
#define TISCI_DEV_AASRC1_RX2_SYNC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 99
#define TISCI_DEV_AASRC1_RX2_SYNC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 100
#define TISCI_DEV_AASRC1_RX2_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 101
#define TISCI_DEV_AASRC1_RX2_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 102
#define TISCI_DEV_AASRC1_RX3_SYNC_CLK 107
#define TISCI_DEV_AASRC1_RX3_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSR_OUT 108
#define TISCI_DEV_AASRC1_RX3_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSR_OUT 109
#define TISCI_DEV_AASRC1_RX3_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSR_OUT 110
#define TISCI_DEV_AASRC1_RX3_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSR_OUT 111
#define TISCI_DEV_AASRC1_RX3_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSR_OUT 112
#define TISCI_DEV_AASRC1_RX3_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSX_OUT 116
#define TISCI_DEV_AASRC1_RX3_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSX_OUT 117
#define TISCI_DEV_AASRC1_RX3_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSX_OUT 118
#define TISCI_DEV_AASRC1_RX3_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSX_OUT 119
#define TISCI_DEV_AASRC1_RX3_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSX_OUT 120
#define TISCI_DEV_AASRC1_RX3_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 124
#define TISCI_DEV_AASRC1_RX3_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 125
#define TISCI_DEV_AASRC1_RX3_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 126
#define TISCI_DEV_AASRC1_RX3_SYNC_CLK_PARENT_ADC_CLK_SEL_OUT0 128
#define TISCI_DEV_AASRC1_RX3_SYNC_CLK_PARENT_BOARD_0_MLB0_MLBCLK_OUT 129
#define TISCI_DEV_AASRC1_RX3_SYNC_CLK_PARENT_ASRC_SYNC_DIV_OUT0 130
#define TISCI_DEV_AASRC1_RX3_SYNC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 132
#define TISCI_DEV_AASRC1_RX3_SYNC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 133
#define TISCI_DEV_AASRC1_RX3_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 134
#define TISCI_DEV_AASRC1_RX3_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 135
#define TISCI_DEV_AASRC1_SYS_CLK 144
#define TISCI_DEV_AASRC1_TX0_SYNC_CLK 145
#define TISCI_DEV_AASRC1_TX0_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSX_OUT 146
#define TISCI_DEV_AASRC1_TX0_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSX_OUT 147
#define TISCI_DEV_AASRC1_TX0_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0 148
#define TISCI_DEV_AASRC1_TX0_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0 149
#define TISCI_DEV_AASRC1_TX0_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0 150
#define TISCI_DEV_AASRC1_TX0_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0 154
#define TISCI_DEV_AASRC1_TX0_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0 155
#define TISCI_DEV_AASRC1_TX0_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSX_OUT 156
#define TISCI_DEV_AASRC1_TX0_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSX_OUT 157
#define TISCI_DEV_AASRC1_TX0_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSX_OUT 158
#define TISCI_DEV_AASRC1_TX0_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 162
#define TISCI_DEV_AASRC1_TX0_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 163
#define TISCI_DEV_AASRC1_TX0_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 164
#define TISCI_DEV_AASRC1_TX0_SYNC_CLK_PARENT_ADC_CLK_SEL_OUT0 166
#define TISCI_DEV_AASRC1_TX0_SYNC_CLK_PARENT_BOARD_0_MLB0_MLBCLK_OUT 167
#define TISCI_DEV_AASRC1_TX0_SYNC_CLK_PARENT_ASRC_SYNC_DIV_OUT0 168
#define TISCI_DEV_AASRC1_TX0_SYNC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 170
#define TISCI_DEV_AASRC1_TX0_SYNC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 171
#define TISCI_DEV_AASRC1_TX0_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 172
#define TISCI_DEV_AASRC1_TX0_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 173
#define TISCI_DEV_AASRC1_TX1_SYNC_CLK 178
#define TISCI_DEV_AASRC1_TX1_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSX_OUT 179
#define TISCI_DEV_AASRC1_TX1_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSX_OUT 180
#define TISCI_DEV_AASRC1_TX1_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0 181
#define TISCI_DEV_AASRC1_TX1_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0 182
#define TISCI_DEV_AASRC1_TX1_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0 183
#define TISCI_DEV_AASRC1_TX1_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0 187
#define TISCI_DEV_AASRC1_TX1_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0 188
#define TISCI_DEV_AASRC1_TX1_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSX_OUT 189
#define TISCI_DEV_AASRC1_TX1_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSX_OUT 190
#define TISCI_DEV_AASRC1_TX1_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSX_OUT 191
#define TISCI_DEV_AASRC1_TX1_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 195
#define TISCI_DEV_AASRC1_TX1_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 196
#define TISCI_DEV_AASRC1_TX1_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 197
#define TISCI_DEV_AASRC1_TX1_SYNC_CLK_PARENT_ADC_CLK_SEL_OUT0 199
#define TISCI_DEV_AASRC1_TX1_SYNC_CLK_PARENT_BOARD_0_MLB0_MLBCLK_OUT 200
#define TISCI_DEV_AASRC1_TX1_SYNC_CLK_PARENT_ASRC_SYNC_DIV_OUT0 201
#define TISCI_DEV_AASRC1_TX1_SYNC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 203
#define TISCI_DEV_AASRC1_TX1_SYNC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 204
#define TISCI_DEV_AASRC1_TX1_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 205
#define TISCI_DEV_AASRC1_TX1_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 206
#define TISCI_DEV_AASRC1_TX2_SYNC_CLK 211
#define TISCI_DEV_AASRC1_TX2_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSX_OUT 212
#define TISCI_DEV_AASRC1_TX2_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSX_OUT 213
#define TISCI_DEV_AASRC1_TX2_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0 214
#define TISCI_DEV_AASRC1_TX2_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0 215
#define TISCI_DEV_AASRC1_TX2_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0 216
#define TISCI_DEV_AASRC1_TX2_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0 220
#define TISCI_DEV_AASRC1_TX2_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0 221
#define TISCI_DEV_AASRC1_TX2_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSX_OUT 222
#define TISCI_DEV_AASRC1_TX2_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSX_OUT 223
#define TISCI_DEV_AASRC1_TX2_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSX_OUT 224
#define TISCI_DEV_AASRC1_TX2_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 228
#define TISCI_DEV_AASRC1_TX2_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 229
#define TISCI_DEV_AASRC1_TX2_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 230
#define TISCI_DEV_AASRC1_TX2_SYNC_CLK_PARENT_ADC_CLK_SEL_OUT0 232
#define TISCI_DEV_AASRC1_TX2_SYNC_CLK_PARENT_BOARD_0_MLB0_MLBCLK_OUT 233
#define TISCI_DEV_AASRC1_TX2_SYNC_CLK_PARENT_ASRC_SYNC_DIV_OUT0 234
#define TISCI_DEV_AASRC1_TX2_SYNC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 236
#define TISCI_DEV_AASRC1_TX2_SYNC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 237
#define TISCI_DEV_AASRC1_TX2_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 238
#define TISCI_DEV_AASRC1_TX2_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 239
#define TISCI_DEV_AASRC1_TX3_SYNC_CLK 244
#define TISCI_DEV_AASRC1_TX3_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSX_OUT 245
#define TISCI_DEV_AASRC1_TX3_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSX_OUT 246
#define TISCI_DEV_AASRC1_TX3_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0 247
#define TISCI_DEV_AASRC1_TX3_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0 248
#define TISCI_DEV_AASRC1_TX3_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0 249
#define TISCI_DEV_AASRC1_TX3_SYNC_CLK_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0 253
#define TISCI_DEV_AASRC1_TX3_SYNC_CLK_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0 254
#define TISCI_DEV_AASRC1_TX3_SYNC_CLK_PARENT_BOARD_0_MCASP2_AFSX_OUT 255
#define TISCI_DEV_AASRC1_TX3_SYNC_CLK_PARENT_BOARD_0_MCASP3_AFSX_OUT 256
#define TISCI_DEV_AASRC1_TX3_SYNC_CLK_PARENT_BOARD_0_MCASP4_AFSX_OUT 257
#define TISCI_DEV_AASRC1_TX3_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 261
#define TISCI_DEV_AASRC1_TX3_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 262
#define TISCI_DEV_AASRC1_TX3_SYNC_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 263
#define TISCI_DEV_AASRC1_TX3_SYNC_CLK_PARENT_ADC_CLK_SEL_OUT0 265
#define TISCI_DEV_AASRC1_TX3_SYNC_CLK_PARENT_BOARD_0_MLB0_MLBCLK_OUT 266
#define TISCI_DEV_AASRC1_TX3_SYNC_CLK_PARENT_ASRC_SYNC_DIV_OUT0 267
#define TISCI_DEV_AASRC1_TX3_SYNC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 269
#define TISCI_DEV_AASRC1_TX3_SYNC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 270
#define TISCI_DEV_AASRC1_TX3_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 271
#define TISCI_DEV_AASRC1_TX3_SYNC_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 272
#define TISCI_DEV_AASRC1_VBUSP_CLK 281
 
#define TISCI_DEV_DDPA0_DDPA_CLK 0
 
#define TISCI_DEV_EPWM0_VBUSP_CLK 0
 
#define TISCI_DEV_EPWM1_VBUSP_CLK 0
 
#define TISCI_DEV_EPWM2_VBUSP_CLK 0
 
#define TISCI_DEV_LED0_VBUS_CLK 1
 
#define TISCI_DEV_PBIST0_CLK8_CLK 7
#define TISCI_DEV_PBIST0_TCLK_CLK 9
 
#define TISCI_DEV_PBIST1_CLK8_CLK 7
#define TISCI_DEV_PBIST1_TCLK_CLK 9
 
#define TISCI_DEV_PBIST2_CLK8_CLK 7
#define TISCI_DEV_PBIST2_TCLK_CLK 9
 
#define TISCI_DEV_PBIST3_CLK8_CLK 7
#define TISCI_DEV_PBIST3_TCLK_CLK 9
 
#define TISCI_DEV_PBIST4_CLK8_CLK 7
#define TISCI_DEV_PBIST4_TCLK_CLK 9
 
#define TISCI_DEV_PBIST5_CLK8_CLK 7
#define TISCI_DEV_PBIST5_TCLK_CLK 9
 
#define TISCI_DEV_PBIST6_CLK8_CLK 7
#define TISCI_DEV_PBIST6_TCLK_CLK 9
 
#define TISCI_DEV_PBIST7_CLK8_CLK 7
#define TISCI_DEV_PBIST7_TCLK_CLK 9
 
#define TISCI_DEV_PBIST8_CLK8_CLK 7
#define TISCI_DEV_PBIST8_TCLK_CLK 9
 
#define TISCI_DEV_WKUP_PBIST1_CLK8_CLK 7
#define TISCI_DEV_WKUP_PBIST1_TCLK_CLK 9
 
#define TISCI_DEV_WKUP_PBIST0_CLK8_CLK 7
 
#define TISCI_DEV_WKUP_VTM0_FIX_REF2_CLK 0
#define TISCI_DEV_WKUP_VTM0_FIX_REF_CLK 1
#define TISCI_DEV_WKUP_VTM0_VBUSP_CLK 2
#define TISCI_DEV_WKUP_VTM0_VBUSP_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK 3
#define TISCI_DEV_WKUP_VTM0_VBUSP_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK 4
 
#define TISCI_DEV_MCAN0_MCANSS_CCLK_CLK 1
#define TISCI_DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK 2
#define TISCI_DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 3
#define TISCI_DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 4
#define TISCI_DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLK 5
#define TISCI_DEV_MCAN0_MCANSS_HCLK_CLK 6
 
#define TISCI_DEV_MCAN1_MCANSS_CCLK_CLK 1
#define TISCI_DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK 2
#define TISCI_DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 3
#define TISCI_DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 4
#define TISCI_DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLK 5
#define TISCI_DEV_MCAN1_MCANSS_HCLK_CLK 6
 
#define TISCI_DEV_MCAN2_MCANSS_CCLK_CLK 1
#define TISCI_DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK 2
#define TISCI_DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 3
#define TISCI_DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 4
#define TISCI_DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLK 5
#define TISCI_DEV_MCAN2_MCANSS_HCLK_CLK 6
 
#define TISCI_DEV_MCAN3_MCANSS_CCLK_CLK 1
#define TISCI_DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK 2
#define TISCI_DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 3
#define TISCI_DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 4
#define TISCI_DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLK 5
#define TISCI_DEV_MCAN3_MCANSS_HCLK_CLK 6
 
#define TISCI_DEV_MCAN4_MCANSS_CCLK_CLK 1
#define TISCI_DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK 2
#define TISCI_DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT 3
#define TISCI_DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 4
#define TISCI_DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLK 5
#define TISCI_DEV_MCAN4_MCANSS_HCLK_CLK 6
 
#define TISCI_DEV_MCASP0_AUX_CLK 0
#define TISCI_DEV_MCASP0_AUX_CLK_PARENT_MCASPN_AUXCLK_LOCAL_SEL_OUT0 1
#define TISCI_DEV_MCASP0_AUX_CLK_PARENT_MCASPN_AUXCLK_SEL_OUT0 2
#define TISCI_DEV_MCASP0_MCASP_ACLKR_PIN 3
#define TISCI_DEV_MCASP0_MCASP_ACLKR_POUT 4
#define TISCI_DEV_MCASP0_MCASP_ACLKX_PIN 5
#define TISCI_DEV_MCASP0_MCASP_ACLKX_POUT 6
#define TISCI_DEV_MCASP0_MCASP_AFSR_PIN 7
#define TISCI_DEV_MCASP0_MCASP_AFSR_POUT 8
#define TISCI_DEV_MCASP0_MCASP_AFSX_PIN 9
#define TISCI_DEV_MCASP0_MCASP_AFSX_POUT 10
#define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN 11
#define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT 12
#define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLK 13
#define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 14
#define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 15
#define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 16
#define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT 18
#define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 20
#define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 21
#define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 22
#define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 23
#define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 24
#define TISCI_DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 25
#define TISCI_DEV_MCASP0_MCASP_AHCLKR_POUT 28
#define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN 29
#define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT 30
#define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLK 31
#define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 32
#define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 33
#define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 34
#define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT 36
#define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 38
#define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 39
#define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 40
#define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 41
#define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 42
#define TISCI_DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 43
#define TISCI_DEV_MCASP0_MCASP_AHCLKX_POUT 46
#define TISCI_DEV_MCASP0_VBUSP_CLK 47
 
#define TISCI_DEV_MCASP1_AUX_CLK 0
#define TISCI_DEV_MCASP1_AUX_CLK_PARENT_MCASPN_AUXCLK_LOCAL_SEL_OUT1 1
#define TISCI_DEV_MCASP1_AUX_CLK_PARENT_MCASPN_AUXCLK_SEL_OUT1 2
#define TISCI_DEV_MCASP1_MCASP_ACLKR_PIN 3
#define TISCI_DEV_MCASP1_MCASP_ACLKR_POUT 4
#define TISCI_DEV_MCASP1_MCASP_ACLKX_PIN 5
#define TISCI_DEV_MCASP1_MCASP_ACLKX_POUT 6
#define TISCI_DEV_MCASP1_MCASP_AFSR_PIN 7
#define TISCI_DEV_MCASP1_MCASP_AFSR_POUT 8
#define TISCI_DEV_MCASP1_MCASP_AFSX_PIN 9
#define TISCI_DEV_MCASP1_MCASP_AFSX_POUT 10
#define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN 11
#define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT 12
#define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLK 13
#define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 14
#define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 15
#define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 16
#define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT 18
#define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 20
#define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 21
#define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 22
#define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 23
#define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 24
#define TISCI_DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 25
#define TISCI_DEV_MCASP1_MCASP_AHCLKR_POUT 28
#define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN 29
#define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT 30
#define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLK 31
#define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 32
#define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 33
#define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 34
#define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT 36
#define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 38
#define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 39
#define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 40
#define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 41
#define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 42
#define TISCI_DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 43
#define TISCI_DEV_MCASP1_MCASP_AHCLKX_POUT 46
#define TISCI_DEV_MCASP1_VBUSP_CLK 47
 
#define TISCI_DEV_MCASP2_AUX_CLK 0
#define TISCI_DEV_MCASP2_AUX_CLK_PARENT_MCASPN_AUXCLK_LOCAL_SEL_OUT2 1
#define TISCI_DEV_MCASP2_AUX_CLK_PARENT_MCASPN_AUXCLK_SEL_OUT2 2
#define TISCI_DEV_MCASP2_MCASP_ACLKR_PIN 3
#define TISCI_DEV_MCASP2_MCASP_ACLKR_POUT 4
#define TISCI_DEV_MCASP2_MCASP_ACLKX_PIN 5
#define TISCI_DEV_MCASP2_MCASP_ACLKX_POUT 6
#define TISCI_DEV_MCASP2_MCASP_AFSR_PIN 7
#define TISCI_DEV_MCASP2_MCASP_AFSR_POUT 8
#define TISCI_DEV_MCASP2_MCASP_AFSX_PIN 9
#define TISCI_DEV_MCASP2_MCASP_AFSX_POUT 10
#define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN 11
#define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT 12
#define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLK 13
#define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 14
#define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 15
#define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 16
#define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT 18
#define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 20
#define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 21
#define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 22
#define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 23
#define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 24
#define TISCI_DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 25
#define TISCI_DEV_MCASP2_MCASP_AHCLKR_POUT 28
#define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN 29
#define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT 30
#define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLK 31
#define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 32
#define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 33
#define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 34
#define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT 36
#define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 38
#define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 39
#define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 40
#define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 41
#define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 42
#define TISCI_DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 43
#define TISCI_DEV_MCASP2_MCASP_AHCLKX_POUT 46
#define TISCI_DEV_MCASP2_VBUSP_CLK 47
 
#define TISCI_DEV_MCASP3_AUX_CLK 0
#define TISCI_DEV_MCASP3_AUX_CLK_PARENT_MCASPN_AUXCLK_LOCAL_SEL_OUT3 1
#define TISCI_DEV_MCASP3_AUX_CLK_PARENT_MCASPN_AUXCLK_SEL_OUT3 2
#define TISCI_DEV_MCASP3_MCASP_ACLKR_PIN 3
#define TISCI_DEV_MCASP3_MCASP_ACLKR_POUT 4
#define TISCI_DEV_MCASP3_MCASP_ACLKX_PIN 5
#define TISCI_DEV_MCASP3_MCASP_ACLKX_POUT 6
#define TISCI_DEV_MCASP3_MCASP_AFSR_PIN 7
#define TISCI_DEV_MCASP3_MCASP_AFSR_POUT 8
#define TISCI_DEV_MCASP3_MCASP_AFSX_PIN 9
#define TISCI_DEV_MCASP3_MCASP_AFSX_POUT 10
#define TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN 11
#define TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT 12
#define TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLK 13
#define TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 14
#define TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 15
#define TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 16
#define TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT 18
#define TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 20
#define TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 21
#define TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 22
#define TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 23
#define TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 24
#define TISCI_DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 25
#define TISCI_DEV_MCASP3_MCASP_AHCLKR_POUT 28
#define TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN 29
#define TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT 30
#define TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLK 31
#define TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 32
#define TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 33
#define TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 34
#define TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT 36
#define TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 38
#define TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 39
#define TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 40
#define TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 41
#define TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 42
#define TISCI_DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 43
#define TISCI_DEV_MCASP3_MCASP_AHCLKX_POUT 46
#define TISCI_DEV_MCASP3_VBUSP_CLK 47
 
#define TISCI_DEV_MCASP4_AUX_CLK 0
#define TISCI_DEV_MCASP4_AUX_CLK_PARENT_MCASPN_AUXCLK_LOCAL_SEL_OUT4 1
#define TISCI_DEV_MCASP4_AUX_CLK_PARENT_MCASPN_AUXCLK_SEL_OUT4 2
#define TISCI_DEV_MCASP4_MCASP_ACLKR_PIN 3
#define TISCI_DEV_MCASP4_MCASP_ACLKR_POUT 4
#define TISCI_DEV_MCASP4_MCASP_ACLKX_PIN 5
#define TISCI_DEV_MCASP4_MCASP_ACLKX_POUT 6
#define TISCI_DEV_MCASP4_MCASP_AFSR_PIN 7
#define TISCI_DEV_MCASP4_MCASP_AFSR_POUT 8
#define TISCI_DEV_MCASP4_MCASP_AFSX_PIN 9
#define TISCI_DEV_MCASP4_MCASP_AFSX_POUT 10
#define TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN 11
#define TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT 12
#define TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLK 13
#define TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 14
#define TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 15
#define TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 16
#define TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT 18
#define TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 20
#define TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 21
#define TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 22
#define TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 23
#define TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 24
#define TISCI_DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 25
#define TISCI_DEV_MCASP4_MCASP_AHCLKR_POUT 28
#define TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN 29
#define TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT 30
#define TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLK 31
#define TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 32
#define TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 33
#define TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 34
#define TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT 36
#define TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 38
#define TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 39
#define TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 40
#define TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 41
#define TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 42
#define TISCI_DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 43
#define TISCI_DEV_MCASP4_MCASP_AHCLKX_POUT 46
#define TISCI_DEV_MCASP4_VBUSP_CLK 47
 
#define TISCI_DEV_MCRC64_0_CLK 0
 
#define TISCI_DEV_MLB0_MLBSS_HCLK_CLK 1
#define TISCI_DEV_MLB0_MLBSS_MLB_CLK 2
#define TISCI_DEV_MLB0_MLBSS_PCLK_CLK 3
#define TISCI_DEV_MLB0_MLBSS_SCLK_CLK 4
 
#define TISCI_DEV_I2C0_CLK 0
#define TISCI_DEV_I2C0_PISCL 1
#define TISCI_DEV_I2C0_PISYS_CLK 2
#define TISCI_DEV_I2C0_PORSCL 3
 
#define TISCI_DEV_I2C1_CLK 0
#define TISCI_DEV_I2C1_PISCL 1
#define TISCI_DEV_I2C1_PISYS_CLK 2
#define TISCI_DEV_I2C1_PORSCL 3
 
#define TISCI_DEV_I2C2_CLK 0
#define TISCI_DEV_I2C2_PISCL 1
#define TISCI_DEV_I2C2_PISYS_CLK 2
#define TISCI_DEV_I2C2_PORSCL 3
 
#define TISCI_DEV_I2C3_CLK 0
#define TISCI_DEV_I2C3_PISCL 1
#define TISCI_DEV_I2C3_PISYS_CLK 2
#define TISCI_DEV_I2C3_PORSCL 3
 
#define TISCI_DEV_I2C4_CLK 0
#define TISCI_DEV_I2C4_PISCL 1
#define TISCI_DEV_I2C4_PISYS_CLK 2
#define TISCI_DEV_I2C4_PORSCL 3
 
#define TISCI_DEV_I2C5_CLK 0
#define TISCI_DEV_I2C5_PISCL 1
#define TISCI_DEV_I2C5_PISYS_CLK 2
#define TISCI_DEV_I2C5_PORSCL 3
 
#define TISCI_DEV_I2C6_CLK 0
#define TISCI_DEV_I2C6_PISCL 1
#define TISCI_DEV_I2C6_PISYS_CLK 2
#define TISCI_DEV_I2C6_PORSCL 3
 
#define TISCI_DEV_WKUP_I2C0_CLK 0
#define TISCI_DEV_WKUP_I2C0_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK 1
#define TISCI_DEV_WKUP_I2C0_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK 2
#define TISCI_DEV_WKUP_I2C0_PISCL 3
#define TISCI_DEV_WKUP_I2C0_PISYS_CLK 4
#define TISCI_DEV_WKUP_I2C0_PORSCL 5
 
#define TISCI_DEV_R5FSS0_CORE0_CPU_CLK 0
#define TISCI_DEV_R5FSS0_CORE0_CPU_CLK_PARENT_HSDIV1_16FFT_MAIN_14_HSDIVOUT0_CLK 1
#define TISCI_DEV_R5FSS0_CORE0_CPU_CLK_PARENT_HSDIV1_16FFT_MAIN_14_HSDIVOUT0_CLK2 2
#define TISCI_DEV_R5FSS0_CORE0_INTERFACE_CLK 3
 
#define TISCI_DEV_R5FSS0_CORE1_CPU_CLK 0
#define TISCI_DEV_R5FSS0_CORE1_CPU_CLK_PARENT_HSDIV1_16FFT_MAIN_14_HSDIVOUT0_CLK 1
#define TISCI_DEV_R5FSS0_CORE1_CPU_CLK_PARENT_HSDIV1_16FFT_MAIN_14_HSDIVOUT0_CLK2 2
#define TISCI_DEV_R5FSS0_CORE1_INTERFACE_CLK 3
 
#define TISCI_DEV_R5FSS1_CORE0_CPU_CLK 0
#define TISCI_DEV_R5FSS1_CORE0_CPU_CLK_PARENT_HSDIV1_16FFT_MAIN_14_HSDIVOUT0_CLK 1
#define TISCI_DEV_R5FSS1_CORE0_CPU_CLK_PARENT_HSDIV1_16FFT_MAIN_14_HSDIVOUT0_CLK2 2
#define TISCI_DEV_R5FSS1_CORE0_INTERFACE_CLK 3
 
#define TISCI_DEV_R5FSS1_CORE1_CPU_CLK 0
#define TISCI_DEV_R5FSS1_CORE1_CPU_CLK_PARENT_HSDIV1_16FFT_MAIN_14_HSDIVOUT0_CLK 1
#define TISCI_DEV_R5FSS1_CORE1_CPU_CLK_PARENT_HSDIV1_16FFT_MAIN_14_HSDIVOUT0_CLK2 2
#define TISCI_DEV_R5FSS1_CORE1_INTERFACE_CLK 3
 
#define TISCI_DEV_WKUP_R5FSS0_CORE0_CPU_CLK 0
#define TISCI_DEV_WKUP_R5FSS0_CORE0_CPU_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK 1
#define TISCI_DEV_WKUP_R5FSS0_CORE0_CPU_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK 2
#define TISCI_DEV_WKUP_R5FSS0_CORE0_INTERFACE_CLK 5
 
#define TISCI_DEV_RL2_OF_CBA4_0_CLK 0
#define TISCI_DEV_RL2_OF_CBA4_0_TAGMEM_CLK 1
 
#define TISCI_DEV_RL2_OF_CBA4_1_CLK 0
#define TISCI_DEV_RL2_OF_CBA4_1_TAGMEM_CLK 1
 
#define TISCI_DEV_RL2_OF_CBA4_2_CLK 0
#define TISCI_DEV_RL2_OF_CBA4_2_TAGMEM_CLK 1
 
#define TISCI_DEV_RL2_OF_CBA4_3_CLK 0
#define TISCI_DEV_RL2_OF_CBA4_3_TAGMEM_CLK 1
 
#define TISCI_DEV_RL2_CORE0_CFG0_CLK 0
 
#define TISCI_DEV_RL2_CORE0_CFG1_CLK 0
 
#define TISCI_DEV_RL2_CORE1_CFG0_CLK 0
 
#define TISCI_DEV_RL2_CORE1_CFG1_CLK 0
 
#define TISCI_DEV_WKUP_RTCSS0_ANA_OSC32K_CLK 0
#define TISCI_DEV_WKUP_RTCSS0_ANA_OSC32K_CLK_PARENT_CLK_32K_RC_SEL_OUT0 1
#define TISCI_DEV_WKUP_RTCSS0_ANA_OSC32K_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 2
#define TISCI_DEV_WKUP_RTCSS0_JTAG_WRCK 4
#define TISCI_DEV_WKUP_RTCSS0_VCLK_CLK 6
#define TISCI_DEV_WKUP_RTCSS0_VCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK 7
#define TISCI_DEV_WKUP_RTCSS0_VCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK 8
 
#define TISCI_DEV_RTI4_RTI_CLK 0
#define TISCI_DEV_RTI4_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLK 1
#define TISCI_DEV_RTI4_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0 2
#define TISCI_DEV_RTI4_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 3
#define TISCI_DEV_RTI4_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 4
#define TISCI_DEV_RTI4_VBUSP_CLK 5
 
#define TISCI_DEV_RTI5_RTI_CLK 0
#define TISCI_DEV_RTI5_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLK 1
#define TISCI_DEV_RTI5_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0 2
#define TISCI_DEV_RTI5_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 3
#define TISCI_DEV_RTI5_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 4
#define TISCI_DEV_RTI5_VBUSP_CLK 5
 
#define TISCI_DEV_RTI0_RTI_CLK 0
#define TISCI_DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLK 1
#define TISCI_DEV_RTI0_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0 2
#define TISCI_DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 3
#define TISCI_DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 4
#define TISCI_DEV_RTI0_VBUSP_CLK 5
 
#define TISCI_DEV_RTI1_RTI_CLK 0
#define TISCI_DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLK 1
#define TISCI_DEV_RTI1_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0 2
#define TISCI_DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 3
#define TISCI_DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 4
#define TISCI_DEV_RTI1_VBUSP_CLK 5
 
#define TISCI_DEV_RTI2_RTI_CLK 0
#define TISCI_DEV_RTI2_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLK 1
#define TISCI_DEV_RTI2_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0 2
#define TISCI_DEV_RTI2_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 3
#define TISCI_DEV_RTI2_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 4
#define TISCI_DEV_RTI2_VBUSP_CLK 5
 
#define TISCI_DEV_RTI3_RTI_CLK 0
#define TISCI_DEV_RTI3_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLK 1
#define TISCI_DEV_RTI3_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0 2
#define TISCI_DEV_RTI3_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 3
#define TISCI_DEV_RTI3_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 4
#define TISCI_DEV_RTI3_VBUSP_CLK 5
 
#define TISCI_DEV_WKUP_RTI0_RTI_CLK 0
#define TISCI_DEV_WKUP_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLK 1
#define TISCI_DEV_WKUP_RTI0_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0 2
#define TISCI_DEV_WKUP_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 3
#define TISCI_DEV_WKUP_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 4
#define TISCI_DEV_WKUP_RTI0_VBUSP_CLK 5
#define TISCI_DEV_WKUP_RTI0_VBUSP_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK 6
#define TISCI_DEV_WKUP_RTI0_VBUSP_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK 7
 
#define TISCI_DEV_WKUP_DEEPSLEEP_SOURCES0_CLK_12M_RC_CLK 0
 
#define TISCI_DEV_DEBUGSS0_CFG_CLK 0
#define TISCI_DEV_DEBUGSS0_DBG_CLK 1
#define TISCI_DEV_DEBUGSS0_SYS_CLK 2
 
#define TISCI_DEV_WKUP_PSC0_CLK 0
#define TISCI_DEV_WKUP_PSC0_SLOW_CLK 1
 
#define TISCI_DEV_MCSPI0_CLKSPIREF_CLK 0
#define TISCI_DEV_MCSPI0_IO_CLKSPII_CLK 1
#define TISCI_DEV_MCSPI0_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI0_CLK_OUT 2
#define TISCI_DEV_MCSPI0_IO_CLKSPII_CLK_PARENT_SPI_MAIN_0_IO_CLKSPIO_CLK 3
#define TISCI_DEV_MCSPI0_IO_CLKSPIO_CLK 4
#define TISCI_DEV_MCSPI0_VBUSP_CLK 5
 
#define TISCI_DEV_MCSPI1_CLKSPIREF_CLK 0
#define TISCI_DEV_MCSPI1_IO_CLKSPII_CLK 1
#define TISCI_DEV_MCSPI1_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI1_CLK_OUT 2
#define TISCI_DEV_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MAIN_1_IO_CLKSPIO_CLK 3
#define TISCI_DEV_MCSPI1_IO_CLKSPIO_CLK 4
#define TISCI_DEV_MCSPI1_VBUSP_CLK 5
 
#define TISCI_DEV_MCSPI2_CLKSPIREF_CLK 0
#define TISCI_DEV_MCSPI2_IO_CLKSPII_CLK 1
#define TISCI_DEV_MCSPI2_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI2_CLK_OUT 2
#define TISCI_DEV_MCSPI2_IO_CLKSPII_CLK_PARENT_SPI_MAIN_2_IO_CLKSPIO_CLK 3
#define TISCI_DEV_MCSPI2_IO_CLKSPIO_CLK 4
#define TISCI_DEV_MCSPI2_VBUSP_CLK 5
 
#define TISCI_DEV_MCSPI3_CLKSPIREF_CLK 0
#define TISCI_DEV_MCSPI3_IO_CLKSPII_CLK 1
#define TISCI_DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI3_CLK_OUT 2
#define TISCI_DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK 3
#define TISCI_DEV_MCSPI3_IO_CLKSPIO_CLK 4
#define TISCI_DEV_MCSPI3_VBUSP_CLK 5
 
#define TISCI_DEV_MCSPI4_CLKSPIREF_CLK 0
#define TISCI_DEV_MCSPI4_IO_CLKSPII_CLK 1
#define TISCI_DEV_MCSPI4_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI4_CLK_OUT 2
#define TISCI_DEV_MCSPI4_IO_CLKSPII_CLK_PARENT_SPI_MAIN_4_IO_CLKSPIO_CLK 3
#define TISCI_DEV_MCSPI4_IO_CLKSPIO_CLK 4
#define TISCI_DEV_MCSPI4_VBUSP_CLK 5
 
#define TISCI_DEV_SPINLOCK0_VCLK_CLK 0
 
#define TISCI_DEV_UART0_FCLK_CLK 0
#define TISCI_DEV_UART0_FCLK_CLK_PARENT_USART_CLK_DIV_OUT0 1
#define TISCI_DEV_UART0_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK 2
#define TISCI_DEV_UART0_VBUSP_CLK 5
 
#define TISCI_DEV_UART1_FCLK_CLK 0
#define TISCI_DEV_UART1_FCLK_CLK_PARENT_USART_CLK_DIV_OUT1 1
#define TISCI_DEV_UART1_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK 2
#define TISCI_DEV_UART1_VBUSP_CLK 5
 
#define TISCI_DEV_UART2_FCLK_CLK 0
#define TISCI_DEV_UART2_FCLK_CLK_PARENT_USART_CLK_DIV_OUT2 1
#define TISCI_DEV_UART2_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK 2
#define TISCI_DEV_UART2_VBUSP_CLK 5
 
#define TISCI_DEV_UART3_FCLK_CLK 0
#define TISCI_DEV_UART3_FCLK_CLK_PARENT_USART_CLK_DIV_OUT3 1
#define TISCI_DEV_UART3_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK 2
#define TISCI_DEV_UART3_VBUSP_CLK 5
 
#define TISCI_DEV_UART4_FCLK_CLK 0
#define TISCI_DEV_UART4_FCLK_CLK_PARENT_USART_CLK_DIV_OUT4 1
#define TISCI_DEV_UART4_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK 2
#define TISCI_DEV_UART4_VBUSP_CLK 5
 
#define TISCI_DEV_UART5_FCLK_CLK 0
#define TISCI_DEV_UART5_FCLK_CLK_PARENT_USART_CLK_DIV_OUT5 1
#define TISCI_DEV_UART5_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK 2
#define TISCI_DEV_UART5_VBUSP_CLK 5
 
#define TISCI_DEV_UART6_FCLK_CLK 0
#define TISCI_DEV_UART6_FCLK_CLK_PARENT_USART_CLK_DIV_OUT6 1
#define TISCI_DEV_UART6_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK 2
#define TISCI_DEV_UART6_VBUSP_CLK 5
 
#define TISCI_DEV_WKUP_UART0_FCLK_CLK 0
#define TISCI_DEV_WKUP_UART0_VBUSP_CLK 3
#define TISCI_DEV_WKUP_UART0_VBUSP_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK 4
#define TISCI_DEV_WKUP_UART0_VBUSP_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK 5
 
#define TISCI_DEV_USB0_BUS_CLK 0
#define TISCI_DEV_USB0_CFG_CLK 1
#define TISCI_DEV_USB0_USB2_APB_PCLK_CLK 2
#define TISCI_DEV_USB0_USB2_REFCLOCK_CLK 3
#define TISCI_DEV_USB0_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLK 4
#define TISCI_DEV_USB0_USB2_REFCLOCK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT8_CLK 5
#define TISCI_DEV_USB0_USB2_TAP_TCK 10
 
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN 0
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT 1
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT 2
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT 3
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT 4
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT 5
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT 6
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT 7
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT 8
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT 9
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT 10
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 11
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 12
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 13
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 14
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK 15
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK 16
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK0_OUT 17
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN 18
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT 19
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT 20
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT 21
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT 22
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT 23
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT 24
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT 25
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT 26
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT 27
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT 28
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 29
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 30
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 31
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 32
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK 33
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK 34
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT 35
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN 36
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT 37
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT 38
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT 39
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT 40
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT 41
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT 42
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT 43
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT 44
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT 45
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT 46
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 47
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 48
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 49
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 50
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK 51
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK 52
#define TISCI_DEV_BOARD0_AUDIO_EXT_REFCLK2_OUT 53
#define TISCI_DEV_BOARD0_CLKOUT0_IN 54
#define TISCI_DEV_BOARD0_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK5 55
#define TISCI_DEV_BOARD0_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK10 56
#define TISCI_DEV_BOARD0_CP_GEMAC_CPTS0_RFT_CLK_OUT 57
#define TISCI_DEV_BOARD0_EXT_REFCLK1_OUT 58
#define TISCI_DEV_BOARD0_HYPERBUS0_CK_IN 59
#define TISCI_DEV_BOARD0_HYPERBUS0_CKN_IN 60
#define TISCI_DEV_BOARD0_I2C0_SCL_IN 61
#define TISCI_DEV_BOARD0_I2C0_SCL_OUT 62
#define TISCI_DEV_BOARD0_I2C1_SCL_IN 63
#define TISCI_DEV_BOARD0_I2C1_SCL_OUT 64
#define TISCI_DEV_BOARD0_I2C2_SCL_IN 65
#define TISCI_DEV_BOARD0_I2C2_SCL_OUT 66
#define TISCI_DEV_BOARD0_I2C3_SCL_IN 67
#define TISCI_DEV_BOARD0_I2C3_SCL_OUT 68
#define TISCI_DEV_BOARD0_I2C4_SCL_IN 69
#define TISCI_DEV_BOARD0_I2C4_SCL_OUT 70
#define TISCI_DEV_BOARD0_I2C5_SCL_IN 71
#define TISCI_DEV_BOARD0_I2C5_SCL_OUT 72
#define TISCI_DEV_BOARD0_I2C6_SCL_IN 73
#define TISCI_DEV_BOARD0_I2C6_SCL_OUT 74
#define TISCI_DEV_BOARD0_MCASP0_ACLKR_IN 76
#define TISCI_DEV_BOARD0_MCASP0_ACLKR_OUT 77
#define TISCI_DEV_BOARD0_MCASP0_ACLKX_IN 78
#define TISCI_DEV_BOARD0_MCASP0_ACLKX_OUT 79
#define TISCI_DEV_BOARD0_MCASP0_AFSR_IN 80
#define TISCI_DEV_BOARD0_MCASP0_AFSR_OUT 81
#define TISCI_DEV_BOARD0_MCASP0_AFSX_IN 82
#define TISCI_DEV_BOARD0_MCASP0_AFSX_OUT 83
#define TISCI_DEV_BOARD0_MCASP1_ACLKR_IN 84
#define TISCI_DEV_BOARD0_MCASP1_ACLKR_OUT 85
#define TISCI_DEV_BOARD0_MCASP1_ACLKX_IN 86
#define TISCI_DEV_BOARD0_MCASP1_ACLKX_OUT 87
#define TISCI_DEV_BOARD0_MCASP1_AFSR_IN 88
#define TISCI_DEV_BOARD0_MCASP1_AFSR_OUT 89
#define TISCI_DEV_BOARD0_MCASP1_AFSX_IN 90
#define TISCI_DEV_BOARD0_MCASP1_AFSX_OUT 91
#define TISCI_DEV_BOARD0_MCASP2_ACLKR_IN 92
#define TISCI_DEV_BOARD0_MCASP2_ACLKR_OUT 93
#define TISCI_DEV_BOARD0_MCASP2_ACLKX_IN 94
#define TISCI_DEV_BOARD0_MCASP2_ACLKX_OUT 95
#define TISCI_DEV_BOARD0_MCASP2_AFSR_IN 96
#define TISCI_DEV_BOARD0_MCASP2_AFSR_OUT 97
#define TISCI_DEV_BOARD0_MCASP2_AFSX_IN 98
#define TISCI_DEV_BOARD0_MCASP2_AFSX_OUT 99
#define TISCI_DEV_BOARD0_MCASP3_ACLKR_IN 100
#define TISCI_DEV_BOARD0_MCASP3_ACLKR_OUT 101
#define TISCI_DEV_BOARD0_MCASP3_ACLKX_IN 102
#define TISCI_DEV_BOARD0_MCASP3_ACLKX_OUT 103
#define TISCI_DEV_BOARD0_MCASP3_AFSR_IN 104
#define TISCI_DEV_BOARD0_MCASP3_AFSR_OUT 105
#define TISCI_DEV_BOARD0_MCASP3_AFSX_IN 106
#define TISCI_DEV_BOARD0_MCASP3_AFSX_OUT 107
#define TISCI_DEV_BOARD0_MCASP4_ACLKR_IN 108
#define TISCI_DEV_BOARD0_MCASP4_ACLKR_OUT 109
#define TISCI_DEV_BOARD0_MCASP4_ACLKX_IN 110
#define TISCI_DEV_BOARD0_MCASP4_ACLKX_OUT 111
#define TISCI_DEV_BOARD0_MCASP4_AFSR_IN 112
#define TISCI_DEV_BOARD0_MCASP4_AFSR_OUT 113
#define TISCI_DEV_BOARD0_MCASP4_AFSX_IN 114
#define TISCI_DEV_BOARD0_MCASP4_AFSX_OUT 115
#define TISCI_DEV_BOARD0_MCU_EXT_REFCLK0_OUT 116
#define TISCI_DEV_BOARD0_MCU_OBSCLK0_IN 117
#define TISCI_DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_MCU_OBSCLK_DIV_OUT0 118
#define TISCI_DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLK 119
#define TISCI_DEV_BOARD0_MCU_SYSCLKOUT0_IN 120
#define TISCI_DEV_BOARD0_MDIO0_MDC_IN 121
#define TISCI_DEV_BOARD0_MLB0_MLBCLK_OUT 122
#define TISCI_DEV_BOARD0_MMC0_CLKLB_IN 123
#define TISCI_DEV_BOARD0_MMC0_CLKLB_OUT 124
#define TISCI_DEV_BOARD0_MMC0_CLK_IN 125
#define TISCI_DEV_BOARD0_MMC0_CLK_OUT 126
#define TISCI_DEV_BOARD0_OBSCLK0_IN 127
#define TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_MAIN_OBSCLK_DIV_OUT0 128
#define TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLK 129
#define TISCI_DEV_BOARD0_OBSCLK1_IN 130
#define TISCI_DEV_BOARD0_OBSCLK1_IN_PARENT_MAIN_OBSCLK_DIV_OUT0 131
#define TISCI_DEV_BOARD0_OBSCLK1_IN_PARENT_GLUELOGIC_HFOSC0_CLK 132
#define TISCI_DEV_BOARD0_OSPI0_CLK_IN 133
#define TISCI_DEV_BOARD0_OSPI0_DQS_OUT 134
#define TISCI_DEV_BOARD0_OSPI0_LBCLKO_IN 135
#define TISCI_DEV_BOARD0_OSPI0_LBCLKO_OUT 136
#define TISCI_DEV_BOARD0_OSPI1_CLK_IN 137
#define TISCI_DEV_BOARD0_OSPI1_DQS_OUT 138
#define TISCI_DEV_BOARD0_OSPI1_LBCLKO_IN 139
#define TISCI_DEV_BOARD0_OSPI1_LBCLKO_OUT 140
#define TISCI_DEV_BOARD0_RGMII1_RXC_OUT 141
#define TISCI_DEV_BOARD0_RGMII2_RXC_OUT 143
#define TISCI_DEV_BOARD0_RMII1_REF_CLK_OUT 145
#define TISCI_DEV_BOARD0_RMII2_REF_CLK_OUT 146
#define TISCI_DEV_BOARD0_SPI0_CLK_IN 147
#define TISCI_DEV_BOARD0_SPI0_CLK_OUT 148
#define TISCI_DEV_BOARD0_SPI1_CLK_IN 149
#define TISCI_DEV_BOARD0_SPI1_CLK_OUT 150
#define TISCI_DEV_BOARD0_SPI2_CLK_IN 151
#define TISCI_DEV_BOARD0_SPI2_CLK_OUT 152
#define TISCI_DEV_BOARD0_SPI3_CLK_IN 153
#define TISCI_DEV_BOARD0_SPI3_CLK_OUT 154
#define TISCI_DEV_BOARD0_SPI4_CLK_IN 155
#define TISCI_DEV_BOARD0_SPI4_CLK_OUT 156
#define TISCI_DEV_BOARD0_SYSCLKOUT0_IN 157
#define TISCI_DEV_BOARD0_TCK_OUT 158
#define TISCI_DEV_BOARD0_TIMER_IO0_IN 159
#define TISCI_DEV_BOARD0_TIMER_IO1_IN 160
#define TISCI_DEV_BOARD0_TIMER_IO2_IN 161
#define TISCI_DEV_BOARD0_TIMER_IO3_IN 162
#define TISCI_DEV_BOARD0_TIMER_IO4_IN 163
#define TISCI_DEV_BOARD0_TIMER_IO5_IN 164
#define TISCI_DEV_BOARD0_TIMER_IO6_IN 165
#define TISCI_DEV_BOARD0_TIMER_IO7_IN 166
#define TISCI_DEV_BOARD0_TRC_CLK_IN 167
#define TISCI_DEV_BOARD0_WKUP_CLKOUT0_IN 168
#define TISCI_DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_WKUP_CLKOUT_SEL_OUT0 169
#define TISCI_DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_GLUELOGIC_HFOSC0_CLK 170
#define TISCI_DEV_BOARD0_WKUP_I2C0_SCL_IN 171
#define TISCI_DEV_BOARD0_WKUP_I2C0_SCL_OUT 172
#define TISCI_DEV_BOARD0_HFOSC1_CLK_OUT 173
 
#define TISCI_DEV_CLK_32K_RC_SEL_DEV_VD_CLK 0
#define TISCI_DEV_CLK_32K_RC_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 1
#define TISCI_DEV_CLK_32K_RC_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLK8 2
#define TISCI_DEV_CLK_32K_RC_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3_DUP0 3
#define TISCI_DEV_CLK_32K_RC_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_LFOSC0_CLKOUT 4
 
#define TISCI_DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK 0
#define TISCI_DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_LFOSC0_CLKOUT 1
#define TISCI_DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK 2
#define TISCI_DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK 3
#define TISCI_DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT9_CLK 4
#define TISCI_DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_CLK_32K_RC_SEL_OUT0 5
#define TISCI_DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 6
#define TISCI_DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLK 7
 
#define TISCI_DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK 0
#define TISCI_DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 1
#define TISCI_DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK 2
#define TISCI_DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT4_CLK 3
#define TISCI_DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK_DUP0 4
#define TISCI_DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 5
#define TISCI_DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLK 6
#define TISCI_DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLK8 7
#define TISCI_DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK 8
#define TISCI_DEV_MCU_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_CLK_32K_RC_SEL_OUT0 9
 
#define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK 0
#define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK 1
#define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK 2
#define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 3
#define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 4
#define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT0_CLK 5
#define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK 6
#define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK 7
#define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_CLK_32K_RC_SEL_OUT0 8
#define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_AM275_C7XV_WRAP_0_MAIN_0_CLOCK_CONTROL_0_C7XV_DIVH_CLK4_OBSCLK_OUT_CLK 9
#define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK 10
#define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK 11
#define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV1_16FFT_MAIN_14_HSDIVOUT0_CLK 12
#define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 13
#define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLK8 14
#define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0 15
#define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLK 16
#define TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 17
 
#define TISCI_DEV_MCASP0_AUXCLK_SEL_DEV_VD_CLK 0
#define TISCI_DEV_MCASP0_AUXCLK_SEL_DEV_VD_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK 1
#define TISCI_DEV_MCASP0_AUXCLK_SEL_DEV_VD_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK 2
#define TISCI_DEV_MCASP0_AUXCLK_SEL_DEV_VD_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 3
#define TISCI_DEV_MCASP0_AUXCLK_SEL_DEV_VD_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 4
#define TISCI_DEV_MCASP0_AUXCLK_SEL_DEV_VD_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 5
#define TISCI_DEV_MCASP0_AUXCLK_SEL_DEV_VD_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 6
#define TISCI_DEV_MCASP0_AUXCLK_SEL_DEV_VD_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 7
 
#define TISCI_DEV_MCASP1_AUXCLK_SEL_DEV_VD_CLK 0
#define TISCI_DEV_MCASP1_AUXCLK_SEL_DEV_VD_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK 1
#define TISCI_DEV_MCASP1_AUXCLK_SEL_DEV_VD_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK 2
#define TISCI_DEV_MCASP1_AUXCLK_SEL_DEV_VD_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 3
#define TISCI_DEV_MCASP1_AUXCLK_SEL_DEV_VD_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 4
#define TISCI_DEV_MCASP1_AUXCLK_SEL_DEV_VD_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 5
#define TISCI_DEV_MCASP1_AUXCLK_SEL_DEV_VD_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 6
#define TISCI_DEV_MCASP1_AUXCLK_SEL_DEV_VD_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 7
 
#define TISCI_DEV_MCASP2_AUXCLK_SEL_DEV_VD_CLK 0
#define TISCI_DEV_MCASP2_AUXCLK_SEL_DEV_VD_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK 1
#define TISCI_DEV_MCASP2_AUXCLK_SEL_DEV_VD_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK 2
#define TISCI_DEV_MCASP2_AUXCLK_SEL_DEV_VD_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 3
#define TISCI_DEV_MCASP2_AUXCLK_SEL_DEV_VD_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 4
#define TISCI_DEV_MCASP2_AUXCLK_SEL_DEV_VD_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 5
#define TISCI_DEV_MCASP2_AUXCLK_SEL_DEV_VD_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 6
#define TISCI_DEV_MCASP2_AUXCLK_SEL_DEV_VD_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 7
 
#define TISCI_DEV_MCASP3_AUXCLK_SEL_DEV_VD_CLK 0
#define TISCI_DEV_MCASP3_AUXCLK_SEL_DEV_VD_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK 1
#define TISCI_DEV_MCASP3_AUXCLK_SEL_DEV_VD_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK 2
#define TISCI_DEV_MCASP3_AUXCLK_SEL_DEV_VD_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 3
#define TISCI_DEV_MCASP3_AUXCLK_SEL_DEV_VD_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 4
#define TISCI_DEV_MCASP3_AUXCLK_SEL_DEV_VD_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 5
#define TISCI_DEV_MCASP3_AUXCLK_SEL_DEV_VD_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 6
#define TISCI_DEV_MCASP3_AUXCLK_SEL_DEV_VD_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 7
 
#define TISCI_DEV_MCASP4_AUXCLK_SEL_DEV_VD_CLK 0
#define TISCI_DEV_MCASP4_AUXCLK_SEL_DEV_VD_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK 1
#define TISCI_DEV_MCASP4_AUXCLK_SEL_DEV_VD_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK 2
#define TISCI_DEV_MCASP4_AUXCLK_SEL_DEV_VD_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 3
#define TISCI_DEV_MCASP4_AUXCLK_SEL_DEV_VD_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 4
#define TISCI_DEV_MCASP4_AUXCLK_SEL_DEV_VD_CLK_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT 5
#define TISCI_DEV_MCASP4_AUXCLK_SEL_DEV_VD_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT 6
#define TISCI_DEV_MCASP4_AUXCLK_SEL_DEV_VD_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 7
 
#define TISCI_DEV_MCASP0_LOCAL_AUXCLK_SEL_DEV_VD_CLK 0
#define TISCI_DEV_MCASP0_LOCAL_AUXCLK_SEL_DEV_VD_CLK_PARENT_MAIN_PLL4_HFOSC_SEL_OUT0 1
#define TISCI_DEV_MCASP0_LOCAL_AUXCLK_SEL_DEV_VD_CLK_PARENT_MAIN_PLL4_HFOSC_SEL_OUT02 2
#define TISCI_DEV_MCASP0_LOCAL_AUXCLK_SEL_DEV_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK 3
 
#define TISCI_DEV_MCASP1_LOCAL_AUXCLK_SEL_DEV_VD_CLK 0
#define TISCI_DEV_MCASP1_LOCAL_AUXCLK_SEL_DEV_VD_CLK_PARENT_MAIN_PLL4_HFOSC_SEL_OUT0 1
#define TISCI_DEV_MCASP1_LOCAL_AUXCLK_SEL_DEV_VD_CLK_PARENT_MAIN_PLL4_HFOSC_SEL_OUT02 2
#define TISCI_DEV_MCASP1_LOCAL_AUXCLK_SEL_DEV_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK 3
 
#define TISCI_DEV_MCASP2_LOCAL_AUXCLK_SEL_DEV_VD_CLK 0
#define TISCI_DEV_MCASP2_LOCAL_AUXCLK_SEL_DEV_VD_CLK_PARENT_MAIN_PLL4_HFOSC_SEL_OUT0 1
#define TISCI_DEV_MCASP2_LOCAL_AUXCLK_SEL_DEV_VD_CLK_PARENT_MAIN_PLL4_HFOSC_SEL_OUT02 2
#define TISCI_DEV_MCASP2_LOCAL_AUXCLK_SEL_DEV_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK 3
 
#define TISCI_DEV_MCASP3_LOCAL_AUXCLK_SEL_DEV_VD_CLK 0
#define TISCI_DEV_MCASP3_LOCAL_AUXCLK_SEL_DEV_VD_CLK_PARENT_MAIN_PLL4_HFOSC_SEL_OUT0 1
#define TISCI_DEV_MCASP3_LOCAL_AUXCLK_SEL_DEV_VD_CLK_PARENT_MAIN_PLL4_HFOSC_SEL_OUT02 2
#define TISCI_DEV_MCASP3_LOCAL_AUXCLK_SEL_DEV_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK 3
 
#define TISCI_DEV_MCASP4_LOCAL_AUXCLK_SEL_DEV_VD_CLK 0
#define TISCI_DEV_MCASP4_LOCAL_AUXCLK_SEL_DEV_VD_CLK_PARENT_MAIN_PLL4_HFOSC_SEL_OUT0 1
#define TISCI_DEV_MCASP4_LOCAL_AUXCLK_SEL_DEV_VD_CLK_PARENT_MAIN_PLL4_HFOSC_SEL_OUT02 2
#define TISCI_DEV_MCASP4_LOCAL_AUXCLK_SEL_DEV_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK 3
 
 
 
#ifdef __cplusplus
}
#endif
 
#endif /* SOC_AM275X_CLOCKS_H */