HYPERBUS peripheral is a driver which provides an interface with storage devices which follows HYPERRAM/HYPERFLASH protocol. The driver supports single bit, four bit and eight bit data lines to communicate with the connected media.
Features Supported
- Support for Cypress® HyperRAM
- Up to 166 MHz maximum memory bus operation for reads
- Low pin count interface with LVCMOS I/O pins (can be muxed with other FSS interfaces (OSPIs)) Two memory chip selects
- Linear incrementing mode for reads and writes
- Asynchronous bus clock
SysConfig Features
- Note
- It is strongly recommend to use SysConfig where it is available instead of using direct SW API calls. This will help simplify the SW application and also catch common mistakes early in the development cycle.
Features not Supported
- Cache-line wrap and fixed address modes for reads or writes
- General Purpose Output register (FSS0_HPB0_MC_GPOR) of the HBMC is not used
- HyperFlash
- ECC
- OTFA
Example Usage
Include the below file to access the APIs
Instance Open Example
Instance Close Example
API
APIs for HYPERBUS