SDL PBIST

Table of Contents

• Introduction
  • Use Cases
• Supported Combinations
• Steps to Run the Example
• See Also
• Sample Output

Introduction

This example demonstrates the usage of the PBIST module. The example shows how to setup and use the PBIST controller. The example configures the algorithm and memory group. Example also prints the time taken for test execution.

Use Cases

Use Case	Description
UC-1	Configure wrong combination of algorithm and memory group.
UC-2	Configure correct combination of algorithm and memory group.

Supported Combinations

Parameter	Value
CPU + OS	r5fss0-0 nortos
Toolchain	ti-arm-clang
Board	am273x-evm
Example folder	examples/sdl/pbist/pbist_mcu/

Steps to Run the Example

• When using CCS projects to build, import the CCS project for the required combination and build it using the CCS project menu (see Using SDK with CCS Projects).
• When using makefiles to build, note the required combination and build using make command (see Using SDK with Makefiles)
• Launch a CCS debug session and run the executable, see CCS Launch, Load and Run

See Also

PBIST

Sample Output

Shown below is a sample output when the application is run,

[Cortex_R5_0]
PBIST Application
 
Starting PBIST failure insertion test on TOP PBIST
PBIST failure Insertion test complete for TOP BIST
PBIST Failure Insertion Test completed in 19 micro secs
 
Starting PBIST test on TOP PBIST
PBIST complete for ADCBUF
PBIST complete for TPCC
PBIST complete for MAILBOX
PBIST complete for COREB VIM
PBIST complete for MCAN
PBIST complete for SPIA
PBIST complete for SPIB
PBIST complete for CORE B R5FSS RAM
PBIST complete for MSS_L2_1
PBIST complete for CPSW
PBIST complete for GPADC
PBIST complete for RETRAM
PBIST complete for STCROM
PBIST complete for CORE B ATCM
PBIST complete for CORE B BTCM
 
All tests have passed.
 
Starting PBIST failure insertion test on TOP PBIST
PBIST failure Insertion test complete for TOP BIST
PBIST Failure Insertion Test completed in 14 micro secs
 
Starting PBIST test on DSP PBIST
PBIST complete for DSS C66 STCROM
PBIST complete for HWA STCROM
PBIST complete for DSS PBISTROM
PBIST complete for C66 L1D
PBIST complete for C66 L1P
PBIST complete for PBIST C66 L2 TAG
PBIST complete for DSS HWA
PBIST complete for DSS HWA MBOX
PBIST complete for PBIST DSS L3 BANKA SUB0
PBIST complete for PBIST DSS L3 BANKB SUB0
PBIST complete for PBIST DSS L3 BANKC SUB0
PBIST complete for DSS MBOX RAM
PBIST complete for DSS TPCC RAM
PBIST complete for DSS L2 BANK0
PBIST complete for DSS L2 BANK1
PBIST complete for DSS L2 PARITY
PBIST complete for HWA RAM
PBIST complete for DSS CBUF
PBIST complete for PBIST DSS L3 BANKA SUB1
PBIST complete for PBIST DSS L3 BANKB SUB1
PBIST complete for PBIST DSS L3 BANKB SUB2
PBIST complete for PBIST DSS L3 BANKC SUB1
 
All tests have passed.
 
[Cortex_R5_1]
 PBIST Application
 
 Starting PBIST failure insertion test on TOP PBIST
 PBIST failure Insertion test complete for TOP BIST
PBIST Failure Insertion Test completed in 19 micro secs
 
 Starting PBIST test on TOP PBIST
 PBIST complete for MSS_TCMAROM_0
 PBIST complete for MSS_TCMAROM_1
 PBIST complete for PBISTROM
 PBIST complete for CORE A VIM
 PBIST complete for MSS_L2_0
 PBIST complete for CORE A ATCM
 PBIST complete for CORE A BTCM
 PBIST complete for CORE A R5SS RAM
 PBIST complete for MEM_TOP_AURORA
 PBIST complete for MEM_TOP_MDO
 PBIST complete for DBGSS_TRACE
 
All tests have passed.