soc_rcm.h

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/*
 *  Copyright (C) 2021 Texas Instruments Incorporated
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef SOC_RCM_AM273X_H_
#define SOC_RCM_AM273X_H_
 
#include <stdint.h>
 
#ifdef __cplusplus
extern "C"
{
#endif
 
#include <kernel/dpl/SystemP.h>
 
#define SOC_RCM_FREQ_HZ2MHZ(hz)     ((hz)/(1000000U))
#define SOC_RCM_FREQ_MHZ2HZ(mhz)    ((mhz)*(1000000U))
 
#define SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB00    (1U << 0U)
 
#define SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB01    (1U << 1U)
 
#define SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB10    (1U << 2U)
 
#define SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB11    (1U << 3U)
 
#define SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB20    (1U << 4U)
 
#define SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB21    (1U << 5U)
 
#define SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB30    (1U << 6U)
 
#define SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB31    (1U << 7U)
 
#define SOC_RCM_MEMINIT_DSSL2_MEMBANK_ALL     (SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB00 | \
                                               SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB01 | \
                                               SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB10 | \
                                               SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB11 | \
                                               SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB20 | \
                                               SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB21 | \
                                               SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB30 | \
                                               SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB31)
 
#define SOC_RCM_MEMINIT_DSSL3_MEMBANK_RAM0    (1U << 0U)
 
#define SOC_RCM_MEMINIT_DSSL3_MEMBANK_RAM1    (1U << 1U)
 
#define SOC_RCM_MEMINIT_DSSL3_MEMBANK_RAM2    (1U << 2U)
 
#define SOC_RCM_MEMINIT_DSSL3_MEMBANK_RAM3    (1U << 3U)
 
#define SOC_RCM_MEMINIT_DSSL3_MEMBANK_ALL     (SOC_RCM_MEMINIT_DSSL3_MEMBANK_RAM0 | \
                                               SOC_RCM_MEMINIT_DSSL3_MEMBANK_RAM1 | \
                                               SOC_RCM_MEMINIT_DSSL3_MEMBANK_RAM2 | \
                                               SOC_RCM_MEMINIT_DSSL3_MEMBANK_RAM3)
 
#define SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_0      (1U << 0U)
 
#define SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_1      (1U << 1U)
 
#define SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_2      (1U << 2U)
 
#define SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_3      (1U << 3U)
 
#define SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_ALL    (SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_0   | \
                                                SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_1   | \
                                                SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_2   | \
                                                SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_3)
 
/* @brief HSDIV output enable bitmask, used with \ref SOC_RcmPllHsDivOutConfig */
#define SOC_RCM_PLL_HSDIV_OUTPUT_COUNT         (4U)
 
typedef enum SOC_WarmResetCause_e
{
    SOC_WarmResetCause_POWER_ON_RESET = 0x09U,
    SOC_WarmResetCause_MSS_WDT = 0x0AU,
    SOC_WarmResetCause_TOP_RCM_WARM_RESET_CONFIG = 0x0CU,
    SOC_WarmResetCause_EXT_PAD_RESET = 0x08U,
    SOC_WarmResetCause_HSM_WDT = 0x18U,
 
}SOC_WarmResetCause;
typedef enum SOC_RcmResetCause_e
{
    SOC_RcmResetCause_POWER_ON_RESET = 0x0U,
    SOC_RcmResetCause_WARM_RESET = 0x1U,
    SOC_RcmResetCause_STC_RESET = 0x2U,
    SOC_RcmResetCause_MMR_CPU0_VIM0_RESET = 0x3U,
    SOC_RcmResetCause_MMR_CPU1_VIM1_RESET = 0x4U,
    SOC_RcmResetCause_MMR_CPU0_RESET = 0x5U,
    SOC_RcmResetCause_MMR_CPU1_RESET = 0x6U,
    SOC_RcmResetCause_DBG_CPU0_RESET = 0x7U,
    SOC_RcmResetCause_DBG_CPU1_RESET = 0x8U,
    SOC_RcmResetCause_FSM_TRIGGER_RESET = 0x9U,
    SOC_RcmResetCause_RST_CAUSE_UNKNOWN = 0xAU,
    SOC_RcmResetCause_MAX_VALUE = 0xFFFFFFFFu,
 
} SOC_RcmResetCause;
 
typedef enum SOC_RcmPeripheralId_e
{
    SOC_RcmPeripheralId_CSIRX,
    SOC_RcmPeripheralId_MSS_MCANA,
    SOC_RcmPeripheralId_MSS_MCANB,
    SOC_RcmPeripheralId_MSS_QSPI,
    SOC_RcmPeripheralId_MSS_RTIA,
    SOC_RcmPeripheralId_MSS_RTIB,
    SOC_RcmPeripheralId_MSS_RTIC,
    SOC_RcmPeripheralId_MSS_WDT,
    SOC_RcmPeripheralId_MSS_SPIA,
    SOC_RcmPeripheralId_MSS_SPIB,
    SOC_RcmPeripheralId_MSS_I2C,
    SOC_RcmPeripheralId_MSS_SCIA,
    SOC_RcmPeripheralId_MSS_SCIB,
    SOC_RcmPeripheralId_MSS_CPTS,
    SOC_RcmPeripheralId_MSS_CPSW,
    SOC_RcmPeripheralId_DSS_RTIA,
    SOC_RcmPeripheralId_DSS_RTIB,
    SOC_RcmPeripheralId_DSS_WDT,
    SOC_RcmPeripheralId_DSS_SCIA,
    SOC_RcmPeripheralId_RCSS_I2CA,
    SOC_RcmPeripheralId_RCSS_I2CB,
    SOC_RcmPeripheralId_RCSS_SCIA,
    SOC_RcmPeripheralId_RCSS_SPIA,
    SOC_RcmPeripheralId_RCSS_SPIB,
    SOC_RcmPeripheralId_RCSS_ATL,
    SOC_RcmPeripheralId_RCSS_MCASPA_AUX,
    SOC_RcmPeripheralId_RCSS_MCASPB_AUX,
    SOC_RcmPeripheralId_RCSS_MCASPC_AUX,
    SOC_RcmPeripheralId_MAX_VALUE = 0xFFFFFFFFu,
 
} SOC_RcmPeripheralId;
 
typedef enum SOC_RcmPeripheralClockSource_e
{
    SOC_RcmPeripheralClockSource_XTAL_CLK,
    SOC_RcmPeripheralClockSource_SYS_CLK,
    SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT1,
    SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT2,
    SOC_RcmPeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT1,
    SOC_RcmPeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT2,
    SOC_RcmPeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT3,
    SOC_RcmPeripheralClockSource_WUCPU_CLK,
    SOC_RcmPeripheralClockSource_XREF_CLK0,
    SOC_RcmPeripheralClockSource_XREF_CLK1,
    SOC_RcmPeripheralClockSource_MAX_VALUE = 0xFFFFFFFFu,
 
} SOC_RcmPeripheralClockSource;
 
typedef enum SOC_RcmDspClockSource_e
{
    SOC_RcmDspClockSource_XTAL_CLK,
    SOC_RcmDspClockSource_DPLL_DSP_HSDIV0_CLKOUT1,
    SOC_RcmDspClockSource_DPLL_CORE_HSDIV0_CLKOUT1,
    SOC_RcmDspClockSource_MAX_VALUE = 0xFFFFFFFFu,
 
} SOC_RcmDspClockSource;
 
typedef enum SOC_RcmR5ClockSource
{
    SOC_RcmR5ClockSource_DPLL_CORE_HSDIV0_CLKOUT2
 
} SOC_RcmR5ClockSource;
 
typedef enum SOC_RcmPllFoutFreqId_e
{
    SOC_RcmPllFoutFreqId_CLK_800MHZ,
    SOC_RcmPllFoutFreqId_CLK_900MHZ,
    SOC_RcmPllFoutFreqId_CLK_2000MHZ,
    SOC_RcmPllFoutFreqId_CLK_1800MHZ,
    SOC_RcmPllFoutFreqId_CLK_1920MHZ,
    SOC_RcmPllFoutFreqId_CLK_1699p21875MHZ,
    SOC_RcmPllFoutFreqId_CLK_1728MHZ,
    SOC_RcmPllFoutFreqId_CLK_1966p08MHZ,
    SOC_RcmPllFoutFreqId_CLK_1806p336MHZ,
    SOC_RcmPllFoutFreqId_MAX_VALUE = 0xFFFFFFFFu,
 
} SOC_RcmPllFoutFreqId;
 
typedef enum SOC_RcmQspiClockFreqId_e {
    SOC_RcmQspiClockFreqId_CLK_40MHZ = 0x0,
    SOC_RcmQspiClockFreqId_CLK_60MHZ = 0x1,
    SOC_RcmQspiClockFreqId_CLK_80MHZ = 0x2,
    SOC_RcmQspiClockFreqId_MAX_VALUE = 0xFFFFFFFFu,
 
} SOC_RcmQspiClockFreqId;
 
typedef enum SOC_RcmEfuseFlashClkModeId_e {
 
    SOC_RcmEfuseFlashClkModeId_0 = 0x0,
    SOC_RcmEfuseFlashClkModeId_3 = 0x3,
    SOC_RcmEfuseFlashClkModeId_MAX_VALUE = 0xFFFFFFFFu,
} SOC_RcmEfuseFlashClkModeId;
 
typedef struct SOC_RcmPllHsDivOutConfig_s
{
    uint32_t hsdivOutEnMask; 
    uint32_t hsDivOutFreqHz[SOC_RCM_PLL_HSDIV_OUTPUT_COUNT]; 
} SOC_RcmPllHsDivOutConfig;
 
typedef struct SOC_RcmEfuseQspiConfig_s
{
    SOC_RcmEfuseFlashClkModeId flashClockModeId;
    SOC_RcmQspiClockFreqId  qspiClockFreqId;
} SOC_RcmEfuseQspiConfig;
 
void SOC_rcmCoreApllConfig(SOC_RcmPllFoutFreqId outFreqId, SOC_RcmPllHsDivOutConfig *hsDivCfg);
 
void SOC_rcmCoreApllHSDivConfig(SOC_RcmPllHsDivOutConfig *hsDivCfg);
 
void SOC_rcmDspPllConfig(SOC_RcmPllFoutFreqId outFreqId, SOC_RcmPllHsDivOutConfig *hsDivCfg);
 
void SOC_rcmPerPllConfig(SOC_RcmPllFoutFreqId outFreqId, SOC_RcmPllHsDivOutConfig *hsDivCfg);
 
int32_t SOC_rcmSetR5Clock(uint32_t r5FreqHz, uint32_t sysClkFreqHz);
 
uint32_t SOC_rcmGetR5Clock(void);
 
int32_t SOC_rcmSetDspClock(SOC_RcmDspClockSource clkSource, uint32_t freqHz);
 
uint32_t SOC_rcmGetDspClock(void);
 
int32_t SOC_rcmSetPeripheralClock(SOC_RcmPeripheralId periphId, SOC_RcmPeripheralClockSource clkSource, uint32_t freqHz);
 
uint32_t SOC_rcmGetPeripheralClock(SOC_RcmPeripheralId periphId);
 
void SOC_rcmDspPowerOnReset(void);
 
void SOC_rcmR5PowerOnReset(void);
 
void SOC_rcmR5ConfigLockStep(void);
 
void SOC_rcmR5ConfigDualCore(void);
 
void SOC_rcmR5TriggerReset(void);
 
void SOC_rcmCr5bUnhalt(void);
 
void SOC_rcmC66xStart(void);
 
void SOC_rcmGetEfuseQspiConfig(SOC_RcmEfuseQspiConfig *qspiEfuseCfg);
 
SOC_RcmResetCause SOC_rcmGetResetCause(void);
 
void SOC_rcmStartMemInitTCMA(void);
 
void SOC_rcmWaitMemInitTCMA(void);
 
void SOC_rcmStartMemInitTCMB(void);
 
void SOC_rcmWaitMemInitTCMB(void);
 
void SOC_rcmMemInitMssMailboxMemory(void);
 
void SOC_rcmMemInitDssMailboxMemory(void);
 
void SOC_rcmStartMemInitMSSL2(void);
 
void SOC_rcmWaitMemInitMSSL2(void);
 
void SOC_rcmStartMemInitDSSL2(uint32_t l2bankMask);
 
void SOC_rcmWaitMemInitDSSL2(uint32_t l2bankMask);
 
void SOC_rcmStartMemInitDSSL3(uint32_t l3bankMask);
 
void SOC_rcmWaitMemInitDSSL3(uint32_t l3bankMask);
 
void SOC_rcmConfigEthMacIf(void);
 
uint32_t SOC_rcmIsR5FInLockStepMode(uint32_t r5fClusterGroupId);
 
void SOC_generateSwWarmReset(void);
 
SOC_WarmResetCause SOC_getWarmResetCause(void);
 
void SOC_clearWarmResetCause(void);
 
#ifdef __cplusplus
}
#endif
 
#endif