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AM273x MCU+ SDK
08.06.00
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Go to the documentation of this file.
33 #ifndef SIPC_NOTIFY__H_
34 #define SIPC_NOTIFY__H_
41 #include <drivers/secure_ipc_notify/soc/sipc_notify_soc.h>
52 typedef struct SIPC_InterruptConfig_s
69 typedef struct SIPC_MailboxConfig_s
SIPC_MailboxConfig gSIPC_R5MboxConfig[CORE_ID_MAX - 1]
Global structure that is pre-defined for this SOC to configure any R5 CPU to HSM mailbox communicatio...
This structure describes the information related to one interrupt that is setup for receiving mailbox...
Definition: sipc_notify_src.h:53
uint32_t writeDoneMailboxBaseAddr
Definition: sipc_notify_src.h:71
@ CORE_ID_MAX
Definition: sipc_notify_cfg.h:114
SIPC swQ structure which holds the data pointer to a fifo Queue in HSM MBOX memory.
Definition: sipc_notify_mailbox.h:63
SIPC_MailboxConfig gSIPC_HsmMboxConfig[CORE_ID_MAX - 1]
Global structure that is pre-defined for this SOC to configure any R5 CPU to HSM mailbox communicatio...
uint32_t intNum
Definition: sipc_notify_src.h:54
uint32_t clearIntOnInit
Definition: sipc_notify_src.h:63
uint8_t numCores
Definition: sipc_notify_src.h:57
SIPC_SwQueue * gSIPC_QueHsmToR5[MAX_SEC_CORES_WITH_HSM - 1]
Global structure holding HSM -> R5 queues addresses indexed by sec core id.
@ MAX_SEC_CORES_WITH_HSM
Definition: sipc_notify_cfg.h:128
HwiP_Object hwiObj
Definition: sipc_notify_src.h:56
uint8_t rdIntrBitPos
Definition: sipc_notify_src.h:74
This structure describes the mailbox information to send a message from core A to core B.
Definition: sipc_notify_src.h:70
SIPC_SwQueue * gSIPC_QueR5ToHsm[MAX_SEC_CORES_WITH_HSM - 1]
Global structure holding R5 to HSM queues addresses indexed by sec core id.
Opaque Hwi object used with the Hwi APIs.
Definition: HwiP.h:91
SIPC_SwQueue * swQ
Definition: sipc_notify_src.h:75
uint32_t readReqMailboxBaseAddr
Definition: sipc_notify_src.h:72
uint8_t wrIntrBitPos
Definition: sipc_notify_src.h:73
uint32_t eventId
Definition: sipc_notify_src.h:55