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AM273x MCU+ SDK
08.06.00
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34 #ifndef CSLR_SOC_DEFINES_H_
35 #define CSLR_SOC_DEFINES_H_
60 #define CSL_CORE_ID_R5FSS0_0 (0U)
61 #define CSL_CORE_ID_R5FSS0_1 (1U)
62 #define CSL_CORE_ID_C66SS0 (2U)
63 #define CSL_CORE_ID_MAX (3U)
71 #define PRIV_ID_HSMM4 (1U)
72 #define PRIV_ID_R5FSS (2U)
73 #define PRIV_ID_R5FSSI (3U)
74 #define PRIV_ID_DSSTPTC (5U)
80 #define CSL_EPWM_PER_CNT (3U)
83 #define CSL_MSS_UART_PER_CNT (2U)
84 #define CSL_DSS_UART_PER_CNT (1U)
85 #define CSL_RCSS_UART_PER_CNT (1U)
88 #define CSL_MSS_MIBSPI_PER_CNT (2U)
89 #define CSL_RCSS_MIBSPI_PER_CNT (2U)
92 #define CSL_MSS_I2C_CNT (1U)
93 #define CSL_RCSS_I2C_CNT (2U)
94 #define CSL_MSS_I2C_PER_CNT (CSL_MSS_I2C_CNT + CSL_RCSS_I2C_CNT)
95 #define CSL_DSS_I2C_PER_CNT (CSL_RCSS_I2C_CNT)
97 #define SOC_DSP_L1P_BASE (CSL_DSP_L1P_U_BASE)
98 #define SOC_DSP_L1D_BASE (CSL_DSP_L1D_U_BASE)
99 #define SOC_DSP_L2_BASE (CSL_DSP_L2_U_BASE)
100 #define SOC_DSP_ICFG_BASE (CSL_DSP_ICFG_U_BASE - 0x800000U)
106 #define SOC_EDMA_NUM_DMACH (64U)
108 #define SOC_EDMA_NUM_QDMACH (8U)
110 #define SOC_EDMA_NUM_PARAMSETS (256U)
112 #define SOC_EDMA_NUM_EVQUE (2U)
114 #define SOC_EDMA_CHMAPEXIST (1U)
116 #define SOC_EDMA_NUM_REGIONS (8U)
118 #define SOC_EDMA_MEMPROTECT (1U)
120 #define MCAN_MSG_RAM_MAX_WORD_COUNT (4352U)
123 #define ESM_NUM_GROUP_MAX (3U)
124 #define ESM_NUM_INTR_PER_GROUP (128U)
127 #define EDMA_DSS_TPCC_A_EVT_RTIA_DMA_REQ0 0
128 #define EDMA_DSS_TPCC_A_EVT_RTIA_DMA_REQ1 1
129 #define EDMA_DSS_TPCC_A_EVT_RTIA_DMA_REQ2 2
130 #define EDMA_DSS_TPCC_A_EVT_RTIA_DMA_REQ3 3
131 #define EDMA_DSS_TPCC_A_EVT_RTIB_DMA_REQ0 4
132 #define EDMA_DSS_TPCC_A_EVT_RTIB_DMA_REQ1 5
133 #define EDMA_DSS_TPCC_A_EVT_RTIB_DMA_REQ2 6
134 #define EDMA_DSS_TPCC_A_EVT_RTIB_DMA_REQ3 7
135 #define EDMA_DSS_TPCC_A_EVT_WDT_DMA_REQ0 8
136 #define EDMA_DSS_TPCC_A_EVT_WDT_DMA_REQ1 9
137 #define EDMA_DSS_TPCC_A_EVT_WDT_DMA_REQ2 10
138 #define EDMA_DSS_TPCC_A_EVT_WDT_DMA_REQ3 11
139 #define EDMA_DSS_TPCC_A_EVT_MCRC_DMA_REQ0 12
140 #define EDMA_DSS_TPCC_A_EVT_MCRC_DMA_REQ1 13
141 #define EDMA_DSS_TPCC_A_EVT_SCIA_RX_DMA_REQ 14
142 #define EDMA_DSS_TPCC_A_EVT_SCIA_TX_DMA_REQ 15
143 #define EDMA_DSS_TPCC_A_EVT_FREE_0 16
144 #define EDMA_DSS_TPCC_A_EVT_FREE_1 17
145 #define EDMA_DSS_TPCC_A_EVT_CBUFF_DMA_REQ0 18
146 #define EDMA_DSS_TPCC_A_EVT_CBUFF_DMA_REQ1 19
147 #define EDMA_DSS_TPCC_A_EVT_CBUFF_DMA_REQ2 20
148 #define EDMA_DSS_TPCC_A_EVT_CBUFF_DMA_REQ3 21
149 #define EDMA_DSS_TPCC_A_EVT_CBUFF_DMA_REQ4 22
150 #define EDMA_DSS_TPCC_A_EVT_CBUFF_DMA_REQ5 23
151 #define EDMA_DSS_TPCC_A_EVT_CBUFF_DMA_REQ6 24
152 #define EDMA_DSS_TPCC_A_EVT_FREE_2 25
153 #define EDMA_DSS_TPCC_A_EVT_FREE_3 26
154 #define EDMA_DSS_TPCC_A_EVT_FREE_4 27
155 #define EDMA_DSS_TPCC_A_EVT_FREE_5 28
156 #define EDMA_DSS_TPCC_A_EVT_FREE_6 29
157 #define EDMA_DSS_TPCC_A_EVT_FREE_7 30
158 #define EDMA_DSS_TPCC_A_EVT_FREE_8 31
159 #define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ0 32
160 #define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ1 33
161 #define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ2 34
162 #define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ3 35
163 #define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ4 36
164 #define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ5 37
165 #define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ6 38
166 #define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ7 39
167 #define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ8 40
168 #define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ9 41
169 #define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ10 42
170 #define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ11 43
171 #define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ12 44
172 #define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ13 45
173 #define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ14 46
174 #define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ15 47
175 #define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ16 48
176 #define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ17 49
177 #define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ18 50
178 #define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ19 51
179 #define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ20 52
180 #define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ21 53
181 #define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ22 54
182 #define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ23 55
183 #define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ24 56
184 #define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ25 57
185 #define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ26 58
186 #define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ27 59
187 #define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ28 60
188 #define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ29 61
189 #define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ30 62
190 #define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ31 63
193 #define EDMA_DSS_TPCC_B_EVT_RTIA_DMA_REQ0 0
194 #define EDMA_DSS_TPCC_B_EVT_RTIA_DMA_REQ1 1
195 #define EDMA_DSS_TPCC_B_EVT_RTIA_DMA_REQ2 2
196 #define EDMA_DSS_TPCC_B_EVT_RTIA_DMA_REQ3 3
197 #define EDMA_DSS_TPCC_B_EVT_RTIB_DMA_REQ0 4
198 #define EDMA_DSS_TPCC_B_EVT_RTIB_DMA_REQ1 5
199 #define EDMA_DSS_TPCC_B_EVT_RTIB_DMA_REQ2 6
200 #define EDMA_DSS_TPCC_B_EVT_RTIB_DMA_REQ3 7
201 #define EDMA_DSS_TPCC_B_EVT_WDT_DMA_REQ0 8
202 #define EDMA_DSS_TPCC_B_EVT_WDT_DMA_REQ1 9
203 #define EDMA_DSS_TPCC_B_EVT_WDT_DMA_REQ2 10
204 #define EDMA_DSS_TPCC_B_EVT_WDT_DMA_REQ3 11
205 #define EDMA_DSS_TPCC_B_EVT_MCRC_DMA_REQ0 12
206 #define EDMA_DSS_TPCC_B_EVT_MCRC_DMA_REQ1 13
207 #define EDMA_DSS_TPCC_B_EVT_SCIA_RX_DMA_REQ 14
208 #define EDMA_DSS_TPCC_B_EVT_SCIA_TX_DMA_REQ 15
209 #define EDMA_DSS_TPCC_B_EVT_CSI2A_EOF_INT 16
210 #define EDMA_DSS_TPCC_B_EVT_CSI2A_EOL_INT 17
211 #define EDMA_DSS_TPCC_B_EVT_CBUFF_DMA_REQ0 18
212 #define EDMA_DSS_TPCC_B_EVT_CBUFF_DMA_REQ1 19
213 #define EDMA_DSS_TPCC_B_EVT_CBUFF_DMA_REQ2 20
214 #define EDMA_DSS_TPCC_B_EVT_CBUFF_DMA_REQ3 21
215 #define EDMA_DSS_TPCC_B_EVT_CBUFF_DMA_REQ4 22
216 #define EDMA_DSS_TPCC_B_EVT_CBUFF_DMA_REQ5 23
217 #define EDMA_DSS_TPCC_B_EVT_CBUFF_DMA_REQ6 24
218 #define EDMA_DSS_TPCC_B_EVT_CSI2A_SOF_INT0 25
219 #define EDMA_DSS_TPCC_B_EVT_CSI2A_SOF_INT1 26
220 #define EDMA_DSS_TPCC_B_EVT_CSI2A_EOL_CNTX0 27
221 #define EDMA_DSS_TPCC_B_EVT_CSI2A_EOL_CNTX1 28
222 #define EDMA_DSS_TPCC_B_EVT_CSI2A_EOL_CNTX2 29
223 #define EDMA_DSS_TPCC_B_EVT_CSI2A_EOL_CNTX3 30
224 #define EDMA_DSS_TPCC_B_EVT_FREE_0 31
225 #define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ0 32
226 #define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ1 33
227 #define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ2 34
228 #define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ3 35
229 #define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ4 36
230 #define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ5 37
231 #define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ6 38
232 #define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ7 39
233 #define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ8 40
234 #define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ9 41
235 #define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ10 42
236 #define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ11 43
237 #define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ12 44
238 #define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ13 45
239 #define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ14 46
240 #define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ15 47
241 #define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ16 48
242 #define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ17 49
243 #define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ18 50
244 #define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ19 51
245 #define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ20 52
246 #define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ21 53
247 #define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ22 54
248 #define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ23 55
249 #define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ24 56
250 #define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ25 57
251 #define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ26 58
252 #define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ27 59
253 #define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ28 60
254 #define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ29 61
255 #define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ30 62
256 #define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ31 63
259 #define EDMA_DSS_TPCC_C_EVT_RTIA_DMA_REQ0 0
260 #define EDMA_DSS_TPCC_C_EVT_RTIA_DMA_REQ1 1
261 #define EDMA_DSS_TPCC_C_EVT_RTIA_DMA_REQ2 2
262 #define EDMA_DSS_TPCC_C_EVT_RTIA_DMA_REQ3 3
263 #define EDMA_DSS_TPCC_C_EVT_RTIB_DMA_REQ0 4
264 #define EDMA_DSS_TPCC_C_EVT_RTIB_DMA_REQ1 5
265 #define EDMA_DSS_TPCC_C_EVT_RTIB_DMA_REQ2 6
266 #define EDMA_DSS_TPCC_C_EVT_RTIB_DMA_REQ3 7
267 #define EDMA_DSS_TPCC_C_EVT_WDT_DMA_REQ0 8
268 #define EDMA_DSS_TPCC_C_EVT_WDT_DMA_REQ1 9
269 #define EDMA_DSS_TPCC_C_EVT_WDT_DMA_REQ2 10
270 #define EDMA_DSS_TPCC_C_EVT_WDT_DMA_REQ3 11
271 #define EDMA_DSS_TPCC_C_EVT_MCRC_DMA_REQ0 12
272 #define EDMA_DSS_TPCC_C_EVT_MCRC_DMA_REQ1 13
273 #define EDMA_DSS_TPCC_C_EVT_SCIA_RX_DMA_REQ 14
274 #define EDMA_DSS_TPCC_C_EVT_SCIA_TX_DMA_REQ 15
275 #define EDMA_DSS_TPCC_C_EVT_CSI2B_EOF_INT 16
276 #define EDMA_DSS_TPCC_C_EVT_CSI2B_EOL_INT 17
277 #define EDMA_DSS_TPCC_C_EVT_CBUFF_DMA_REQ0 18
278 #define EDMA_DSS_TPCC_C_EVT_CBUFF_DMA_REQ1 19
279 #define EDMA_DSS_TPCC_C_EVT_CBUFF_DMA_REQ2 20
280 #define EDMA_DSS_TPCC_C_EVT_CBUFF_DMA_REQ3 21
281 #define EDMA_DSS_TPCC_C_EVT_CBUFF_DMA_REQ4 22
282 #define EDMA_DSS_TPCC_C_EVT_CBUFF_DMA_REQ5 23
283 #define EDMA_DSS_TPCC_C_EVT_CBUFF_DMA_REQ6 24
284 #define EDMA_DSS_TPCC_C_EVT_CSI2B_SOF_INT0 25
285 #define EDMA_DSS_TPCC_C_EVT_CSI2B_SOF_INT1 26
286 #define EDMA_DSS_TPCC_C_EVT_CSI2B_EOL_CNTX0 27
287 #define EDMA_DSS_TPCC_C_EVT_CSI2B_EOL_CNTX1 28
288 #define EDMA_DSS_TPCC_C_EVT_CSI2B_EOL_CNTX2 29
289 #define EDMA_DSS_TPCC_C_EVT_CSI2B_EOL_CNTX3 30
290 #define EDMA_DSS_TPCC_C_EVT_FREE_0 31
291 #define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ0 32
292 #define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ1 33
293 #define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ2 34
294 #define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ3 35
295 #define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ4 36
296 #define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ5 37
297 #define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ6 38
298 #define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ7 39
299 #define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ8 40
300 #define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ9 41
301 #define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ10 42
302 #define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ11 43
303 #define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ12 44
304 #define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ13 45
305 #define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ14 46
306 #define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ15 47
307 #define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ16 48
308 #define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ17 49
309 #define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ18 50
310 #define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ19 51
311 #define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ20 52
312 #define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ21 53
313 #define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ22 54
314 #define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ23 55
315 #define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ24 56
316 #define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ25 57
317 #define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ26 58
318 #define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ27 59
319 #define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ28 60
320 #define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ29 61
321 #define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ30 62
322 #define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ31 63
326 #define EDMA_MSS_TPCC_A_EVT_SPIA_DMA_REQ0 0
327 #define EDMA_MSS_TPCC_A_EVT_SPIA_DMA_REQ1 1
328 #define EDMA_MSS_TPCC_A_EVT_SPIA_DMA_REQ2 2
329 #define EDMA_MSS_TPCC_A_EVT_SPIA_DMA_REQ3 3
330 #define EDMA_MSS_TPCC_A_EVT_SPIA_DMA_REQ4 4
331 #define EDMA_MSS_TPCC_A_EVT_SPIA_DMA_REQ5 5
332 #define EDMA_MSS_TPCC_A_EVT_SPIB_DMA_REQ0 6
333 #define EDMA_MSS_TPCC_A_EVT_SPIB_DMA_REQ1 7
334 #define EDMA_MSS_TPCC_A_EVT_SPIB_DMA_REQ2 8
335 #define EDMA_MSS_TPCC_A_EVT_SPIB_DMA_REQ3 9
336 #define EDMA_MSS_TPCC_A_EVT_SPIB_DMA_REQ4 10
337 #define EDMA_MSS_TPCC_A_EVT_SPIB_DMA_REQ5 11
338 #define EDMA_MSS_TPCC_A_EVT_QSPI_DMA_REQ0 12
339 #define EDMA_MSS_TPCC_A_EVT_MCRC_DMA_REQ0 13
340 #define EDMA_MSS_TPCC_A_EVT_MCRC_DMA_REQ1 14
341 #define EDMA_MSS_TPCC_A_EVT_RTIA_DMA_REQ0 15
342 #define EDMA_MSS_TPCC_A_EVT_RTIA_DMA_REQ1 16
343 #define EDMA_MSS_TPCC_A_EVT_RTIA_DMA_REQ2 17
344 #define EDMA_MSS_TPCC_A_EVT_RTIA_DMA_REQ3 18
345 #define EDMA_MSS_TPCC_A_EVT_RTIB_DMA_REQ0 19
346 #define EDMA_MSS_TPCC_A_EVT_RTIB_DMA_REQ1 20
347 #define EDMA_MSS_TPCC_A_EVT_RTIC_DMA_REQ0 21
348 #define EDMA_MSS_TPCC_A_EVT_RTIC_DMA_REQ1 22
349 #define EDMA_MSS_TPCC_A_EVT_WDT_DMA_REQ0 23
350 #define EDMA_MSS_TPCC_A_EVT_WDT_DMA_REQ1 24
351 #define EDMA_MSS_TPCC_A_EVT_WDT_DMA_REQ2 25
352 #define EDMA_MSS_TPCC_A_EVT_WDT_DMA_REQ3 26
353 #define EDMA_MSS_TPCC_A_EVT_ETPWMA_DMA_REQ0 27
354 #define EDMA_MSS_TPCC_A_EVT_ETPWMA_DMA_REQ1 28
355 #define EDMA_MSS_TPCC_A_EVT_ETPWMB_DMA_REQ0 29
356 #define EDMA_MSS_TPCC_A_EVT_ETPWMB_DMA_REQ1 30
357 #define EDMA_MSS_TPCC_A_EVT_ETPWMC_DMA_REQ0 31
358 #define EDMA_MSS_TPCC_A_EVT_ETPWMC_DMA_REQ1 32
359 #define EDMA_MSS_TPCC_A_EVT_MCANA_DMA_REQ0 33
360 #define EDMA_MSS_TPCC_A_EVT_MCANA_DMA_REQ1 34
361 #define EDMA_MSS_TPCC_A_EVT_MCANA_FE_INT1 35
362 #define EDMA_MSS_TPCC_A_EVT_MCANA_FE_INT2 36
363 #define EDMA_MSS_TPCC_A_EVT_MCANA_FE_INT4 37
364 #define EDMA_MSS_TPCC_A_EVT_MCANB_DMA_REQ0 38
365 #define EDMA_MSS_TPCC_A_EVT_MCANB_DMA_REQ1 39
366 #define EDMA_MSS_TPCC_A_EVT_MCANB_FE_INT1 40
367 #define EDMA_MSS_TPCC_A_EVT_MCANB_FE_INT2 41
368 #define EDMA_MSS_TPCC_A_EVT_MCANB_FE_INT4 42
369 #define EDMA_MSS_TPCC_A_EVT_RTIB_DMA_REQ2 43
370 #define EDMA_MSS_TPCC_A_EVT_RTIB_DMA_REQ3 44
371 #define EDMA_MSS_TPCC_A_EVT_RTIC_DMA_REQ2 45
372 #define EDMA_MSS_TPCC_A_EVT_RTIC_DMA_REQ3 46
373 #define EDMA_MSS_TPCC_A_EVT_FREE_0 47
374 #define EDMA_MSS_TPCC_A_EVT_FREE_1 48
375 #define EDMA_MSS_TPCC_A_EVT_GIO_PAD_INT0 49
376 #define EDMA_MSS_TPCC_A_EVT_GIO_PAD_INT1 50
377 #define EDMA_MSS_TPCC_A_EVT_GIO_PAD_INT2 51
378 #define EDMA_MSS_TPCC_A_EVT_GIO_PAD_INT3 52
379 #define EDMA_MSS_TPCC_A_EVT_GIO_PAD_INT4 53
380 #define EDMA_MSS_TPCC_A_EVT_FREE_2 54
381 #define EDMA_MSS_TPCC_A_EVT_I2C_DMA_REQ0 55
382 #define EDMA_MSS_TPCC_A_EVT_I2C_DMA_REQ1 56
383 #define EDMA_MSS_TPCC_A_EVT_SCIA_RX_DMA_REQ 57
384 #define EDMA_MSS_TPCC_A_EVT_SCIA_TX_DMA_REQ 58
385 #define EDMA_MSS_TPCC_A_EVT_SCIB_RX_DMA_REQ 59
386 #define EDMA_MSS_TPCC_A_EVT_SCIB_TX_DMA_REQ 60
387 #define EDMA_MSS_TPCC_A_EVT_FREE_3 61
388 #define EDMA_MSS_TPCC_A_EVT_FREE_4 62
389 #define EDMA_MSS_TPCC_A_EVT_CBUFF_DMA_REQ 63
392 #define EDMA_MSS_TPCC_B_EVT_MCRC_DMA_REQ0 0
393 #define EDMA_MSS_TPCC_B_EVT_MCRC_DMA_REQ1 1
394 #define EDMA_MSS_TPCC_B_EVT_ETPWMA_DMA_REQ0 2
395 #define EDMA_MSS_TPCC_B_EVT_ETPWMA_DMA_REQ1 3
396 #define EDMA_MSS_TPCC_B_EVT_ETPWMB_DMA_REQ0 4
397 #define EDMA_MSS_TPCC_B_EVT_ETPWMB_DMA_REQ1 5
398 #define EDMA_MSS_TPCC_B_EVT_ETPWMC_DMA_REQ0 6
399 #define EDMA_MSS_TPCC_B_EVT_ETPWMC_DMA_REQ1 7
400 #define EDMA_MSS_TPCC_B_EVT_MCANA_DMA_REQ0 8
401 #define EDMA_MSS_TPCC_B_EVT_MCANA_DMA_REQ1 9
402 #define EDMA_MSS_TPCC_B_EVT_MCANB_DMA_REQ0 10
403 #define EDMA_MSS_TPCC_B_EVT_MCANB_DMA_REQ1 11
404 #define EDMA_MSS_TPCC_B_EVT_FREE_0 12
405 #define EDMA_MSS_TPCC_B_EVT_FREE_1 13
406 #define EDMA_MSS_TPCC_B_EVT_FREE_2 14
407 #define EDMA_MSS_TPCC_B_EVT_FREE_3 15
408 #define EDMA_MSS_TPCC_B_EVT_GIO_PAD_INT0 16
409 #define EDMA_MSS_TPCC_B_EVT_GIO_PAD_INT1 17
410 #define EDMA_MSS_TPCC_B_EVT_GIO_PAD_INT2 18
411 #define EDMA_MSS_TPCC_B_EVT_GIO_PAD_INT3 19
412 #define EDMA_MSS_TPCC_B_EVT_GIO_PAD_INT4 20
413 #define EDMA_MSS_TPCC_B_EVT_FREE_4 21
414 #define EDMA_MSS_TPCC_B_EVT_FREE_5 22
415 #define EDMA_MSS_TPCC_B_EVT_FREE_6 23
416 #define EDMA_MSS_TPCC_B_EVT_FREE_7 24
417 #define EDMA_MSS_TPCC_B_EVT_FREE_8 25
418 #define EDMA_MSS_TPCC_B_EVT_DTHE_SHA_DMA_REQ0 26
419 #define EDMA_MSS_TPCC_B_EVT_DTHE_SHA_DMA_REQ1 27
420 #define EDMA_MSS_TPCC_B_EVT_DTHE_SHA_DMA_REQ2 28
421 #define EDMA_MSS_TPCC_B_EVT_DTHE_SHA_DMA_REQ3 29
422 #define EDMA_MSS_TPCC_B_EVT_DTHE_SHA_DMA_REQ4 30
423 #define EDMA_MSS_TPCC_B_EVT_DTHE_SHA_DMA_REQ5 31
424 #define EDMA_MSS_TPCC_B_EVT_DTHE_AES_DMA_REQ0 32
425 #define EDMA_MSS_TPCC_B_EVT_DTHE_AES_DMA_REQ1 33
426 #define EDMA_MSS_TPCC_B_EVT_DTHE_AES_DMA_REQ2 34
427 #define EDMA_MSS_TPCC_B_EVT_DTHE_AES_DMA_REQ3 35
428 #define EDMA_MSS_TPCC_B_EVT_DTHE_AES_DMA_REQ4 36
429 #define EDMA_MSS_TPCC_B_EVT_DTHE_AES_DMA_REQ5 37
430 #define EDMA_MSS_TPCC_B_EVT_DTHE_AES_DMA_REQ6 38
431 #define EDMA_MSS_TPCC_B_EVT_DTHE_AES_DMA_REQ7 39
432 #define EDMA_MSS_TPCC_B_EVT_FREE_9 40
433 #define EDMA_MSS_TPCC_B_EVT_FREE_10 41
434 #define EDMA_MSS_TPCC_B_EVT_FREE_11 42
435 #define EDMA_MSS_TPCC_B_EVT_MCANA_FE_INT1 43
436 #define EDMA_MSS_TPCC_B_EVT_MCANA_FE_INT2 44
437 #define EDMA_MSS_TPCC_B_EVT_MCANA_FE_INT3 45
438 #define EDMA_MSS_TPCC_B_EVT_MCANA_FE_INT4 46
439 #define EDMA_MSS_TPCC_B_EVT_MCANA_FE_INT5 47
440 #define EDMA_MSS_TPCC_B_EVT_MCANA_FE_INT6 48
441 #define EDMA_MSS_TPCC_B_EVT_MCANA_FE_INT7 49
442 #define EDMA_MSS_TPCC_B_EVT_MCANB_FE_INT1 50
443 #define EDMA_MSS_TPCC_B_EVT_MCANB_FE_INT2 51
444 #define EDMA_MSS_TPCC_B_EVT_MCANB_FE_INT3 52
445 #define EDMA_MSS_TPCC_B_EVT_MCANB_FE_INT4 53
446 #define EDMA_MSS_TPCC_B_EVT_MCANB_FE_INT5 54
447 #define EDMA_MSS_TPCC_B_EVT_MCANB_FE_INT6 55
448 #define EDMA_MSS_TPCC_B_EVT_MCANB_FE_INT7 56
449 #define EDMA_MSS_TPCC_B_EVT_FREE_12 57
450 #define EDMA_MSS_TPCC_B_EVT_FREE_13 58
451 #define EDMA_MSS_TPCC_B_EVT_FREE_14 59
452 #define EDMA_MSS_TPCC_B_EVT_FREE_15 60
453 #define EDMA_MSS_TPCC_B_EVT_FREE_16 61
454 #define EDMA_MSS_TPCC_B_EVT_FREE_17 62
455 #define EDMA_MSS_TPCC_B_EVT_FREE_18 63
458 #define EDMA_RCSS_TPCC_A_EVT_SPIA_DMA_REQ0 0
459 #define EDMA_RCSS_TPCC_A_EVT_SPIA_DMA_REQ1 1
460 #define EDMA_RCSS_TPCC_A_EVT_SPIA_DMA_REQ2 2
461 #define EDMA_RCSS_TPCC_A_EVT_SPIA_DMA_REQ3 3
462 #define EDMA_RCSS_TPCC_A_EVT_SPIA_DMA_REQ4 4
463 #define EDMA_RCSS_TPCC_A_EVT_SPIA_DMA_REQ5 5
464 #define EDMA_RCSS_TPCC_A_EVT_SPIB_DMA_REQ0 6
465 #define EDMA_RCSS_TPCC_A_EVT_SPIB_DMA_REQ1 7
466 #define EDMA_RCSS_TPCC_A_EVT_SPIB_DMA_REQ2 8
467 #define EDMA_RCSS_TPCC_A_EVT_SPIB_DMA_REQ3 9
468 #define EDMA_RCSS_TPCC_A_EVT_SPIB_DMA_REQ4 10
469 #define EDMA_RCSS_TPCC_A_EVT_SPIB_DMA_REQ5 11
470 #define EDMA_RCSS_TPCC_A_EVT_ECAP_DMA_REQ 12
471 #define EDMA_RCSS_TPCC_A_EVT_FREE_0 13
472 #define EDMA_RCSS_TPCC_A_EVT_FREE_1 14
473 #define EDMA_RCSS_TPCC_A_EVT_FREE_2 15
474 #define EDMA_RCSS_TPCC_A_EVT_CSI2A_EOF_INT 16
475 #define EDMA_RCSS_TPCC_A_EVT_CSI2A_EOL_INT 17
476 #define EDMA_RCSS_TPCC_A_EVT_CSI2A_EOL_CNTX0_INT 18
477 #define EDMA_RCSS_TPCC_A_EVT_CSI2A_EOL_CNTX1_INT 19
478 #define EDMA_RCSS_TPCC_A_EVT_CSI2A_EOL_CNTX2_INT 20
479 #define EDMA_RCSS_TPCC_A_EVT_CSI2A_EOL_CNTX3_INT 21
480 #define EDMA_RCSS_TPCC_A_EVT_CSI2A_EOL_CNTX4_INT 22
481 #define EDMA_RCSS_TPCC_A_EVT_CSI2A_EOL_CNTX5_INT 23
482 #define EDMA_RCSS_TPCC_A_EVT_CSI2A_EOL_CNTX6_INT 24
483 #define EDMA_RCSS_TPCC_A_EVT_CSI2A_EOL_CNTX7_INT 25
484 #define EDMA_RCSS_TPCC_A_EVT_CSI2A_SOF_TRIG0_INT 26
485 #define EDMA_RCSS_TPCC_A_EVT_CSI2A_SOF_TRIG1_INT 27
486 #define EDMA_RCSS_TPCC_A_EVT_FREE_3 28
487 #define EDMA_RCSS_TPCC_A_EVT_FREE_4 29
488 #define EDMA_RCSS_TPCC_A_EVT_FREE_5 30
489 #define EDMA_RCSS_TPCC_A_EVT_FREE_6 31
490 #define EDMA_RCSS_TPCC_A_EVT_CSI2B_EOF_INT 32
491 #define EDMA_RCSS_TPCC_A_EVT_CSI2B_EOL_INT 33
492 #define EDMA_RCSS_TPCC_A_EVT_CSI2B_EOL_CNTX0_INT 34
493 #define EDMA_RCSS_TPCC_A_EVT_CSI2B_EOL_CNTX1_INT 35
494 #define EDMA_RCSS_TPCC_A_EVT_CSI2B_EOL_CNTX2_INT 36
495 #define EDMA_RCSS_TPCC_A_EVT_CSI2B_EOL_CNTX3_INT 37
496 #define EDMA_RCSS_TPCC_A_EVT_CSI2B_EOL_CNTX4_INT 38
497 #define EDMA_RCSS_TPCC_A_EVT_CSI2B_EOL_CNTX5_INT 39
498 #define EDMA_RCSS_TPCC_A_EVT_CSI2B_EOL_CNTX6_INT 40
499 #define EDMA_RCSS_TPCC_A_EVT_CSI2B_EOL_CNTX7_INT 41
500 #define EDMA_RCSS_TPCC_A_EVT_CSI2B_SOF_TRIG0_INT 42
501 #define EDMA_RCSS_TPCC_A_EVT_CSI2B_SOF_TRIG1_INT 43
502 #define EDMA_RCSS_TPCC_A_EVT_SCIA_TX_SINGLE_REQ 44
503 #define EDMA_RCSS_TPCC_A_EVT_SCIA_TX_BURST_REQ 45
504 #define EDMA_RCSS_TPCC_A_EVT_FREE_7 46
505 #define EDMA_RCSS_TPCC_A_EVT_FREE_8 47
506 #define EDMA_RCSS_TPCC_A_EVT_MCASPA_TX_REQ 48
507 #define EDMA_RCSS_TPCC_A_EVT_MCASPB_TX_REQ 49
508 #define EDMA_RCSS_TPCC_A_EVT_MCASPC_TX_REQ 50
509 #define EDMA_RCSS_TPCC_A_EVT_MCASPA_RX_REQ 51
510 #define EDMA_RCSS_TPCC_A_EVT_MCASPB_RX_REQ 52
511 #define EDMA_RCSS_TPCC_A_EVT_MCASPC_RX_REQ 53
512 #define EDMA_RCSS_TPCC_A_EVT_I2CA_TX_DMA_REQ 54
513 #define EDMA_RCSS_TPCC_A_EVT_I2CA_RX_DMA_REQ 55
514 #define EDMA_RCSS_TPCC_A_EVT_I2CB_TX_DMA_REQ 56
515 #define EDMA_RCSS_TPCC_A_EVT_I2CB_RX_DMA_REQ 57
516 #define EDMA_RCSS_TPCC_A_EVT_SCIA_RX_SINGLE_REQ 58
517 #define EDMA_RCSS_TPCC_A_EVT_SCIA_RX_BURST_REQ 59
518 #define EDMA_RCSS_TPCC_A_EVT_FREE_9 60
519 #define EDMA_RCSS_TPCC_A_EVT_FREE_10 61
520 #define EDMA_RCSS_TPCC_A_EVT_FREE_11 62
521 #define EDMA_RCSS_TPCC_A_EVT_FREE_12 63
524 #define EDMA_DSS_TPCC_A_NUM_PARAM_SETS (128U)
525 #define EDMA_DSS_TPCC_A_NUM_DMA_CHANS (64U)
526 #define EDMA_DSS_TPCC_A_NUM_TC (2U)
528 #define EDMA_DSS_TPCC_B_NUM_PARAM_SETS (128U)
529 #define EDMA_DSS_TPCC_B_NUM_DMA_CHANS (64U)
530 #define EDMA_DSS_TPCC_B_NUM_TC (2U)
532 #define EDMA_DSS_TPCC_C_NUM_PARAM_SETS (256U)
533 #define EDMA_DSS_TPCC_C_NUM_DMA_CHANS (64U)
537 #define EDMA_DSS_TPCC_C_NUM_TC (2U)
539 #define EDMA_RCSS_TPCC_A_NUM_PARAM_SETS (128U)
540 #define EDMA_RDSS_TPCC_A_NUM_DMA_CHANS (64U)
541 #define EDMA_RCSS_TPCC_A_NUM_TC (2U)
543 #define EDMA_MSS_TPCC_A_NUM_PARAM_SETS (128U)
544 #define EDMA_MSS_TPCC_A_NUM_DMA_CHANS (64U)
545 #define EDMA_MSS_TPCC_A_NUM_TC (2U)
547 #define EDMA_MSS_TPCC_B_NUM_PARAM_SETS (128U)
548 #define EDMA_MSS_TPCC_B_NUM_DMA_CHANS (64U)
549 #define EDMA_MSS_TPCC_B_NUM_TC (1U)
551 #define EDMA_HSM_TPCC_A_NUM_PARAM_SETS (128U)
552 #define EDMA_HSM_TPCC_A_NUM_TC (2U)
554 #define EDMA_TPCC_ERRAGG_TPCC_EERINT__POS (0U)
555 #define EDMA_TPCC_INTAGG_TPCC_INTG__POS (0U)
556 #define EDMA_TPCC_ERRAGG_TPTC_MIN_ERR__POS (2U)
558 #define EDMA_DSS_NUM_CC 4
560 #define EDMA_DSS_MAX_NUM_TC CSL_MAX(EDMA_DSS_TPCC_A_NUM_TC, \
561 CSL_MAX(EDMA_DSS_TPCC_B_NUM_TC, \
562 CSL_MAX(EDMA_DSS_TPCC_C_NUM_TC, \
563 EDMA_RCSS_TPCC_A_NUM_TC)))
565 #define EDMA_MSS_NUM_CC 6
567 #define EDMA_MSS_MAX_NUM_TC CSL_MAX(EDMA_MSS_TPCC_A_NUM_TC, \
568 CSL_MAX(EDMA_MSS_TPCC_B_NUM_TC, \
569 CSL_MAX(EDMA_DSS_TPCC_A_NUM_TC, \
570 CSL_MAX(EDMA_DSS_TPCC_B_NUM_TC, \
571 CSL_MAX(EDMA_DSS_TPCC_C_NUM_TC, \
572 EDMA_RCSS_TPCC_A_NUM_TC)))))
577 #define HWA_NUM_INSTANCES (1U)
580 #define SOC_HWA_NUM_MEM_BANKS (8U)
582 #define SOC_HWA_NUM_PARAM_SETS (64U)
584 #define SOC_HWA_NUM_DMA_CHANNEL (32U)
586 #define SOC_HWA_NUM_CSIRX_IRQS (20U)
588 #define SOC_HWA_MEM_SIZE (CSL_DSS_HWA_BANK_SIZE * SOC_HWA_NUM_MEM_BANKS)
593 #define HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_0_LINE_END (0U)
594 #define HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_1_LINE_END (1U)
595 #define HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_2_LINE_END (2U)
596 #define HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_3_LINE_END (3U)
597 #define HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_4_LINE_END (4U)
598 #define HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_5_LINE_END (5U)
599 #define HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_6_LINE_END (6U)
600 #define HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_7_LINE_END (7U)
601 #define HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_FRAME_START_0 (8U)
602 #define HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_FRAME_START_1 (9U)
604 #define HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_0_LINE_END (10U)
605 #define HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_1_LINE_END (11U)
606 #define HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_2_LINE_END (12U)
607 #define HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_3_LINE_END (13U)
608 #define HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_4_LINE_END (14U)
609 #define HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_5_LINE_END (15U)
610 #define HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_6_LINE_END (16U)
611 #define HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_7_LINE_END (17U)
612 #define HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_FRAME_START_0 (18U)
613 #define HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_FRAME_START_1 (19U)
620 #define MSS_SYS_VCLK 200000000U
621 #define R5F_CLOCK_MHZ 400U
630 #define CSL_ARM_R5_CLUSTER_GROUP_ID_0 ((uint32_t) 0x00U)
640 #define CSL_ARM_R5_CPU_ID_0 ((uint32_t) 0x00U)
642 #define CSL_ARM_R5_CPU_ID_1 ((uint32_t) 0x01U)
648 #if (__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R')
649 #define CSL_CACHE_L1P_LINESIZE (32U)
650 #define CSL_CACHE_L1D_LINESIZE (32U)
651 #elif defined(_TMS320C6X)
652 #define CSL_CACHE_L1P_LINESIZE (32U)
653 #define CSL_CACHE_L1D_LINESIZE (64U)
654 #define CSL_CACHE_L2_LINESIZE (128U)