AM273x MCU+ SDK  08.06.00
am273x/sdl_ecc_soc.h
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1 /*
2  * SDL ECC
3  *
4  * Software Diagnostics Library module for ECC
5  *
6  * Copyright (c) Texas Instruments Incorporated 2022-2023
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  *
12  * Redistributions of source code must retain the above copyright
13  * notice, this list of conditions and the following disclaimer.
14  *
15  * Redistributions in binary form must reproduce the above copyright
16  * notice, this list of conditions and the following disclaimer in the
17  * documentation and/or other materials provided with the
18  * distribution.
19  *
20  * Neither the name of Texas Instruments Incorporated nor the names of
21  * its contributors may be used to endorse or promote products derived
22  * from this software without specific prior written permission.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35  *
36  */
37 
38 #ifndef INCLUDE_SDL_ECC_SOC_H_
39 #define INCLUDE_SDL_ECC_SOC_H_
40 
41 #include <stdint.h>
42 #include <sdl/sdl_ecc.h>
43 #include <sdl/ecc/sdl_ip_ecc.h>
44 #include <sdl/include/sdl_types.h>
45 #include <sdl/esm/soc/am273x/sdl_esm_core.h>
46 #include <sdl/ecc/sdl_ecc_priv.h>
47 #include <sdl/include/am273x/sdlr_soc_ecc_aggr.h>
48 #include <sdl/include/am273x/soc_config.h>
49 #include <sdl/include/am273x/sdlr_intr_esm_dss.h>
50 #include <sdl/include/am273x/sdlr_intr_esm_mss.h>
51 #include <sdl/include/am273x/sdlr_soc_baseaddress.h>
52 
53 
54 #define SDL_ECC_WIDTH_UNDEFINED 0x1
55 
56 /* define Max memEntries for each aggregator (i.e. the number of RAM ID's with * Wrapper type) */
57 #define SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (28U)
58 #define SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (28U)
59 #define SDL_MSS_ECC_AGG_MSS_RAM_IDS_TOTAL_ENTRIES (8U)
60 #define SDL_DSS_ECC_AGG_RAM_IDS_TOTAL_ENTRIES (22U)
61 #define SDL_MSS_MCANA_ECC_RAM_IDS_TOTAL_ENTRIES (1U)
62 #define SDL_MSS_MCANB_ECC_RAM_IDS_TOTAL_ENTRIES (1U)
63 #define SDL_CPSW3GCSS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (8U)
64 #define SDL_ECC_Base_Address_TOTAL_ENTRIES (7U)
65 
66 #define SDL_MSS_CPSW0_ECC_U_BASE (SDL_MSS_CPSW_U_BASE + 0x3F000u)
67 /* define parity control register addresses */
68 #define SDL_TCM_PARITY_ERRFRC (0x02120144)
69 
70 /* MSS TPCC */
71 #define TPCC_PARITY_CTRL (0x0212015Cu)
72 #define SDL_R5FSS0_CORE0_TPCC0_PARITY_STATUS (0x02120160u)
73 /* DSS TPCC */
74 #define DSS_TPCCA_PARITY_CTRL (0x060200BCU)
75 #define DSS_TPCCB_PARITY_CTRL (0x060200C0U)
76 #define DSS_TPCCC_PARITY_CTRL (0x060200C4U)
77 #define SDL_R5FSS0_CORE0_TPCCA_PARITY_STATUS (0x060200C8U)
78 #define SDL_R5FSS0_CORE0_TPCCB_PARITY_STATUS (0x060200CCU)
79 #define SDL_R5FSS0_CORE0_TPCCC_PARITY_STATUS (0x060200D0U)
80 
85 static const SDL_MemConfig_t SDL_R5FSS0_CORE0_ECC_AGGR_MemEntries[SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
86 {
87  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID, 0u,
88  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_SIZE, 4u,
89  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_ROW_WIDTH, ((bool)false) },
90  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID, 0u,
91  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_SIZE, 4u,
92  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_ROW_WIDTH, ((bool)false) },
93  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID, 0u,
94  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_SIZE, 4u,
95  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_ROW_WIDTH, ((bool)false) },
96  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID, 0u,
97  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_SIZE, 4u,
98  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_ROW_WIDTH, ((bool)false) },
99  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID, 0u,
100  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_SIZE, 8u,
101  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_ROW_WIDTH, ((bool)false) },
102  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID, 0u,
103  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_SIZE, 8u,
104  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_ROW_WIDTH, ((bool)false) },
105  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID, 0u,
106  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_SIZE, 8u,
107  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_ROW_WIDTH, ((bool)false) },
108  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID, 0u,
109  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_SIZE, 8u,
110  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_ROW_WIDTH, ((bool)false) },
111  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID, 0u,
112  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_SIZE, 4u,
113  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_ROW_WIDTH, ((bool)false) },
114  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID, 0u,
115  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_SIZE, 4u,
116  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_ROW_WIDTH, ((bool)false) },
117  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID, 0u,
118  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_SIZE, 4u,
119  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_ROW_WIDTH, ((bool)false) },
120  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID, 0u,
121  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_SIZE, 4u,
122  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_ROW_WIDTH, ((bool)false) },
123  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID, 0u,
124  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_SIZE, 4u,
125  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_ROW_WIDTH, ((bool)false) },
126  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID, 0u,
127  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_SIZE, 4u,
128  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_ROW_WIDTH, ((bool)false) },
129  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID, 0u,
130  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_SIZE, 4u,
131  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_ROW_WIDTH, ((bool)false) },
132  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID, 0u,
133  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_SIZE, 4u,
134  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_ROW_WIDTH, ((bool)false) },
135  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID, 0u,
136  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_SIZE, 4u,
137  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_ROW_WIDTH, ((bool)false) },
138  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID, 0u,
139  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_SIZE, 4u,
140  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_ROW_WIDTH, ((bool)false) },
141  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID, 0u,
142  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_SIZE, 4u,
143  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_ROW_WIDTH, ((bool)false) },
144  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID, 0u,
145  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_SIZE, 4u,
146  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_ROW_WIDTH, ((bool)false) },
147  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID, 0u,
148  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_SIZE, 4u,
149  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_ROW_WIDTH, ((bool)false) },
150  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_ID, 0x0u,
151  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_SIZE, 4u,
152  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_ROW_WIDTH, ((bool)true) },
153  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_ID, 0x00u,
154  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_SIZE, 4u,
155  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_ROW_WIDTH, ((bool)true) },
156  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_ID, 0x00080000u,
157  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_SIZE, 4u,
158  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_ROW_WIDTH, ((bool)true) },
159  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_ID, 0x00080000u,
160  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_SIZE, 4u,
161  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_ROW_WIDTH, ((bool)true) },
162  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_ID, 0x00080000u,
163  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_SIZE, 4u,
164  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_ROW_WIDTH, ((bool)true) },
165  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_ID, 0x00080000u,
166  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_SIZE, 4u,
167  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_ROW_WIDTH, ((bool)true) },
168  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID, 0x02080000u,
169  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_SIZE, 4u,
170  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ROW_WIDTH, ((bool)true) },
171 };
172 
177 static const SDL_MemConfig_t SDL_R5FSS0_CORE1_ECC_AGGR_MemEntries[SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
178 {
179  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_RAM_ID, 0u,
180  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_RAM_SIZE, 4u,
181  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_ROW_WIDTH, ((bool)false) },
182  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_RAM_ID, 0u,
183  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_RAM_SIZE, 4u,
184  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_ROW_WIDTH, ((bool)false) },
185  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_RAM_ID, 0u,
186  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_RAM_SIZE, 4u,
187  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_ROW_WIDTH, ((bool)false) },
188  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_RAM_ID, 0u,
189  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_RAM_SIZE, 4u,
190  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_ROW_WIDTH, ((bool)false) },
191  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_RAM_ID, 0u,
192  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_RAM_SIZE, 8u,
193  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_ROW_WIDTH, ((bool)false) },
194  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_RAM_ID, 0u,
195  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_RAM_SIZE, 8u,
196  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_ROW_WIDTH, ((bool)false) },
197  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_RAM_ID, 0u,
198  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_RAM_SIZE, 8u,
199  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_ROW_WIDTH, ((bool)false) },
200  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_RAM_ID, 0u,
201  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_RAM_SIZE, 8u,
202  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_ROW_WIDTH, ((bool)false) },
203  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_RAM_ID, 0u,
204  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_RAM_SIZE, 4u,
205  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_ROW_WIDTH, ((bool)false) },
206  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_RAM_ID, 0u,
207  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_RAM_SIZE, 4u,
208  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_ROW_WIDTH, ((bool)false) },
209  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_RAM_ID, 0u,
210  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_RAM_SIZE, 4u,
211  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_ROW_WIDTH, ((bool)false) },
212  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_RAM_ID, 0u,
213  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_RAM_SIZE, 4u,
214  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_ROW_WIDTH, ((bool)false) },
215  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_RAM_ID, 0u,
216  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_RAM_SIZE, 4u,
217  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_ROW_WIDTH, ((bool)false) },
218  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_RAM_ID, 0u,
219  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_RAM_SIZE, 4u,
220  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_ROW_WIDTH, ((bool)false) },
221  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_RAM_ID, 0u,
222  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_RAM_SIZE, 4u,
223  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_ROW_WIDTH, ((bool)false) },
224  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_RAM_ID, 0u,
225  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_RAM_SIZE, 4u,
226  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_ROW_WIDTH, ((bool)false) },
227  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_RAM_ID, 0u,
228  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_RAM_SIZE, 4u,
229  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_ROW_WIDTH, ((bool)false) },
230  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_RAM_ID, 0u,
231  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_RAM_SIZE, 4u,
232  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_ROW_WIDTH, ((bool)false) },
233  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_RAM_ID, 0u,
234  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_RAM_SIZE, 4u,
235  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_ROW_WIDTH, ((bool)false) },
236  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_RAM_ID, 0u,
237  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_RAM_SIZE, 4u,
238  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_ROW_WIDTH, ((bool)false) },
239  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_RAM_ID, 0u,
240  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_RAM_SIZE, 4u,
241  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_ROW_WIDTH, ((bool)false) },
242  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_RAM_ID, 0x4000u,
243  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_RAM_SIZE, 4u,
244  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_ROW_WIDTH, ((bool)true) },
245  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_RAM_ID, 0x4000u,
246  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_RAM_SIZE, 4u,
247  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_ROW_WIDTH, ((bool)true) },
248  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_RAM_ID, 0x00084000u,
249  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_RAM_SIZE, 4u,
250  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_ROW_WIDTH, ((bool)true) },
251  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_RAM_ID, 0x00084000u,
252  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_RAM_SIZE, 4u,
253  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_ROW_WIDTH, ((bool)true) },
254  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_RAM_ID, 0x00084000u,
255  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_RAM_SIZE, 4u,
256  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_ROW_WIDTH, ((bool)true) },
257  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_RAM_ID, 0x00084000u,
258  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_RAM_SIZE, 4u,
259  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_ROW_WIDTH, ((bool)true) },
260  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_RAM_ID, 0x020A0000u,
261  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_RAM_SIZE, 4u,
262  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_ROW_WIDTH, ((bool)true) },
263 };
264 
269 const SDL_MemConfig_t SDL_MSS_ECC_AGG_MSS_MemEntries[SDL_MSS_ECC_AGG_MSS_RAM_IDS_TOTAL_ENTRIES] =
270 {
271  { SDL_MSS_ECC_AGG_MSS_MSS_L2RAMA_ECC_RAM_ID, 0x10200000u,
272  SDL_MSS_ECC_AGG_MSS_MSS_L2RAMA_ECC_RAM_SIZE, 8u,
273  SDL_MSS_ECC_AGG_MSS_MSS_L2RAMA_ECC_ROW_WIDTH, ((bool)true) },
274  { SDL_MSS_ECC_AGG_MSS_MSS_L2RAMB_ECC_RAM_ID, 0x10280000u,
275  SDL_MSS_ECC_AGG_MSS_MSS_L2RAMB_ECC_RAM_SIZE, 8u,
276  SDL_MSS_ECC_AGG_MSS_MSS_L2RAMB_ECC_ROW_WIDTH, ((bool)true) },
277  { SDL_MSS_ECC_AGG_MSS_MSS_MBOX_ECC_RAM_ID, 0xC5000000u,
278  SDL_MSS_ECC_AGG_MSS_MSS_MBOX_ECC_RAM_SIZE, 8u,
279  SDL_MSS_ECC_AGG_MSS_MSS_MBOX_ECC_ROW_WIDTH, ((bool)true) },
280  { SDL_MSS_ECC_AGG_MSS_MSS_RETRAM_ECC_RAM_ID, 0xC5010000u,
281  SDL_MSS_ECC_AGG_MSS_MSS_RETRAM_ECC_RAM_SIZE, 8u,
282  SDL_MSS_ECC_AGG_MSS_MSS_RETRAM_ECC_ROW_WIDTH, ((bool)true) },
283  { SDL_MSS_ECC_AGG_MSS_MSS_GPADC_DATA_RAM_ECC_RAM_ID, 0xC5030000u,
284  SDL_MSS_ECC_AGG_MSS_MSS_GPADC_DATA_RAM_ECC_RAM_SIZE, 8u,
285  SDL_MSS_ECC_AGG_MSS_MSS_GPADC_DATA_RAM_ECC_ROW_WIDTH, ((bool)true) },
286  { SDL_MSS_ECC_AGG_MSS_MSS_TPTC_A0_ECC_RAM_ID, 0u,
287  SDL_MSS_ECC_AGG_MSS_MSS_TPTC_A0_ECC_RAM_SIZE, 8u,
288  SDL_MSS_ECC_AGG_MSS_MSS_TPTC_A0_ECC_ROW_WIDTH, ((bool)false) },
289  { SDL_MSS_ECC_AGG_MSS_MSS_TPTC_A1_ECC_RAM_ID, 0u,
290  SDL_MSS_ECC_AGG_MSS_MSS_TPTC_A1_ECC_RAM_SIZE, 8u,
291  SDL_MSS_ECC_AGG_MSS_MSS_TPTC_A1_ECC_ROW_WIDTH, ((bool)false) },
292  { SDL_MSS_ECC_AGG_MSS_MSS_TPTC_B0_ECC_RAM_ID, 0u,
293  SDL_MSS_ECC_AGG_MSS_MSS_TPTC_B0_ECC_RAM_SIZE, 8u,
294  SDL_MSS_ECC_AGG_MSS_MSS_TPTC_B0_ECC_ROW_WIDTH, ((bool)false) },
295 };
296 
301 const SDL_MemConfig_t SDL_DSS_ECC_AGG_MemEntries[SDL_DSS_ECC_AGG_RAM_IDS_TOTAL_ENTRIES] =
302 {
303  { SDL_DSS_ECC_AGG_DSS_L3RAMA_ECC_RAM_ID, 0x88000000u,
304  SDL_DSS_ECC_AGG_DSS_L3RAMA_ECC_RAM_SIZE, 8u,
305  SDL_DSS_ECC_AGG_DSS_L3RAMA_ECC_ROW_WIDTH, ((bool)true) },
306  { SDL_DSS_ECC_AGG_DSS_L3RAMB_ECC_RAM_ID, 0x88100000u,
307  SDL_DSS_ECC_AGG_DSS_L3RAMB_ECC_RAM_SIZE, 8u,
308  SDL_DSS_ECC_AGG_DSS_L3RAMB_ECC_ROW_WIDTH, ((bool)true) },
309  { SDL_DSS_ECC_AGG_DSS_L3RAMC_ECC_RAM_ID, 0x88200000u,
310  SDL_DSS_ECC_AGG_DSS_L3RAMC_ECC_RAM_SIZE, 8u,
311  SDL_DSS_ECC_AGG_DSS_L3RAMC_ECC_ROW_WIDTH, ((bool)true) },
312  { SDL_DSS_ECC_AGG_DSS_L3RAMD_ECC_RAM_ID, 0x88300000u,
313  SDL_DSS_ECC_AGG_DSS_L3RAMD_ECC_RAM_SIZE, 8u,
314  SDL_DSS_ECC_AGG_DSS_L3RAMD_ECC_ROW_WIDTH, ((bool)true) },
315  { SDL_DSS_ECC_AGG_DSS_MAILBOX_ECC_RAM_ID, 0x83100000u,
316  SDL_DSS_ECC_AGG_DSS_MAILBOX_ECC_RAM_SIZE, 8u,
317  SDL_DSS_ECC_AGG_DSS_MAILBOX_ECC_ROW_WIDTH, ((bool)true) },
318  { SDL_DSS_ECC_AGG_DSS_CM4_RAM_B0_ECC_RAM_ID, 0u,
319  SDL_DSS_ECC_AGG_DSS_CM4_RAM_B0_ECC_RAM_SIZE, 4u,
320  SDL_DSS_ECC_AGG_DSS_CM4_RAM_B0_ECC_ROW_WIDTH, ((bool)true) },
321  { SDL_DSS_ECC_AGG_DSS_CM4_RAM_B1_ECC_RAM_ID, 0u,
322  SDL_DSS_ECC_AGG_DSS_CM4_RAM_B1_ECC_RAM_SIZE, 4u,
323  SDL_DSS_ECC_AGG_DSS_CM4_RAM_B1_ECC_ROW_WIDTH, ((bool)true) },
324  { SDL_DSS_ECC_AGG_DSS_CM4_RAM_B2_ECC_RAM_ID, 0u,
325  SDL_DSS_ECC_AGG_DSS_CM4_RAM_B2_ECC_RAM_SIZE, 4u,
326  SDL_DSS_ECC_AGG_DSS_CM4_RAM_B2_ECC_ROW_WIDTH, ((bool)true) },
327  { SDL_DSS_ECC_AGG_DSS_CM4_MAILBOX_ECC_RAM_ID, 0x48000000u,
328  SDL_DSS_ECC_AGG_DSS_CM4_MAILBOX_ECC_RAM_SIZE, 8u,
329  SDL_DSS_ECC_AGG_DSS_CM4_MAILBOX_ECC_ROW_WIDTH, ((bool)true) },
330  { SDL_DSS_ECC_AGG_DSS_TPTC_A0_FIFO_ECC_RAM_ID, 0u,
331  SDL_DSS_ECC_AGG_DSS_TPTC_A0_FIFO_ECC_RAM_SIZE, 8u,
332  SDL_DSS_ECC_AGG_DSS_TPTC_A0_FIFO_ECC_ROW_WIDTH, ((bool)false) },
333  { SDL_DSS_ECC_AGG_DSS_TPTC_A1_FIFO_ECC_RAM_ID, 0u,
334  SDL_DSS_ECC_AGG_DSS_TPTC_A1_FIFO_ECC_RAM_SIZE, 8u,
335  SDL_DSS_ECC_AGG_DSS_TPTC_A1_FIFO_ECC_ROW_WIDTH, ((bool)false) },
336  { SDL_DSS_ECC_AGG_DSS_TPTC_B0_FIFO_ECC_RAM_ID, 0u,
337  SDL_DSS_ECC_AGG_DSS_TPTC_B0_FIFO_ECC_RAM_SIZE, 8u,
338  SDL_DSS_ECC_AGG_DSS_TPTC_B0_FIFO_ECC_ROW_WIDTH, ((bool)false) },
339  { SDL_DSS_ECC_AGG_DSS_TPTC_B1_FIFO_ECC_RAM_ID, 0u,
340  SDL_DSS_ECC_AGG_DSS_TPTC_B1_FIFO_ECC_RAM_SIZE, 8u,
341  SDL_DSS_ECC_AGG_DSS_TPTC_B1_FIFO_ECC_ROW_WIDTH, ((bool)false) },
342  { SDL_DSS_ECC_AGG_DSS_TPTC_C0_FIFO_ECC_RAM_ID, 0u,
343  SDL_DSS_ECC_AGG_DSS_TPTC_C0_FIFO_ECC_RAM_SIZE, 8u,
344  SDL_DSS_ECC_AGG_DSS_TPTC_C0_FIFO_ECC_ROW_WIDTH, ((bool)false) },
345  { SDL_DSS_ECC_AGG_DSS_TPTC_C1_FIFO_ECC_RAM_ID, 0u,
346  SDL_DSS_ECC_AGG_DSS_TPTC_C1_FIFO_ECC_RAM_SIZE, 8u,
347  SDL_DSS_ECC_AGG_DSS_TPTC_C1_FIFO_ECC_ROW_WIDTH, ((bool)false) },
348  { SDL_DSS_ECC_AGG_DSS_TPTC_C2_FIFO_ECC_RAM_ID, 0u,
349  SDL_DSS_ECC_AGG_DSS_TPTC_C2_FIFO_ECC_RAM_SIZE, 8u,
350  SDL_DSS_ECC_AGG_DSS_TPTC_C2_FIFO_ECC_ROW_WIDTH, ((bool)false) },
351  { SDL_DSS_ECC_AGG_DSS_TPTC_C3_FIFO_ECC_RAM_ID, 0u,
352  SDL_DSS_ECC_AGG_DSS_TPTC_C3_FIFO_ECC_RAM_SIZE, 8u,
353  SDL_DSS_ECC_AGG_DSS_TPTC_C3_FIFO_ECC_ROW_WIDTH, ((bool)false) },
354  { SDL_DSS_ECC_AGG_DSS_TPTC_C4_FIFO_ECC_RAM_ID, 0u,
355  SDL_DSS_ECC_AGG_DSS_TPTC_C4_FIFO_ECC_RAM_SIZE, 8u,
356  SDL_DSS_ECC_AGG_DSS_TPTC_C4_FIFO_ECC_ROW_WIDTH, ((bool)false) },
357  { SDL_DSS_ECC_AGG_DSS_TPTC_C5_FIFO_ECC_RAM_ID, 0u,
358  SDL_DSS_ECC_AGG_DSS_TPTC_C5_FIFO_ECC_RAM_SIZE, 8u,
359  SDL_DSS_ECC_AGG_DSS_TPTC_C5_FIFO_ECC_ROW_WIDTH, ((bool)false) },
360  { SDL_DSS_ECC_AGG_RSS_TPTC_A0_FIFO_ECC_RAM_ID, 0u,
361  SDL_DSS_ECC_AGG_RSS_TPTC_A0_FIFO_ECC_RAM_SIZE, 8u,
362  SDL_DSS_ECC_AGG_RSS_TPTC_A0_FIFO_ECC_ROW_WIDTH, ((bool)false) },
363  { SDL_DSS_ECC_AGG_RSS_TPTC_A1_FIFO_ECC_RAM_ID, 0u,
364  SDL_DSS_ECC_AGG_RSS_TPTC_A1_FIFO_ECC_RAM_SIZE, 8u,
365  SDL_DSS_ECC_AGG_RSS_TPTC_A1_FIFO_ECC_ROW_WIDTH, ((bool)false) },
366  { SDL_DSS_ECC_AGG_DSS_HWA_PARAM_RAM_ECC_RAM_ID, 0x06060000u,
367  SDL_DSS_ECC_AGG_DSS_HWA_PARAM_RAM_ECC_RAM_SIZE, 8u,
368  SDL_DSS_ECC_AGG_DSS_HWA_PARAM_RAM_ECC_ROW_WIDTH, ((bool)true) },
369 };
370 
375 const SDL_MemConfig_t SDL_MSS_MCANA_ECC_MemEntries[SDL_MSS_MCANA_ECC_RAM_IDS_TOTAL_ENTRIES] =
376 {
377  { SDL_MSS_MCANA_ECC_MSS_MCANA_ECC_RAM_ID, 0u,
378  SDL_MSS_MCANA_ECC_MSS_MCANA_ECC_RAM_SIZE, 4u,
379  SDL_MSS_MCANA_ECC_MSS_MCANA_ECC_ROW_WIDTH, ((bool)false) },
380 };
381 
386 const SDL_MemConfig_t SDL_MSS_MCANB_ECC_MemEntries[SDL_MSS_MCANB_ECC_RAM_IDS_TOTAL_ENTRIES] =
387 {
388  { SDL_MSS_MCANB_ECC_MSS_MCANB_ECC_RAM_ID, 0u,
389  SDL_MSS_MCANB_ECC_MSS_MCANB_ECC_RAM_SIZE, 4u,
390  SDL_MSS_MCANB_ECC_MSS_MCANB_ECC_ROW_WIDTH, ((bool)false) },
391 };
392 
397 static const SDL_MemConfig_t SDL_CPSW3GCSS_ECC_AGGR_MemEntries[SDL_CPSW3GCSS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
398 {
399  { SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_ALE_RAM_ECC_RAM_ID, 0x0703E000u,
400  SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_ALE_RAM_ECC_RAM_SIZE, 71u,
401  SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_ALE_RAM_ECC_ROW_WIDTH, ((bool)true) },
402  { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL1_ECC_RAM_ID, 0u,
403  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL1_ECC_RAM_SIZE, 32u,
404  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL1_ECC_ROW_WIDTH, ((bool)false) },
405  { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL2_ECC_RAM_ID, 0u,
406  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL2_ECC_RAM_SIZE, 32u,
407  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL2_ECC_ROW_WIDTH, ((bool)false) },
408  { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL3_ECC_RAM_ID, 0u,
409  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL3_ECC_RAM_SIZE, 32u,
410  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL3_ECC_ROW_WIDTH, ((bool)false) },
411  { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL4_ECC_RAM_ID, 0u,
412  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL4_ECC_RAM_SIZE, 32u,
413  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL4_ECC_ROW_WIDTH, ((bool)false) },
414  { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL5_ECC_RAM_ID, 0u,
415  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL5_ECC_RAM_SIZE, 32u,
416  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL5_ECC_ROW_WIDTH, ((bool)false) },
417  { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL6_ECC_RAM_ID, 0u,
418  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL6_ECC_RAM_SIZE, 32u,
419  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL6_ECC_ROW_WIDTH, ((bool)false) },
420  { SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_EST_RAM_ECC_RAM_ID, 0x07032000u,
421  SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_EST_RAM_ECC_RAM_SIZE, 4u,
422  SDL_ECC_WIDTH_UNDEFINED, ((bool)true) },
423 };
424 
429 static const SDL_RAMIdEntry_t SDL_R5FSS0_CORE0_ECC_AGGR_RamIdTable[SDL_R5FSS0_CORE0_ECC_AGGR_NUM_RAMS] =
430 {
431  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID,
432  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_INJECT_TYPE,
433  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_ECC_TYPE,
434  0u,
435  NULL },
436  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID,
437  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_INJECT_TYPE,
438  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_ECC_TYPE,
439  0u,
440  NULL },
441  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID,
442  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_INJECT_TYPE,
443  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_ECC_TYPE,
444  0u,
445  NULL },
446  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID,
447  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_INJECT_TYPE,
448  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_ECC_TYPE,
449  0u,
450  NULL },
451  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID,
452  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_INJECT_TYPE,
453  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_ECC_TYPE,
454  0u,
455  NULL },
456  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID,
457  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_INJECT_TYPE,
458  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_ECC_TYPE,
459  0u,
460  NULL },
461  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID,
462  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_INJECT_TYPE,
463  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_ECC_TYPE,
464  0u,
465  NULL },
466  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID,
467  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_INJECT_TYPE,
468  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_ECC_TYPE,
469  0u,
470  NULL },
471  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID,
472  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_INJECT_TYPE,
473  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_ECC_TYPE,
474  0u,
475  NULL },
476  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID,
477  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_INJECT_TYPE,
478  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_ECC_TYPE,
479  0u,
480  NULL },
481  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID,
482  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_INJECT_TYPE,
483  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_ECC_TYPE,
484  0u,
485  NULL },
486  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID,
487  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_INJECT_TYPE,
488  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_ECC_TYPE,
489  0u,
490  NULL },
491  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID,
492  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_INJECT_TYPE,
493  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_ECC_TYPE,
494  0u,
495  NULL },
496  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID,
497  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_INJECT_TYPE,
498  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_ECC_TYPE,
499  0u,
500  NULL },
501  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID,
502  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_INJECT_TYPE,
503  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_ECC_TYPE,
504  0u,
505  NULL },
506  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID,
507  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_INJECT_TYPE,
508  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_ECC_TYPE,
509  0u,
510  NULL },
511  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID,
512  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_INJECT_TYPE,
513  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_ECC_TYPE,
514  0u,
515  NULL },
516  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID,
517  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_INJECT_TYPE,
518  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_ECC_TYPE,
519  0u,
520  NULL },
521  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID,
522  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_INJECT_TYPE,
523  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_ECC_TYPE,
524  0u,
525  NULL },
526  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID,
527  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_INJECT_TYPE,
528  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_ECC_TYPE,
529  0u,
530  NULL },
531  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID,
532  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_INJECT_TYPE,
533  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_ECC_TYPE,
534  0u,
535  NULL },
536  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_ID,
537  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_INJECT_TYPE,
538  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_ECC_TYPE,
539  0u,
540  NULL },
541  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_ID,
542  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_INJECT_TYPE,
543  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_ECC_TYPE,
544  0u,
545  NULL },
546  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_ID,
547  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_INJECT_TYPE,
548  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_ECC_TYPE,
549  0u,
550  NULL },
551  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_ID,
552  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_INJECT_TYPE,
553  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_ECC_TYPE,
554  0u,
555  NULL },
556  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_ID,
557  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_INJECT_TYPE,
558  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_ECC_TYPE,
559  0u,
560  NULL },
561  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_ID,
562  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_INJECT_TYPE,
563  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_ECC_TYPE,
564  0u,
565  NULL },
566  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID,
567  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_INJECT_TYPE,
568  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ECC_TYPE,
569  0u,
570  NULL },
571 };
572 
577 static const SDL_RAMIdEntry_t SDL_R5FSS0_CORE1_ECC_AGGR_RamIdTable[SDL_R5FSS0_CORE1_ECC_AGGR_NUM_RAMS] =
578 {
579  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_RAM_ID,
580  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_INJECT_TYPE,
581  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_ECC_TYPE,
582  0u,
583  NULL },
584  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_RAM_ID,
585  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_INJECT_TYPE,
586  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_ECC_TYPE,
587  0u,
588  NULL },
589  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_RAM_ID,
590  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_INJECT_TYPE,
591  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_ECC_TYPE,
592  0u,
593  NULL },
594  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_RAM_ID,
595  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_INJECT_TYPE,
596  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_ECC_TYPE,
597  0u,
598  NULL },
599  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_RAM_ID,
600  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_INJECT_TYPE,
601  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_ECC_TYPE,
602  0u,
603  NULL },
604  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_RAM_ID,
605  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_INJECT_TYPE,
606  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_ECC_TYPE,
607  0u,
608  NULL },
609  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_RAM_ID,
610  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_INJECT_TYPE,
611  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_ECC_TYPE,
612  0u,
613  NULL },
614  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_RAM_ID,
615  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_INJECT_TYPE,
616  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_ECC_TYPE,
617  0u,
618  NULL },
619  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_RAM_ID,
620  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_INJECT_TYPE,
621  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_ECC_TYPE,
622  0u,
623  NULL },
624  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_RAM_ID,
625  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_INJECT_TYPE,
626  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_ECC_TYPE,
627  0u,
628  NULL },
629  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_RAM_ID,
630  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_INJECT_TYPE,
631  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_ECC_TYPE,
632  0u,
633  NULL },
634  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_RAM_ID,
635  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_INJECT_TYPE,
636  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_ECC_TYPE,
637  0u,
638  NULL },
639  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_RAM_ID,
640  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_INJECT_TYPE,
641  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_ECC_TYPE,
642  0u,
643  NULL },
644  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_RAM_ID,
645  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_INJECT_TYPE,
646  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_ECC_TYPE,
647  0u,
648  NULL },
649  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_RAM_ID,
650  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_INJECT_TYPE,
651  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_ECC_TYPE,
652  0u,
653  NULL },
654  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_RAM_ID,
655  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_INJECT_TYPE,
656  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_ECC_TYPE,
657  0u,
658  NULL },
659  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_RAM_ID,
660  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_INJECT_TYPE,
661  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_ECC_TYPE,
662  0u,
663  NULL },
664  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_RAM_ID,
665  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_INJECT_TYPE,
666  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_ECC_TYPE,
667  0u,
668  NULL },
669  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_RAM_ID,
670  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_INJECT_TYPE,
671  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_ECC_TYPE,
672  0u,
673  NULL },
674  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_RAM_ID,
675  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_INJECT_TYPE,
676  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_ECC_TYPE,
677  0u,
678  NULL },
679  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_RAM_ID,
680  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_INJECT_TYPE,
681  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_ECC_TYPE,
682  0u,
683  NULL },
684  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_RAM_ID,
685  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_INJECT_TYPE,
686  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_ECC_TYPE,
687  0u,
688  NULL },
689  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_RAM_ID,
690  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_INJECT_TYPE,
691  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_ECC_TYPE,
692  0u,
693  NULL },
694  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_RAM_ID,
695  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_INJECT_TYPE,
696  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_ECC_TYPE,
697  0u,
698  NULL },
699  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_RAM_ID,
700  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_INJECT_TYPE,
701  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_ECC_TYPE,
702  0u,
703  NULL },
704  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_RAM_ID,
705  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_INJECT_TYPE,
706  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_ECC_TYPE,
707  0u,
708  NULL },
709  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_RAM_ID,
710  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_INJECT_TYPE,
711  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_ECC_TYPE,
712  0u,
713  NULL },
714  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_RAM_ID,
715  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_INJECT_TYPE,
716  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_ECC_TYPE,
717  0u,
718  NULL },
719 };
720 
725 const SDL_RAMIdEntry_t SDL_MSS_ECC_AGG_MSS_RamIdTable[SDL_MSS_ECC_AGG_MSS_NUM_RAMS] =
726 {
727  { SDL_MSS_ECC_AGG_MSS_MSS_L2RAMA_ECC_RAM_ID,
728  SDL_MSS_ECC_AGG_MSS_MSS_L2RAMA_ECC_INJECT_TYPE,
729  SDL_MSS_ECC_AGG_MSS_MSS_L2RAMA_ECC_ECC_TYPE,
730  0u,
731  NULL },
732  { SDL_MSS_ECC_AGG_MSS_MSS_L2RAMB_ECC_RAM_ID,
733  SDL_MSS_ECC_AGG_MSS_MSS_L2RAMB_ECC_INJECT_TYPE,
734  SDL_MSS_ECC_AGG_MSS_MSS_L2RAMB_ECC_ECC_TYPE,
735  0u,
736  NULL },
737  { SDL_MSS_ECC_AGG_MSS_MSS_MBOX_ECC_RAM_ID,
738  SDL_MSS_ECC_AGG_MSS_MSS_MBOX_ECC_INJECT_TYPE,
739  SDL_MSS_ECC_AGG_MSS_MSS_MBOX_ECC_ECC_TYPE,
740  0u,
741  NULL },
742  { SDL_MSS_ECC_AGG_MSS_MSS_RETRAM_ECC_RAM_ID,
743  SDL_MSS_ECC_AGG_MSS_MSS_RETRAM_ECC_INJECT_TYPE,
744  SDL_MSS_ECC_AGG_MSS_MSS_RETRAM_ECC_ECC_TYPE,
745  0u,
746  NULL },
747  { SDL_MSS_ECC_AGG_MSS_MSS_GPADC_DATA_RAM_ECC_RAM_ID,
748  SDL_MSS_ECC_AGG_MSS_MSS_GPADC_DATA_RAM_ECC_INJECT_TYPE,
749  SDL_MSS_ECC_AGG_MSS_MSS_GPADC_DATA_RAM_ECC_ECC_TYPE,
750  0u,
751  NULL },
752  { SDL_MSS_ECC_AGG_MSS_MSS_TPTC_A0_ECC_RAM_ID,
753  SDL_MSS_ECC_AGG_MSS_MSS_TPTC_A0_ECC_INJECT_TYPE,
754  SDL_MSS_ECC_AGG_MSS_MSS_TPTC_A0_ECC_ECC_TYPE,
755  0u,
756  NULL },
757  { SDL_MSS_ECC_AGG_MSS_MSS_TPTC_A1_ECC_RAM_ID,
758  SDL_MSS_ECC_AGG_MSS_MSS_TPTC_A1_ECC_INJECT_TYPE,
759  SDL_MSS_ECC_AGG_MSS_MSS_TPTC_A1_ECC_ECC_TYPE,
760  0u,
761  NULL },
762  { SDL_MSS_ECC_AGG_MSS_MSS_TPTC_B0_ECC_RAM_ID,
763  SDL_MSS_ECC_AGG_MSS_MSS_TPTC_B0_ECC_INJECT_TYPE,
764  SDL_MSS_ECC_AGG_MSS_MSS_TPTC_B0_ECC_ECC_TYPE,
765  0u,
766  NULL },
767 };
768 
773 const SDL_RAMIdEntry_t SDL_DSS_ECC_AGG_RamIdTable[SDL_DSS_ECC_AGG_NUM_RAMS] =
774 {
775  { SDL_DSS_ECC_AGG_DSS_L3RAMA_ECC_RAM_ID,
776  SDL_DSS_ECC_AGG_DSS_L3RAMA_ECC_INJECT_TYPE,
777  SDL_DSS_ECC_AGG_DSS_L3RAMA_ECC_ECC_TYPE,
778  0u,
779  NULL },
780  { SDL_DSS_ECC_AGG_DSS_L3RAMB_ECC_RAM_ID,
781  SDL_DSS_ECC_AGG_DSS_L3RAMB_ECC_INJECT_TYPE,
782  SDL_DSS_ECC_AGG_DSS_L3RAMB_ECC_ECC_TYPE,
783  0u,
784  NULL },
785  { SDL_DSS_ECC_AGG_DSS_L3RAMC_ECC_RAM_ID,
786  SDL_DSS_ECC_AGG_DSS_L3RAMC_ECC_INJECT_TYPE,
787  SDL_DSS_ECC_AGG_DSS_L3RAMC_ECC_ECC_TYPE,
788  0u,
789  NULL },
790  { SDL_DSS_ECC_AGG_DSS_L3RAMD_ECC_RAM_ID,
791  SDL_DSS_ECC_AGG_DSS_L3RAMD_ECC_INJECT_TYPE,
792  SDL_DSS_ECC_AGG_DSS_L3RAMD_ECC_ECC_TYPE,
793  0u,
794  NULL },
795  { SDL_DSS_ECC_AGG_DSS_MAILBOX_ECC_RAM_ID,
796  SDL_DSS_ECC_AGG_DSS_MAILBOX_ECC_INJECT_TYPE,
797  SDL_DSS_ECC_AGG_DSS_MAILBOX_ECC_ECC_TYPE,
798  0u,
799  NULL },
800  { SDL_DSS_ECC_AGG_DSS_CM4_RAM_B0_ECC_RAM_ID,
801  SDL_DSS_ECC_AGG_DSS_CM4_RAM_B0_ECC_INJECT_TYPE,
802  SDL_DSS_ECC_AGG_DSS_CM4_RAM_B0_ECC_ECC_TYPE,
803  0u,
804  NULL },
805  { SDL_DSS_ECC_AGG_DSS_CM4_RAM_B1_ECC_RAM_ID,
806  SDL_DSS_ECC_AGG_DSS_CM4_RAM_B1_ECC_INJECT_TYPE,
807  SDL_DSS_ECC_AGG_DSS_CM4_RAM_B1_ECC_ECC_TYPE,
808  0u,
809  NULL },
810  { SDL_DSS_ECC_AGG_DSS_CM4_RAM_B2_ECC_RAM_ID,
811  SDL_DSS_ECC_AGG_DSS_CM4_RAM_B2_ECC_INJECT_TYPE,
812  SDL_DSS_ECC_AGG_DSS_CM4_RAM_B2_ECC_ECC_TYPE,
813  0u,
814  NULL },
815  { SDL_DSS_ECC_AGG_DSS_CM4_MAILBOX_ECC_RAM_ID,
816  SDL_DSS_ECC_AGG_DSS_CM4_MAILBOX_ECC_INJECT_TYPE,
817  SDL_DSS_ECC_AGG_DSS_CM4_MAILBOX_ECC_ECC_TYPE,
818  0u,
819  NULL },
820  { SDL_DSS_ECC_AGG_DSS_TPTC_A0_FIFO_ECC_RAM_ID,
821  SDL_DSS_ECC_AGG_DSS_TPTC_A0_FIFO_ECC_INJECT_TYPE,
822  SDL_DSS_ECC_AGG_DSS_TPTC_A0_FIFO_ECC_ECC_TYPE,
823  0u,
824  NULL },
825  { SDL_DSS_ECC_AGG_DSS_TPTC_A1_FIFO_ECC_RAM_ID,
826  SDL_DSS_ECC_AGG_DSS_TPTC_A1_FIFO_ECC_INJECT_TYPE,
827  SDL_DSS_ECC_AGG_DSS_TPTC_A1_FIFO_ECC_ECC_TYPE,
828  0u,
829  NULL },
830  { SDL_DSS_ECC_AGG_DSS_TPTC_B0_FIFO_ECC_RAM_ID,
831  SDL_DSS_ECC_AGG_DSS_TPTC_B0_FIFO_ECC_INJECT_TYPE,
832  SDL_DSS_ECC_AGG_DSS_TPTC_B0_FIFO_ECC_ECC_TYPE,
833  0u,
834  NULL },
835  { SDL_DSS_ECC_AGG_DSS_TPTC_B1_FIFO_ECC_RAM_ID,
836  SDL_DSS_ECC_AGG_DSS_TPTC_B1_FIFO_ECC_INJECT_TYPE,
837  SDL_DSS_ECC_AGG_DSS_TPTC_B1_FIFO_ECC_ECC_TYPE,
838  0u,
839  NULL },
840  { SDL_DSS_ECC_AGG_DSS_TPTC_C0_FIFO_ECC_RAM_ID,
841  SDL_DSS_ECC_AGG_DSS_TPTC_C0_FIFO_ECC_INJECT_TYPE,
842  SDL_DSS_ECC_AGG_DSS_TPTC_C0_FIFO_ECC_ECC_TYPE,
843  0u,
844  NULL },
845  { SDL_DSS_ECC_AGG_DSS_TPTC_C1_FIFO_ECC_RAM_ID,
846  SDL_DSS_ECC_AGG_DSS_TPTC_C1_FIFO_ECC_INJECT_TYPE,
847  SDL_DSS_ECC_AGG_DSS_TPTC_C1_FIFO_ECC_ECC_TYPE,
848  0u,
849  NULL },
850  { SDL_DSS_ECC_AGG_DSS_TPTC_C2_FIFO_ECC_RAM_ID,
851  SDL_DSS_ECC_AGG_DSS_TPTC_C2_FIFO_ECC_INJECT_TYPE,
852  SDL_DSS_ECC_AGG_DSS_TPTC_C2_FIFO_ECC_ECC_TYPE,
853  0u,
854  NULL },
855  { SDL_DSS_ECC_AGG_DSS_TPTC_C3_FIFO_ECC_RAM_ID,
856  SDL_DSS_ECC_AGG_DSS_TPTC_C3_FIFO_ECC_INJECT_TYPE,
857  SDL_DSS_ECC_AGG_DSS_TPTC_C3_FIFO_ECC_ECC_TYPE,
858  0u,
859  NULL },
860  { SDL_DSS_ECC_AGG_DSS_TPTC_C4_FIFO_ECC_RAM_ID,
861  SDL_DSS_ECC_AGG_DSS_TPTC_C4_FIFO_ECC_INJECT_TYPE,
862  SDL_DSS_ECC_AGG_DSS_TPTC_C4_FIFO_ECC_ECC_TYPE,
863  0u,
864  NULL },
865  { SDL_DSS_ECC_AGG_DSS_TPTC_C5_FIFO_ECC_RAM_ID,
866  SDL_DSS_ECC_AGG_DSS_TPTC_C5_FIFO_ECC_INJECT_TYPE,
867  SDL_DSS_ECC_AGG_DSS_TPTC_C5_FIFO_ECC_ECC_TYPE,
868  0u,
869  NULL },
870  { SDL_DSS_ECC_AGG_RSS_TPTC_A0_FIFO_ECC_RAM_ID,
871  SDL_DSS_ECC_AGG_RSS_TPTC_A0_FIFO_ECC_INJECT_TYPE,
872  SDL_DSS_ECC_AGG_RSS_TPTC_A0_FIFO_ECC_ECC_TYPE,
873  0u,
874  NULL },
875  { SDL_DSS_ECC_AGG_RSS_TPTC_A1_FIFO_ECC_RAM_ID,
876  SDL_DSS_ECC_AGG_RSS_TPTC_A1_FIFO_ECC_INJECT_TYPE,
877  SDL_DSS_ECC_AGG_RSS_TPTC_A1_FIFO_ECC_ECC_TYPE,
878  0u,
879  NULL },
880  { SDL_DSS_ECC_AGG_DSS_HWA_PARAM_RAM_ECC_RAM_ID,
881  SDL_DSS_ECC_AGG_DSS_HWA_PARAM_RAM_ECC_INJECT_TYPE,
882  SDL_DSS_ECC_AGG_DSS_HWA_PARAM_RAM_ECC_ECC_TYPE,
883  0u,
884  NULL },
885 };
886 
891 const SDL_RAMIdEntry_t SDL_MSS_MCANA_ECC_RamIdTable[SDL_MSS_MCANA_ECC_NUM_RAMS] =
892 {
893  { SDL_MSS_MCANA_ECC_MSS_MCANA_ECC_RAM_ID,
894  SDL_MSS_MCANA_ECC_MSS_MCANA_ECC_INJECT_TYPE,
895  SDL_MSS_MCANA_ECC_MSS_MCANA_ECC_ECC_TYPE,
896  0u,
897  NULL },
898 };
899 
904 const SDL_RAMIdEntry_t SDL_MSS_MCANB_ECC_RamIdTable[SDL_MSS_MCANB_ECC_NUM_RAMS] =
905 {
906  { SDL_MSS_MCANB_ECC_MSS_MCANB_ECC_RAM_ID,
907  SDL_MSS_MCANB_ECC_MSS_MCANB_ECC_INJECT_TYPE,
908  SDL_MSS_MCANB_ECC_MSS_MCANB_ECC_ECC_TYPE,
909  0u,
910  NULL },
911 };
912 
917 static const SDL_RAMIdEntry_t SDL_CPSW3GCSS_ECC_AGGR_RamIdTable[SDL_CPSW3GCSS_ECC_AGGR_NUM_RAMS] =
918 {
919  { SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_ALE_RAM_ECC_RAM_ID,
920  SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_ALE_RAM_ECC_INJECT_TYPE,
921  SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_ALE_RAM_ECC_ECC_TYPE,
922  0u,
923  NULL },
924  { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL1_ECC_RAM_ID,
925  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL1_ECC_INJECT_TYPE,
926  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL1_ECC_ECC_TYPE,
927  0u,
928  NULL },
929  { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL2_ECC_RAM_ID,
930  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL2_ECC_INJECT_TYPE,
931  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL2_ECC_ECC_TYPE,
932  0u,
933  NULL },
934  { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL3_ECC_RAM_ID,
935  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL3_ECC_INJECT_TYPE,
936  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL3_ECC_ECC_TYPE,
937  0u,
938  NULL },
939  { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL4_ECC_RAM_ID,
940  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL4_ECC_INJECT_TYPE,
941  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL4_ECC_ECC_TYPE,
942  0u,
943  NULL },
944  { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL5_ECC_RAM_ID,
945  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL5_ECC_INJECT_TYPE,
946  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL5_ECC_ECC_TYPE,
947  0u,
948  NULL },
949  { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL6_ECC_RAM_ID,
950  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL6_ECC_INJECT_TYPE,
951  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL6_ECC_ECC_TYPE,
952  0u,
953  NULL },
954  { SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_EST_RAM_ECC_RAM_ID,
955  SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_EST_RAM_ECC_INJECT_TYPE,
956  SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_EST_RAM_ECC_ECC_TYPE,
957  0u,
958  NULL },
959 };
960 
961 static SDL_ecc_aggrRegs * const SDL_ECC_aggrBaseAddressTable[SDL_ECC_Base_Address_TOTAL_ENTRIES] =
962 {
963  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MSS_ECC_AGG_R5A_U_BASE)),
964  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MSS_ECC_AGG_R5B_U_BASE)),
965  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MSS_ECC_AGG_MSS_U_BASE)),
966  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_DSS_ECC_AGG_U_BASE)),
967  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MSS_MCANA_ECC_U_BASE )),
968  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MSS_MCANB_ECC_U_BASE)),
969  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MSS_CPSW0_ECC_U_BASE)),
970 };
971 
972 SDL_ecc_aggrRegs * SDL_ECC_aggrTransBaseAddressTable[SDL_ECC_MEMTYPE_MAX];
975 static const SDL_EccAggrEntry_t SDL_ECC_aggrTable[SDL_ECC_MEMTYPE_MAX] =
976 {
977 
978  /* Index: SDL_MSS_ECC_AGG_R5A (0) */
979  {
980  SDL_R5FSS0_CORE0_ECC_AGGR_NUM_RAMS,
981  SDL_R5FSS0_CORE0_ECC_AGGR_RamIdTable,
982  SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
983  SDL_R5FSS0_CORE0_ECC_AGGR_MemEntries,
984  SDL_ESM_INST_MSS_ESM,
985  SDL_ESMG1_ECCAGGA_SERR,
986  SDL_ESMG1_ECCAGGA_UERR
987  },
988  /* Index: SDL_MSS_ECC_AGG_R5B (1) */
989  {
990  SDL_R5FSS0_CORE1_ECC_AGGR_NUM_RAMS,
991  SDL_R5FSS0_CORE1_ECC_AGGR_RamIdTable,
992  SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
993  SDL_R5FSS0_CORE1_ECC_AGGR_MemEntries,
994  SDL_ESM_INST_MSS_ESM,
995  SDL_ESMG1_ECCAGGB_SERR,
996  SDL_ESMG1_ECCAGGB_UERR
997  },
998  /* Index: SDL_MSS_ECC_AGG_MSS (2) */
999  {
1000  SDL_MSS_ECC_AGG_MSS_NUM_RAMS,
1001  SDL_MSS_ECC_AGG_MSS_RamIdTable,
1002  SDL_MSS_ECC_AGG_MSS_RAM_IDS_TOTAL_ENTRIES,
1003  SDL_MSS_ECC_AGG_MSS_MemEntries,
1004  SDL_ESM_INST_MSS_ESM,
1005  SDL_ESMG1_ECCAGGMSS_SERR,
1006  SDL_ESMG1_ECCAGGMSS_UERR
1007  },
1008  /* Index: SDL_DSS_ECC_AGG (3) */
1009  {
1010  SDL_DSS_ECC_AGG_NUM_RAMS,
1011  SDL_DSS_ECC_AGG_RamIdTable,
1012  SDL_DSS_ECC_AGG_RAM_IDS_TOTAL_ENTRIES,
1013  SDL_DSS_ECC_AGG_MemEntries,
1014  SDL_ESM_INST_DSS_ESM,
1015  SDL_DSS_ESMG1_DSS_ECC_AGG_SERR,
1016  SDL_DSS_ESMG1_DSS_ECC_AGG_UERR
1017  },
1018  /* Index: SDL_MSS_MCANA_ECC (4) */
1019  {
1020  SDL_MSS_MCANA_ECC_NUM_RAMS,
1021  SDL_MSS_MCANA_ECC_RamIdTable,
1022  SDL_MSS_MCANA_ECC_RAM_IDS_TOTAL_ENTRIES,
1023  SDL_MSS_MCANA_ECC_MemEntries,
1024  SDL_ESM_INST_MSS_ESM,
1025  SDL_ESMG1_MCANA_SERR,
1026  SDL_ESMG1_MCANA_UERR
1027  },
1028  /* Index: SDL_MSS_MCANB_ECC (5) */
1029  {
1030  SDL_MSS_MCANB_ECC_NUM_RAMS,
1031  SDL_MSS_MCANB_ECC_RamIdTable,
1032  SDL_MSS_MCANB_ECC_RAM_IDS_TOTAL_ENTRIES,
1033  SDL_MSS_MCANB_ECC_MemEntries,
1034  SDL_ESM_INST_MSS_ESM,
1035  SDL_ESMG1_MCANB_SERR,
1036  SDL_ESMG1_MCANB_UERR
1037  },
1038  /* Index: SDL_CPSW3GCSS_ECC_AGGR (6) */
1039  {
1040  SDL_CPSW3GCSS_ECC_AGGR_NUM_RAMS,
1041  SDL_CPSW3GCSS_ECC_AGGR_RamIdTable,
1042  SDL_CPSW3GCSS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1043  SDL_CPSW3GCSS_ECC_AGGR_MemEntries,
1044  SDL_ESM_INST_MSS_ESM,
1045  SDL_ESMG1_CPSW_SERR,
1046  SDL_ESMG1_CPSW_UERR,
1047  }
1048 
1049  };
1050  #endif /* INCLUDE_SDL_ECC_SOC_H_ */
SDL_MSS_ECC_AGG_MSS_MemEntries
const SDL_MemConfig_t SDL_MSS_ECC_AGG_MSS_MemEntries[SDL_MSS_ECC_AGG_MSS_RAM_IDS_TOTAL_ENTRIES]
Definition: am273x/sdl_ecc_soc.h:269
SDL_R5FSS0_CORE0_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_R5FSS0_CORE0_ECC_AGGR_RamIdTable[SDL_R5FSS0_CORE0_ECC_AGGR_NUM_RAMS]
Definition: am273x/sdl_ecc_soc.h:429
SDL_ECC_WIDTH_UNDEFINED
#define SDL_ECC_WIDTH_UNDEFINED
Definition: am273x/sdl_ecc_soc.h:54
SDL_ecc_aggrRegs
Definition: V1/sdlr_ecc.h:53
SDL_MSS_MCANA_ECC_MemEntries
const SDL_MemConfig_t SDL_MSS_MCANA_ECC_MemEntries[SDL_MSS_MCANA_ECC_RAM_IDS_TOTAL_ENTRIES]
Definition: am273x/sdl_ecc_soc.h:375
SDL_DSS_ECC_AGG_RAM_IDS_TOTAL_ENTRIES
#define SDL_DSS_ECC_AGG_RAM_IDS_TOTAL_ENTRIES
Definition: am273x/sdl_ecc_soc.h:60
SDL_DSS_ECC_AGG_RamIdTable
const SDL_RAMIdEntry_t SDL_DSS_ECC_AGG_RamIdTable[SDL_DSS_ECC_AGG_NUM_RAMS]
Definition: am273x/sdl_ecc_soc.h:773
SDL_R5FSS0_CORE0_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_R5FSS0_CORE0_ECC_AGGR_MemEntries[SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: am273x/sdl_ecc_soc.h:85
SDL_CPSW3GCSS_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_CPSW3GCSS_ECC_AGGR_MemEntries[SDL_CPSW3GCSS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: am273x/sdl_ecc_soc.h:397
SDL_DSS_ECC_AGG_MemEntries
const SDL_MemConfig_t SDL_DSS_ECC_AGG_MemEntries[SDL_DSS_ECC_AGG_RAM_IDS_TOTAL_ENTRIES]
Definition: am273x/sdl_ecc_soc.h:301
SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: am273x/sdl_ecc_soc.h:57
SDL_CPSW3GCSS_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_CPSW3GCSS_ECC_AGGR_RamIdTable[SDL_CPSW3GCSS_ECC_AGGR_NUM_RAMS]
Definition: am273x/sdl_ecc_soc.h:917
SDL_MSS_MCANB_ECC_RamIdTable
const SDL_RAMIdEntry_t SDL_MSS_MCANB_ECC_RamIdTable[SDL_MSS_MCANB_ECC_NUM_RAMS]
Definition: am273x/sdl_ecc_soc.h:904
SDL_MSS_CPSW0_ECC_U_BASE
#define SDL_MSS_CPSW0_ECC_U_BASE
Definition: am273x/sdl_ecc_soc.h:66
sdl_ip_ecc.h
SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: am273x/sdl_ecc_soc.h:58
SDL_MSS_MCANA_ECC_RamIdTable
const SDL_RAMIdEntry_t SDL_MSS_MCANA_ECC_RamIdTable[SDL_MSS_MCANA_ECC_NUM_RAMS]
Definition: am273x/sdl_ecc_soc.h:891
SDL_ECC_Base_Address_TOTAL_ENTRIES
#define SDL_ECC_Base_Address_TOTAL_ENTRIES
Definition: am273x/sdl_ecc_soc.h:64
SDL_MemConfig_t
Definition: sdl_ecc_priv.h:88
sdl_ecc.h
Header file contains enumerations, structure definitions and function.
SDL_CPSW3GCSS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_CPSW3GCSS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: am273x/sdl_ecc_soc.h:63
SDL_ECC_aggrBaseAddressTable
static SDL_ecc_aggrRegs *const SDL_ECC_aggrBaseAddressTable[SDL_ECC_Base_Address_TOTAL_ENTRIES]
Definition: am273x/sdl_ecc_soc.h:961
SDL_ECC_aggrTransBaseAddressTable
SDL_ecc_aggrRegs * SDL_ECC_aggrTransBaseAddressTable[SDL_ECC_MEMTYPE_MAX]
Definition: am273x/sdl_ecc_soc.h:972
SDL_MSS_ECC_AGG_MSS_RamIdTable
const SDL_RAMIdEntry_t SDL_MSS_ECC_AGG_MSS_RamIdTable[SDL_MSS_ECC_AGG_MSS_NUM_RAMS]
Definition: am273x/sdl_ecc_soc.h:725
SDL_RAMIdEntry_t
Definition: sdl_ecc_priv.h:63
SDL_ECC_aggrTable
static const SDL_EccAggrEntry_t SDL_ECC_aggrTable[SDL_ECC_MEMTYPE_MAX]
Definition: am273x/sdl_ecc_soc.h:975
SDL_R5FSS0_CORE1_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_R5FSS0_CORE1_ECC_AGGR_RamIdTable[SDL_R5FSS0_CORE1_ECC_AGGR_NUM_RAMS]
Definition: am273x/sdl_ecc_soc.h:577
SDL_MSS_MCANB_ECC_MemEntries
const SDL_MemConfig_t SDL_MSS_MCANB_ECC_MemEntries[SDL_MSS_MCANB_ECC_RAM_IDS_TOTAL_ENTRIES]
Definition: am273x/sdl_ecc_soc.h:386
SDL_EccAggrEntry_t
Definition: sdl_ecc_priv.h:104
SDL_R5FSS0_CORE1_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_R5FSS0_CORE1_ECC_AGGR_MemEntries[SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: am273x/sdl_ecc_soc.h:177
SDL_MSS_MCANA_ECC_RAM_IDS_TOTAL_ENTRIES
#define SDL_MSS_MCANA_ECC_RAM_IDS_TOTAL_ENTRIES
Definition: am273x/sdl_ecc_soc.h:61
SDL_MSS_MCANB_ECC_RAM_IDS_TOTAL_ENTRIES
#define SDL_MSS_MCANB_ECC_RAM_IDS_TOTAL_ENTRIES
Definition: am273x/sdl_ecc_soc.h:62
SDL_MSS_ECC_AGG_MSS_RAM_IDS_TOTAL_ENTRIES
#define SDL_MSS_ECC_AGG_MSS_RAM_IDS_TOTAL_ENTRIES
Definition: am273x/sdl_ecc_soc.h:59
sdl_ecc_priv.h