AM273x MCU+ SDK  08.05.00
am273x/sdl_ecc_soc.h
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1 /*
2  * SDL ECC
3  *
4  * Software Diagnostics Library module for ECC
5  *
6  * Copyright (c) Texas Instruments Incorporated 2022
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  *
12  * Redistributions of source code must retain the above copyright
13  * notice, this list of conditions and the following disclaimer.
14  *
15  * Redistributions in binary form must reproduce the above copyright
16  * notice, this list of conditions and the following disclaimer in the
17  * documentation and/or other materials provided with the
18  * distribution.
19  *
20  * Neither the name of Texas Instruments Incorporated nor the names of
21  * its contributors may be used to endorse or promote products derived
22  * from this software without specific prior written permission.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35  *
36  */
37 
38 #ifndef INCLUDE_SDL_ECC_SOC_H_
39 #define INCLUDE_SDL_ECC_SOC_H_
40 
41 #include <stdint.h>
42 #include <sdl/sdl_ecc.h>
43 #include <sdl/ecc/sdl_ip_ecc.h>
44 #include <sdl/include/sdl_types.h>
45 #include <sdl/esm/soc/am273x/sdl_esm_core.h>
46 #include <sdl/ecc/sdl_ecc_priv.h>
47 #include <sdl/include/am273x/sdlr_soc_ecc_aggr.h>
48 #include <sdl/include/am273x/soc_config.h>
49 #include <sdl/include/am273x/sdlr_intr_esm_dss.h>
50 #include <sdl/include/am273x/sdlr_intr_esm_mss.h>
51 #include <sdl/include/am273x/sdlr_soc_baseaddress.h>
52 
53 #define SDL_ECC_WIDTH_UNDEFINED 0x1
54 
55 /* define Max memEntries for each aggregator (i.e. the number of RAM ID's with * Wrapper type) */
56 #define SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (28U)
57 #define SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (28U)
58 #define SDL_MSS_ECC_AGG_MSS_RAM_IDS_TOTAL_ENTRIES (8U)
59 #define SDL_DSS_ECC_AGG_RAM_IDS_TOTAL_ENTRIES (22U)
60 #define SDL_MSS_MCANA_ECC_RAM_IDS_TOTAL_ENTRIES (1U)
61 #define SDL_MSS_MCANB_ECC_RAM_IDS_TOTAL_ENTRIES (1U)
62 #define SDL_ECC_Base_Address_TOTAL_ENTRIES (6U)
63 
64 
69 static const SDL_MemConfig_t SDL_R5FSS0_CORE0_ECC_AGGR_MemEntries[SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
70 {
71  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID, 0u,
72  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_SIZE, 4u,
73  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_ROW_WIDTH, ((bool)false) },
74  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID, 0u,
75  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_SIZE, 4u,
76  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_ROW_WIDTH, ((bool)false) },
77  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID, 0u,
78  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_SIZE, 4u,
79  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_ROW_WIDTH, ((bool)false) },
80  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID, 0u,
81  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_SIZE, 4u,
82  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_ROW_WIDTH, ((bool)false) },
83  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID, 0u,
84  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_SIZE, 4u,
85  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_ROW_WIDTH, ((bool)false) },
86  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID, 0u,
87  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_SIZE, 4u,
88  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_ROW_WIDTH, ((bool)false) },
89  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID, 0u,
90  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_SIZE, 4u,
91  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_ROW_WIDTH, ((bool)false) },
92  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID, 0u,
93  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_SIZE, 4u,
94  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_ROW_WIDTH, ((bool)false) },
95  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID, 0u,
96  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_SIZE, 4u,
97  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_ROW_WIDTH, ((bool)false) },
98  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID, 0u,
99  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_SIZE, 4u,
100  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_ROW_WIDTH, ((bool)false) },
101  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID, 0u,
102  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_SIZE, 4u,
103  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_ROW_WIDTH, ((bool)false) },
104  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID, 0u,
105  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_SIZE, 4u,
106  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_ROW_WIDTH, ((bool)false) },
107  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID, 0u,
108  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_SIZE, 4u,
109  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_ROW_WIDTH, ((bool)false) },
110  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID, 0u,
111  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_SIZE, 4u,
112  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_ROW_WIDTH, ((bool)false) },
113  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID, 0u,
114  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_SIZE, 4u,
115  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_ROW_WIDTH, ((bool)false) },
116  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID, 0u,
117  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_SIZE, 4u,
118  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_ROW_WIDTH, ((bool)false) },
119  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID, 0u,
120  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_SIZE, 4u,
121  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_ROW_WIDTH, ((bool)false) },
122  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID, 0u,
123  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_SIZE, 4u,
124  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_ROW_WIDTH, ((bool)false) },
125  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID, 0u,
126  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_SIZE, 4u,
127  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_ROW_WIDTH, ((bool)false) },
128  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID, 0u,
129  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_SIZE, 4u,
130  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_ROW_WIDTH, ((bool)false) },
131  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID, 0u,
132  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_SIZE, 4u,
133  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_ROW_WIDTH, ((bool)false) },
134  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_ID, 0x00u,
135  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_SIZE, 4u,
136  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_ROW_WIDTH, ((bool)true) },
137  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_ID, 0x00004000u,
138  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_SIZE, 4u,
139  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_ROW_WIDTH, ((bool)true) },
140  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_ID, 0x00080000u,
141  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_SIZE, 4u,
142  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_ROW_WIDTH, ((bool)true) },
143  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_ID, 0x00082000u,
144  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_SIZE, 4u,
145  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_ROW_WIDTH, ((bool)true) },
146  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_ID, 0x00084000u,
147  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_SIZE, 4u,
148  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_ROW_WIDTH, ((bool)true) },
149  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_ID, 0x00086000u,
150  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_SIZE, 4u,
151  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_ROW_WIDTH, ((bool)true) },
152  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID, 0xc1018c40u,
153  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_SIZE, 4u,
154  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ROW_WIDTH, ((bool)true) },
155 };
156 
161 static const SDL_MemConfig_t SDL_R5FSS0_CORE1_ECC_AGGR_MemEntries[SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
162 {
163  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_RAM_ID, 0u,
164  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_RAM_SIZE, 4u,
165  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_ROW_WIDTH, ((bool)false) },
166  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_RAM_ID, 0u,
167  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_RAM_SIZE, 4u,
168  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_ROW_WIDTH, ((bool)false) },
169  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_RAM_ID, 0u,
170  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_RAM_SIZE, 4u,
171  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_ROW_WIDTH, ((bool)false) },
172  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_RAM_ID, 0u,
173  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_RAM_SIZE, 4u,
174  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_ROW_WIDTH, ((bool)false) },
175  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_RAM_ID, 0u,
176  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_RAM_SIZE, 4u,
177  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_ROW_WIDTH, ((bool)false) },
178  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_RAM_ID, 0u,
179  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_RAM_SIZE, 4u,
180  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_ROW_WIDTH, ((bool)false) },
181  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_RAM_ID, 0u,
182  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_RAM_SIZE, 4u,
183  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_ROW_WIDTH, ((bool)false) },
184  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_RAM_ID, 0u,
185  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_RAM_SIZE, 4u,
186  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_ROW_WIDTH, ((bool)false) },
187  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_RAM_ID, 0u,
188  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_RAM_SIZE, 4u,
189  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_ROW_WIDTH, ((bool)false) },
190  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_RAM_ID, 0u,
191  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_RAM_SIZE, 4u,
192  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_ROW_WIDTH, ((bool)false) },
193  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_RAM_ID, 0u,
194  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_RAM_SIZE, 4u,
195  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_ROW_WIDTH, ((bool)false) },
196  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_RAM_ID, 0u,
197  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_RAM_SIZE, 4u,
198  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_ROW_WIDTH, ((bool)false) },
199  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_RAM_ID, 0u,
200  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_RAM_SIZE, 4u,
201  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_ROW_WIDTH, ((bool)false) },
202  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_RAM_ID, 0u,
203  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_RAM_SIZE, 4u,
204  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_ROW_WIDTH, ((bool)false) },
205  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_RAM_ID, 0u,
206  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_RAM_SIZE, 4u,
207  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_ROW_WIDTH, ((bool)false) },
208  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_RAM_ID, 0u,
209  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_RAM_SIZE, 4u,
210  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_ROW_WIDTH, ((bool)false) },
211  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_RAM_ID, 0u,
212  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_RAM_SIZE, 4u,
213  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_ROW_WIDTH, ((bool)false) },
214  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_RAM_ID, 0u,
215  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_RAM_SIZE, 4u,
216  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_ROW_WIDTH, ((bool)false) },
217  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_RAM_ID, 0u,
218  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_RAM_SIZE, 4u,
219  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_ROW_WIDTH, ((bool)false) },
220  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_RAM_ID, 0u,
221  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_RAM_SIZE, 4u,
222  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_ROW_WIDTH, ((bool)false) },
223  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_RAM_ID, 0u,
224  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_RAM_SIZE, 4u,
225  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_ROW_WIDTH, ((bool)false) },
226  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_RAM_ID, 0xc3008c40u,
227  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_RAM_SIZE, 8u,
228  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_ROW_WIDTH, ((bool)true) },
229  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_RAM_ID, 0xc300cc40u,
230  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_RAM_SIZE, 4u,
231  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_ROW_WIDTH, ((bool)true) },
232  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_RAM_ID, 0xc3010c40u,
233  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_RAM_SIZE, 4u,
234  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_ROW_WIDTH, ((bool)true) },
235  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_RAM_ID, 0xc3012c40u,
236  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_RAM_SIZE, 4u,
237  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_ROW_WIDTH, ((bool)true) },
238  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_RAM_ID, 0xc3014c40u,
239  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_RAM_SIZE, 4u,
240  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_ROW_WIDTH, ((bool)true) },
241  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_RAM_ID, 0xc3016c40u,
242  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_RAM_SIZE, 4u,
243  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_ROW_WIDTH, ((bool)true) },
244  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_RAM_ID, 0xc3018c40u,
245  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_RAM_SIZE, 4u,
246  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_ROW_WIDTH, ((bool)true) },
247 };
248 
253 const SDL_MemConfig_t SDL_MSS_ECC_AGG_MSS_MemEntries[SDL_MSS_ECC_AGG_MSS_RAM_IDS_TOTAL_ENTRIES] =
254 {
255  { SDL_MSS_ECC_AGG_MSS_MSS_L2RAMA_ECC_RAM_ID, 0x10200000u,
256  SDL_MSS_ECC_AGG_MSS_MSS_L2RAMA_ECC_RAM_SIZE, 4u,
257  SDL_MSS_ECC_AGG_MSS_MSS_L2RAMA_ECC_ROW_WIDTH, ((bool)true) },
258  { SDL_MSS_ECC_AGG_MSS_MSS_L2RAMB_ECC_RAM_ID, 0x10280000u,
259  SDL_MSS_ECC_AGG_MSS_MSS_L2RAMB_ECC_RAM_SIZE, 4u,
260  SDL_MSS_ECC_AGG_MSS_MSS_L2RAMB_ECC_ROW_WIDTH, ((bool)true) },
261  { SDL_MSS_ECC_AGG_MSS_MSS_MBOX_ECC_RAM_ID, 0xC5000000u,
262  SDL_MSS_ECC_AGG_MSS_MSS_MBOX_ECC_RAM_SIZE, 4u,
263  SDL_MSS_ECC_AGG_MSS_MSS_MBOX_ECC_ROW_WIDTH, ((bool)true) },
264  { SDL_MSS_ECC_AGG_MSS_MSS_RETRAM_ECC_RAM_ID, 0xC5010000u,
265  SDL_MSS_ECC_AGG_MSS_MSS_RETRAM_ECC_RAM_SIZE, 4u,
266  SDL_MSS_ECC_AGG_MSS_MSS_RETRAM_ECC_ROW_WIDTH, ((bool)true) },
267  { SDL_MSS_ECC_AGG_MSS_MSS_GPADC_DATA_RAM_ECC_RAM_ID, 0xC5030000u,
268  SDL_MSS_ECC_AGG_MSS_MSS_GPADC_DATA_RAM_ECC_RAM_SIZE, 4u,
269  SDL_MSS_ECC_AGG_MSS_MSS_GPADC_DATA_RAM_ECC_ROW_WIDTH, ((bool)true) },
270  { SDL_MSS_ECC_AGG_MSS_MSS_TPTC_A0_ECC_RAM_ID, 0x03140000u,
271  SDL_MSS_ECC_AGG_MSS_MSS_TPTC_A0_ECC_RAM_SIZE, 4u,
272  SDL_MSS_ECC_AGG_MSS_MSS_TPTC_A0_ECC_ROW_WIDTH, ((bool)true) },
273  { SDL_MSS_ECC_AGG_MSS_MSS_TPTC_A1_ECC_RAM_ID, 0x03160000u,
274  SDL_MSS_ECC_AGG_MSS_MSS_TPTC_A1_ECC_RAM_SIZE, 4u,
275  SDL_MSS_ECC_AGG_MSS_MSS_TPTC_A1_ECC_ROW_WIDTH, ((bool)true) },
276  { SDL_MSS_ECC_AGG_MSS_MSS_TPTC_B0_ECC_RAM_ID, 0x03180000u,
277  SDL_MSS_ECC_AGG_MSS_MSS_TPTC_B0_ECC_RAM_SIZE, 4u,
278  SDL_MSS_ECC_AGG_MSS_MSS_TPTC_B0_ECC_ROW_WIDTH, ((bool)true) },
279 };
280 
285 const SDL_MemConfig_t SDL_DSS_ECC_AGG_MemEntries[SDL_DSS_ECC_AGG_RAM_IDS_TOTAL_ENTRIES] =
286 {
287  { SDL_DSS_ECC_AGG_DSS_L3RAMA_ECC_RAM_ID, 0x88000000u,
288  SDL_DSS_ECC_AGG_DSS_L3RAMA_ECC_RAM_SIZE, 4u,
289  SDL_DSS_ECC_AGG_DSS_L3RAMA_ECC_ROW_WIDTH, ((bool)true) },
290  { SDL_DSS_ECC_AGG_DSS_L3RAMB_ECC_RAM_ID, 0x88100000u,
291  SDL_DSS_ECC_AGG_DSS_L3RAMB_ECC_RAM_SIZE, 4u,
292  SDL_DSS_ECC_AGG_DSS_L3RAMB_ECC_ROW_WIDTH, ((bool)true) },
293  { SDL_DSS_ECC_AGG_DSS_L3RAMC_ECC_RAM_ID, 0x88200000u,
294  SDL_DSS_ECC_AGG_DSS_L3RAMC_ECC_RAM_SIZE, 4u,
295  SDL_DSS_ECC_AGG_DSS_L3RAMC_ECC_ROW_WIDTH, ((bool)true) },
296  { SDL_DSS_ECC_AGG_DSS_L3RAMD_ECC_RAM_ID, 0x88280000u,
297  SDL_DSS_ECC_AGG_DSS_L3RAMD_ECC_RAM_SIZE, 4u,
298  SDL_DSS_ECC_AGG_DSS_L3RAMD_ECC_ROW_WIDTH, ((bool)true) },
299  { SDL_DSS_ECC_AGG_DSS_MAILBOX_ECC_RAM_ID, 0x83100000u,
300  SDL_DSS_ECC_AGG_DSS_MAILBOX_ECC_RAM_SIZE, 4u,
301  SDL_DSS_ECC_AGG_DSS_MAILBOX_ECC_ROW_WIDTH, ((bool)true) },
302  { SDL_DSS_ECC_AGG_DSS_CM4_RAM_B0_ECC_RAM_ID, 0u,
303  SDL_DSS_ECC_AGG_DSS_CM4_RAM_B0_ECC_RAM_SIZE, 4u,
304  SDL_DSS_ECC_AGG_DSS_CM4_RAM_B0_ECC_ROW_WIDTH, ((bool)true) },
305  { SDL_DSS_ECC_AGG_DSS_CM4_RAM_B1_ECC_RAM_ID, 0u,
306  SDL_DSS_ECC_AGG_DSS_CM4_RAM_B1_ECC_RAM_SIZE, 4u,
307  SDL_DSS_ECC_AGG_DSS_CM4_RAM_B1_ECC_ROW_WIDTH, ((bool)true) },
308  { SDL_DSS_ECC_AGG_DSS_CM4_RAM_B2_ECC_RAM_ID, 0u,
309  SDL_DSS_ECC_AGG_DSS_CM4_RAM_B2_ECC_RAM_SIZE, 4u,
310  SDL_DSS_ECC_AGG_DSS_CM4_RAM_B2_ECC_ROW_WIDTH, ((bool)true) },
311  { SDL_DSS_ECC_AGG_DSS_CM4_MAILBOX_ECC_RAM_ID, 0x48000000u,
312  SDL_DSS_ECC_AGG_DSS_CM4_MAILBOX_ECC_RAM_SIZE, 4u,
313  SDL_DSS_ECC_AGG_DSS_CM4_MAILBOX_ECC_ROW_WIDTH, ((bool)true) },
314  { SDL_DSS_ECC_AGG_DSS_TPTC_A0_FIFO_ECC_RAM_ID, 0x06160000u,
315  SDL_DSS_ECC_AGG_DSS_TPTC_A0_FIFO_ECC_RAM_SIZE, 4u,
316  SDL_DSS_ECC_AGG_DSS_TPTC_A0_FIFO_ECC_ROW_WIDTH, ((bool)true) },
317  { SDL_DSS_ECC_AGG_DSS_TPTC_A1_FIFO_ECC_RAM_ID, 0x06180000u,
318  SDL_DSS_ECC_AGG_DSS_TPTC_A1_FIFO_ECC_RAM_SIZE, 4u,
319  SDL_DSS_ECC_AGG_DSS_TPTC_A1_FIFO_ECC_ROW_WIDTH, ((bool)true) },
320  { SDL_DSS_ECC_AGG_DSS_TPTC_B0_FIFO_ECC_RAM_ID, 0x061a0000u,
321  SDL_DSS_ECC_AGG_DSS_TPTC_B0_FIFO_ECC_RAM_SIZE, 4u,
322  SDL_DSS_ECC_AGG_DSS_TPTC_B0_FIFO_ECC_ROW_WIDTH, ((bool)true) },
323  { SDL_DSS_ECC_AGG_DSS_TPTC_B1_FIFO_ECC_RAM_ID, 0x061c0000u,
324  SDL_DSS_ECC_AGG_DSS_TPTC_B1_FIFO_ECC_RAM_SIZE, 4u,
325  SDL_DSS_ECC_AGG_DSS_TPTC_B1_FIFO_ECC_ROW_WIDTH, ((bool)true) },
326  { SDL_DSS_ECC_AGG_DSS_TPTC_C0_FIFO_ECC_RAM_ID, 0x061e0000u,
327  SDL_DSS_ECC_AGG_DSS_TPTC_C0_FIFO_ECC_RAM_SIZE, 4u,
328  SDL_DSS_ECC_AGG_DSS_TPTC_C0_FIFO_ECC_ROW_WIDTH, ((bool)true) },
329  { SDL_DSS_ECC_AGG_DSS_TPTC_C1_FIFO_ECC_RAM_ID, 0x06200000u,
330  SDL_DSS_ECC_AGG_DSS_TPTC_C1_FIFO_ECC_RAM_SIZE, 4u,
331  SDL_DSS_ECC_AGG_DSS_TPTC_C1_FIFO_ECC_ROW_WIDTH, ((bool)true) },
332  { SDL_DSS_ECC_AGG_DSS_TPTC_C2_FIFO_ECC_RAM_ID, 0x06220000u,
333  SDL_DSS_ECC_AGG_DSS_TPTC_C2_FIFO_ECC_RAM_SIZE, 4u,
334  SDL_DSS_ECC_AGG_DSS_TPTC_C2_FIFO_ECC_ROW_WIDTH, ((bool)true) },
335  { SDL_DSS_ECC_AGG_DSS_TPTC_C3_FIFO_ECC_RAM_ID, 0x06240000u,
336  SDL_DSS_ECC_AGG_DSS_TPTC_C3_FIFO_ECC_RAM_SIZE, 4u,
337  SDL_DSS_ECC_AGG_DSS_TPTC_C3_FIFO_ECC_ROW_WIDTH, ((bool)true) },
338  { SDL_DSS_ECC_AGG_DSS_TPTC_C4_FIFO_ECC_RAM_ID, 0x06260000u,
339  SDL_DSS_ECC_AGG_DSS_TPTC_C4_FIFO_ECC_RAM_SIZE, 4u,
340  SDL_DSS_ECC_AGG_DSS_TPTC_C4_FIFO_ECC_ROW_WIDTH, ((bool)true) },
341  { SDL_DSS_ECC_AGG_DSS_TPTC_C5_FIFO_ECC_RAM_ID, 0x06280000u,
342  SDL_DSS_ECC_AGG_DSS_TPTC_C5_FIFO_ECC_RAM_SIZE, 4u,
343  SDL_DSS_ECC_AGG_DSS_TPTC_C5_FIFO_ECC_ROW_WIDTH, ((bool)true) },
344  { SDL_DSS_ECC_AGG_RSS_TPTC_A0_FIFO_ECC_RAM_ID, 0u,
345  SDL_DSS_ECC_AGG_RSS_TPTC_A0_FIFO_ECC_RAM_SIZE, 4u,
346  SDL_DSS_ECC_AGG_RSS_TPTC_A0_FIFO_ECC_ROW_WIDTH, ((bool)true) },
347  { SDL_DSS_ECC_AGG_RSS_TPTC_A1_FIFO_ECC_RAM_ID, 0u,
348  SDL_DSS_ECC_AGG_RSS_TPTC_A1_FIFO_ECC_RAM_SIZE, 4u,
349  SDL_DSS_ECC_AGG_RSS_TPTC_A1_FIFO_ECC_ROW_WIDTH, ((bool)true) },
350  { SDL_DSS_ECC_AGG_DSS_HWA_PARAM_RAM_ECC_RAM_ID, 0x06060000u,
351  SDL_DSS_ECC_AGG_DSS_HWA_PARAM_RAM_ECC_RAM_SIZE, 4u,
352  SDL_DSS_ECC_AGG_DSS_HWA_PARAM_RAM_ECC_ROW_WIDTH, ((bool)true) },
353 };
354 
359 const SDL_MemConfig_t SDL_MSS_MCANA_ECC_MemEntries[SDL_MSS_MCANA_ECC_RAM_IDS_TOTAL_ENTRIES] =
360 {
361  { SDL_MSS_MCANA_ECC_MSS_MCANA_ECC_RAM_ID, 0u,
362  SDL_MSS_MCANA_ECC_MSS_MCANA_ECC_RAM_SIZE, 4u,
363  SDL_MSS_MCANA_ECC_MSS_MCANA_ECC_ROW_WIDTH, ((bool)false) },
364 };
365 
370 const SDL_MemConfig_t SDL_MSS_MCANB_ECC_MemEntries[SDL_MSS_MCANB_ECC_RAM_IDS_TOTAL_ENTRIES] =
371 {
372  { SDL_MSS_MCANB_ECC_MSS_MCANB_ECC_RAM_ID, 0u,
373  SDL_MSS_MCANB_ECC_MSS_MCANB_ECC_RAM_SIZE, 4u,
374  SDL_MSS_MCANB_ECC_MSS_MCANB_ECC_ROW_WIDTH, ((bool)false) },
375 };
376 
381 static const SDL_RAMIdEntry_t SDL_R5FSS0_CORE0_ECC_AGGR_RamIdTable[SDL_R5FSS0_CORE0_ECC_AGGR_NUM_RAMS] =
382 {
383  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID,
384  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_INJECT_TYPE,
385  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_ECC_TYPE,
386  0u,
387  NULL },
388  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID,
389  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_INJECT_TYPE,
390  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_ECC_TYPE,
391  0u,
392  NULL },
393  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID,
394  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_INJECT_TYPE,
395  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_ECC_TYPE,
396  0u,
397  NULL },
398  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID,
399  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_INJECT_TYPE,
400  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_ECC_TYPE,
401  0u,
402  NULL },
403  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID,
404  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_INJECT_TYPE,
405  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_ECC_TYPE,
406  0u,
407  NULL },
408  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID,
409  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_INJECT_TYPE,
410  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_ECC_TYPE,
411  0u,
412  NULL },
413  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID,
414  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_INJECT_TYPE,
415  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_ECC_TYPE,
416  0u,
417  NULL },
418  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID,
419  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_INJECT_TYPE,
420  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_ECC_TYPE,
421  0u,
422  NULL },
423  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID,
424  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_INJECT_TYPE,
425  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_ECC_TYPE,
426  0u,
427  NULL },
428  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID,
429  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_INJECT_TYPE,
430  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_ECC_TYPE,
431  0u,
432  NULL },
433  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID,
434  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_INJECT_TYPE,
435  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_ECC_TYPE,
436  0u,
437  NULL },
438  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID,
439  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_INJECT_TYPE,
440  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_ECC_TYPE,
441  0u,
442  NULL },
443  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID,
444  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_INJECT_TYPE,
445  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_ECC_TYPE,
446  0u,
447  NULL },
448  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID,
449  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_INJECT_TYPE,
450  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_ECC_TYPE,
451  0u,
452  NULL },
453  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID,
454  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_INJECT_TYPE,
455  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_ECC_TYPE,
456  0u,
457  NULL },
458  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID,
459  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_INJECT_TYPE,
460  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_ECC_TYPE,
461  0u,
462  NULL },
463  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID,
464  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_INJECT_TYPE,
465  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_ECC_TYPE,
466  0u,
467  NULL },
468  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID,
469  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_INJECT_TYPE,
470  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_ECC_TYPE,
471  0u,
472  NULL },
473  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID,
474  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_INJECT_TYPE,
475  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_ECC_TYPE,
476  0u,
477  NULL },
478  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID,
479  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_INJECT_TYPE,
480  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_ECC_TYPE,
481  0u,
482  NULL },
483  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID,
484  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_INJECT_TYPE,
485  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_ECC_TYPE,
486  0u,
487  NULL },
488  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_ID,
489  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_INJECT_TYPE,
490  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_ECC_TYPE,
491  0u,
492  NULL },
493  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_ID,
494  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_INJECT_TYPE,
495  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_ECC_TYPE,
496  0u,
497  NULL },
498  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_ID,
499  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_INJECT_TYPE,
500  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_ECC_TYPE,
501  0u,
502  NULL },
503  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_ID,
504  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_INJECT_TYPE,
505  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_ECC_TYPE,
506  0u,
507  NULL },
508  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_ID,
509  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_INJECT_TYPE,
510  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_ECC_TYPE,
511  0u,
512  NULL },
513  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_ID,
514  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_INJECT_TYPE,
515  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_ECC_TYPE,
516  0u,
517  NULL },
518  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID,
519  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_INJECT_TYPE,
520  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ECC_TYPE,
521  0u,
522  NULL },
523 };
524 
529 static const SDL_RAMIdEntry_t SDL_R5FSS0_CORE1_ECC_AGGR_RamIdTable[SDL_R5FSS0_CORE1_ECC_AGGR_NUM_RAMS] =
530 {
531  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_RAM_ID,
532  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_INJECT_TYPE,
533  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_ECC_TYPE,
534  0u,
535  NULL },
536  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_RAM_ID,
537  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_INJECT_TYPE,
538  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_ECC_TYPE,
539  0u,
540  NULL },
541  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_RAM_ID,
542  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_INJECT_TYPE,
543  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_ECC_TYPE,
544  0u,
545  NULL },
546  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_RAM_ID,
547  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_INJECT_TYPE,
548  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_ECC_TYPE,
549  0u,
550  NULL },
551  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_RAM_ID,
552  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_INJECT_TYPE,
553  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_ECC_TYPE,
554  0u,
555  NULL },
556  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_RAM_ID,
557  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_INJECT_TYPE,
558  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_ECC_TYPE,
559  0u,
560  NULL },
561  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_RAM_ID,
562  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_INJECT_TYPE,
563  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_ECC_TYPE,
564  0u,
565  NULL },
566  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_RAM_ID,
567  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_INJECT_TYPE,
568  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_ECC_TYPE,
569  0u,
570  NULL },
571  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_RAM_ID,
572  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_INJECT_TYPE,
573  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_ECC_TYPE,
574  0u,
575  NULL },
576  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_RAM_ID,
577  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_INJECT_TYPE,
578  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_ECC_TYPE,
579  0u,
580  NULL },
581  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_RAM_ID,
582  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_INJECT_TYPE,
583  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_ECC_TYPE,
584  0u,
585  NULL },
586  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_RAM_ID,
587  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_INJECT_TYPE,
588  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_ECC_TYPE,
589  0u,
590  NULL },
591  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_RAM_ID,
592  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_INJECT_TYPE,
593  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_ECC_TYPE,
594  0u,
595  NULL },
596  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_RAM_ID,
597  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_INJECT_TYPE,
598  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_ECC_TYPE,
599  0u,
600  NULL },
601  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_RAM_ID,
602  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_INJECT_TYPE,
603  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_ECC_TYPE,
604  0u,
605  NULL },
606  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_RAM_ID,
607  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_INJECT_TYPE,
608  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_ECC_TYPE,
609  0u,
610  NULL },
611  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_RAM_ID,
612  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_INJECT_TYPE,
613  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_ECC_TYPE,
614  0u,
615  NULL },
616  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_RAM_ID,
617  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_INJECT_TYPE,
618  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_ECC_TYPE,
619  0u,
620  NULL },
621  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_RAM_ID,
622  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_INJECT_TYPE,
623  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_ECC_TYPE,
624  0u,
625  NULL },
626  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_RAM_ID,
627  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_INJECT_TYPE,
628  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_ECC_TYPE,
629  0u,
630  NULL },
631  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_RAM_ID,
632  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_INJECT_TYPE,
633  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_ECC_TYPE,
634  0u,
635  NULL },
636  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_RAM_ID,
637  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_INJECT_TYPE,
638  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_ECC_TYPE,
639  0u,
640  NULL },
641  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_RAM_ID,
642  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_INJECT_TYPE,
643  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_ECC_TYPE,
644  0u,
645  NULL },
646  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_RAM_ID,
647  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_INJECT_TYPE,
648  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_ECC_TYPE,
649  0u,
650  NULL },
651  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_RAM_ID,
652  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_INJECT_TYPE,
653  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_ECC_TYPE,
654  0u,
655  NULL },
656  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_RAM_ID,
657  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_INJECT_TYPE,
658  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_ECC_TYPE,
659  0u,
660  NULL },
661  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_RAM_ID,
662  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_INJECT_TYPE,
663  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_ECC_TYPE,
664  0u,
665  NULL },
666  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_RAM_ID,
667  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_INJECT_TYPE,
668  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_ECC_TYPE,
669  0u,
670  NULL },
671 };
672 
677 const SDL_RAMIdEntry_t SDL_MSS_ECC_AGG_MSS_RamIdTable[SDL_MSS_ECC_AGG_MSS_NUM_RAMS] =
678 {
679  { SDL_MSS_ECC_AGG_MSS_MSS_L2RAMA_ECC_RAM_ID,
680  SDL_MSS_ECC_AGG_MSS_MSS_L2RAMA_ECC_INJECT_TYPE,
681  SDL_MSS_ECC_AGG_MSS_MSS_L2RAMA_ECC_ECC_TYPE,
682  0u,
683  NULL },
684  { SDL_MSS_ECC_AGG_MSS_MSS_L2RAMB_ECC_RAM_ID,
685  SDL_MSS_ECC_AGG_MSS_MSS_L2RAMB_ECC_INJECT_TYPE,
686  SDL_MSS_ECC_AGG_MSS_MSS_L2RAMB_ECC_ECC_TYPE,
687  0u,
688  NULL },
689  { SDL_MSS_ECC_AGG_MSS_MSS_MBOX_ECC_RAM_ID,
690  SDL_MSS_ECC_AGG_MSS_MSS_MBOX_ECC_INJECT_TYPE,
691  SDL_MSS_ECC_AGG_MSS_MSS_MBOX_ECC_ECC_TYPE,
692  0u,
693  NULL },
694  { SDL_MSS_ECC_AGG_MSS_MSS_RETRAM_ECC_RAM_ID,
695  SDL_MSS_ECC_AGG_MSS_MSS_RETRAM_ECC_INJECT_TYPE,
696  SDL_MSS_ECC_AGG_MSS_MSS_RETRAM_ECC_ECC_TYPE,
697  0u,
698  NULL },
699  { SDL_MSS_ECC_AGG_MSS_MSS_GPADC_DATA_RAM_ECC_RAM_ID,
700  SDL_MSS_ECC_AGG_MSS_MSS_GPADC_DATA_RAM_ECC_INJECT_TYPE,
701  SDL_MSS_ECC_AGG_MSS_MSS_GPADC_DATA_RAM_ECC_ECC_TYPE,
702  0u,
703  NULL },
704  { SDL_MSS_ECC_AGG_MSS_MSS_TPTC_A0_ECC_RAM_ID,
705  SDL_MSS_ECC_AGG_MSS_MSS_TPTC_A0_ECC_INJECT_TYPE,
706  SDL_MSS_ECC_AGG_MSS_MSS_TPTC_A0_ECC_ECC_TYPE,
707  0u,
708  NULL },
709  { SDL_MSS_ECC_AGG_MSS_MSS_TPTC_A1_ECC_RAM_ID,
710  SDL_MSS_ECC_AGG_MSS_MSS_TPTC_A1_ECC_INJECT_TYPE,
711  SDL_MSS_ECC_AGG_MSS_MSS_TPTC_A1_ECC_ECC_TYPE,
712  0u,
713  NULL },
714  { SDL_MSS_ECC_AGG_MSS_MSS_TPTC_B0_ECC_RAM_ID,
715  SDL_MSS_ECC_AGG_MSS_MSS_TPTC_B0_ECC_INJECT_TYPE,
716  SDL_MSS_ECC_AGG_MSS_MSS_TPTC_B0_ECC_ECC_TYPE,
717  0u,
718  NULL },
719 };
720 
725 const SDL_RAMIdEntry_t SDL_DSS_ECC_AGG_RamIdTable[SDL_DSS_ECC_AGG_NUM_RAMS] =
726 {
727  { SDL_DSS_ECC_AGG_DSS_L3RAMA_ECC_RAM_ID,
728  SDL_DSS_ECC_AGG_DSS_L3RAMA_ECC_INJECT_TYPE,
729  SDL_DSS_ECC_AGG_DSS_L3RAMA_ECC_ECC_TYPE,
730  0u,
731  NULL },
732  { SDL_DSS_ECC_AGG_DSS_L3RAMB_ECC_RAM_ID,
733  SDL_DSS_ECC_AGG_DSS_L3RAMB_ECC_INJECT_TYPE,
734  SDL_DSS_ECC_AGG_DSS_L3RAMB_ECC_ECC_TYPE,
735  0u,
736  NULL },
737  { SDL_DSS_ECC_AGG_DSS_L3RAMC_ECC_RAM_ID,
738  SDL_DSS_ECC_AGG_DSS_L3RAMC_ECC_INJECT_TYPE,
739  SDL_DSS_ECC_AGG_DSS_L3RAMC_ECC_ECC_TYPE,
740  0u,
741  NULL },
742  { SDL_DSS_ECC_AGG_DSS_L3RAMD_ECC_RAM_ID,
743  SDL_DSS_ECC_AGG_DSS_L3RAMD_ECC_INJECT_TYPE,
744  SDL_DSS_ECC_AGG_DSS_L3RAMD_ECC_ECC_TYPE,
745  0u,
746  NULL },
747  { SDL_DSS_ECC_AGG_DSS_MAILBOX_ECC_RAM_ID,
748  SDL_DSS_ECC_AGG_DSS_MAILBOX_ECC_INJECT_TYPE,
749  SDL_DSS_ECC_AGG_DSS_MAILBOX_ECC_ECC_TYPE,
750  0u,
751  NULL },
752  { SDL_DSS_ECC_AGG_DSS_CM4_RAM_B0_ECC_RAM_ID,
753  SDL_DSS_ECC_AGG_DSS_CM4_RAM_B0_ECC_INJECT_TYPE,
754  SDL_DSS_ECC_AGG_DSS_CM4_RAM_B0_ECC_ECC_TYPE,
755  0u,
756  NULL },
757  { SDL_DSS_ECC_AGG_DSS_CM4_RAM_B1_ECC_RAM_ID,
758  SDL_DSS_ECC_AGG_DSS_CM4_RAM_B1_ECC_INJECT_TYPE,
759  SDL_DSS_ECC_AGG_DSS_CM4_RAM_B1_ECC_ECC_TYPE,
760  0u,
761  NULL },
762  { SDL_DSS_ECC_AGG_DSS_CM4_RAM_B2_ECC_RAM_ID,
763  SDL_DSS_ECC_AGG_DSS_CM4_RAM_B2_ECC_INJECT_TYPE,
764  SDL_DSS_ECC_AGG_DSS_CM4_RAM_B2_ECC_ECC_TYPE,
765  0u,
766  NULL },
767  { SDL_DSS_ECC_AGG_DSS_CM4_MAILBOX_ECC_RAM_ID,
768  SDL_DSS_ECC_AGG_DSS_CM4_MAILBOX_ECC_INJECT_TYPE,
769  SDL_DSS_ECC_AGG_DSS_CM4_MAILBOX_ECC_ECC_TYPE,
770  0u,
771  NULL },
772  { SDL_DSS_ECC_AGG_DSS_TPTC_A0_FIFO_ECC_RAM_ID,
773  SDL_DSS_ECC_AGG_DSS_TPTC_A0_FIFO_ECC_INJECT_TYPE,
774  SDL_DSS_ECC_AGG_DSS_TPTC_A0_FIFO_ECC_ECC_TYPE,
775  0u,
776  NULL },
777  { SDL_DSS_ECC_AGG_DSS_TPTC_A1_FIFO_ECC_RAM_ID,
778  SDL_DSS_ECC_AGG_DSS_TPTC_A1_FIFO_ECC_INJECT_TYPE,
779  SDL_DSS_ECC_AGG_DSS_TPTC_A1_FIFO_ECC_ECC_TYPE,
780  0u,
781  NULL },
782  { SDL_DSS_ECC_AGG_DSS_TPTC_B0_FIFO_ECC_RAM_ID,
783  SDL_DSS_ECC_AGG_DSS_TPTC_B0_FIFO_ECC_INJECT_TYPE,
784  SDL_DSS_ECC_AGG_DSS_TPTC_B0_FIFO_ECC_ECC_TYPE,
785  0u,
786  NULL },
787  { SDL_DSS_ECC_AGG_DSS_TPTC_B1_FIFO_ECC_RAM_ID,
788  SDL_DSS_ECC_AGG_DSS_TPTC_B1_FIFO_ECC_INJECT_TYPE,
789  SDL_DSS_ECC_AGG_DSS_TPTC_B1_FIFO_ECC_ECC_TYPE,
790  0u,
791  NULL },
792  { SDL_DSS_ECC_AGG_DSS_TPTC_C0_FIFO_ECC_RAM_ID,
793  SDL_DSS_ECC_AGG_DSS_TPTC_C0_FIFO_ECC_INJECT_TYPE,
794  SDL_DSS_ECC_AGG_DSS_TPTC_C0_FIFO_ECC_ECC_TYPE,
795  0u,
796  NULL },
797  { SDL_DSS_ECC_AGG_DSS_TPTC_C1_FIFO_ECC_RAM_ID,
798  SDL_DSS_ECC_AGG_DSS_TPTC_C1_FIFO_ECC_INJECT_TYPE,
799  SDL_DSS_ECC_AGG_DSS_TPTC_C1_FIFO_ECC_ECC_TYPE,
800  0u,
801  NULL },
802  { SDL_DSS_ECC_AGG_DSS_TPTC_C2_FIFO_ECC_RAM_ID,
803  SDL_DSS_ECC_AGG_DSS_TPTC_C2_FIFO_ECC_INJECT_TYPE,
804  SDL_DSS_ECC_AGG_DSS_TPTC_C2_FIFO_ECC_ECC_TYPE,
805  0u,
806  NULL },
807  { SDL_DSS_ECC_AGG_DSS_TPTC_C3_FIFO_ECC_RAM_ID,
808  SDL_DSS_ECC_AGG_DSS_TPTC_C3_FIFO_ECC_INJECT_TYPE,
809  SDL_DSS_ECC_AGG_DSS_TPTC_C3_FIFO_ECC_ECC_TYPE,
810  0u,
811  NULL },
812  { SDL_DSS_ECC_AGG_DSS_TPTC_C4_FIFO_ECC_RAM_ID,
813  SDL_DSS_ECC_AGG_DSS_TPTC_C4_FIFO_ECC_INJECT_TYPE,
814  SDL_DSS_ECC_AGG_DSS_TPTC_C4_FIFO_ECC_ECC_TYPE,
815  0u,
816  NULL },
817  { SDL_DSS_ECC_AGG_DSS_TPTC_C5_FIFO_ECC_RAM_ID,
818  SDL_DSS_ECC_AGG_DSS_TPTC_C5_FIFO_ECC_INJECT_TYPE,
819  SDL_DSS_ECC_AGG_DSS_TPTC_C5_FIFO_ECC_ECC_TYPE,
820  0u,
821  NULL },
822  { SDL_DSS_ECC_AGG_RSS_TPTC_A0_FIFO_ECC_RAM_ID,
823  SDL_DSS_ECC_AGG_RSS_TPTC_A0_FIFO_ECC_INJECT_TYPE,
824  SDL_DSS_ECC_AGG_RSS_TPTC_A0_FIFO_ECC_ECC_TYPE,
825  0u,
826  NULL },
827  { SDL_DSS_ECC_AGG_RSS_TPTC_A1_FIFO_ECC_RAM_ID,
828  SDL_DSS_ECC_AGG_RSS_TPTC_A1_FIFO_ECC_INJECT_TYPE,
829  SDL_DSS_ECC_AGG_RSS_TPTC_A1_FIFO_ECC_ECC_TYPE,
830  0u,
831  NULL },
832  { SDL_DSS_ECC_AGG_DSS_HWA_PARAM_RAM_ECC_RAM_ID,
833  SDL_DSS_ECC_AGG_DSS_HWA_PARAM_RAM_ECC_INJECT_TYPE,
834  SDL_DSS_ECC_AGG_DSS_HWA_PARAM_RAM_ECC_ECC_TYPE,
835  0u,
836  NULL },
837 };
838 
843 const SDL_RAMIdEntry_t SDL_MSS_MCANA_ECC_RamIdTable[SDL_MSS_MCANA_ECC_NUM_RAMS] =
844 {
845  { SDL_MSS_MCANA_ECC_MSS_MCANA_ECC_RAM_ID,
846  SDL_MSS_MCANA_ECC_MSS_MCANA_ECC_INJECT_TYPE,
847  SDL_MSS_MCANA_ECC_MSS_MCANA_ECC_ECC_TYPE,
848  0u,
849  NULL },
850 };
851 
856 const SDL_RAMIdEntry_t SDL_MSS_MCANB_ECC_RamIdTable[SDL_MSS_MCANB_ECC_NUM_RAMS] =
857 {
858  { SDL_MSS_MCANB_ECC_MSS_MCANB_ECC_RAM_ID,
859  SDL_MSS_MCANB_ECC_MSS_MCANB_ECC_INJECT_TYPE,
860  SDL_MSS_MCANB_ECC_MSS_MCANB_ECC_ECC_TYPE,
861  0u,
862  NULL },
863 };
864 
865 static SDL_ecc_aggrRegs * const SDL_ECC_aggrBaseAddressTable[SDL_ECC_Base_Address_TOTAL_ENTRIES] =
866 {
867  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MSS_ECC_AGG_R5A_U_BASE)),
868  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MSS_ECC_AGG_R5B_U_BASE)),
869  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MSS_ECC_AGG_MSS_U_BASE)),
870  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_DSS_ECC_AGG_U_BASE)),
871  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MSS_MCANA_ECC_U_BASE )),
872  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MSS_MCANB_ECC_U_BASE)),
873 
874 };
875 
876 SDL_ecc_aggrRegs * SDL_ECC_aggrTransBaseAddressTable[SDL_ECC_MEMTYPE_MAX];
879 static const SDL_EccAggrEntry_t SDL_ECC_aggrTable[SDL_ECC_MEMTYPE_MAX] =
880 {
881 
882  // SDL_MSS_ECC_AGG_R5A (0)
883  {
884  SDL_R5FSS0_CORE0_ECC_AGGR_NUM_RAMS,
885  SDL_R5FSS0_CORE0_ECC_AGGR_RamIdTable,
886  SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
887  SDL_R5FSS0_CORE0_ECC_AGGR_MemEntries,
888  SDL_ESM_INST_MSS_ESM,
889  SDL_ESMG1_ECCAGGA_SERR,
890  SDL_ESMG1_ECCAGGA_UERR
891  },
892  // Index: SDL_MSS_ECC_AGG_R5B (1)
893  {
894  SDL_R5FSS0_CORE1_ECC_AGGR_NUM_RAMS,
895  SDL_R5FSS0_CORE1_ECC_AGGR_RamIdTable,
896  SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
897  SDL_R5FSS0_CORE1_ECC_AGGR_MemEntries,
898  SDL_ESM_INST_MSS_ESM,
899  SDL_ESMG1_ECCAGGB_SERR,
900  SDL_ESMG1_ECCAGGB_UERR
901  },
902  // Index: SDL_MSS_ECC_AGG_MSS (2)
903  {
904  SDL_MSS_ECC_AGG_MSS_NUM_RAMS,
905  SDL_MSS_ECC_AGG_MSS_RamIdTable,
906  SDL_MSS_ECC_AGG_MSS_RAM_IDS_TOTAL_ENTRIES,
907  SDL_MSS_ECC_AGG_MSS_MemEntries,
908  SDL_ESM_INST_MSS_ESM,
909  SDL_ESMG1_ECCAGGMSS_SERR,
910  SDL_ESMG1_ECCAGGMSS_UERR
911  },
912  // Index: SDL_DSS_ECC_AGG (3)
913  {
914  SDL_DSS_ECC_AGG_NUM_RAMS,
915  SDL_DSS_ECC_AGG_RamIdTable,
916  SDL_DSS_ECC_AGG_RAM_IDS_TOTAL_ENTRIES,
917  SDL_DSS_ECC_AGG_MemEntries,
918  SDL_ESM_INST_DSS_ESM,
919  SDL_DSS_ESMG1_DSS_ECC_AGG_SERR,
920  SDL_DSS_ESMG1_DSS_ECC_AGG_UERR
921  },
922  // Index: SDL_MSS_MCANA_ECC (4)
923  {
924  SDL_MSS_MCANA_ECC_NUM_RAMS,
925  SDL_MSS_MCANA_ECC_RamIdTable,
926  SDL_MSS_MCANA_ECC_RAM_IDS_TOTAL_ENTRIES,
927  SDL_MSS_MCANA_ECC_MemEntries,
928  SDL_ESM_INST_MSS_ESM,
929  SDL_ESMG1_MCANA_SERR,
930  SDL_ESMG1_MCANA_UERR
931  },
932  // Index: SDL_MSS_MCANB_ECC (5)
933  {
934  SDL_MSS_MCANB_ECC_NUM_RAMS,
935  SDL_MSS_MCANB_ECC_RamIdTable,
936  SDL_MSS_MCANB_ECC_RAM_IDS_TOTAL_ENTRIES,
937  SDL_MSS_MCANB_ECC_MemEntries,
938  SDL_ESM_INST_MSS_ESM,
939  SDL_ESMG1_MCANB_SERR,
940  SDL_ESMG1_MCANB_UERR
941  }
942 
943  };
944  #endif /* INCLUDE_SDL_ECC_SOC_H_ */
SDL_MSS_ECC_AGG_MSS_MemEntries
const SDL_MemConfig_t SDL_MSS_ECC_AGG_MSS_MemEntries[SDL_MSS_ECC_AGG_MSS_RAM_IDS_TOTAL_ENTRIES]
Definition: am273x/sdl_ecc_soc.h:253
SDL_R5FSS0_CORE0_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_R5FSS0_CORE0_ECC_AGGR_RamIdTable[SDL_R5FSS0_CORE0_ECC_AGGR_NUM_RAMS]
Definition: am273x/sdl_ecc_soc.h:381
SDL_ecc_aggrRegs
Definition: V1/sdlr_ecc.h:53
SDL_MSS_MCANA_ECC_MemEntries
const SDL_MemConfig_t SDL_MSS_MCANA_ECC_MemEntries[SDL_MSS_MCANA_ECC_RAM_IDS_TOTAL_ENTRIES]
Definition: am273x/sdl_ecc_soc.h:359
SDL_DSS_ECC_AGG_RAM_IDS_TOTAL_ENTRIES
#define SDL_DSS_ECC_AGG_RAM_IDS_TOTAL_ENTRIES
Definition: am273x/sdl_ecc_soc.h:59
SDL_DSS_ECC_AGG_RamIdTable
const SDL_RAMIdEntry_t SDL_DSS_ECC_AGG_RamIdTable[SDL_DSS_ECC_AGG_NUM_RAMS]
Definition: am273x/sdl_ecc_soc.h:725
SDL_R5FSS0_CORE0_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_R5FSS0_CORE0_ECC_AGGR_MemEntries[SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: am273x/sdl_ecc_soc.h:69
SDL_DSS_ECC_AGG_MemEntries
const SDL_MemConfig_t SDL_DSS_ECC_AGG_MemEntries[SDL_DSS_ECC_AGG_RAM_IDS_TOTAL_ENTRIES]
Definition: am273x/sdl_ecc_soc.h:285
SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: am273x/sdl_ecc_soc.h:56
SDL_MSS_MCANB_ECC_RamIdTable
const SDL_RAMIdEntry_t SDL_MSS_MCANB_ECC_RamIdTable[SDL_MSS_MCANB_ECC_NUM_RAMS]
Definition: am273x/sdl_ecc_soc.h:856
sdl_ip_ecc.h
SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: am273x/sdl_ecc_soc.h:57
SDL_MSS_MCANA_ECC_RamIdTable
const SDL_RAMIdEntry_t SDL_MSS_MCANA_ECC_RamIdTable[SDL_MSS_MCANA_ECC_NUM_RAMS]
Definition: am273x/sdl_ecc_soc.h:843
SDL_ECC_Base_Address_TOTAL_ENTRIES
#define SDL_ECC_Base_Address_TOTAL_ENTRIES
Definition: am273x/sdl_ecc_soc.h:62
SDL_MemConfig_t
Definition: sdl_ecc_priv.h:88
sdl_ecc.h
Header file contains enumerations, structure definitions and function.
SDL_ECC_aggrBaseAddressTable
static SDL_ecc_aggrRegs *const SDL_ECC_aggrBaseAddressTable[SDL_ECC_Base_Address_TOTAL_ENTRIES]
Definition: am273x/sdl_ecc_soc.h:865
SDL_ECC_aggrTransBaseAddressTable
SDL_ecc_aggrRegs * SDL_ECC_aggrTransBaseAddressTable[SDL_ECC_MEMTYPE_MAX]
Definition: am273x/sdl_ecc_soc.h:876
SDL_MSS_ECC_AGG_MSS_RamIdTable
const SDL_RAMIdEntry_t SDL_MSS_ECC_AGG_MSS_RamIdTable[SDL_MSS_ECC_AGG_MSS_NUM_RAMS]
Definition: am273x/sdl_ecc_soc.h:677
SDL_RAMIdEntry_t
Definition: sdl_ecc_priv.h:63
SDL_ECC_aggrTable
static const SDL_EccAggrEntry_t SDL_ECC_aggrTable[SDL_ECC_MEMTYPE_MAX]
Definition: am273x/sdl_ecc_soc.h:879
SDL_R5FSS0_CORE1_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_R5FSS0_CORE1_ECC_AGGR_RamIdTable[SDL_R5FSS0_CORE1_ECC_AGGR_NUM_RAMS]
Definition: am273x/sdl_ecc_soc.h:529
SDL_MSS_MCANB_ECC_MemEntries
const SDL_MemConfig_t SDL_MSS_MCANB_ECC_MemEntries[SDL_MSS_MCANB_ECC_RAM_IDS_TOTAL_ENTRIES]
Definition: am273x/sdl_ecc_soc.h:370
SDL_EccAggrEntry_t
Definition: sdl_ecc_priv.h:104
SDL_R5FSS0_CORE1_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_R5FSS0_CORE1_ECC_AGGR_MemEntries[SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: am273x/sdl_ecc_soc.h:161
SDL_MSS_MCANA_ECC_RAM_IDS_TOTAL_ENTRIES
#define SDL_MSS_MCANA_ECC_RAM_IDS_TOTAL_ENTRIES
Definition: am273x/sdl_ecc_soc.h:60
SDL_MSS_MCANB_ECC_RAM_IDS_TOTAL_ENTRIES
#define SDL_MSS_MCANB_ECC_RAM_IDS_TOTAL_ENTRIES
Definition: am273x/sdl_ecc_soc.h:61
SDL_MSS_ECC_AGG_MSS_RAM_IDS_TOTAL_ENTRIES
#define SDL_MSS_ECC_AGG_MSS_RAM_IDS_TOTAL_ENTRIES
Definition: am273x/sdl_ecc_soc.h:58
sdl_ecc_priv.h