This example demonstrates how to configure the DCC and use it to monitor clocks in the two supported modes (continuous and single-shot modes). It also demonstrates how to receive errors generated by DCC in the DSP and Main domain.
This example displays:
* Initializing the ESM to detect the DCC error event(s) * Registration of application callback for notification of ESM error events for the MSS ESM instance * Configuration of one MSS DCC instance to monitor a single clock in continuous mode * Forcing of an error to create a DCC error event
The following methods can be used as a trigger for the DCC error event:
* Change ratio criterion for stable clocks * Turn off power for the monitored input clock
FOR MSS INSTANCES
Use Case | Reference Clock | Test Clock | Description |
---|---|---|---|
UC-0 | XTAL_CLK | "MSS_RTIA_CLK" | Configuration of MSS DCCA instance in continuous mode and error event is forced |
UC-1 | XTAL_CLK | "MSS_RTIA_CLK" | Configuration of MSS DCCA instance in single-shot mode and completion with no errors |
UC-2 | XTAL_CLK | "MSS_RTIA_CLK" | Configuration of MSS DCCA instance in continuous mode and error event is forced |
UC-3 | XTAL_CLK | "SYS_CLK" | Configuration of MSS DCCA instance in single-shot mode and completion with no errors |
UC-4 | XTAL_CLK | "PLL_PER_HSDIV1_CLKOUT1" | Configuration of MSS DCCD instance in continuous mode and error event is forced |
UC-5 | XTAL_CLK | "MSS_MCANA_CLK" | Configuration of MSS DCCD instance in continuous mode and error event is forced |
UC-6 | XTAL_CLK | "MSS_MCANA_CLK" | Configuration of MSS DCCD instance in continuous mode and completion with no errors |
UC-7 | XTAL_CLK | "MSS_MCANA_CLK" | Configuration of MSS DCCD instance in continuous mode and completion with no errors |
UC-8 | XTAL_CLK | "SYS_CLK" | Configuration of MSS DCCA instance in continuous mode and completion with no errors |
FOR DSS INSTANCES
Use Case | Reference Clock | Test Clock | Description |
---|---|---|---|
UC-0 | XTAL_CLK | "DSS_WDG_CLK" | Configuration of DSS DCCA instance in continuous mode and error event is forced |
UC-1 | XTAL_CLK | "DSS_WDG_CLK" | Configuration of DSS DCCA instance in single-shot mode and completion with no errors |
UC-2 | XTAL_CLK | "DSS_RTIA_CLK" | Configuration of DSS DCCA instance in continuous mode and error event is forced |
UC-3 | XTAL_CLK | "DSS_RTIA_CLK" | Configuration of DSS DCCA instance in single-shot mode and completion with no errors |
UC-4 | XTAL_CLK | "DSS_RTIA_CLK" | Configuration of DSS DCCA instance in continuous mode and error event is forced |
UC-5 | XTAL_CLK | "DSS_WDG_CLK" | Configuration of DSS DCCA instance in continuous mode and error event is forced |
UC-6 | XTAL_CLK | "DSS_WDG_CLK" | Configuration of DSS DCCB instance in continuous mode and completion with no errors |
UC-7 | XTAL_CLK | "DSS_WDG_CLK" | Configuration of DSS DCCB instance in continuous mode and completion with no errors |
UC-8 | XTAL_CLK | "DSS_WDG_CLK" | Configuration of DSS DCCB instance in continuous mode and completion with no errors |
Parameter | Value |
---|---|
CPU + OS | r5fss0-0 nortos |
c66ss0 nortos | |
Toolchain | ti-arm-clang |
ti-c6000 | |
Board | am273x-evm |
Example folder | examples/sdl/dcc/dcc_modes1/ |
Shown below is a sample output when the application is run,