AM263x MCU+ SDK  10.01.00
soc_xbar.h
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32  * Name : soc_xbar.h
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34 
35 #ifndef SOC_XBAR_AM263X_H_
36 #define SOC_XBAR_AM263X_H_
37 
38 //*****************************************************************************
39 //
40 // If building with a C++ compiler, make all of the definitions in this header
41 // have a C binding.
42 //
43 //*****************************************************************************
44 #ifdef __cplusplus
45 extern "C"
46 {
47 #endif
48 
58 #include <stdbool.h>
59 #include <stdint.h>
60 #include <drivers/hw_include/hw_types.h>
61 #include <drivers/hw_include/cslr_soc.h>
62 #include <kernel/dpl/DebugP.h>
63 
64 #define CSL_CONTROLSS_INPUTXBAR_STEP (CSL_CONTROLSS_INPUTXBAR_INPUTXBAR1_GSEL - CSL_CONTROLSS_INPUTXBAR_INPUTXBAR0_GSEL)
65 #define CSL_CONTROLSS_PWMXBAR_STEP (CSL_CONTROLSS_PWMXBAR_PWMXBAR1_G0 - CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G0)
66 #define CSL_CONTROLSS_MDLXBAR_STEP (CSL_CONTROLSS_MDLXBAR_MDLXBAR1_G0 - CSL_CONTROLSS_MDLXBAR_MDLXBAR0_G0)
67 #define CSL_CONTROLSS_ICLXBAR_STEP (CSL_CONTROLSS_ICLXBAR_ICLXBAR1_G0 - CSL_CONTROLSS_ICLXBAR_ICLXBAR0_G0)
68 #define CSL_CONTROLSS_INTXBAR_STEP (CSL_CONTROLSS_INTXBAR_INTXBAR1_G0 - CSL_CONTROLSS_INTXBAR_INTXBAR0_G0)
69 #define CSL_CONTROLSS_DMAXBAR_STEP (CSL_CONTROLSS_DMAXBAR_DMAXBAR1_GSEL - CSL_CONTROLSS_DMAXBAR_DMAXBAR0_GSEL)
70 #define CSL_CONTROLSS_OUTPUTXBAR_STEP (CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR1_G0 - CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G0)
71 #define CSL_CONTROLSS_PWMSYNCOUTXBAR_STEP (CSL_CONTROLSS_PWMSYNCOUTXBAR_PWMSYNCOUTXBAR1_G0 - CSL_CONTROLSS_PWMSYNCOUTXBAR_PWMSYNCOUTXBAR0_G0)
72 
83 static inline void
84 SOC_xbarSelectInputXBarInputSource(uint32_t base, uint8_t out, uint8_t group_select, uint8_t group0_muxctl, uint8_t group1_muxctl)
85 {
86  HW_WR_REG32(base + CSL_CONTROLSS_INPUTXBAR_INPUTXBAR0_GSEL + ((uint32_t)out * CSL_CONTROLSS_INPUTXBAR_STEP), (uint32_t)group_select & CSL_CONTROLSS_INPUTXBAR_INPUTXBAR0_GSEL_GSEL_MASK);
87  HW_WR_REG32(base + CSL_CONTROLSS_INPUTXBAR_INPUTXBAR0_G0 + ((uint32_t)out * CSL_CONTROLSS_INPUTXBAR_STEP), (uint32_t)group0_muxctl & CSL_CONTROLSS_INPUTXBAR_INPUTXBAR0_G0_SEL_MASK);
88  HW_WR_REG32(base + CSL_CONTROLSS_INPUTXBAR_INPUTXBAR0_G1 + ((uint32_t)out * CSL_CONTROLSS_INPUTXBAR_STEP), (uint32_t)group1_muxctl & CSL_CONTROLSS_INPUTXBAR_INPUTXBAR0_G1_SEL_MASK);
89 
90 }
91 
99 static inline uint32_t
100 SOC_xbarGetPWMXBarOutputSignalStatus(uint32_t base)
101 {
102  return(HW_RD_REG32(base + CSL_CONTROLSS_PWMXBAR_PWMXBAR_STATUS) & CSL_CONTROLSS_PWMXBAR_PWMXBAR_STATUS_STS_MASK);
103 }
104 
112 static inline void
113 SOC_xbarInvertPWMXBarOutputSignalBeforeLatch(uint32_t base, uint32_t invert_mask)
114 {
115  HW_WR_REG32(base + CSL_CONTROLSS_PWMXBAR_PWMXBAR_FLAGINVERT, invert_mask & CSL_CONTROLSS_PWMXBAR_PWMXBAR_FLAGINVERT_INVERT_MASK);
116 }
117 
125 static inline uint32_t
126 SOC_xbarGetPWMXBarOutputSignalLatchedFlag(uint32_t base)
127 {
128  return(HW_RD_REG32(base + CSL_CONTROLSS_PWMXBAR_PWMXBAR_FLAG));
129 }
130 
138 static inline void
139 SOC_xbarClearPWMXBarOutputSignalLatchedFlag(uint32_t base, uint32_t clr)
140 {
141  HW_WR_REG32(base + CSL_CONTROLSS_PWMXBAR_PWMXBAR_FLAG_CLR, clr);
142 }
143 
160 static inline void
161 SOC_xbarSelectPWMXBarInputSource(uint32_t base, uint8_t out, uint32_t group0_mask, uint32_t group1_mask, uint32_t group2_mask, uint32_t group3_mask, uint32_t group4_mask, uint32_t group5_mask, uint32_t group6_mask, uint32_t group7_mask, uint32_t group8_mask)
162 {
163  HW_WR_REG32(base + (out*CSL_CONTROLSS_PWMXBAR_STEP) + CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G0, group0_mask & CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G0_SEL_MASK);
164  HW_WR_REG32(base + (out*CSL_CONTROLSS_PWMXBAR_STEP) + CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G1, group1_mask & CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G1_SEL_MASK);
165  HW_WR_REG32(base + (out*CSL_CONTROLSS_PWMXBAR_STEP) + CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G2, group2_mask & CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G2_SEL_MASK);
166  HW_WR_REG32(base + (out*CSL_CONTROLSS_PWMXBAR_STEP) + CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G3, group3_mask & CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G3_SEL_MASK);
167  HW_WR_REG32(base + (out*CSL_CONTROLSS_PWMXBAR_STEP) + CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G4, group4_mask & CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G4_SEL_MASK);
168  HW_WR_REG32(base + (out*CSL_CONTROLSS_PWMXBAR_STEP) + CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G5, group5_mask & CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G5_SEL_MASK);
169  HW_WR_REG32(base + (out*CSL_CONTROLSS_PWMXBAR_STEP) + CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G6, group6_mask & CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G6_SEL_MASK);
170  HW_WR_REG32(base + (out*CSL_CONTROLSS_PWMXBAR_STEP) + CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G7, group7_mask & CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G7_SEL_MASK);
171  HW_WR_REG32(base + (out*CSL_CONTROLSS_PWMXBAR_STEP) + CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G8, group8_mask & CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G8_SEL_MASK);
172 }
173 
184 static inline void
185 SOC_xbarSelectMinimumDeadBandLogicXBarInputSource(uint32_t base, uint8_t out, uint32_t group0_mask, uint32_t group1_mask, uint32_t group2_mask)
186 {
187  //TBD: 32 bit field required?
188  HW_WR_REG32(base + (out*CSL_CONTROLSS_MDLXBAR_STEP) + CSL_CONTROLSS_MDLXBAR_MDLXBAR0_G0, group0_mask & CSL_CONTROLSS_MDLXBAR_MDLXBAR0_G0_SEL_MASK);
189  HW_WR_REG32(base + (out*CSL_CONTROLSS_MDLXBAR_STEP) + CSL_CONTROLSS_MDLXBAR_MDLXBAR0_G1, group1_mask & CSL_CONTROLSS_MDLXBAR_MDLXBAR0_G1_SEL_MASK);
190  HW_WR_REG32(base + (out*CSL_CONTROLSS_MDLXBAR_STEP) + CSL_CONTROLSS_MDLXBAR_MDLXBAR0_G2, group2_mask & CSL_CONTROLSS_MDLXBAR_MDLXBAR0_G2_SEL_MASK);
191 }
192 
203 static inline void
204 SOC_xbarSelectIllegalComboLogicXBarInputSource(uint32_t base, uint8_t out, uint32_t group0_mask, uint32_t group1_mask, uint32_t group2_mask)
205 {
206  //TBD: 32 bit field required?
207  HW_WR_REG32(base + (out*CSL_CONTROLSS_ICLXBAR_STEP) + CSL_CONTROLSS_ICLXBAR_ICLXBAR0_G0, group0_mask & CSL_CONTROLSS_ICLXBAR_ICLXBAR0_G0_SEL_MASK);
208  HW_WR_REG32(base + (out*CSL_CONTROLSS_ICLXBAR_STEP) + CSL_CONTROLSS_ICLXBAR_ICLXBAR0_G1, group1_mask & CSL_CONTROLSS_ICLXBAR_ICLXBAR0_G1_SEL_MASK);
209  HW_WR_REG32(base + (out*CSL_CONTROLSS_ICLXBAR_STEP) + CSL_CONTROLSS_ICLXBAR_ICLXBAR0_G2, group2_mask & CSL_CONTROLSS_ICLXBAR_ICLXBAR0_G2_SEL_MASK);
210 }
211 
226 static inline void
227 SOC_xbarSelectInterruptXBarInputSource(uint32_t base, uint8_t out, uint32_t group0_mask, uint32_t group1_mask, uint32_t group2_mask, uint32_t group3_mask, uint32_t group4_mask, uint32_t group5_mask, uint32_t group6_mask)
228 {
229  //TBD: 32 bit field required?
230  HW_WR_REG32(base + (out*CSL_CONTROLSS_INTXBAR_STEP) + CSL_CONTROLSS_INTXBAR_INTXBAR0_G0, group0_mask & CSL_CONTROLSS_INTXBAR_INTXBAR0_G0_SEL_MASK);
231  HW_WR_REG32(base + (out*CSL_CONTROLSS_INTXBAR_STEP) + CSL_CONTROLSS_INTXBAR_INTXBAR0_G1, group1_mask & CSL_CONTROLSS_INTXBAR_INTXBAR0_G1_SEL_MASK);
232  HW_WR_REG32(base + (out*CSL_CONTROLSS_INTXBAR_STEP) + CSL_CONTROLSS_INTXBAR_INTXBAR0_G2, group2_mask & CSL_CONTROLSS_INTXBAR_INTXBAR0_G2_SEL_MASK);
233  HW_WR_REG32(base + (out*CSL_CONTROLSS_INTXBAR_STEP) + CSL_CONTROLSS_INTXBAR_INTXBAR0_G3, group3_mask & CSL_CONTROLSS_INTXBAR_INTXBAR0_G3_SEL_MASK);
234  HW_WR_REG32(base + (out*CSL_CONTROLSS_INTXBAR_STEP) + CSL_CONTROLSS_INTXBAR_INTXBAR0_G4, group4_mask & CSL_CONTROLSS_INTXBAR_INTXBAR0_G4_SEL_MASK);
235  HW_WR_REG32(base + (out*CSL_CONTROLSS_INTXBAR_STEP) + CSL_CONTROLSS_INTXBAR_INTXBAR0_G5, group5_mask & CSL_CONTROLSS_INTXBAR_INTXBAR0_G5_SEL_MASK);
236  HW_WR_REG32(base + (out*CSL_CONTROLSS_INTXBAR_STEP) + CSL_CONTROLSS_INTXBAR_INTXBAR0_G6, group6_mask & CSL_CONTROLSS_INTXBAR_INTXBAR0_G6_SEL_MASK);
237 }
238 
253 static inline void
254 SOC_xbarSelectDMAXBarInputSource(uint32_t base, uint8_t out, uint8_t group_select, uint8_t group0_muxctl, uint8_t group1_muxctl, uint8_t group2_muxctl, uint8_t group3_muxctl, uint8_t group4_muxctl, uint8_t group5_muxctl)
255 {
256  HW_WR_REG32(base + ((uint32_t)out*CSL_CONTROLSS_DMAXBAR_STEP) + CSL_CONTROLSS_DMAXBAR_DMAXBAR0_GSEL , (uint32_t)group_select & CSL_CONTROLSS_DMAXBAR_DMAXBAR0_GSEL_GSEL_MASK);
257  HW_WR_REG32(base + ((uint32_t)out*CSL_CONTROLSS_DMAXBAR_STEP) + CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G0 , (uint32_t)group0_muxctl & CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G0_SEL_MASK);
258  HW_WR_REG32(base + ((uint32_t)out*CSL_CONTROLSS_DMAXBAR_STEP) + CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G1 , (uint32_t)group1_muxctl & CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G1_SEL_MASK);
259  HW_WR_REG32(base + ((uint32_t)out*CSL_CONTROLSS_DMAXBAR_STEP) + CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G2 , (uint32_t)group2_muxctl & CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G2_SEL_MASK);
260  HW_WR_REG32(base + ((uint32_t)out*CSL_CONTROLSS_DMAXBAR_STEP) + CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G3 , (uint32_t)group3_muxctl & CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G3_SEL_MASK);
261  HW_WR_REG32(base + ((uint32_t)out*CSL_CONTROLSS_DMAXBAR_STEP) + CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G4 , (uint32_t)group4_muxctl & CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G4_SEL_MASK);
262  HW_WR_REG32(base + ((uint32_t)out*CSL_CONTROLSS_DMAXBAR_STEP) + CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G5 , (uint32_t)group5_muxctl & CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G5_SEL_MASK);
263 
264 }
265 
273 static inline uint32_t
274 SOC_xbarGetOutputXBarOutputSignalStatus(uint32_t base)
275 {
276  return(HW_RD_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_STATUS)& CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_STATUS_STS_MASK);
277 }
278 
286 static inline void
287 SOC_xbarInvertOutputXBarOutputSignalBeforeLatch(uint32_t base, uint32_t invert)
288 {
289  HW_WR_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_FLAGINVERT, invert & CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_FLAGINVERT_INVERT_MASK);
290 }
291 
299 static inline uint32_t
300 SOC_xbarGetOutputXBarOutputSignalLatchedFlag(uint32_t base)
301 {
302  return(HW_RD_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_FLAG));
303 }
304 
312 static inline void
313 SOC_xbarClearOutputXBarOutputSignalLatchedFlag(uint32_t base, uint32_t clr)
314 {
315  HW_WR_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_FLAG_CLR, clr);
316 }
317 
325 static inline void
326 SOC_xbarForceOutputXBarOutputSignalLatchedFlag(uint32_t base, uint32_t force)
327 {
328  HW_WR_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_FLAGFORCE, force & CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_FLAGFORCE_FRC_MASK);
329 }
330 
338 static inline void
339 SOC_xbarSelectLatchOutputXBarOutputSignal(uint32_t base, uint32_t latchselect)
340 {
341  HW_WR_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_OUTLATCH, latchselect & CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_OUTLATCH_LATCHSEL_MASK);
342 }
343 
351 static inline void
352 SOC_xbarSelectStretchedPulseOutputXBarOutputSignal(uint32_t base, uint32_t stretchselect)
353 {
354  HW_WR_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_OUTSTRETCH, stretchselect & CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_OUTSTRETCH_STRETCHSEL_MASK);
355 }
356 
364 static inline void
365 SOC_xbarSelectStretchedPulseLengthOutputXBarOutputSignal(uint32_t base, uint32_t lengthselect)
366 {
367  HW_WR_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_OUTLENGTH, lengthselect & CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_OUTLENGTH_LENGTHSEL_MASK);
368 }
369 
377 static inline void
378 SOC_xbarInvertOutputXBarOutputSignal(uint32_t base, uint32_t invertout)
379 {
380  HW_WR_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_OUTINVERT, invertout & CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_OUTINVERT_OUTINVERT_MASK);
381 }
382 
401 static inline void
402 SOC_xbarSelectOutputXBarInputSource(uint32_t base, uint8_t out, uint32_t group0_mask, uint32_t group1_mask, uint32_t group2_mask, uint32_t group3_mask, uint32_t group4_mask, uint32_t group5_mask, uint32_t group6_mask, uint32_t group7_mask, uint32_t group8_mask, uint32_t group9_mask, uint32_t group10_mask)
403 {
404  HW_WR_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G0 + (out * CSL_CONTROLSS_OUTPUTXBAR_STEP), group0_mask & CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G0_SEL_MASK);
405  HW_WR_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G1 + (out * CSL_CONTROLSS_OUTPUTXBAR_STEP), group1_mask & CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G1_SEL_MASK);
406  HW_WR_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G2 + (out * CSL_CONTROLSS_OUTPUTXBAR_STEP), group2_mask & CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G2_SEL_MASK);
407  HW_WR_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G3 + (out * CSL_CONTROLSS_OUTPUTXBAR_STEP), group3_mask & CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G3_SEL_MASK);
408  HW_WR_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G4 + (out * CSL_CONTROLSS_OUTPUTXBAR_STEP), group4_mask & CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G4_SEL_MASK);
409  HW_WR_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G5 + (out * CSL_CONTROLSS_OUTPUTXBAR_STEP), group5_mask & CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G5_SEL_MASK);
410  HW_WR_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G6 + (out * CSL_CONTROLSS_OUTPUTXBAR_STEP), group6_mask & CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G6_SEL_MASK);
411  HW_WR_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G7 + (out * CSL_CONTROLSS_OUTPUTXBAR_STEP), group7_mask & CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G7_SEL_MASK);
412  HW_WR_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G8 + (out * CSL_CONTROLSS_OUTPUTXBAR_STEP), group8_mask & CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G8_SEL_MASK);
413  HW_WR_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G9 + (out * CSL_CONTROLSS_OUTPUTXBAR_STEP), group9_mask & CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G9_SEL_MASK);
414  HW_WR_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G10 + (out * CSL_CONTROLSS_OUTPUTXBAR_STEP), group10_mask & CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G10_SEL_MASK);
415 }
416 
425 static inline void
426 SOC_xbarSelectPWMSyncOutXBarInput(uint32_t base, uint8_t out, uint32_t input)
427 {
428  //TBD: 32 bit field for selecting 32 inputs
429  HW_WR_REG32(base + CSL_CONTROLSS_PWMSYNCOUTXBAR_PWMSYNCOUTXBAR0_G0 + (out * CSL_CONTROLSS_PWMSYNCOUTXBAR_STEP), input & CSL_CONTROLSS_PWMSYNCOUTXBAR_PWMSYNCOUTXBAR0_G0_SEL_MASK);
430 }
431 
432 
433 
442 static inline void
443 SOC_xbarSelectEdmaTrigXbarInputSource(uint32_t base, uint8_t out, uint8_t mux_control)
444 {
445  HW_WR_REG32(base + CSL_EDMA_TRIG_XBAR_MUXCNTL(out), (CSL_EDMA_TRIG_XBAR_MUXCNTL_INT_ENABLE_MASK) | (mux_control & CSL_EDMA_TRIG_XBAR_MUXCNTL_ENABLE_MASK));
446 }
447 
456 static inline void
457 SOC_xbarSelectGpioIntrXbarInputSource(uint32_t base, uint8_t out, uint8_t mux_control)
458 {
459  HW_WR_REG32(base + CSL_GPIO_INTR_XBAR_MUXCNTL(out), (CSL_GPIO_INTR_XBAR_MUXCNTL_INT_ENABLE_MASK) | (mux_control & CSL_GPIO_INTR_XBAR_MUXCNTL_ENABLE_MASK));
460 }
461 
470 static inline void
471 SOC_xbarSelectIcssmIntrXbarInputSource(uint32_t base, uint8_t out, uint8_t mux_control)
472 {
473  HW_WR_REG32(base + CSL_ICSSM_INTR_XBAR_MUXCNTL(out), (CSL_ICSSM_INTR_XBAR_MUXCNTL_INT_ENABLE_MASK) | (mux_control & CSL_ICSSM_INTR_XBAR_MUXCNTL_ENABLE_MASK));
474 }
475 
484 static inline void
485 SOC_xbarSelectTimesyncXbar0InputSource(uint32_t base, uint8_t out, uint8_t mux_control)
486 {
487  HW_WR_REG32(base + CSL_SOC_TIMESYNC_XBAR0_MUXCNTL(out), (CSL_SOC_TIMESYNC_XBAR0_MUXCNTL_INT_ENABLE_MASK) | (mux_control & CSL_SOC_TIMESYNC_XBAR0_MUXCNTL_ENABLE_MASK));
488 }
489 
498 static inline void
499 SOC_xbarSelectTimesyncXbar1InputSource(uint32_t base, uint8_t out, uint8_t mux_control)
500 {
501  HW_WR_REG32(base + CSL_SOC_TIMESYNC_XBAR1_MUXCNTL(out), (CSL_SOC_TIMESYNC_XBAR1_MUXCNTL_INT_ENABLE_MASK) | (mux_control & CSL_SOC_TIMESYNC_XBAR1_MUXCNTL_ENABLE_MASK));
502 }
503 
506 #ifdef __cplusplus
507 }
508 #endif
509 
510 #endif // SOC_XBAR_AM263X_H_
CSL_CONTROLSS_PWMSYNCOUTXBAR_STEP
#define CSL_CONTROLSS_PWMSYNCOUTXBAR_STEP
Definition: soc_xbar.h:71
SOC_xbarSelectEdmaTrigXbarInputSource
static void SOC_xbarSelectEdmaTrigXbarInputSource(uint32_t base, uint8_t out, uint8_t mux_control)
SoC level xbars: API to select input source of EDMA Trigger XBar.
Definition: soc_xbar.h:443
SOC_xbarInvertOutputXBarOutputSignalBeforeLatch
static void SOC_xbarInvertOutputXBarOutputSignalBeforeLatch(uint32_t base, uint32_t invert)
Trip & Sync xbar: API to configure inversion of output signal status flag (latched) of Output XBars.
Definition: soc_xbar.h:287
SOC_xbarSelectInterruptXBarInputSource
static void SOC_xbarSelectInterruptXBarInputSource(uint32_t base, uint8_t out, uint32_t group0_mask, uint32_t group1_mask, uint32_t group2_mask, uint32_t group3_mask, uint32_t group4_mask, uint32_t group5_mask, uint32_t group6_mask)
Trip & Sync xbar: API to select input sources of Interrupt XBar.
Definition: soc_xbar.h:227
SOC_xbarSelectMinimumDeadBandLogicXBarInputSource
static void SOC_xbarSelectMinimumDeadBandLogicXBarInputSource(uint32_t base, uint8_t out, uint32_t group0_mask, uint32_t group1_mask, uint32_t group2_mask)
Trip & Sync xbar: API to select input sources of MDL XBar.
Definition: soc_xbar.h:185
SOC_xbarSelectPWMSyncOutXBarInput
static void SOC_xbarSelectPWMSyncOutXBarInput(uint32_t base, uint8_t out, uint32_t input)
Trip & Sync xbar: API to select input sources of PWM Syncout XBar.
Definition: soc_xbar.h:426
CSL_CONTROLSS_INTXBAR_STEP
#define CSL_CONTROLSS_INTXBAR_STEP
Definition: soc_xbar.h:68
SOC_xbarGetOutputXBarOutputSignalLatchedFlag
static uint32_t SOC_xbarGetOutputXBarOutputSignalLatchedFlag(uint32_t base)
Trip & Sync xbar: API to read latched output signal status of all Output XBars.
Definition: soc_xbar.h:300
CSL_CONTROLSS_OUTPUTXBAR_STEP
#define CSL_CONTROLSS_OUTPUTXBAR_STEP
Definition: soc_xbar.h:70
SOC_xbarSelectStretchedPulseLengthOutputXBarOutputSignal
static void SOC_xbarSelectStretchedPulseLengthOutputXBarOutputSignal(uint32_t base, uint32_t lengthselect)
Trip & Sync xbar: API to configure pulse streching length of output of Output XBars.
Definition: soc_xbar.h:365
SOC_xbarSelectGpioIntrXbarInputSource
static void SOC_xbarSelectGpioIntrXbarInputSource(uint32_t base, uint8_t out, uint8_t mux_control)
SoC level xbars: API to select input source of GPIO Interrupt XBar.
Definition: soc_xbar.h:457
SOC_xbarSelectIllegalComboLogicXBarInputSource
static void SOC_xbarSelectIllegalComboLogicXBarInputSource(uint32_t base, uint8_t out, uint32_t group0_mask, uint32_t group1_mask, uint32_t group2_mask)
Trip & Sync xbar: API to select input sources of ICL XBar.
Definition: soc_xbar.h:204
SOC_xbarSelectLatchOutputXBarOutputSignal
static void SOC_xbarSelectLatchOutputXBarOutputSignal(uint32_t base, uint32_t latchselect)
Trip & Sync xbar: API to select output of Output XBars.
Definition: soc_xbar.h:339
CSL_CONTROLSS_PWMXBAR_STEP
#define CSL_CONTROLSS_PWMXBAR_STEP
Definition: soc_xbar.h:65
CSL_CONTROLSS_MDLXBAR_STEP
#define CSL_CONTROLSS_MDLXBAR_STEP
Definition: soc_xbar.h:66
SOC_xbarInvertOutputXBarOutputSignal
static void SOC_xbarInvertOutputXBarOutputSignal(uint32_t base, uint32_t invertout)
Trip & Sync xbar: API to configure inversion of output signal of Output XBars.
Definition: soc_xbar.h:378
CSL_CONTROLSS_DMAXBAR_STEP
#define CSL_CONTROLSS_DMAXBAR_STEP
Definition: soc_xbar.h:69
SOC_xbarClearOutputXBarOutputSignalLatchedFlag
static void SOC_xbarClearOutputXBarOutputSignalLatchedFlag(uint32_t base, uint32_t clr)
Trip & Sync xbar: API to clear output signal status flag (latched) of Output XBars.
Definition: soc_xbar.h:313
SOC_xbarSelectTimesyncXbar0InputSource
static void SOC_xbarSelectTimesyncXbar0InputSource(uint32_t base, uint8_t out, uint8_t mux_control)
SoC level xbars: API to select input source of TimeSync XBar0.
Definition: soc_xbar.h:485
SOC_xbarSelectTimesyncXbar1InputSource
static void SOC_xbarSelectTimesyncXbar1InputSource(uint32_t base, uint8_t out, uint8_t mux_control)
SoC level xbars: API to select input source of TimeSync XBar1.
Definition: soc_xbar.h:499
SOC_xbarSelectPWMXBarInputSource
static void SOC_xbarSelectPWMXBarInputSource(uint32_t base, uint8_t out, uint32_t group0_mask, uint32_t group1_mask, uint32_t group2_mask, uint32_t group3_mask, uint32_t group4_mask, uint32_t group5_mask, uint32_t group6_mask, uint32_t group7_mask, uint32_t group8_mask)
Trip & Sync xbar: API to select input sources of PWM XBar.
Definition: soc_xbar.h:161
SOC_xbarSelectInputXBarInputSource
static void SOC_xbarSelectInputXBarInputSource(uint32_t base, uint8_t out, uint8_t group_select, uint8_t group0_muxctl, uint8_t group1_muxctl)
Trip & Sync xbar: API to select input source of Input XBar.
Definition: soc_xbar.h:84
SOC_xbarSelectOutputXBarInputSource
static void SOC_xbarSelectOutputXBarInputSource(uint32_t base, uint8_t out, uint32_t group0_mask, uint32_t group1_mask, uint32_t group2_mask, uint32_t group3_mask, uint32_t group4_mask, uint32_t group5_mask, uint32_t group6_mask, uint32_t group7_mask, uint32_t group8_mask, uint32_t group9_mask, uint32_t group10_mask)
Trip & Sync xbar: API to select input sources of Output XBar.
Definition: soc_xbar.h:402
SOC_xbarInvertPWMXBarOutputSignalBeforeLatch
static void SOC_xbarInvertPWMXBarOutputSignalBeforeLatch(uint32_t base, uint32_t invert_mask)
Trip & Sync xbar: API to configure inversion of output signal status flag (latched) of PWM XBars.
Definition: soc_xbar.h:113
DebugP.h
SOC_xbarSelectDMAXBarInputSource
static void SOC_xbarSelectDMAXBarInputSource(uint32_t base, uint8_t out, uint8_t group_select, uint8_t group0_muxctl, uint8_t group1_muxctl, uint8_t group2_muxctl, uint8_t group3_muxctl, uint8_t group4_muxctl, uint8_t group5_muxctl)
Trip & Sync xbar: API to select input source of DMA XBar.
Definition: soc_xbar.h:254
CSL_CONTROLSS_ICLXBAR_STEP
#define CSL_CONTROLSS_ICLXBAR_STEP
Definition: soc_xbar.h:67
SOC_xbarGetOutputXBarOutputSignalStatus
static uint32_t SOC_xbarGetOutputXBarOutputSignalStatus(uint32_t base)
Trip & Sync xbar: API to read raw output signal status of all Output XBars.
Definition: soc_xbar.h:274
SOC_xbarForceOutputXBarOutputSignalLatchedFlag
static void SOC_xbarForceOutputXBarOutputSignalLatchedFlag(uint32_t base, uint32_t force)
Trip & Sync xbar: API to force output signal status flag (latched) of Output XBars.
Definition: soc_xbar.h:326
SOC_xbarSelectStretchedPulseOutputXBarOutputSignal
static void SOC_xbarSelectStretchedPulseOutputXBarOutputSignal(uint32_t base, uint32_t stretchselect)
Trip & Sync xbar: API to enable pulse stretching of output of Output XBars.
Definition: soc_xbar.h:352
SOC_xbarGetPWMXBarOutputSignalStatus
static uint32_t SOC_xbarGetPWMXBarOutputSignalStatus(uint32_t base)
Trip & Sync xbar: API to read raw output signal status of all PWM XBars.
Definition: soc_xbar.h:100
SOC_xbarClearPWMXBarOutputSignalLatchedFlag
static void SOC_xbarClearPWMXBarOutputSignalLatchedFlag(uint32_t base, uint32_t clr)
Trip & Sync xbar: API to clear output signal status flag (latched) of PWM XBars.
Definition: soc_xbar.h:139
CSL_CONTROLSS_INPUTXBAR_STEP
#define CSL_CONTROLSS_INPUTXBAR_STEP
Definition: soc_xbar.h:64
SOC_xbarSelectIcssmIntrXbarInputSource
static void SOC_xbarSelectIcssmIntrXbarInputSource(uint32_t base, uint8_t out, uint8_t mux_control)
SoC level xbars: API to select input source of ICSSM Interrupt XBar.
Definition: soc_xbar.h:471
SOC_xbarGetPWMXBarOutputSignalLatchedFlag
static uint32_t SOC_xbarGetPWMXBarOutputSignalLatchedFlag(uint32_t base)
Trip & Sync xbar: API to read latched output signal status of all PWM XBars.
Definition: soc_xbar.h:126