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AM263x MCU+ SDK
09.02.00
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Go to the documentation of this file.
32 #ifndef SIPC_NOTIFY_CFG_H_
33 #define SIPC_NOTIFY_CFG_H_
40 #include <drivers/hw_include/am263x/cslr_soc.h>
46 #define SIPC_MSG_SIZE (13u)
49 #define INTR_CFG_NUM_MAX (1u)
57 #define HSM_SOC_CTRL_U_BASE (0x40000000U)
58 #define HSM_SOC_CTRL_HSM_MBOX_READ_DONE_ACK (0x00000048U)
59 #define HSM_SOC_CTRL_HSM_MBOX_READ_DONE (0x0000004CU)
65 #define R5FSS0_0_MBOX_READ_DONE_ACK (CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_R5SS0_CORE0_MBOX_READ_DONE_ACK)
66 #define R5FSS0_0_MBOX_READ_DONE (CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_R5SS0_CORE0_MBOX_READ_DONE)
67 #define R5FSS0_1_MBOX_READ_DONE_ACK (CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_R5SS0_CORE1_MBOX_READ_DONE_ACK)
68 #define R5FSS0_1_MBOX_READ_DONE (CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_R5SS0_CORE1_MBOX_READ_DONE)
69 #define R5FSS1_0_MBOX_READ_DONE_ACK (CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_R5SS1_CORE0_MBOX_READ_DONE_ACK)
70 #define R5FSS1_0_MBOX_READ_DONE (CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_R5SS1_CORE0_MBOX_READ_DONE)
71 #define R5FSS1_1_MBOX_READ_DONE_ACK (CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_R5SS1_CORE1_MBOX_READ_DONE_ACK)
72 #define R5FSS1_1_MBOX_READ_DONE (CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_R5SS1_CORE1_MBOX_READ_DONE)
75 #define HSM0_0_MBOX_READ_DONE_ACK (HSM_SOC_CTRL_U_BASE + HSM_SOC_CTRL_HSM_MBOX_READ_DONE_ACK)
76 #define HSM0_0_MBOX_READ_DONE (HSM_SOC_CTRL_U_BASE + HSM_SOC_CTRL_HSM_MBOX_READ_DONE)
80 #define R5FSS0_0_MBOX_WRITE_PROC_BIT_POS ( 0U)
81 #define R5FSS0_1_MBOX_WRITE_PROC_BIT_POS ( 4U)
82 #define R5FSS1_0_MBOX_WRITE_PROC_BIT_POS ( 8U)
83 #define R5FSS1_1_MBOX_WRITE_PROC_BIT_POS ( 12U)
86 #define HSM0_0_MBOX_WRITE_PROC_BIT_POS ( 6U)
89 #define R5FSS0_0_MBOX_READ_PROC_BIT_POS ( 0U)
90 #define R5FSS0_1_MBOX_READ_PROC_BIT_POS ( 4U)
91 #define R5FSS1_0_MBOX_READ_PROC_BIT_POS ( 8U)
92 #define R5FSS1_1_MBOX_READ_PROC_BIT_POS (12U)
93 #define HSM0_0_MBOX_READ_PROC_BIT_POS (24U)
96 #define R5FSS0_0_MBOX_READ_ACK_INTR ( 137U)
97 #define R5FSS0_1_MBOX_READ_ACK_INTR ( 137U)
98 #define R5FSS1_0_MBOX_READ_ACK_INTR ( 137U)
99 #define R5FSS1_1_MBOX_READ_ACK_INTR ( 137U)
100 #define HSM0_0_MBOX_READ_ACK_INTR ( 56U )
107 typedef enum SIPC_CoreId_
123 typedef enum SIPC_SecCoreId_
131 #if defined(__ARM_ARCH_7R__)
134 static uint32_t SIPC_readSelfCoreID(
void)
144 #define SELF_CORE_ID (SIPC_readSelfCoreID())
152 #define SIPC_CLIENT_ID_MAX (5U)
155 #define SIPC_CLIENT_ID_MAX (2U)
156 #define SELF_CORE_ID (CORE_ID_HSM0_0)
162 #define SIPC_BOOT_NOTIFY_CLIENT_ID (0U)
SIPC_SecCoreId
Secure host Id to identify different secure hosts. Max number of secure host on AM263x is 2.
Definition: sipc_notify_cfg.h:124
@ CORE_INDEX_SEC_MASTER_1
Definition: sipc_notify_cfg.h:126
@ CORE_ID_R5FSS1_1
Definition: sipc_notify_cfg.h:112
@ CORE_INDEX_HSM
Definition: sipc_notify_cfg.h:127
uint32_t grpId
Definition: CpuIdP.h:62
@ CORE_ID_MAX
Definition: sipc_notify_cfg.h:114
@ CORE_ID_R5FSS1_0
Definition: sipc_notify_cfg.h:111
Structure containing the CPU Info such as CPU ID and Cluster Group ID.
Definition: CpuIdP.h:57
@ CORE_ID_R5FSS0_0
Definition: sipc_notify_cfg.h:109
@ CORE_ID_HSM0_0
Definition: sipc_notify_cfg.h:113
SIPC_coreId
Core Ids to identify different cores.
Definition: sipc_notify_cfg.h:108
@ MAX_SEC_CORES_WITH_HSM
Definition: sipc_notify_cfg.h:128
@ CORE_INDEX_SEC_MASTER_0
Definition: sipc_notify_cfg.h:125
uint32_t cpuID
Definition: CpuIdP.h:58
void CSL_armR5GetCpuID(CSL_ArmR5CPUInfo *cpuInfo)
Get the cluster group and CPU ID for current R5 Core.
@ CORE_ID_R5FSS0_1
Definition: sipc_notify_cfg.h:110