AM263x MCU+ SDK  11.00.00
enetphy.h
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1 /*
2  * Copyright (c) Texas Instruments Incorporated 2020
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
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10  *
11  * Redistributions in binary form must reproduce the above copyright
12  * notice, this list of conditions and the following disclaimer in the
13  * documentation and/or other materials provided with the
14  * distribution.
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18  * from this software without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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23  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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25  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  */
32 
61 #ifndef ENETPHY_H_
62 #define ENETPHY_H_
63 
64 /* ========================================================================== */
65 /* Include Files */
66 /* ========================================================================== */
67 
68 #include <stdint.h>
69 #include <stdbool.h>
70 #include "phy_common.h"
71 
72 #ifdef __cplusplus
73 extern "C" {
74 #endif
75 
76 /* ========================================================================== */
77 /* Macros */
78 /* ========================================================================== */
79 
81 #define ENETPHY_IS_ADDR_VALID(addr) ((addr) <= 31U)
82 
84 #define ENETPHY_BIT(n) (1U << (n))
85 
87 #define ENETPHY_IS_BIT_SET(val, n) (((val) & ENETPHY_BIT(n)) != 0U)
88 
90 #define ENETPHY_ARRAYSIZE(x) (sizeof(x) / sizeof(x[0]))
91 
101 /* Ethernet PHY driver error codes are same as CSL's to maintain consistency */
102 
104 #define ENETPHY_SOK (CSL_PASS)
105 
107 #define ENETPHY_EFAIL (CSL_EFAIL)
108 
110 #define ENETPHY_EBADARGS (CSL_EBADARGS)
111 
113 #define ENETPHY_EINVALIDPARAMS (CSL_EINVALID_PARAMS)
114 
116 #define ENETPHY_ETIMEOUT (CSL_ETIMEOUT)
117 
119 #define ENETPHY_EALLOC (CSL_EALLOC)
120 
122 #define ENETPHY_EPERM (CSL_EALLOC - 4)
123 
125 #define ENETPHY_ENOTSUPPORTED (CSL_EALLOC - 5)
126 
128 #define ENETPHY_EUNAVAILABLE (CSL_EALLOC - 6)
129 
142 #define ENETPHY_LINK_CAP_HD10 ENETPHY_BIT(1)
143 
145 #define ENETPHY_LINK_CAP_FD10 ENETPHY_BIT(2)
146 
148 #define ENETPHY_LINK_CAP_HD100 ENETPHY_BIT(3)
149 
151 #define ENETPHY_LINK_CAP_FD100 ENETPHY_BIT(4)
152 
154 #define ENETPHY_LINK_CAP_HD1000 ENETPHY_BIT(5)
155 
157 #define ENETPHY_LINK_CAP_FD1000 ENETPHY_BIT(6)
158 
160 #define ENETPHY_LINK_CAP_10 (ENETPHY_LINK_CAP_HD10 | \
161  ENETPHY_LINK_CAP_FD10)
162 
164 #define ENETPHY_LINK_CAP_100 (ENETPHY_LINK_CAP_HD100 | \
165  ENETPHY_LINK_CAP_FD100)
166 
168 #define ENETPHY_LINK_CAP_1000 (ENETPHY_LINK_CAP_HD1000 | \
169  ENETPHY_LINK_CAP_FD1000)
170 
172 #define ENETPHY_LINK_CAP_ALL (ENETPHY_LINK_CAP_HD10 | \
173  ENETPHY_LINK_CAP_FD10 | \
174  ENETPHY_LINK_CAP_HD100 | \
175  ENETPHY_LINK_CAP_FD100 | \
176  ENETPHY_LINK_CAP_HD1000 | \
177  ENETPHY_LINK_CAP_FD1000)
178 
182 #define ENETPHY_EXTENDED_CFG_SIZE_MAX (128U)
183 
185 #define ENETPHY_FSM_TICK_PERIOD_MS (100U)
186 
188 #define ENETPHY_INVALID_PHYADDR (~0U)
189 
191 #define ENETPHY_TIMEOUT_WAIT_FOREVER (0xFFFFFFFFU)
192 
194 #define ENETPHY_TIMEOUT_NO_WAIT (0U)
195 
196 /* ========================================================================== */
197 /* Structures and Enums */
198 /* ========================================================================== */
199 
200 typedef struct Mdio_Obj_s Mdio_Obj;
201 
205 typedef enum EnetPhy_Magic_e
206 {
208  ENETPHY_MAGIC = 0xCADACADAU,
209 
212 } EnetPhy_Magic;
213 
217 typedef enum EnetPhy_Mii_e
218 {
221 
224 
227 
230 
233 
236 } EnetPhy_Mii;
237 
241 typedef enum EnetPhy_Speed_e
242 {
245 
248 
251 
254 } EnetPhy_Speed;
255 
259 typedef enum EnetPhy_Duplexity_e
260 {
263 
266 
270 
274 typedef struct EnetPhy_Version_s
275 {
277  uint32_t oui;
278 
280  uint32_t model;
281 
283  uint32_t revision;
285 
289 typedef enum EnetPhy_LinkStatus_e
290 {
293 
296 
299 
303 
307 typedef struct EnetPhy_LinkCfg_s
308 {
311 
315 
319 typedef struct EnetPhy_FsmTimeoutCfg_s
320 {
326 
332 
335 
341 
347 
353 
355  uint32_t mdixTicks;
357 
361 typedef struct EnetPhy_Cfg_s
362 {
364  uint32_t phyGroup;
365 
367  uint32_t phyAddr;
368 
370  uint32_t nwayCaps;
371 
373  bool mdixEn;
374 
379 
382 
385 
388 
391 
394 
397 
399  uint8_t extendedCfg[ENETPHY_EXTENDED_CFG_SIZE_MAX];
400 
402  uint32_t extendedCfgSize;
403 
404 } EnetPhy_Cfg;
405 
409 typedef struct EnetPhy_Mdio_s
410 {
423  int32_t (*isAlive)(uint32_t phyAddr,
424  bool *isAlive,
425  Mdio_Obj * arg);
426 
439  int32_t (*isLinked)(uint32_t phyAddr,
440  bool *isLinked,
441  Mdio_Obj * arg);
442 
456  int32_t (*readC22)(uint32_t group,
457  uint32_t phyAddr,
458  uint32_t reg,
459  uint16_t *val,
460  Mdio_Obj * arg);
461 
475  int32_t (*writeC22)(uint32_t group,
476  uint32_t phyAddr,
477  uint32_t reg,
478  uint16_t val,
479  Mdio_Obj * arg);
480 
495  int32_t (*readC45)(uint32_t group,
496  uint32_t phyAddr,
497  uint8_t mmd,
498  uint16_t reg,
499  uint16_t *val,
500  Mdio_Obj * arg);
501 
516  int32_t (*writeC45)(uint32_t group,
517  uint32_t phyAddr,
518  uint8_t mmd,
519  uint16_t reg,
520  uint16_t val,
521  Mdio_Obj * arg);
522 } EnetPhy_Mdio;
523 
528 
532 typedef enum EnetPhy_FsmState_e
533 {
536 
539 
542 
545 
548 
551 
554 
557 
560 
563 
567 
571 typedef struct EnetPhy_State_s
572 {
575 
578 
581 
584 
586  uint32_t timeout;
587 
589  uint32_t residenceTime;
590 
593 
596 
599 
602 
604  uint32_t linkCaps;
605 
607  uint32_t phyLinkCaps;
608 
611 
614 
617 } EnetPhy_State;
618 
622 typedef struct EnetPhy_Obj_s
623 {
626 
629 
632 
634  uint32_t macCaps;
635 
638 
641 
644 
646  uint32_t group;
647 
649  uint32_t addr;
650 
652  uint32_t reqLinkCaps;
653 
656 
659 
662 
664  void *priv;
665 } EnetPhy_Obj;
666 
672 typedef struct EnetPhy_Obj_s *EnetPhy_Handle;
673 
674 /* ========================================================================== */
675 /* Global Variables Declarations */
676 /* ========================================================================== */
677 
678 /* None */
679 
680 /* ========================================================================== */
681 /* Function Declarations */
682 /* ========================================================================== */
683 
692 
703  const void *extendedCfg,
704  uint32_t extendedCfgSize);
705 
724  EnetPhy_Mii mii,
725  const EnetPhy_LinkCfg *linkCfg,
726  uint32_t macPortCaps,
727  EnetPhy_MdioHandle hMdio,
728  Mdio_Obj *mdioArgs);
729 
738 
749 
761  EnetPhy_Version *version);
762 
773 
787 
801  EnetPhy_LinkCfg *linkCfg);
802 
814 int32_t EnetPhy_readReg(void* pArgs,
815  uint32_t reg,
816  uint16_t *val);
817 
829 int32_t EnetPhy_writeReg(void* pArgs,
830  uint32_t reg,
831  uint16_t val);
832 
845 int32_t EnetPhy_rmwReg(void* pArgs,
846  uint32_t reg,
847  uint16_t mask,
848  uint16_t val);
849 
861 int32_t EnetPhy_readExtReg(void* pArgs,
862  uint32_t reg,
863  uint16_t *val);
864 
876 int32_t EnetPhy_writeExtReg(void* pArgs,
877  uint32_t reg,
878  uint16_t val);
879 
893  uint32_t reg,
894  uint16_t mask,
895  uint16_t val);
896 
910  uint8_t mmd,
911  uint32_t reg,
912  uint16_t *val);
913 
927  uint8_t mmd,
928  uint32_t reg,
929  uint16_t val);
930 
945  uint8_t mmd,
946  uint32_t reg,
947  uint16_t mask,
948  uint16_t val);
949 
958 
969 int32_t EnetPhy_adjPtpFreq(EnetPhy_Handle hPhy, int64_t ppb);
970 
981 int32_t EnetPhy_adjPtpPhase(EnetPhy_Handle hPhy, int64_t offset);
982 
993 int32_t EnetPhy_getPtpTime(EnetPhy_Handle hPhy, uint64_t *ts64);
994 
1005 int32_t EnetPhy_setPtpTime(EnetPhy_Handle hPhy, uint64_t ts64);
1006 
1020 int32_t EnetPhy_getPtpTxTime(EnetPhy_Handle hPhy, uint32_t domain,
1021  uint32_t msgType, uint32_t seqId, uint64_t *ts64);
1022 
1036 int32_t EnetPhy_getPtpRxTime(EnetPhy_Handle hPhy, uint32_t domain,
1037  uint32_t msgType, uint32_t seqId, uint64_t *ts64);
1038 
1051 int32_t EnetPhy_waitPtpTxTime(EnetPhy_Handle hPhy, uint32_t domain,
1052  uint32_t msgType, uint32_t seqId);
1053 
1066 int32_t EnetPhy_procStatusFrame(EnetPhy_Handle hPhy, uint8_t *frame,
1067  uint32_t size, uint32_t *types);
1068 
1081  uint8_t *ethhdr, uint32_t size);
1082 
1094 int32_t EnetPhy_enablePtp(EnetPhy_Handle hPhy, bool on,
1095  uint32_t srcMacStatusFrameType);
1096 
1107 
1120 int32_t EnetPhy_enableEventCapture(EnetPhy_Handle hPhy, uint32_t eventIdx,
1121  bool falling, bool on);
1122 
1137 int32_t EnetPhy_enableTriggerOutput(EnetPhy_Handle hPhy, uint32_t triggerIdx,
1138  uint64_t start, uint64_t period, bool repeat);
1139 
1152 int32_t EnetPhy_getEventTs(EnetPhy_Handle hPhy, uint32_t *eventIdx,
1153  uint32_t *seqId, uint64_t *ts64);
1154 /* ========================================================================== */
1155 /* Deprecated Function Declarations */
1156 /* ========================================================================== */
1157 
1158 /* None */
1159 
1160 /* ========================================================================== */
1161 /* Static Function Definitions */
1162 /* ========================================================================== */
1163 
1164 /* None */
1165 
1166 #ifdef __cplusplus
1167 }
1168 #endif
1169 
1170 #endif /* ENETPHY_H_ */
1171 
EnetPhy_State::enableMdix
bool enableMdix
Definition: enetphy.h:616
PHY_MAC_MII_RGMII
@ PHY_MAC_MII_RGMII
RGMII interface.
Definition: phy_common.h:207
EnetPhy_Obj::timeoutCfg
EnetPhy_FsmTimeoutCfg timeoutCfg
Definition: enetphy.h:640
EnetPhy_waitPtpTxTime
int32_t EnetPhy_waitPtpTxTime(EnetPhy_Handle hPhy, uint32_t domain, uint32_t msgType, uint32_t seqId)
Add PHY PTP TX packet info to a waiting TX timestamp list.
EnetPhy_Obj::priv
void * priv
Definition: enetphy.h:664
EnetPhy_adjPtpFreq
int32_t EnetPhy_adjPtpFreq(EnetPhy_Handle hPhy, int64_t ppb)
Adjust PHY PTP clock frequency.
EnetPhy_setExtendedCfg
void EnetPhy_setExtendedCfg(EnetPhy_Cfg *phyCfg, const void *extendedCfg, uint32_t extendedCfgSize)
Set PHY extended parameters.
EnetPhy_enableEventCapture
int32_t EnetPhy_enableEventCapture(EnetPhy_Handle hPhy, uint32_t eventIdx, bool falling, bool on)
Enable/Disable an event capture on a PHY GPIO pin.
EnetPhy_writeExtReg
int32_t EnetPhy_writeExtReg(void *pArgs, uint32_t reg, uint16_t val)
Write PHY extended register.
EnetPhy_getEventTs
int32_t EnetPhy_getEventTs(EnetPhy_Handle hPhy, uint32_t *eventIdx, uint32_t *seqId, uint64_t *ts64)
Get event timestamp.
EnetPhy_getPtpTime
int32_t EnetPhy_getPtpTime(EnetPhy_Handle hPhy, uint64_t *ts64)
Get current PHY PTP clock time.
EnetPhy_readExtReg
int32_t EnetPhy_readExtReg(void *pArgs, uint32_t reg, uint16_t *val)
Read PHY extended register.
EnetPhy_FsmTimeoutCfg::nwayStartStateTicks
uint32_t nwayStartStateTicks
NWAY_START state timeout (in ticks).
Definition: enetphy.h:340
EnetPhy_enablePtp
int32_t EnetPhy_enablePtp(EnetPhy_Handle hPhy, bool on, uint32_t srcMacStatusFrameType)
Enable/Disable PHY PTP module.
EnetPhy_FsmTimeoutCfg::findingStateTicks
uint32_t findingStateTicks
FINDING state timeout (in ticks).
Definition: enetphy.h:325
EnetPhy_Cfg::extClkSource
bool extClkSource
Definition: enetphy.h:390
EnetPhy_Cfg::loopbackEn
bool loopbackEn
Definition: enetphy.h:384
EnetPhy_Obj::hMdio
EnetPhy_MdioHandle hMdio
Definition: enetphy.h:625
EnetPhy_Cfg::isIsolateStateReq
bool isIsolateStateReq
Definition: enetphy.h:381
EnetPhy_Obj::addr
uint32_t addr
Definition: enetphy.h:649
EnetPhy_rmwC45Reg
int32_t EnetPhy_rmwC45Reg(EnetPhy_Handle hPhy, uint8_t mmd, uint32_t reg, uint16_t mask, uint16_t val)
Read-modify-write PHY register using Clause-45 frame.
EnetPhy_Cfg::timeoutCfg
EnetPhy_FsmTimeoutCfg timeoutCfg
Definition: enetphy.h:396
ENETPHY_SPEED_10MBIT
@ ENETPHY_SPEED_10MBIT
Definition: enetphy.h:244
EnetPhy_State::residenceTime
uint32_t residenceTime
Definition: enetphy.h:589
EnetPhy_procStatusFrame
int32_t EnetPhy_procStatusFrame(EnetPhy_Handle hPhy, uint8_t *frame, uint32_t size, uint32_t *types)
Process PHY status frame.
ENETPHY_FSM_STATE_FOUND
@ ENETPHY_FSM_STATE_FOUND
FOUND state.
Definition: enetphy.h:547
EnetPhy_Cfg::phyAddr
uint32_t phyAddr
Definition: enetphy.h:367
ENETPHY_FSM_STATE_NWAY_WAIT
@ ENETPHY_FSM_STATE_NWAY_WAIT
NWAY_WAIT state (auto-negotiation path)
Definition: enetphy.h:553
EnetPhy_State::speed
EnetPhy_Speed speed
Definition: enetphy.h:580
EnetPhy_getLinkCfg
int32_t EnetPhy_getLinkCfg(EnetPhy_Handle hPhy, EnetPhy_LinkCfg *linkCfg)
Get link configuration.
EnetPhy_readC45Reg
int32_t EnetPhy_readC45Reg(EnetPhy_Handle hPhy, uint8_t mmd, uint32_t reg, uint16_t *val)
Read PHY register using Clause-45 frame.
EnetPhy_rmwExtReg
int32_t EnetPhy_rmwExtReg(EnetPhy_Handle hPhy, uint32_t reg, uint16_t mask, uint16_t val)
Read-modify-write PHY extended register.
EnetPhy_writeReg
int32_t EnetPhy_writeReg(void *pArgs, uint32_t reg, uint16_t val)
Write PHY register.
EnetPhy_printRegs
void EnetPhy_printRegs(EnetPhy_Handle hPhy)
Print all PHY registers.
ENETPHY_FSM_STATE_LINK_WAIT
@ ENETPHY_FSM_STATE_LINK_WAIT
LINK_WAIT state.
Definition: enetphy.h:556
EnetPhy_Mii
EnetPhy_Mii
MAC Media-Independent Interface (MII).
Definition: enetphy.h:218
Phy_DrvObj_t
Definition: phy_common.h:239
ENETPHY_MAGIC
@ ENETPHY_MAGIC
Definition: enetphy.h:208
ENETPHY_LINK_DOWN
@ ENETPHY_LINK_DOWN
Definition: enetphy.h:301
ENETPHY_FSM_STATE_ENABLE
@ ENETPHY_FSM_STATE_ENABLE
ENABLE state.
Definition: enetphy.h:544
EnetPhy_State::linkCaps
uint32_t linkCaps
Definition: enetphy.h:604
EnetPhy_getPtpRxTime
int32_t EnetPhy_getPtpRxTime(EnetPhy_Handle hPhy, uint32_t domain, uint32_t msgType, uint32_t seqId, uint64_t *ts64)
Get PHY PTP RX packet timestamp.
ENETPHY_MAC_MII_RMII
@ ENETPHY_MAC_MII_RMII
RMII interface.
Definition: enetphy.h:223
ENETPHY_MAC_MII_GMII
@ ENETPHY_MAC_MII_GMII
GMII interface.
Definition: enetphy.h:226
EnetPhy_Cfg::skipExtendedCfg
bool skipExtendedCfg
Definition: enetphy.h:393
EnetPhy_getPtpTxTime
int32_t EnetPhy_getPtpTxTime(EnetPhy_Handle hPhy, uint32_t domain, uint32_t msgType, uint32_t seqId, uint64_t *ts64)
Get PHY PTP TX packet timestamp.
ENETPHY_SPEED_AUTO
@ ENETPHY_SPEED_AUTO
Definition: enetphy.h:253
PHY_MAC_MII_GMII
@ PHY_MAC_MII_GMII
GMII interface.
Definition: phy_common.h:204
PHY_MAC_MII_QSGMII
@ PHY_MAC_MII_QSGMII
QSGMII interface.
Definition: phy_common.h:213
EnetPhy_Version::revision
uint32_t revision
Definition: enetphy.h:283
EnetPhy_LinkCfg::duplexity
EnetPhy_Duplexity duplexity
Definition: enetphy.h:313
EnetPhy_State::needsManualCfg
bool needsManualCfg
Definition: enetphy.h:598
EnetPhy_tickDriver
int32_t EnetPhy_tickDriver(EnetPhy_Handle hPhy)
Provide timer tick to the driver.
EnetPhy_Cfg
PHY configuration parameters.
Definition: enetphy.h:362
EnetPhy_FsmState
EnetPhy_FsmState
PHY driver state-machine states.
Definition: enetphy.h:533
EnetPhy_getId
int32_t EnetPhy_getId(EnetPhy_Handle hPhy, EnetPhy_Version *version)
Get PHY id.
ENETPHY_MAC_MII_MII
@ ENETPHY_MAC_MII_MII
MII interface.
Definition: enetphy.h:220
EnetPhy_isAlive
bool EnetPhy_isAlive(EnetPhy_Handle hPhy)
Get PHY alive status.
EnetPhy_FsmTimeoutCfg::mdixTicks
uint32_t mdixTicks
Timeout if MDIX is enabled (in ticks).
Definition: enetphy.h:355
ENETPHY_DUPLEX_HALF
@ ENETPHY_DUPLEX_HALF
Definition: enetphy.h:262
EnetPhy_State::needsMdixSwitch
bool needsMdixSwitch
Definition: enetphy.h:613
PHY_MAC_MII_SGMII
@ PHY_MAC_MII_SGMII
SGMII interface.
Definition: phy_common.h:210
EnetPhy_Version
PHY version (ID).
Definition: enetphy.h:275
EnetPhy_FsmTimeoutCfg::resetWaitStateTicks
uint32_t resetWaitStateTicks
RESET_WAIT state timeout (in ticks).
Definition: enetphy.h:331
ENETPHY_DUPLEX_FULL
@ ENETPHY_DUPLEX_FULL
Definition: enetphy.h:265
EnetPhy_Obj::state
EnetPhy_State state
Definition: enetphy.h:643
EnetPhy_close
void EnetPhy_close(EnetPhy_Handle hPhy)
Close the PHY driver.
EnetPhy_Obj::linkCfg
EnetPhy_LinkCfg linkCfg
Definition: enetphy.h:637
ENETPHY_SPEED_1GBIT
@ ENETPHY_SPEED_1GBIT
Definition: enetphy.h:250
EnetPhy_MdioHandle
EnetPhy_Mdio * EnetPhy_MdioHandle
MDIO driver handle.
Definition: enetphy.h:527
ENETPHY_FSM_STATE_LOOPBACK
@ ENETPHY_FSM_STATE_LOOPBACK
LOOPBACK state.
Definition: enetphy.h:562
EnetPhy_LinkCfg::speed
EnetPhy_Speed speed
Definition: enetphy.h:310
EnetPhy_FsmTimeoutCfg
PHY State-Machine time-out values.
Definition: enetphy.h:320
EnetPhy_Handle
struct EnetPhy_Obj_s * EnetPhy_Handle
PHY driver object handle.
Definition: enetphy.h:672
EnetPhy_isLinked
bool EnetPhy_isLinked(EnetPhy_Handle hPhy)
Get link status.
ENETPHY_LOST_LINK
@ ENETPHY_LOST_LINK
Definition: enetphy.h:298
EnetPhy_writeC45Reg
int32_t EnetPhy_writeC45Reg(EnetPhy_Handle hPhy, uint8_t mmd, uint32_t reg, uint16_t val)
Write PHY register using Clause-45 frame.
ENETPHY_NO_MAGIC
@ ENETPHY_NO_MAGIC
Definition: enetphy.h:211
EnetPhy_Obj::mdioArgs
Mdio_Obj * mdioArgs
Definition: enetphy.h:661
ENETPHY_GOT_LINK
@ ENETPHY_GOT_LINK
Definition: enetphy.h:292
EnetPhy_Obj::magic
EnetPhy_Magic magic
Definition: enetphy.h:658
EnetPhy_Version::model
uint32_t model
Definition: enetphy.h:280
ENETPHY_FSM_STATE_NWAY_START
@ ENETPHY_FSM_STATE_NWAY_START
NWAY_START state (auto-negotiation path)
Definition: enetphy.h:550
ENETPHY_DUPLEX_AUTO
@ ENETPHY_DUPLEX_AUTO
Definition: enetphy.h:268
EnetPhy_Obj::mii
EnetPhy_Mii mii
Definition: enetphy.h:631
ENETPHY_LINK_UP
@ ENETPHY_LINK_UP
Definition: enetphy.h:295
EnetPhy_State
PHY driver FSM state.
Definition: enetphy.h:572
EnetPhy_FsmTimeoutCfg::nwayWaitStateTicks
uint32_t nwayWaitStateTicks
NWAY_WAIT state timeout (in ticks).
Definition: enetphy.h:346
EnetPhy_FsmTimeoutCfg::resetWaitStateResidenceTicks
uint32_t resetWaitStateResidenceTicks
RESET_WAIT state residence time (in ticks).
Definition: enetphy.h:334
ENETPHY_SPEED_100MBIT
@ ENETPHY_SPEED_100MBIT
Definition: enetphy.h:247
ENETPHY_FSM_STATE_FINDING
@ ENETPHY_FSM_STATE_FINDING
FINDING state.
Definition: enetphy.h:538
EnetPhy_open
EnetPhy_Handle EnetPhy_open(const EnetPhy_Cfg *phyCfg, EnetPhy_Mii mii, const EnetPhy_LinkCfg *linkCfg, uint32_t macPortCaps, EnetPhy_MdioHandle hMdio, Mdio_Obj *mdioArgs)
Open the PHY driver.
ENETPHY_MAC_MII_SGMII
@ ENETPHY_MAC_MII_SGMII
SGMII interface.
Definition: enetphy.h:232
phy_common.h
EnetPhy_Cfg::mdixEn
bool mdixEn
Definition: enetphy.h:373
EnetPhy_getStatusFrameEthHeader
int32_t EnetPhy_getStatusFrameEthHeader(EnetPhy_Handle hPhy, uint8_t *ethhdr, uint32_t size)
Get PHY status frame header.
EnetPhy_Cfg::extendedCfgSize
uint32_t extendedCfgSize
Definition: enetphy.h:402
EnetPhy_Cfg::masterMode
bool masterMode
Definition: enetphy.h:387
ENETPHY_FSM_STATE_INIT
@ ENETPHY_FSM_STATE_INIT
INIT state.
Definition: enetphy.h:535
EnetPhy_State::isNwayCapable
bool isNwayCapable
Definition: enetphy.h:592
ENETPHY_EXTENDED_CFG_SIZE_MAX
#define ENETPHY_EXTENDED_CFG_SIZE_MAX
Max extended configuration size, arbitrarily chosen.
Definition: enetphy.h:182
EnetPhy_State::needsNwayCfg
bool needsNwayCfg
Definition: enetphy.h:601
ENETPHY_MAC_MII_QSGMII
@ ENETPHY_MAC_MII_QSGMII
QSGMII interface.
Definition: enetphy.h:235
EnetPhy_Version::oui
uint32_t oui
Definition: enetphy.h:277
EnetPhy_LinkCfg
Link speed and duplexity configuration.
Definition: enetphy.h:308
EnetPhy_initCfg
void EnetPhy_initCfg(EnetPhy_Cfg *phyCfg)
Initialize PHY config params.
EnetPhy_State::fsmState
EnetPhy_FsmState fsmState
Definition: enetphy.h:574
EnetPhy_State::duplexity
EnetPhy_Duplexity duplexity
Definition: enetphy.h:583
EnetPhy_rmwReg
int32_t EnetPhy_rmwReg(void *pArgs, uint32_t reg, uint16_t mask, uint16_t val)
Read-modify-write PHY register.
EnetPhy_State::fsmStateChanged
bool fsmStateChanged
Definition: enetphy.h:577
EnetPhy_Cfg::nwayCaps
uint32_t nwayCaps
Definition: enetphy.h:370
EnetPhy_FsmTimeoutCfg::linkWaitStateTicks
uint32_t linkWaitStateTicks
LINK_WAIT state timeout (in ticks).
Definition: enetphy.h:352
EnetPhy_readReg
int32_t EnetPhy_readReg(void *pArgs, uint32_t reg, uint16_t *val)
Read PHY register.
EnetPhy_Duplexity
EnetPhy_Duplexity
MAC interface duplexity.
Definition: enetphy.h:260
EnetPhy_enableTriggerOutput
int32_t EnetPhy_enableTriggerOutput(EnetPhy_Handle hPhy, uint32_t triggerIdx, uint64_t start, uint64_t period, bool repeat)
Enable/Disable clock trigger on a GPIO pin.
ENETPHY_MAC_MII_RGMII
@ ENETPHY_MAC_MII_RGMII
RGMII interface.
Definition: enetphy.h:229
EnetPhy_setPtpTime
int32_t EnetPhy_setPtpTime(EnetPhy_Handle hPhy, uint64_t ts64)
Set PHY PTP clock time.
EnetPhy_State::loopbackEn
bool loopbackEn
Definition: enetphy.h:610
EnetPhy_State::enableNway
bool enableNway
Definition: enetphy.h:595
EnetPhy_Obj
PHY driver object.
Definition: enetphy.h:623
EnetPhy_Obj::group
uint32_t group
Definition: enetphy.h:646
EnetPhy_Obj::macCaps
uint32_t macCaps
Definition: enetphy.h:634
EnetPhy_State::phyLinkCaps
uint32_t phyLinkCaps
Definition: enetphy.h:607
EnetPhy_Obj::reqLinkCaps
uint32_t reqLinkCaps
Definition: enetphy.h:652
EnetPhy_Cfg::phyGroup
uint32_t phyGroup
Definition: enetphy.h:364
EnetPhy_tick
EnetPhy_LinkStatus EnetPhy_tick(EnetPhy_Handle hPhy)
Run PHY state machine.
EnetPhy_Speed
EnetPhy_Speed
MAC interface speed.
Definition: enetphy.h:242
EnetPhy_Cfg::isStrapped
bool isStrapped
Definition: enetphy.h:378
ENETPHY_FSM_STATE_ISOLATE
@ ENETPHY_FSM_STATE_ISOLATE
ISOLATE state.
Definition: enetphy.h:565
EnetPhy_Mdio
MDIO driver.
Definition: enetphy.h:410
ENETPHY_FSM_STATE_RESET_WAIT
@ ENETPHY_FSM_STATE_RESET_WAIT
RESET_WAIT state.
Definition: enetphy.h:541
PHY_MAC_MII_MII
@ PHY_MAC_MII_MII
MII interface.
Definition: phy_common.h:198
EnetPhy_Obj::hDrvIf
Phy_DrvObj_t hDrvIf
Definition: enetphy.h:655
EnetPhy_Obj::phyCfg
EnetPhy_Cfg phyCfg
Definition: enetphy.h:628
ENETPHY_FSM_STATE_LINKED
@ ENETPHY_FSM_STATE_LINKED
LINKED state.
Definition: enetphy.h:559
EnetPhy_Magic
EnetPhy_Magic
EnetPhy driver magic value, used to indicate if driver is open or not.
Definition: enetphy.h:206
Mdio_Obj
struct Mdio_Obj_s Mdio_Obj
Definition: enetphy.h:200
EnetPhy_State::timeout
uint32_t timeout
Definition: enetphy.h:586
EnetPhy_adjPtpPhase
int32_t EnetPhy_adjPtpPhase(EnetPhy_Handle hPhy, int64_t offset)
Adjust PHY PTP clock phase.
PHY_MAC_MII_RMII
@ PHY_MAC_MII_RMII
RMII interface.
Definition: phy_common.h:201
EnetPhy_LinkStatus
EnetPhy_LinkStatus
PHY link status.
Definition: enetphy.h:290