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AM263x MCU+ SDK
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81 #define ENETPHY_IS_ADDR_VALID(addr) ((addr) <= 31U)
84 #define ENETPHY_BIT(n) (1U << (n))
87 #define ENETPHY_IS_BIT_SET(val, n) (((val) & ENETPHY_BIT(n)) != 0U)
90 #define ENETPHY_ARRAYSIZE(x) (sizeof(x) / sizeof(x[0]))
104 #define ENETPHY_SOK (CSL_PASS)
107 #define ENETPHY_EFAIL (CSL_EFAIL)
110 #define ENETPHY_EBADARGS (CSL_EBADARGS)
113 #define ENETPHY_EINVALIDPARAMS (CSL_EINVALID_PARAMS)
116 #define ENETPHY_ETIMEOUT (CSL_ETIMEOUT)
119 #define ENETPHY_EALLOC (CSL_EALLOC)
122 #define ENETPHY_EPERM (CSL_EALLOC - 4)
125 #define ENETPHY_ENOTSUPPORTED (CSL_EALLOC - 5)
128 #define ENETPHY_EUNAVAILABLE (CSL_EALLOC - 6)
142 #define ENETPHY_LINK_CAP_HD10 ENETPHY_BIT(1)
145 #define ENETPHY_LINK_CAP_FD10 ENETPHY_BIT(2)
148 #define ENETPHY_LINK_CAP_HD100 ENETPHY_BIT(3)
151 #define ENETPHY_LINK_CAP_FD100 ENETPHY_BIT(4)
154 #define ENETPHY_LINK_CAP_HD1000 ENETPHY_BIT(5)
157 #define ENETPHY_LINK_CAP_FD1000 ENETPHY_BIT(6)
160 #define ENETPHY_LINK_CAP_10 (ENETPHY_LINK_CAP_HD10 | \
161 ENETPHY_LINK_CAP_FD10)
164 #define ENETPHY_LINK_CAP_100 (ENETPHY_LINK_CAP_HD100 | \
165 ENETPHY_LINK_CAP_FD100)
168 #define ENETPHY_LINK_CAP_1000 (ENETPHY_LINK_CAP_HD1000 | \
169 ENETPHY_LINK_CAP_FD1000)
172 #define ENETPHY_LINK_CAP_ALL (ENETPHY_LINK_CAP_HD10 | \
173 ENETPHY_LINK_CAP_FD10 | \
174 ENETPHY_LINK_CAP_HD100 | \
175 ENETPHY_LINK_CAP_FD100 | \
176 ENETPHY_LINK_CAP_HD1000 | \
177 ENETPHY_LINK_CAP_FD1000)
182 #define ENETPHY_EXTENDED_CFG_SIZE_MAX (128U)
185 #define ENETPHY_FSM_TICK_PERIOD_MS (100U)
188 #define ENETPHY_INVALID_PHYADDR (~0U)
191 #define ENETPHY_TIMEOUT_WAIT_FOREVER (0xFFFFFFFFU)
194 #define ENETPHY_TIMEOUT_NO_WAIT (0U)
205 typedef enum EnetPhy_Magic_e
217 typedef enum EnetPhy_Mii_e
241 typedef enum EnetPhy_Speed_e
259 typedef enum EnetPhy_Duplexity_e
274 typedef struct EnetPhy_Version_s
289 typedef enum EnetPhy_LinkStatus_e
307 typedef struct EnetPhy_LinkCfg_s
319 typedef struct EnetPhy_FsmTimeoutCfg_s
361 typedef struct EnetPhy_Cfg_s
409 typedef struct EnetPhy_Mdio_s
423 int32_t (*isAlive)(uint32_t phyAddr,
439 int32_t (*isLinked)(uint32_t phyAddr,
456 int32_t (*readC22)(uint32_t group,
475 int32_t (*writeC22)(uint32_t group,
495 int32_t (*readC45)(uint32_t group,
516 int32_t (*writeC45)(uint32_t group,
532 typedef enum EnetPhy_FsmState_e
571 typedef struct EnetPhy_State_s
622 typedef struct EnetPhy_Obj_s
703 const void *extendedCfg,
704 uint32_t extendedCfgSize);
726 uint32_t macPortCaps,
1021 uint32_t msgType, uint32_t seqId, uint64_t *ts64);
1037 uint32_t msgType, uint32_t seqId, uint64_t *ts64);
1052 uint32_t msgType, uint32_t seqId);
1067 uint32_t size, uint32_t *types);
1081 uint8_t *ethhdr, uint32_t size);
1095 uint32_t srcMacStatusFrameType);
1121 bool falling,
bool on);
1138 uint64_t start, uint64_t period,
bool repeat);
1153 uint32_t *seqId, uint64_t *ts64);
bool enableMdix
Definition: enetphy.h:616
@ PHY_MAC_MII_RGMII
RGMII interface.
Definition: phy_common.h:207
EnetPhy_FsmTimeoutCfg timeoutCfg
Definition: enetphy.h:640
int32_t EnetPhy_waitPtpTxTime(EnetPhy_Handle hPhy, uint32_t domain, uint32_t msgType, uint32_t seqId)
Add PHY PTP TX packet info to a waiting TX timestamp list.
void * priv
Definition: enetphy.h:664
int32_t EnetPhy_adjPtpFreq(EnetPhy_Handle hPhy, int64_t ppb)
Adjust PHY PTP clock frequency.
void EnetPhy_setExtendedCfg(EnetPhy_Cfg *phyCfg, const void *extendedCfg, uint32_t extendedCfgSize)
Set PHY extended parameters.
int32_t EnetPhy_enableEventCapture(EnetPhy_Handle hPhy, uint32_t eventIdx, bool falling, bool on)
Enable/Disable an event capture on a PHY GPIO pin.
int32_t EnetPhy_writeExtReg(void *pArgs, uint32_t reg, uint16_t val)
Write PHY extended register.
int32_t EnetPhy_getEventTs(EnetPhy_Handle hPhy, uint32_t *eventIdx, uint32_t *seqId, uint64_t *ts64)
Get event timestamp.
int32_t EnetPhy_getPtpTime(EnetPhy_Handle hPhy, uint64_t *ts64)
Get current PHY PTP clock time.
int32_t EnetPhy_readExtReg(void *pArgs, uint32_t reg, uint16_t *val)
Read PHY extended register.
uint32_t nwayStartStateTicks
NWAY_START state timeout (in ticks).
Definition: enetphy.h:340
int32_t EnetPhy_enablePtp(EnetPhy_Handle hPhy, bool on, uint32_t srcMacStatusFrameType)
Enable/Disable PHY PTP module.
uint32_t findingStateTicks
FINDING state timeout (in ticks).
Definition: enetphy.h:325
bool extClkSource
Definition: enetphy.h:390
bool loopbackEn
Definition: enetphy.h:384
EnetPhy_MdioHandle hMdio
Definition: enetphy.h:625
bool isIsolateStateReq
Definition: enetphy.h:381
uint32_t addr
Definition: enetphy.h:649
int32_t EnetPhy_rmwC45Reg(EnetPhy_Handle hPhy, uint8_t mmd, uint32_t reg, uint16_t mask, uint16_t val)
Read-modify-write PHY register using Clause-45 frame.
EnetPhy_FsmTimeoutCfg timeoutCfg
Definition: enetphy.h:396
@ ENETPHY_SPEED_10MBIT
Definition: enetphy.h:244
uint32_t residenceTime
Definition: enetphy.h:589
int32_t EnetPhy_procStatusFrame(EnetPhy_Handle hPhy, uint8_t *frame, uint32_t size, uint32_t *types)
Process PHY status frame.
@ ENETPHY_FSM_STATE_FOUND
FOUND state.
Definition: enetphy.h:547
uint32_t phyAddr
Definition: enetphy.h:367
@ ENETPHY_FSM_STATE_NWAY_WAIT
NWAY_WAIT state (auto-negotiation path)
Definition: enetphy.h:553
EnetPhy_Speed speed
Definition: enetphy.h:580
int32_t EnetPhy_getLinkCfg(EnetPhy_Handle hPhy, EnetPhy_LinkCfg *linkCfg)
Get link configuration.
int32_t EnetPhy_readC45Reg(EnetPhy_Handle hPhy, uint8_t mmd, uint32_t reg, uint16_t *val)
Read PHY register using Clause-45 frame.
int32_t EnetPhy_rmwExtReg(EnetPhy_Handle hPhy, uint32_t reg, uint16_t mask, uint16_t val)
Read-modify-write PHY extended register.
int32_t EnetPhy_writeReg(void *pArgs, uint32_t reg, uint16_t val)
Write PHY register.
void EnetPhy_printRegs(EnetPhy_Handle hPhy)
Print all PHY registers.
@ ENETPHY_FSM_STATE_LINK_WAIT
LINK_WAIT state.
Definition: enetphy.h:556
EnetPhy_Mii
MAC Media-Independent Interface (MII).
Definition: enetphy.h:218
Definition: phy_common.h:239
@ ENETPHY_MAGIC
Definition: enetphy.h:208
@ ENETPHY_LINK_DOWN
Definition: enetphy.h:301
@ ENETPHY_FSM_STATE_ENABLE
ENABLE state.
Definition: enetphy.h:544
uint32_t linkCaps
Definition: enetphy.h:604
int32_t EnetPhy_getPtpRxTime(EnetPhy_Handle hPhy, uint32_t domain, uint32_t msgType, uint32_t seqId, uint64_t *ts64)
Get PHY PTP RX packet timestamp.
@ ENETPHY_MAC_MII_RMII
RMII interface.
Definition: enetphy.h:223
@ ENETPHY_MAC_MII_GMII
GMII interface.
Definition: enetphy.h:226
bool skipExtendedCfg
Definition: enetphy.h:393
int32_t EnetPhy_getPtpTxTime(EnetPhy_Handle hPhy, uint32_t domain, uint32_t msgType, uint32_t seqId, uint64_t *ts64)
Get PHY PTP TX packet timestamp.
@ ENETPHY_SPEED_AUTO
Definition: enetphy.h:253
@ PHY_MAC_MII_GMII
GMII interface.
Definition: phy_common.h:204
@ PHY_MAC_MII_QSGMII
QSGMII interface.
Definition: phy_common.h:213
uint32_t revision
Definition: enetphy.h:283
EnetPhy_Duplexity duplexity
Definition: enetphy.h:313
bool needsManualCfg
Definition: enetphy.h:598
int32_t EnetPhy_tickDriver(EnetPhy_Handle hPhy)
Provide timer tick to the driver.
PHY configuration parameters.
Definition: enetphy.h:362
EnetPhy_FsmState
PHY driver state-machine states.
Definition: enetphy.h:533
int32_t EnetPhy_getId(EnetPhy_Handle hPhy, EnetPhy_Version *version)
Get PHY id.
@ ENETPHY_MAC_MII_MII
MII interface.
Definition: enetphy.h:220
bool EnetPhy_isAlive(EnetPhy_Handle hPhy)
Get PHY alive status.
uint32_t mdixTicks
Timeout if MDIX is enabled (in ticks).
Definition: enetphy.h:355
@ ENETPHY_DUPLEX_HALF
Definition: enetphy.h:262
bool needsMdixSwitch
Definition: enetphy.h:613
@ PHY_MAC_MII_SGMII
SGMII interface.
Definition: phy_common.h:210
PHY version (ID).
Definition: enetphy.h:275
uint32_t resetWaitStateTicks
RESET_WAIT state timeout (in ticks).
Definition: enetphy.h:331
@ ENETPHY_DUPLEX_FULL
Definition: enetphy.h:265
EnetPhy_State state
Definition: enetphy.h:643
void EnetPhy_close(EnetPhy_Handle hPhy)
Close the PHY driver.
EnetPhy_LinkCfg linkCfg
Definition: enetphy.h:637
@ ENETPHY_SPEED_1GBIT
Definition: enetphy.h:250
EnetPhy_Mdio * EnetPhy_MdioHandle
MDIO driver handle.
Definition: enetphy.h:527
@ ENETPHY_FSM_STATE_LOOPBACK
LOOPBACK state.
Definition: enetphy.h:562
EnetPhy_Speed speed
Definition: enetphy.h:310
PHY State-Machine time-out values.
Definition: enetphy.h:320
struct EnetPhy_Obj_s * EnetPhy_Handle
PHY driver object handle.
Definition: enetphy.h:672
bool EnetPhy_isLinked(EnetPhy_Handle hPhy)
Get link status.
@ ENETPHY_LOST_LINK
Definition: enetphy.h:298
int32_t EnetPhy_writeC45Reg(EnetPhy_Handle hPhy, uint8_t mmd, uint32_t reg, uint16_t val)
Write PHY register using Clause-45 frame.
@ ENETPHY_NO_MAGIC
Definition: enetphy.h:211
Mdio_Obj * mdioArgs
Definition: enetphy.h:661
@ ENETPHY_GOT_LINK
Definition: enetphy.h:292
EnetPhy_Magic magic
Definition: enetphy.h:658
uint32_t model
Definition: enetphy.h:280
@ ENETPHY_FSM_STATE_NWAY_START
NWAY_START state (auto-negotiation path)
Definition: enetphy.h:550
@ ENETPHY_DUPLEX_AUTO
Definition: enetphy.h:268
EnetPhy_Mii mii
Definition: enetphy.h:631
@ ENETPHY_LINK_UP
Definition: enetphy.h:295
PHY driver FSM state.
Definition: enetphy.h:572
uint32_t nwayWaitStateTicks
NWAY_WAIT state timeout (in ticks).
Definition: enetphy.h:346
uint32_t resetWaitStateResidenceTicks
RESET_WAIT state residence time (in ticks).
Definition: enetphy.h:334
@ ENETPHY_SPEED_100MBIT
Definition: enetphy.h:247
@ ENETPHY_FSM_STATE_FINDING
FINDING state.
Definition: enetphy.h:538
EnetPhy_Handle EnetPhy_open(const EnetPhy_Cfg *phyCfg, EnetPhy_Mii mii, const EnetPhy_LinkCfg *linkCfg, uint32_t macPortCaps, EnetPhy_MdioHandle hMdio, Mdio_Obj *mdioArgs)
Open the PHY driver.
@ ENETPHY_MAC_MII_SGMII
SGMII interface.
Definition: enetphy.h:232
bool mdixEn
Definition: enetphy.h:373
int32_t EnetPhy_getStatusFrameEthHeader(EnetPhy_Handle hPhy, uint8_t *ethhdr, uint32_t size)
Get PHY status frame header.
uint32_t extendedCfgSize
Definition: enetphy.h:402
bool masterMode
Definition: enetphy.h:387
@ ENETPHY_FSM_STATE_INIT
INIT state.
Definition: enetphy.h:535
bool isNwayCapable
Definition: enetphy.h:592
#define ENETPHY_EXTENDED_CFG_SIZE_MAX
Max extended configuration size, arbitrarily chosen.
Definition: enetphy.h:182
bool needsNwayCfg
Definition: enetphy.h:601
@ ENETPHY_MAC_MII_QSGMII
QSGMII interface.
Definition: enetphy.h:235
uint32_t oui
Definition: enetphy.h:277
Link speed and duplexity configuration.
Definition: enetphy.h:308
void EnetPhy_initCfg(EnetPhy_Cfg *phyCfg)
Initialize PHY config params.
EnetPhy_FsmState fsmState
Definition: enetphy.h:574
EnetPhy_Duplexity duplexity
Definition: enetphy.h:583
int32_t EnetPhy_rmwReg(void *pArgs, uint32_t reg, uint16_t mask, uint16_t val)
Read-modify-write PHY register.
bool fsmStateChanged
Definition: enetphy.h:577
uint32_t nwayCaps
Definition: enetphy.h:370
uint32_t linkWaitStateTicks
LINK_WAIT state timeout (in ticks).
Definition: enetphy.h:352
int32_t EnetPhy_readReg(void *pArgs, uint32_t reg, uint16_t *val)
Read PHY register.
EnetPhy_Duplexity
MAC interface duplexity.
Definition: enetphy.h:260
int32_t EnetPhy_enableTriggerOutput(EnetPhy_Handle hPhy, uint32_t triggerIdx, uint64_t start, uint64_t period, bool repeat)
Enable/Disable clock trigger on a GPIO pin.
@ ENETPHY_MAC_MII_RGMII
RGMII interface.
Definition: enetphy.h:229
int32_t EnetPhy_setPtpTime(EnetPhy_Handle hPhy, uint64_t ts64)
Set PHY PTP clock time.
bool loopbackEn
Definition: enetphy.h:610
bool enableNway
Definition: enetphy.h:595
PHY driver object.
Definition: enetphy.h:623
uint32_t group
Definition: enetphy.h:646
uint32_t macCaps
Definition: enetphy.h:634
uint32_t phyLinkCaps
Definition: enetphy.h:607
uint32_t reqLinkCaps
Definition: enetphy.h:652
uint32_t phyGroup
Definition: enetphy.h:364
EnetPhy_LinkStatus EnetPhy_tick(EnetPhy_Handle hPhy)
Run PHY state machine.
EnetPhy_Speed
MAC interface speed.
Definition: enetphy.h:242
bool isStrapped
Definition: enetphy.h:378
@ ENETPHY_FSM_STATE_ISOLATE
ISOLATE state.
Definition: enetphy.h:565
MDIO driver.
Definition: enetphy.h:410
@ ENETPHY_FSM_STATE_RESET_WAIT
RESET_WAIT state.
Definition: enetphy.h:541
@ PHY_MAC_MII_MII
MII interface.
Definition: phy_common.h:198
Phy_DrvObj_t hDrvIf
Definition: enetphy.h:655
EnetPhy_Cfg phyCfg
Definition: enetphy.h:628
@ ENETPHY_FSM_STATE_LINKED
LINKED state.
Definition: enetphy.h:559
EnetPhy_Magic
EnetPhy driver magic value, used to indicate if driver is open or not.
Definition: enetphy.h:206
struct Mdio_Obj_s Mdio_Obj
Definition: enetphy.h:200
uint32_t timeout
Definition: enetphy.h:586
int32_t EnetPhy_adjPtpPhase(EnetPhy_Handle hPhy, int64_t offset)
Adjust PHY PTP clock phase.
@ PHY_MAC_MII_RMII
RMII interface.
Definition: phy_common.h:201
EnetPhy_LinkStatus
PHY link status.
Definition: enetphy.h:290