| Peripheral | Supported CPUs | SysConfig Support | DMA Supported | Key features tested | Key features not tested / NOT supported |
| ADC | R5F | YES | Yes. Example: adc_soc_continuous_dma | Single software triggered conversion, Multiple ADC trigger using PWM, Result read using DMA, EPWM trip through PPB limit, PPB features, Burst mode, Single and Differential mode, Interrupt with Offset from Aquisition Window, EPWM/ECAP/RTI triggered conversions | - |
| Bootloader | R5F | YES | Yes. DMA enabled for SBL QSPI | Boot modes: QSPI, UART. All R5F's | - |
| CMPSS | R5F | YES | NA | Asynchronous PWM trip, Digital Filter, Calibration, | - |
| CPSW | R5F | YES | No | MAC loopback, PHY loopback, LWIP: Getting IP, Ping, Iperf, Layer 2 MAC, Layer 2 PTP Timestamping and Ethernet CPSW Switch support, TSN stack | RMII, MII mode |
| DAC | R5F | YES | Yes. Example: dac_sine_dma | Constant voltage, Square wave generation, Sine wave generation with and without DMA, Ramp wave generation, Random Voltage generation | - |
| ECAP | R5F | YES | yes. Example : ecap_edma | ECAP APWM mode, PWM capture, DMA trigger in both APWM and Capture Modes | - |
| EDMA | R5F | YES | NA | DMA transfer using interrupt and polling mode, QDMA Transfer, Channel Chaining, PaRAM Linking, Error Handling | - |
| EPWM | R5F | YES | Yes. Example: epwm_dma | PWM outputs A and B in up-down count mode, Trip zone, Update PWM using EDMA, Valley switching, High resolution time period adjustment, type5 feature | - |
| EQEP | R5F | YES | NA | Speed and Position measurement. Frequency Measurement, Speed and Direction Measurement, cw-ccw modes | - |
| FSI | R5F | YES | Yes. Example: fsi_loopback_dma | RX, TX, polling, interrupt mode, Dma, single lane loopback. | - FSI Spi Mode |
| GPIO | R5F | YES | NA | Output, Input and Interrupt functionality | - |
| I2C | R5F | YES | No | Controller mode, basic read/write | - |
| IPC Notify | R5F | YES | NA | Mailbox functionality, IPC between RTOS/NORTOS CPUs | M4F core |
| IPC Rpmsg | R5F | YES | NA | RPMessage protocol based IPC | M4F core |
| LIN | R5F | YES | YES | RX, TX, polling, interrupt, DMA mode. | - |
| MCAN | R5F | YES | No | RX, TX, interrupt and polling mode, Corrupt Message Transmission Prevention, Error Passive state, Bus Off State, Bus Monitoring Mode | - |
| MCSPI | R5F | YES | Yes. Example: mcspi_loopback_dma | Controller/Peripheral mode, basic read/write, polling, interrupt and DMA mode | - |
| MDIO | R5F | YES | NA | Register read/write, link status and link interrupt enable API | - |
| MPU Firewall | R5F | YES | NA | Only compiled (Works only on HS-SE device) | - |
| MMCSD | R5F | YES | NA | MMCSD 4bit, Raw read/write, file IO | - |
| PINMUX | R5F | YES | NA | Tested with multiple peripheral pinmuxes | - |
| PMU | R5F | NO | NA | Tested various PMU events | Counter overflow detection is not enabled |
| PRUICSS | R5F | YES | NA | Tested with Ethercat FW HAL | - |
| QSPI | R5F | YES | Yes. Example: qspi_flash_dma_transfer | Read direct, Write indirect, Read/Write commands, DMA for read | - |
| RTI | R5F | YES | No | Counter read, timebase selction, comparator setup for Interrupt, DMA requests | Capture feature, fast enabling/disabling of events not tested |
| SDFM | R5F | YES | Yes. Example: sdfm_filter_sync_dmaread | Filter data read from CPU, Filter data read with PWM sync | - |
| SOC | R5F | YES | NA | Lock/unlock MMRs, clock enable, set Hz, Xbar configuration, SW Warm Reset, Address Translation | - |
| SPINLOCK | R5F | NA | NA | Lock, unlock HW spinlocks | - |
| UART | R5F | YES | Yes. Example: uart_echo_dma | Basic read/write at baud rate 115200, polling, interrupt mode | HW flow control not tested, DMA mode not supported |
| WATCHDOG | R5F | YES | NA | Reset mode, Interrupt mode | - |
| Module | Supported CPUs | SysConfig Support | OS Support | Key features tested | Key features not tested |
| Time-Sensitive Networking(gPTP-IEEE 802.1AS) | R5F | NO | FreeRTOS | gPTP IEEE 802.1 AS-2020 compliant gPTP stack, End Nodes and Bridge mode support, YANG data model configuration, IEEE 1722 compliant AVTP Stack | Multi-Clock Domain |
| LwIP | R5F | YES | FreeRTOS | TCP/UDP IP networking stack with and without checksum offload enabled, TCP/UDP IP networking stack with server and client functionality, basic Socket APIs, netconn APIs and raw APIs, DHCP, ping, TCP iperf, scatter-gather, DSCP priority mapping | Other LwIP features |
| Ethernet driver (ENET) | R5F | YES | FreeRTOS | Ethernet as port using CPSW, MAC loopback and PHY loopback, Layer 2 MAC, Packet Timestamping, CPSW Switch, CPSW EST, interrupt pacing, Policer and Classifier, MDIO Manual Mode, Credit Based Shaper (IEEE 802.1Qav), Strapped PHY (Early Ethernet) | N/A |
| ICSS-EMAC | R5F | YES | FreeRTOS | Switch and MAC features, Storm Prevention (MAC), Host Statistics, Multicast Filtering | Promiscuous Mode |
| Mbed-TLS | R5F | NO | FreeRTOS | Tested software cryptography after porting, used mbedTLS with LwIP to implement HTTPS server | Hardware offloaded cryptography |
| Ether-ring Implementation | R5F | NO | FreeRTOS | Duplicate Rejection, Ring termination and Packet Duplication, Latency measurement for different real-time traffic profiles, Performance KPIs | N/A |
| Module | Supported CPUs | SysConfig Support | OS support | Key features tested | Key features not tested / NOT supported |
| MCRC | R5F | NA | NORTOS | Full CPU, Auto CPU Mode and Semi CPU Auto Mode | - |
| DCC | R5F | NA | NORTOS | Single Shot and Continuous modes | - |
| PBIST | R5F | NA | NORTOS | Memories supported by MSS PBIST controller. | - |
| ESM | R5F | NA | NORTOS | Tested in combination with RTI, DCC | - |
| RTI | R5F | NA | NORTOS | WINDOWSIZE_100_PERCENT, WINDOWSIZE_50_PERCENT ,Latency/Propagation timing error(early)(50% window),Latency/Propagation timing error(late)(50% window) | - |
| ECC | R5F | NA | NORTOS | ECC of MSS_L2, R5F TCM, MCAN, VIM, ICSSM, TPTC | - |
| ECC Bus Safety | R5F | NA | NORTOS | AHB, AXI, TPTC | - |
| CCM | R5F | NA | NORTOS | CCM Self Test Mode,Error Forcing Mode and Self Test Error Forcing Mode. | - |
| R5F STC(LBIST), Static Register Read | R5F | NA | NORTOS | STC of R5F, R5F CPU Static Register Read | - |
| Integrated Example | R5F | NA | FreeRTOS | Integrated example with all the SDL modules integrated in to one example. | ECC Bu Safety and STC. |
| ID | Head Line | Module | Applicable Releases | Applicable Devices | Resolution/Comments |
| MCUSDK-14749 | McSPI: Non Powers of 2 cannot be configured as fifo trigger levels in polling and interrupt mode | McSPI | 10.02.00 onwards | AM263x, AM263Px | Fix in SysCfg Meta file. |
| MCUSDK-13966 | All UART triggers levels not exposed in SysCfg | UART | 10.00.00 onwards | AM263x, AM263Px | Update SysCfg to show all trigger levels from 1 to 64. |
| MCUSDK-14573 | Incorrect handling of errata i2310 in UART isr | UART | 10.00.00 onwards | AM263x, AM263Px | Reorder the ISR state machine for handling UART errata correctly. |
| MCUSDK-14704 | Adding multiple instances of UART DMA LLD causes failure | UART | 10.01.00 onwards | AM263x, AM263Px | SysCfg template update to pass the EDMA handle correctly |
| MCUSDK-14706 | GPIO Qual selection API missing | GPIO | 10.00.00 onwards | AM263x, AM263Px | Qual sel API added in pinmux driver |
| MCUSDK-14569 | UART Errata i2310 is missing a step | UART | 10.00.00 onwards | AM263x, AM263Px | Added IIR register read to clear the interrupt |
| MCUSDK-14620 | SDK build fails in Mac Machines | Build | 10.02.00 onwards | AM263x, AM263Px | Added GMAC library for MAC into SDK |
| MCUSDK-14857, MCUSDK-14731 | Core 1 unhalted in SBL before FSM Trigger, Memory load | SBL | 10.00.00 onwards | AM263x, AM263Px | Skip unhalting core 1 of both clusters in dual core mode |
| MCUSDK-14695 | SDFM_configComparator has incorrect input in examples | SDFM | 10.00.00 onwards | AM263x, AM263Px | Updated example to pass correct value |
| MCUSDK-13153 | Self nesting of interrupts is not working | DPL | 09.01.00 onwards | AM263x, AM263Px | Added macros for handling self re-entrant IRQ |
| MCUSDK-11935 | DPL Low Latency Interrupt Application: controlfnc section missing in linker command | DPL | 09.00.00 onwards | AM263x, AM263Px | Added missing .controlfnc section in linker command file of DPL Low Latency Interrupt example |
| MCUSDK-14917 | "Selected mode" in pinmux.csv.xdt file not being updated correctly in SysCfg | Pinmux | 10.01.00 onwards | AM263x, AM263Px, AM261x | Fixed in Pinmux CSV template |
| PROC_SDL-9148 | ECC D-Data fail during release | SDL | 10.02.00 onwards | AM263x, AM263Px | Fixed in example |
| PROC_SDL-9160 | PBIST does not cover the VIM memories | SDL | 10.02.00 onwards | AM263x, AM263Px, AM261x | Fixed in Source and Used polling method instead of ISR to cover VIM memory |
| ID | Head Line | Module | Reported in release | Workaround |
| MCUSDK-13865 | HRPWM Deadband sfo example has 1ns jitter | EPWM | 10.00.00 onwards | - |
| MCUSDK-13201 | HRPWM waveform not generating (in updwon count) when prescaler is non-zero and HRPE is enabled | EPWM | 10.00.01 onwards | None |
| MCUSDK-13834 | EQEP: EQEP frequency measurement example is not working as expected | EQEP | 10.00.01 onwards | None |
| MCUSDK-13164 | AM263x: EPWM deadband example failure | EPWM | 09.02.00 | remove sync between the epwms and use the global tbclksync to synchronize the EPWMs |
| MCUSDK-7319 | CONTROLSS-SDFM: Two Back-to-Back Writes to SDCPARMx Register Bit Fields CEVT1SEL, CEVT2SEL, and HZEN Within Three SD-Modulator Clock Cycles can Corrupt SDFM State Machine, Resulting in Spurious Comparator Events | SDFM | 08.04.00 onwards | Avoid back-to-back writes within three SD-modulator clock cycles or have the SDCPARMx register bit fields configured in one register write. |
| MCUSDK-9082 | MbedTLS - RSA exploit by kernel-privileged cache side-channel attackers | Mbed-TLS | 08.06.00 onwards | - |
| MCUSDK-13011 | Multicore Empty project not working properly | FreeRTOS | 09.01.00 onwards | - |
| PINDSW-7715 | Dual EMAC instance not working with both ports together for icss_emac_lwip example | ICSS-EMAC | 09.02.00 onwards | None |
| PINDSW-7746 | icss_emac_lwip example having low iperf values in TCP and UDP | ICSS-EMAC | 09.02.00 onwards | None |
| PINDSW-8118 | Enabling DHCP mode in icss_emac_lwip example causes assert | ICSS-EMAC | 09.02.00 onwards | None |
| MCUSDK-12756 | MbedTLS - Timing side channel attack in RSA private operation exposing plaintext. | Mbed-TLS | 08.06.00 onwards | None |
| MCUSDK-13164 | AM263x: epwm deadband example validation failure | EPWM | 09.01.00 onwards | The Waveform of the EPWM is correct and is as expected. |
| MCUSDK-13202 | Frame drops are seen in PRU GPIO based SENT decoder example while sending frames in burst format | PRU-IO | 09.00.00 onwards | None |
| PROC_SDL-8392 | In ECC bus safety example, ECC error is not properly cleared at the source. | SDL | 08.06.00 onwards | None |
| PROC_SDL-8857 | SDL integrated example does not support ECC Bus Safety. | SDL | 10.01.00 onwards | Use standalone example. |
| MCUSDK-14898 | SDL apps fails on other than RFSS0-0 with SBL | SBL, SDL | 11.00.00 onwards | This because SBL brings the RFSS1-0 out of reset before the SBL UART prints gets flushed. This will be fixed in next release. As a workaround the application in R5FSS1-0 can delay the start of application till SBL UART prints gets completed. |
| MCUSDK-13652 | Readelf throws warning while parsing RS note | SBL, QSPI | Readelf command throws error when trying to read the RS note segment from an mcelf file. | - |
| MCUSDK-14509 | AM263x/Am263px/AM261x: 10% Packet drop with UDP iperf in 100M bandwidth in 1Gbps FullDuplex linkspeed | Networking | 10.00.00 onwards | - |
| MCUSDK-14883 | AM263x, AM263Px: SBL: RPRC descoping broke SBL over Ethernet example | Networking | 11.00.00 onwards | - |
| MCUSDK-14647 | All CANFD standard ID conigurations are not exposed in SysCfg | CAN | 10.02.00 onwards | Configure Config type, ID's,etc in application |
| MCUSDK-14714 | Bufnum of 6 and 12 will cause the vring indexes to get corrupted | IPC | 10.00.00 onwards | Use other VRING buffer numbers. |
| MCUSDK-14879 | Potential system hang issue due to priority mask based critical sections. | FreeRTOS | 10.00.00 onwards | Not to use Priority mask based critical sections (Disabled by default in SDK). |
| MCUSDK-14893 | Sub projects under system projects cannot be changed in CCS Theia | CCS | 11.00.00 onwards | - |
| MCUSDK-14895 | UART LLD Rx error checking logic checks if all errors exist at once | UART | 10.00.00 onwards | - |
| MCUSDK-13011 | Data Abort in application when all cores are running freertos using Gel files(CCS) | FreeRTOS | 10.00.00 onwards | Flash and use SBL NULL instead of gel files |
| MCUSDK-14914 | Unable to add UART communication port to target configuration in Theia | Real Time Debug | 10.02.00 onwards | Use the CCXML file from CCS eclipse after updating to correct COM port. |
| ID | Head Line | Module | SDK Status |
| i2311 | USART: Spurious DMA Interrupts | UART | Implemented |
| i2313 | GPMC: Sub-32-bit read issue with NAND and FPGA/FIFO | GPMC | Not supported in SDK |
| i2324 | No synchronizer present between GCM and GCD status signals | Common | Implemented |
| i2345 | CPSW: Ethernet Packet corruption occurs if CPDMA fetches a packet which spans across memory banks | CPSW | Implemented |
| i2350 | McSPI data transfer using EDMA in 'ABSYNC' mode stops after 32 bits transfer | McSPI | Implemented |
| i2354 | SDFM: Two Back-to-Back Writes to SDCPARMx Register Bit Fields CEVT1SEL, CEVT2SEL, and HZEN Within Three SD-Modulator Clock Cycles can Corrupt SDFM State Machine, Resulting in Spurious Comparator Events | SDFM | Open |
| i2375 | SDFM: SDFM module event flags (SDIFLG.FLTx_FLG_CEVTx) do not get set again if the comparator event is still active and digital filter path (using SDCOMPxCTL.CEVTxDIGFILTSEL) is being selected | SDFM | Open |
| i2355 | ADC: DMA Read of Stale Result | ADC | Implemented |
| i2356 | ADC: Interrupts may Stop if INTxCONT (Continue-to-Interrupt Mode) is not Set | ADC | Implemented |
| i2375 | SDFM module event flags (SDIFLG.FLTx_FLG_CEVTx) do not get set again if the comparator event is still active and digital filter path (using SDCOMPxCTL.CEVTxDIGFILTSEL) is being selected | SDFM | Open |
| i2392 | Race condition in capture registers resulting in events miss | Common | Open |
| i2394 | Race condition in interrupt and error aggregator capture registers resulting in events miss | Common | Updated error aggregator registers in EDMA. |
| i2401 | CPSW: Host Timestamps Cause CPSW Port to Lock up | CPSW | Open |
| i2402 | CPSW: Ethernet to Host Checksum Offload does not work | CPSW | Open |
| i2404 | Race condition in mailbox registers resulting in events miss | IPC | Implemented |
| i2405 | CONTROLSS: Race condition OUTPUT_XBAR and PWM_XBAR resulting in event miss | XBAR | Open |
Currently the gmac library packaged within SDK is compiled using gcc darwin23.6.0 on Apple MAC. To build SDK examples on a different toolchain, recompile the gmac library by using these steps:
RPRC image format is no longer supported and MCELF will be the only file format. Older SBL's and Cfg files which mapped to RPRC format are removed and replaced with MCELF variants. Below is the list of updated SBL's and Cfg files:
Please refer to the updated SDK example makefiles for Infra changes.
Previously our SDK had a mix of hardcoded clock configurations and limited configuration flexibility through sysconfig for the modules. With Clocktree, we now have a clear view of the entire clock tree with configurable components like PLL, DPLL, muxes, dividers added with validity checks. Earlier, the Input clock source and frequency for any module was configured through the module view in SysCfg. From now, this has to be done through clocktree.
SDK was supporting CCS Eclipse until this release and now been migrated to support CCS Theia Out of Box. Below sections describe how to update the applications for Eclipse if needed.
CCS Projectspec files are same for both Theia and Eclipse. Hence, no update is needed to import and build an SDK application on Eclipse.
JS Script for SBL loading on eclipse is updated to "load_sbl_eclipse.js". Please refer to CCS Tools for more details.
From 11.00.00 SDK all the libraries are built separately for OS. There are separate libraries available for NoRTOS and FreeROTS. So the makefiles needs to be updated accordingly. Please refer the sample changes on the makefile below. These changes are not applicbale for the librarries which were already built separately for NoRTOS/FreeRTOS like kernel libraries.
Additional macro OS_NORTOS or OS_FREERTOS should be defined on the makefile or CC project based on the OS of the project.
VIM Memory groups are added to PBIST self test from this release. Because of this change, Self test (SDL_PBIST_selfTest) API has to be called in polling mode only and interrupt mode is not supported.
1.8.20