| Module | Supported CPUs | SysConfig Support | OS support | Key features tested | Key features not tested / NOT supported |
| Cache | R5F | YES | FreeRTOS, NORTOS | Cache write back, invalidate, enable/disable | - |
| Clock | R5F | YES | FreeRTOS, NORTOS | Tick timer at user specified resolution, timeouts and delays | - |
| CpuId | R5F | NA | FreeRTOS, NORTOS | Verify Core ID and Cluster ID that application is currently running on | - |
| CycleCounter | R5F | NA | FreeRTOS, NORTOS | Measure CPU cycles using CPU specific internal counters | - |
| Debug | R5F | YES | FreeRTOS, NORTOS | Logging and assert to any combo of: UART, CCS, shared memory | - |
| Heap | R5F | NA | FreeRTOS, NORTOS | Create arbitrary heaps in user defined memory segments | - |
| Hwi | R5F | YES | FreeRTOS, NORTOS | Interrupt register, enable/disable/restore, Interrupt prioritization | - |
| MPU | R5F | YES | FreeRTOS, NORTOS | Setup MPU and control access to address space | - |
| Semaphore | R5F | NA | FreeRTOS, NORTOS | Binary, Counting Semaphore, recursive mutexs with timeout | - |
| Task | R5F | NA | FreeRTOS | Create, delete tasks | - |
| Timer | R5F | YES | FreeRTOS, NORTOS | Configure arbitrary timers | - |
| Peripheral | Supported CPUs | SysConfig Support | DMA Supported | Key features tested | Key features not tested / NOT supported |
| ADC | R5F | YES | Yes. Example: adc_soc_continuous_dma | Single software triggered conversion, Multiple ADC trigger using PWM, Result read using DMA, EPWM trip through PPB limit, PPB features, Burst mode, Single and Differential mode, Interrupt with Offset from Aquisition Window, EPWM/ECAP/RTI triggered conversions | - |
| Bootloader | R5F | YES | Yes. DMA enabled for SBL QSPI | Boot modes: QSPI, UART. All R5F's | - |
| CMPSS | R5F | YES | NA | Asynchronous PWM trip, Digital Filter | - |
| CPSW | R5F | YES | No | MAC loopback, PHY loopback, LWIP: Getting IP, Ping, Iperf, Layer 2 MAC, Layer 2 PTP Timestamping and Ethernet CPSW Switch support, TSN stack | RMII, MII mode |
| DAC | R5F | YES | Yes. Example: dac_sine_dma | Constant voltage, Square wave generation, Sine wave generation with and without DMA, Ramp wave generation, Random Voltage generation | - |
| ECAP | R5F | YES | yes. Example : ecap_edma | ECAP APWM mode, PWM capture, DMA trigger in both APWM and Capture Modes | - |
| EDMA | R5F | YES | NA | DMA transfer using interrupt and polling mode, QDMA Transfer, Channel Chaining, PaRAM Linking | - |
| EPWM | R5F | YES | Yes. Example: epwm_dma | PWM outputs A and B in up-down count mode, Trip zone, Update PWM using EDMA, Valley switching, High resolution time period adjustment, type5 feature | - |
| EQEP | R5F | YES | NA | Speed and Position measurement. Frequency Measurement | - |
| FSI | R5F | YES | Yes. Example: fsi_loopback_dma | RX, TX, polling, interrupt mode, Dma, single lane loopback. | - FSI Spi Mode |
| GPIO | R5F | YES | NA | Output, Input and Interrupt functionality | - |
| I2C | R5F | YES | No | Controller mode, basic read/write | - |
| IPC Notify | R5F | YES | NA | Mailbox functionality, IPC between RTOS/NORTOS CPUs | M4F core |
| IPC Rpmsg | R5F | YES | NA | RPMessage protocol based IPC | M4F core |
| MCAN | R5F | YES | No | RX, TX, interrupt and polling mode, Corrupt Message Transmission Prevention, Error Passive state, Bus Off State, Bus Monitoring Mode | - |
| MCSPI | R5F | YES | Yes. Example: mcspi_loopback_dma | Controller/Peripheral mode, basic read/write, polling, interrupt and DMA mode | - |
| MDIO | R5F | YES | NA | Register read/write, link status and link interrupt enable API | - |
| MPU Firewall | R5F | YES | NA | Only compiled (Works only on HS-SE device) | - |
| MMCSD | R5F | YES | NA | MMCSD 4bit, Raw read/write | - file IO, eMMC |
PINMUX | R5F | YES | NA | Tested with multiple peripheral pinmuxes PMU | R5F | NO | NA | Tested various PMU events | Counter overflow detection is not enabled | - PRUICSS | R5F | YES | NA | Tested with Ethercat FW HAL | - QSPI | R5F | YES | Yes. Example: qspi_flash_dma_transfer | Read direct, Write indirect, Read/Write commands, DMA for read | - RTI | R5F | YES | No | Counter read, timebase selction, comparator setup for Interrupt, DMA requests | Capture feature, fast enabling/disabling of events not tested SDFM | R5F | YES | Yes. Example: sdfm_filter_sync_dmaread| Filter data read from CPU, Filter data read with PWM sync | - SOC | R5F | YES | NA | Lock/unlock MMRs, clock enable, set Hz, Xbar configuration, SW Warm Reset, Address Translation | - SPINLOCK | R5F | NA | NA | Lock, unlock HW spinlocks | - UART | R5F | YES | Yes. Example: uart_echo_dma | Basic read/write at baud rate 115200, polling, interrupt mode | HW flow control not tested, DMA mode not supported WATCHDOG | R5F | YES | NA | Reset mode, Interrupt mode | -
| Module | Supported CPUs | SysConfig Support | OS Support | Key features tested | Key features not tested |
| Time-Sensitive Networking(gPTP-IEEE 802.1AS) | R5F | NO | FreeRTOS | gPTP IEEE 802.1 AS-2020 compliant gPTP stack, End Nodes and Bridge mode support, YANG data model configuration | Multi-Clock Domain |
| LwIP | R5F | YES | FreeRTOS | TCP/UDP IP networking stack with and without checksum offload enabled, TCP/UDP IP networking stack with server and client functionality, basic Socket APIs, netconn APIs and raw APIs, DHCP, ping, TCP iperf, scatter-gather, DSCP priority mapping | Other LwIP features |
| Ethernet driver (ENET) | R5F | YES | FreeRTOS | Ethernet as port using CPSW, MAC loopback and PHY loopback, Layer 2 MAC, Packet Timestamping, CPSW Switch, CPSW EST, interrupt pacing, Policer and Classifier, MDIO Manual Mode, Credit Based Shaper (IEEE 802.1Qav), Strapped PHY (Early Ethernet) | RMII, MII mode |
| ICSS-EMAC | R5F | YES | FreeRTOS | Switch and MAC features, Storm Prevention (MAC), Host Statistics, Multicast Filtering | Promiscuous Mode |
| Mbed-TLS | R5F | NO | FreeRTOS | Tested software cryptography after porting, used mbedTLS with LwIP to implement HTTPS server | Hardware offloaded cryptography |
| Module | Supported CPUs | SysConfig Support | OS support | Key features tested | Key features not tested / NOT supported |
| MCRC | R5F | NA | NORTOS | Full CPU, Auto CPU Mode and Semi CPU Auto Mode | - |
| DCC | R5F | NA | NORTOS | Single Shot and Continuous modes | - |
| PBIST | R5F | NA | NORTOS | Memories supported by MSS PBIST controller. | - |
| ESM | R5F | NA | NORTOS | Tested in combination with RTI, DCC | - |
| RTI | R5F | NA | NORTOS | WINDOWSIZE_100_PERCENT, WINDOWSIZE_50_PERCENT ,Latency/Propagation timing error(early)(50% window),Latency/Propagation timing error(late)(50% window) | - |
| ECC | R5F | NA | NORTOS | ECC of MSS_L2, R5F TCM, MCAN, VIM, ICSSM, TPTC | R5F data Cache(DED) |
| ECC Bus Safety | R5F | NA | NORTOS | AHB, AXI, TPTC | - |
| CCM | R5F | NA | NORTOS | CCM Self Test Mode,Error Forcing Mode and Self Test Error Forcing Mode. | - |
| R5F STC(LBIST), Static Register Read | R5F | NA | NORTOS | STC of R5F, R5F CPU Static Register Read | - |
| ID | Head Line | Module | Applicable Releases | Applicable Devices | Resolution/Comments |
| PROC_SDL-7347 | MCRC does not provide API to configure data width, CRC algo etc. | MCRC | 08.06.00 Onwards | AM263x, AM263Px | |
| PROC_SDL-6910 | Update to move some of the non static registers. | R5F CPU UTILS | 09.00.00 Onwards | AM263x, AM263Px | Updated R5F UTILS structure to move some of the non static registers. |
| PROC_SDL-5979 | ECC test on R5F cache memories needed to be implemented. | ECC on Cache memory | 08.06.00 Onwards | AM263x | Added examples for ECC test on R5F cache memories. |
| MCUSDK-13491 | API EPWM_setActionQualifierShadowLoadMode does not set Shadow Mode | EPWM | 09.02.00 | AM263x, AM263Px | |
| MCUSDK-13199 | EPWM : HRPWM_setHiResCounterCompareValue writes incorrect value | EPWM | 09.02.00 | AM263x, AM263Px | |
| PINDSW-8097 | Wrong PHY Config when using the QSPI Boot mode | ICSS-EMAC | 09.02.00 Onwards | AM263x, AM263Px | Fixed the application intiialization sequence and added required delay for PHY Powerup to SMI ready. |
| MCUSDK-13531 | UART DMA transfer fail | UART | 09.02.00 Onwards | AM263x, AM263Px | Added typecasting for UART Transaction in driver. |
| MCUSDK-13427 | McSPI 3 Pin mode failure in DMA mode | McSPI | 09.02.00 Onwards | AM263x, AM263Px | Update XBAR config in 3 Pin mode. |
| MCUSDK-13275 | UART Clock selection missing options in SysCfg | UART | 09.02.00 Onwards | AM263x, AM263Px | Updated SysCfg module to add UART clock selection. |
| MCUSDK-13210 | GPMC PSRAM IO failure | GPMC | 09.02.00 Onwards | AM263x | BP Input pin pulled down in GPIO SysCfg. |
| MCUSDK-12651 | Data flush missing DMA mode | UART | 09.02.00 Onwards | AM263x, AM263Px | Added Data flush in UART DMA TX ISR. |
| MCUSDK-9459 | UART DMA transfer fail for Trigger level > 1 | UART | 09.02.00 Onwards | AM263x, AM263Px | Added trigger level selection support in SysCfg. |
| ID | Head Line | Module | Reported in release | Workaround |
| MCUSDK-13702 | am263x-lp: sbl sd not working for multicore appimages | MMCSD, SBL | 10.00.00 | - |
| MCUSDK-13164 | AM263x: EPWM deadband example failure | EPWM | 09.02.00 | remove sync between the epwms and use the global tbclksync to synchronize the EPWMs |
| MCUSDK-13641, CODEGEN-12832 | Increased build time for examples using Link Time Optimization (-flto) with TI-ARM-CLANG 4.0.0 LTS | Build | 10.00.00 onwards | - |
| MCUSDK-7319 | CONTROLSS-SDFM: Two Back-to-Back Writes to SDCPARMx Register Bit Fields CEVT1SEL, CEVT2SEL, and HZEN Within Three SD-Modulator Clock Cycles can Corrupt SDFM State Machine, Resulting in Spurious Comparator Events | SDFM | 08.04.00 onwards | Avoid back-to-back writes within three SD-modulator clock cycles or have the SDCPARMx register bit fields configured in one register write. |
| MCUSDK-9082 | MbedTLS - RSA exploit by kernel-privileged cache side-channel attackers | Mbed-TLS | 08.06.00 onwards | - |
| MCUSDK-11730 | A wrong counter is used for Event 2 in PMU configuration | PMU | 09.00.00 onwards | - |
| MCUSDK-13111 | Memory Configurator/syscfg auto-linker generator doesn't support reordering | Build | 09.01.00 onwards | - |
| MCUSDK-13109 | RTI Interrupt req is pulse type and not level type | RTI | 09.01.00 onwards | - |
| MCUSDK-13014 | The memory read feature of uniflash erases the memory | Flash | 09.01.00 onwards | - |
| MCUSDK-13011 | Multicore Empty project not working properly | FreeRTOS | 09.01.00 onwards | - |
| MCUSDK-12986 | FreeRTOS: Barrier instructions missing in Interrupt Disable/Enable API's | FreeRTOS | 09.01.00 onwards | - |
| PINDSW-7715 | Dual EMAC instance not working with both ports together for icss_emac_lwip example | ICSS-EMAC | 09.02.00 onwards | None |
| PINDSW-7746 | icss_emac_lwip example having low iperf values in TCP and UDP | ICSS-EMAC | 09.02.00 onwards | None |
| PINDSW-8118 | Enabling DHCP mode in icss_emac_lwip example causes assert | ICSS-EMAC | 09.02.00 onwards | None |
| PROC_SDL-5979 | R5F Cache ECC diagnostics are not supported. | SDL | 8.5.0 onwards | None. |
| MCUSDK-12756 | MbedTLS - Timing side channel attack in RSA private operation exposing plaintext. | Mbed-TLS | 08.06.00 onwards | None |
| MCUSDK-13164 | AM263x: epwm deadband example validation failure | EPWM | 09.01.00 onwards | The Waveform of the EPWM is correct and is as expected. |
| PROC_SDL-7615 | ECC example fails for SEC and DED for TPTC memories. | SDL | 09.02.00 onwards | None |
| MCUSDK-13202 | Frame drops are seen in PRU GPIO based SENT decoder example while sending frames in burst format | PRU-IO | 09.00.00 onwards | None |
| PROC_SDL-8392 | In ECC bus safety example, ECC error is not properly cleared at the source. | SDL | 08.06.00 onwards | None |
| PROC_SDL-8393 | In ECC bus safety, error injection test writes to address 0x0. | SDL | 08.06.00 onwards | None |
| PROC_SDL-8519 | In ECC for R5F data cache only, double bit test is not supported. | SDL | 10.00.00 onwards | ECC test for single bit injection on R5F data cache, release profile binary is showing some inconsistency on result. |
| PROC_SDL-8518 | Integrated example should have checked ECC for TPTC, ATCM, BTCM memories. | SDL | 10.00.00 onwards | None. |
| MCUSDK-13466 | UART Transfer fails in 10MHz Auto Baud mode | UART | 10.00.00 onwards | Use different mode for 10MHz clock |
| MCUSDK-13193 | SBL SD transfer time increased w.r.t SDK 9.2 | SBL | 10.00.00 onwards | None. |
| MCUSDK-13511 | MPU region count incorrect in SysCfg | MPU Firewall | 09.02.00 onwards | None. |
| MCUSDK-13473 | UART uniflash script fails with large images ( > 1MB) | SBL | 10.00.00 onwards | Use JTAG based flashing |
| MCUSDK-11730 | A wrong counter is used for Event 2 in PMU configuration | PMU | 10.00.00 onwards | Comment out the code in PMU_init() whcih configures Cycle Counter. |
| MCUSDK-13630 | Cache should not be enabled at L2 Bank boundaries | Cache | Cache should not be enabled at last 32Bytes of L2 Bank | Create MPU configurations for end of each L2 Bank with Non Cached attribute |
| MCUSDK-13165 | SBL QSPI flow has incorrect addressing for Secure Boot flow | SBL, QSPI | SBL QSPI flow has incorrect addressing for Secure Boot flow since it expects MEMMAP configuration | Use MCELF Image format |
| MCUSDK-13652 | Readelf throws warning while parsing RS note | SBL, QSPI | Readelf command throws error when trying to read the RS note segment from an mcelf file. | - |
| ID | Head Line | Module | SDK Status |
| i2311 | USART: Spurious DMA Interrupts | UART | Implemented |
| i2313 | GPMC: Sub-32-bit read issue with NAND and FPGA/FIFO | GPMC | Not supported in SDK |
| i2324 | No synchronizer present between GCM and GCD status signals | Common | Implemented |
| i2345 | CPSW: Ethernet Packet corruption occurs if CPDMA fetches a packet which spans across memory banks | CPSW | Implemented |
| i2350 | McSPI data transfer using EDMA in 'ABSYNC' mode stops after 32 bits transfer | McSPI | Implemented |
| i2354 | SDFM: Two Back-to-Back Writes to SDCPARMx Register Bit Fields CEVT1SEL, CEVT2SEL, and HZEN Within Three SD-Modulator Clock Cycles can Corrupt SDFM State Machine, Resulting in Spurious Comparator Events | SDFM | Open |
| i2355 | ADC: DMA Read of Stale Result | ADC | Implemented |
| i2356 | ADC: Interrupts may Stop if INTxCONT (Continue-to-Interrupt Mode) is not Set | ADC | Implemented |
| i2375 | SDFM module event flags (SDIFLG.FLTx_FLG_CEVTx) do not get set again if the comparator event is still active and digital filter path (using SDCOMPxCTL.CEVTxDIGFILTSEL) is being selected | SDFM | Open |
| i2392 | Race condition in capture registers resulting in events miss | Common | Open |
| i2394 | Race condition in interrupt and error aggregator capture registers resulting in events miss | Common | Open |
| i2401 | CPSW: Host Timestamps Cause CPSW Port to Lock up | CPSW | Open |
| i2402 | CPSW: Ethernet to Host Checksum Offload does not work | CPSW | Open |
| i2404 | Race condition in mailbox registers resulting in events miss | IPC | Implemented |
| i2405 | CONTROLSS: Race condition OUTPUT_XBAR and PWM_XBAR resulting in event miss | XBAR | Open |
| Module | Affected API | Change | Additional Remarks |
| Sysconfig | EPWM | TBCLKSYNC and Halt configurations moved to ti_drivers_open_close.c | The TBCLKSYNC should be not enabled until the init configurations are done. The individual control to enable the tbclksyn in the init or not is added. Refer to SOC_setMultipleEpwmTbClk for usage in the applications. |
| Sysconfig | ADC | Added Internal Refernece enable controls | Default is set as enabled, to maintain backward compatibility |
| ADC | SOC_enableAdcInternalReference, SOC_enableAdcReferenceMonitor, SOC_getAdcReferenceStatus | Added Internal Refernece enable controls in drivers | Reference monitoring status should be checked before powering up the ADC analog converter. |
| EPWM | EPWM_setActionQualifierShadowLoadMode | updated parenthesis for API operations | - |
| EPWM | HRPWM_setHiResCounterCompareValue | Updated the Assert check. Fixed Overwriting to the CMPx register. | - |
| Security | HSM Client, Secure IPC Notify, Crypto driver | These drivers are moved to "source/security/security_common". All drivers will be part of security libs. | Update the include paths and included libraries for application build. |
1.8.20