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AM263x MCU+ SDK
09.00.00
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34 #ifndef CSLR_SOC_DEFINES_H_
35 #define CSLR_SOC_DEFINES_H_
52 #define CSL_UART_PER_CNT (6U)
55 #define CSL_SPI_PER_CNT (5U)
58 #define CSL_LIN_PER_CNT (5U)
61 #define CSL_I2C_PER_CNT (4U)
64 #define CSL_MCAN_PER_CNT (4U)
67 #define CSL_ETPWM_PER_CNT (32U)
70 #define CSL_ECAP_PER_CNT (10U)
73 #define CSL_EQEP_PER_CNT (3U)
76 #define CSL_SDFM_PER_CNT (2U)
79 #define CSL_ADC_PER_CNT (5U)
82 #define CSL_CMPSSA_PER_CNT (10U)
85 #define CSL_CMPSSB_PER_CNT (10U)
88 #define SOC_EDMA_NUM_DMACH (64U)
90 #define SOC_EDMA_NUM_QDMACH (8U)
92 #define SOC_EDMA_NUM_PARAMSETS (256U)
94 #define SOC_EDMA_NUM_EVQUE (2U)
96 #define SOC_EDMA_CHMAPEXIST (1U)
98 #define SOC_EDMA_NUM_REGIONS (8U)
100 #define SOC_EDMA_MEMPROTECT (1U)
102 #define MCAN_MSG_RAM_MAX_WORD_COUNT (4352U)
110 #define CSL_CORE_ID_R5FSS0_0 (0U)
111 #define CSL_CORE_ID_R5FSS0_1 (1U)
112 #define CSL_CORE_ID_R5FSS1_0 (2U)
113 #define CSL_CORE_ID_R5FSS1_1 (3U)
114 #define CSL_CORE_ID_MAX (4U)
123 #define PRIV_ID_M4FSS0_0 (1U)
124 #define PRIV_ID_R5FSS0_0 (4U)
125 #define PRIV_ID_R5FSS0_1 (5U)
126 #define PRIV_ID_R5FSS1_0 (6U)
127 #define PRIV_ID_R5FSS1_1 (7U)
128 #define PRIV_ID_ICSSM (9U)
129 #define PRIV_ID_CPSW (10U)
137 #define MSS_SYS_VCLK 200000000U
138 #define R5F_CLOCK_MHZ 400U
147 #define CSL_ARM_R5_CLUSTER_GROUP_ID_0 ((uint32_t) 0x00U)
149 #define CSL_ARM_R5_CLUSTER_GROUP_ID_1 ((uint32_t) 0x01U)
159 #define CSL_ARM_R5_CPU_ID_0 ((uint32_t) 0x00U)
161 #define CSL_ARM_R5_CPU_ID_1 ((uint32_t) 0x01U)
168 #if (__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R')
169 #define CSL_CACHE_L1P_LINESIZE (32U)
170 #define CSL_CACHE_L1D_LINESIZE (32U)
171 #elif (__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'M')