In this example ePWM uses Minimum Deadband to do various operations on the signal coming to the MDL block.
We will be using some terminologies like EPWMxA_DE.sclk and EPWMxA_DE. The reference diagrams at the end can be referred for understanding. Note that DEPWMA(B).sclk and EPWMxA(B)_DE.sclk are used interchangeably. Same for DEPWMA(B) and EPWMxA(B)_DE.
The screenshots attached in the documentation are as per the results obtained by executing the example on CC. Please note that there are some instance differences between CC and LP.
The mapping is such that:
EPWM0A(B) on CC <--> EPWM0A(B) on LP
EPWM1A(B) on CC <--> EPWM1A(B) on LP
EPWM2A(B) on CC <--> EPWM2A(B) on LP
EPWM3A(B) on CC <--> EPWM3A(B) on LP
EPWM4A(B) on CC <--> EPWM9A(B) on LP
EPWM6A(B) on CC <--> EPWM12A(B) on LP
We can introduce a falling edge delay on the same signal.
In our example, EPWM3A is used as the reference for comparing with EPWM2A. EPWM3A has all configurations same as EPWM2A but with MDL disabled.
The first waveform shows the signal before entering into the MINDB logic block. The second one shows the BLOCK signal which is falling edge stretched version of the reference signal. The third shows OR-ed result of BLOCK and the original signal that comes out of the MDL block. The shift in the falling edge (marked in red) is 10 Us.
Note that there's no way to tap the first 2 waveforms from inside the block. We have configured one ePWM instance with same configuration other than the MDL enabled just for reference.
We can introduce a rising edge delay on the same signal.
In our example, EPWM3B is used as the reference for comparing with EPWM2B. EPWM3B has all configurations same as EPWM2B but with MDL disabled.
The first waveform shows the signal before entering into the MINDB logic block. The second one shows the BLOCK signal which is the falling edge stretched and inverted version of the reference signal. The third shows inverted BLOCK signal AND-ed with the original signal to get a shift in the rising edge (marked in green). The value of it is 15 Us.
We can delay the occurrence of rising edge of one signal wrt the falling edge of another signal.
In our example, EPWM1A/B are used as the references for comparing with EPWM0A/B. EPWM1A/B have all configurations same as EPWM0A/B but with MDL disabled.
In this case, the upper 2 signals show channel A and B output before entering the MDL logic. They are complementary to each other. With help of MDL, we can delay the rising of B by some amount wrt falling edge of A (marked in blue). Similarly, we can delay the rising of A by some amount wrt falling edge of B (marked in orange). In order to achieve this, we can do the following configuration: For output channel A:
For better understanding on how the block signal A is applied on output channel B, the below diagram can be referred.
The second waveform shows the block signal: which is the falling edge stretched of reference signal i.e. EPWM0A before entering MDL and then inverting it. This is then AND-ed with EPWM0B to get the forth waveform i.e. EPWM0B after MDL.
Delay the rising edge wrt the rising edge of the other channel.
In our example, EPWM3A/B are used as the references for comparing with EPWM4A/B. EPWM3A/B have all configurations same as EPWM4A/B but with MDL disabled.
This is similar to Case 2 where the Block signal is applied on itself but here EPWMxB can use the BLOCKA as its blocking signal.
Till now all cases were based on channel A and B of the same epwm instance. This case shows that we can even add delay wrt to signal of some other output channel belonging to some other instance.
The second waveform is generated by EPWM6B.
The EPWM6_A before entering into MDL is shown in the second waveform. Inside EPWM6_A, we have taken the reference signal for block signal as EPWM3_A (the first waveform). Then added delay of 4000 i.e. 20 Us wrt falling edge of EPWM3_A. The rising edge of EPWM6_A occurs only after this delay. Till then it is pulled low by the BLOCK signal. We select EPWM3A_sclk as the output for MDLXBAR_1.
When using AM263x-CC with TMDSHSECDOCK (HSEC180 controlCARD Baseboard Docking Station)
Parameter | Value |
---|---|
CPU + OS | r5fss0-0 nortos |
Toolchain | ti-arm-clang |
Board | am263x-cc, am263x-lp |
Example folder | examples/drivers/epwm/epwm_minimum_deadband/ |
Shown below is a sample output when the application is run,
PWMxA.sclk and PWMxB.sclk are tapped from the EPWM modules. These two signals are PWM signals which are tapped before the signals pass through the high resolution delay lines.
In our case, DEPWMA(B), DEPWMA(B).sclk are driven by PWMA(B) and PWMA(B).sclk respectively.