sdfm/v0/sdfm.h

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/********************************************************************
 * Copyright (C) 2021 Texas Instruments Incorporated.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
#ifndef SDFM_V0_H_
#define SDFM_V0_H_
 
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
 
#ifdef __cplusplus
extern "C"
{
#endif
 
//*****************************************************************************
//
//
//*****************************************************************************
 
#include <stdbool.h>
#include <stdint.h>
#include <drivers/hw_include/cslr_sdfm.h>
#include <drivers/hw_include/cslr_soc.h>
#include <drivers/hw_include/hw_types.h>
#include <kernel/dpl/DebugP.h>
 
//*****************************************************************************
//
// Defines for the API.
//
//*****************************************************************************
#define SDFM_GET_LOW_THRESHOLD(C)    ((uint16_t)(C))
 
#define SDFM_GET_HIGH_THRESHOLD(C)   ((uint16_t)((uint32_t)(C) >> 16U))
 
#define SDFM_GET_LOW_THRESHOLD_BOTH(C1, C2)                                   \
                        ((((uint32_t)(SDFM_GET_LOW_THRESHOLD(C2))) << 16U) |  \
                         ((uint32_t)(SDFM_GET_LOW_THRESHOLD(C1))))
 
#define SDFM_GET_HIGH_THRESHOLD_BOTH(C1, C2)                                  \
                        ((((uint32_t)(SDFM_GET_HIGH_THRESHOLD(C2))) << 16U) | \
                         ((uint32_t)(SDFM_GET_HIGH_THRESHOLD(C1))))
 
#define SDFM_SET_OSR(X)    (((X) - 1) << 8U)
 
#define SDFM_SHIFT_VALUE(X)    ((X) << 2U)
 
#define SDFM_THRESHOLD(H, L)    ((((uint32_t)(H)) << 16U) | (L))
 
#define SDFM_SET_FIFO_LEVEL(X)    ((X) << 7U)
 
#define SDFM_SET_ZERO_CROSS_THRESH_VALUE(X)    (0x8000 | (X))
 
#define SDFM_FILTER_DISABLE    (0x0U)
#define SDFM_FILTER_ENABLE    (0x2U)
 
//*****************************************************************************
//
// Defines for SDFM register offsets. Added for internal use. Not to be used by
// application.
//
//*****************************************************************************
#define SDFM_SDFIL_OFFSET    (CSL_SDFM_SDCTLPARM2 - CSL_SDFM_SDCTLPARM1)
 
#define SDFM_DIGFIL_OFFSET    (CSL_SDFM_SDCOMP2CTL - CSL_SDFM_SDCOMP1CTL)
 
#define SDFM_SDFLT1CMPHx_OFFSET    (CSL_SDFM_SDFLT1CMPH2 - CSL_SDFM_SDFLT1CMPH1)
 
#define SDFM_SDFLT1CMPLx_OFFSET    (CSL_SDFM_SDFLT1CMPL2 - CSL_SDFM_SDFLT1CMPL1)
 
//*****************************************************************************
//
// Define to mask out the bits in the SDCOMPHFILCTL register that aren't
// associated with comparator event filter configurations. Added for internal
// use, not to be used in application code.
//
//*****************************************************************************
#define SDFM_COMPEVT_FILTER_CONFIG_M  (CSL_SDFM_SDCOMP1EVT1FLTCTL_SAMPWIN_MASK  | \
                                       CSL_SDFM_SDCOMP1EVT1FLTCTL_THRESH_MASK)
 
//*****************************************************************************
//
// Define to mask out the bits in the SDCOMPLOCK register that aren't
// associated with lock configuration.  Added for internal use, not to be used
// in application code.
//
//*****************************************************************************
#define SDFM_COMPEVT_FILTER_LOCK_M  (SDFM_SDCOMPLOCK_SDCOMPCTL | \
                                     SDFM_SDCOMPLOCK_COMP)
 
//*****************************************************************************
//
// Values that can be passed to SDFM_enableSynchronizer() or
// SDFM_disableSynchronizer() as syncConfig parameter.
//
//*****************************************************************************
#define SDFM_CLOCK_SYNCHRONIZER    CSL_SDFM_SDCTLPARM1_SDCLKSYNC_MASK
#define SDFM_DATA_SYNCHRONIZER    CSL_SDFM_SDCTLPARM1_SDDATASYNC_MASK
 
//*****************************************************************************
//
//
//*****************************************************************************
#define SDFM_OUTPUT_WITHIN_THRESHOLD  (0)  
#define SDFM_OUTPUT_ABOVE_THRESHOLD  (1)  
#define SDFM_OUTPUT_BELOW_THRESHOLD  (2)  
 
//*****************************************************************************
//
//
//*****************************************************************************
#define SDFM_FILTER_1  (0)  
#define SDFM_FILTER_2  (1)  
#define SDFM_FILTER_3  (2)  
#define SDFM_FILTER_4  (3)  
 
//*****************************************************************************
//
//
//*****************************************************************************
#define SDFM_FILTER_SINC_FAST    (0x00)
#define SDFM_FILTER_SINC_1    (0x10)
#define SDFM_FILTER_SINC_2    (0x20)
#define SDFM_FILTER_SINC_3    (0x30)
 
//*****************************************************************************
//
//
//*****************************************************************************
#define SDFM_MODULATOR_CLK_EQUAL_DATA_RATE    (0)
 
//*****************************************************************************
//
//
//*****************************************************************************
#define SDFM_DATA_FORMAT_16_BIT    (0)
#define SDFM_DATA_FORMAT_32_BIT    (1)
 
//*****************************************************************************
//
//
//*****************************************************************************
#define SDFM_DATA_READY_SOURCE_DIRECT    (0)
#define SDFM_DATA_READY_SOURCE_FIFO    (1)
 
//*****************************************************************************
//
//
//*****************************************************************************
#define SDFM_SYNC_PWM0_SOCA   (0)   
#define SDFM_SYNC_PWM0_SOCB   (1)   
#define SDFM_SYNC_PWM1_SOCA   (2)   
#define SDFM_SYNC_PWM1_SOCB   (3)   
#define SDFM_SYNC_PWM2_SOCA   (4)   
#define SDFM_SYNC_PWM2_SOCB   (5)   
#define SDFM_SYNC_PWM3_SOCA   (6)   
#define SDFM_SYNC_PWM3_SOCB   (7)   
#define SDFM_SYNC_PWM4_SOCA   (8)   
#define SDFM_SYNC_PWM4_SOCB   (9)   
#define SDFM_SYNC_PWM5_SOCA   (10)  
#define SDFM_SYNC_PWM5_SOCB   (11)  
#define SDFM_SYNC_PWM6_SOCA   (12)  
#define SDFM_SYNC_PWM6_SOCB   (13)  
#define SDFM_SYNC_PWM7_SOCA   (14)  
#define SDFM_SYNC_PWM7_SOCB   (15)  
#define SDFM_SYNC_PWM8_SOCA   (16)  
#define SDFM_SYNC_PWM8_SOCB   (17)  
#define SDFM_SYNC_PWM9_SOCA   (18)  
#define SDFM_SYNC_PWM9_SOCB   (19)  
#define SDFM_SYNC_PWM10_SOCA  (20)  
#define SDFM_SYNC_PWM10_SOCB  (21)  
#define SDFM_SYNC_PWM11_SOCA  (22)  
#define SDFM_SYNC_PWM11_SOCB  (23)  
#define SDFM_SYNC_PWM12_SOCA  (24)  
#define SDFM_SYNC_PWM12_SOCB  (25)  
#define SDFM_SYNC_PWM13_SOCA  (26)  
#define SDFM_SYNC_PWM13_SOCB  (27)  
#define SDFM_SYNC_PWM14_SOCA  (28)  
#define SDFM_SYNC_PWM14_SOCB  (29)  
#define SDFM_SYNC_PWM15_SOCA  (30)  
#define SDFM_SYNC_PWM15_SOCB  (31)  
#define SDFM_SYNC_PWM16_SOCA  (32)  
#define SDFM_SYNC_PWM16_SOCB  (33)  
#define SDFM_SYNC_PWM17_SOCA  (34)  
#define SDFM_SYNC_PWM17_SOCB  (35)  
#define SDFM_SYNC_PWM18_SOCA  (36)  
#define SDFM_SYNC_PWM18_SOCB  (37)  
#define SDFM_SYNC_PWM19_SOCA  (38)  
#define SDFM_SYNC_PWM19_SOCB  (39)  
#define SDFM_SYNC_PWM20_SOCA  (40)  
#define SDFM_SYNC_PWM20_SOCB  (41)  
#define SDFM_SYNC_PWM21_SOCA  (42)  
#define SDFM_SYNC_PWM21_SOCB  (43)  
#define SDFM_SYNC_PWM22_SOCA  (44)  
#define SDFM_SYNC_PWM22_SOCB  (45)  
#define SDFM_SYNC_PWM23_SOCA  (46)  
#define SDFM_SYNC_PWM23_SOCB  (47)  
#define SDFM_SYNC_PWM24_SOCA  (48)  
#define SDFM_SYNC_PWM24_SOCB  (49)  
#define SDFM_SYNC_PWM25_SOCA  (50)  
#define SDFM_SYNC_PWM25_SOCB  (51)  
#define SDFM_SYNC_PWM26_SOCA  (52)  
#define SDFM_SYNC_PWM26_SOCB  (53)  
#define SDFM_SYNC_PWM27_SOCA  (54)  
#define SDFM_SYNC_PWM27_SOCB  (55)  
#define SDFM_SYNC_PWM28_SOCA  (56)  
#define SDFM_SYNC_PWM28_SOCB  (57)  
#define SDFM_SYNC_PWM29_SOCA  (58)  
#define SDFM_SYNC_PWM29_SOCB  (59)  
#define SDFM_SYNC_PWM30_SOCA  (60)  
#define SDFM_SYNC_PWM30_SOCB  (61)  
#define SDFM_SYNC_PWM31_SOCA  (62)  
#define SDFM_SYNC_PWM31_SOCB  (63)  
 
//*****************************************************************************
//
//
//*****************************************************************************
#define SDFM_FIFO_NOT_CLEARED_ON_SYNC    (0)
#define SDFM_FIFO_CLEARED_ON_SYNC    (1)
 
//*****************************************************************************
//
//
//*****************************************************************************
#define SDFM_MANUAL_CLEAR_WAIT_FOR_SYNC    (0)
#define SDFM_AUTO_CLEAR_WAIT_FOR_SYNC    (1)
 
//*****************************************************************************
//
//
//*****************************************************************************
#define SDFM_COMP_EVENT_1  CSL_SDFM_SDCPARM1_CEVT1SEL_SHIFT  
#define SDFM_COMP_EVENT_2  CSL_SDFM_SDCPARM1_CEVT2SEL_SHIFT  
 
//*****************************************************************************
//
//
//*****************************************************************************
#define SDFM_COMP_EVENT_SRC_COMPH1    (0)
#define SDFM_COMP_EVENT_SRC_COMPH1_L1    (1)
#define SDFM_COMP_EVENT_SRC_COMPH2    (2)
#define SDFM_COMP_EVENT_SRC_COMPH2_L2    (3)
#define SDFM_COMP_EVENT_SRC_COMPL1    (0)
#define SDFM_COMP_EVENT_SRC_COMPL2    (2)
 
//*****************************************************************************
//
//
//*****************************************************************************
#define SDFM_CLK_SOURCE_CHANNEL_CLK  (0x0)
#define SDFM_CLK_SOURCE_SD1_CLK  CSL_SDFM_SDCTLPARM1_SDCLKSEL_MASK
 
//*****************************************************************************
//
//
//*****************************************************************************
#define SDFM_COMPHOUT_SOURCE_COMPHIN    (0x0)
#define SDFM_COMPHOUT_SOURCE_FILTER    (0x8)
 
//*****************************************************************************
//
//
//*****************************************************************************
#define SDFM_COMPLOUT_SOURCE_COMPLIN    (0x000)
#define SDFM_COMPLOUT_SOURCE_FILTER    (0x800)
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef struct
{
    uint16_t sampleWindow; 
    uint16_t threshold;    
    uint16_t clkPrescale;  
} SDFM_CompEventFilterConfig;
 
//*****************************************************************************
//
// Values that can be passed to SDFM_enableInterrupt and SDFM_disableInterrupt
// as intFlags parameter
//
//*****************************************************************************
#define SDFM_MODULATOR_FAILURE_INTERRUPT    (0x200U)
#define SDFM_CEVT2_INTERRUPT    (0x40U)
#define SDFM_CEVT1_INTERRUPT    (0x20U)
#define SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT    (0x1U)
#define SDFM_FIFO_INTERRUPT    (0x1000U)
#define SDFM_FIFO_OVERFLOW_INTERRUPT    (0x8000U)
 
//*****************************************************************************
//
// Values that can be passed to SDFM_clearInterruptFlag flags parameter
//
//*****************************************************************************
#define SDFM_MASTER_INTERRUPT_FLAG    (0x80000000U)
#define SDFM_FILTER_1_HIGH_THRESHOLD_FLAG    (0x1U)
#define SDFM_FILTER_1_LOW_THRESHOLD_FLAG    (0x2U)
#define SDFM_FILTER_2_HIGH_THRESHOLD_FLAG    (0x4U)
#define SDFM_FILTER_2_LOW_THRESHOLD_FLAG    (0x8U)
#define SDFM_FILTER_3_HIGH_THRESHOLD_FLAG    (0x10U)
#define SDFM_FILTER_3_LOW_THRESHOLD_FLAG    (0x20U)
#define SDFM_FILTER_4_HIGH_THRESHOLD_FLAG    (0x40U)
#define SDFM_FILTER_4_LOW_THRESHOLD_FLAG    (0x80U)
#define SDFM_FILTER_1_MOD_FAILED_FLAG    (0x100U)
#define SDFM_FILTER_2_MOD_FAILED_FLAG    (0x200U)
#define SDFM_FILTER_3_MOD_FAILED_FLAG    (0x400U)
#define SDFM_FILTER_4_MOD_FAILED_FLAG    (0x800U)
#define SDFM_FILTER_1_NEW_DATA_FLAG    (0x1000U)
#define SDFM_FILTER_2_NEW_DATA_FLAG    (0x2000U)
#define SDFM_FILTER_3_NEW_DATA_FLAG    (0x4000U)
#define SDFM_FILTER_4_NEW_DATA_FLAG    (0x8000U)
#define SDFM_FILTER_1_FIFO_OVERFLOW_FLAG    (0x10000U)
#define SDFM_FILTER_2_FIFO_OVERFLOW_FLAG    (0x20000U)
#define SDFM_FILTER_3_FIFO_OVERFLOW_FLAG    (0x40000U)
#define SDFM_FILTER_4_FIFO_OVERFLOW_FLAG    (0x80000U)
#define SDFM_FILTER_1_FIFO_INTERRUPT_FLAG    (0x100000U)
#define SDFM_FILTER_2_FIFO_INTERRUPT_FLAG    (0x200000U)
#define SDFM_FILTER_3_FIFO_INTERRUPT_FLAG    (0x400000U)
#define SDFM_FILTER_4_FIFO_INTERRUPT_FLAG    (0x800000U)
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
SDFM_enableExternalReset(uint32_t base, uint32_t filterNumber)
{
    //
    // Set the SDSYNCEN bit
    //
    HW_WR_REG16((base + CSL_SDFM_SDDFPARM1 +
        ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET)),
        HW_RD_REG16(base + CSL_SDFM_SDDFPARM1 +
        ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET)) |
        CSL_SDFM_SDDFPARM1_SDSYNCEN_MASK);
}
 
//*****************************************************************************
//
//*****************************************************************************
static inline void
SDFM_disableExternalReset(uint32_t base, uint32_t filterNumber)
{
    //
    // Clear the SDSYNCEN bit
    //
    HW_WR_REG16((base + CSL_SDFM_SDDFPARM1 +
        ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET)),
        HW_RD_REG16(base + CSL_SDFM_SDDFPARM1 +
        ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET)) &
        ~CSL_SDFM_SDDFPARM1_SDSYNCEN_MASK);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
SDFM_enableFilter(uint32_t base, uint32_t filterNumber)
{
    //
    // Set the FEN bit
    //
    HW_WR_REG16((base + CSL_SDFM_SDDFPARM1 +
        ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET)),
        HW_RD_REG16(base + CSL_SDFM_SDDFPARM1 +
        ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET)) |
        CSL_SDFM_SDDFPARM1_FEN_MASK);
}
 
//*****************************************************************************
//
//*****************************************************************************
static inline void
SDFM_disableFilter(uint32_t base, uint32_t filterNumber)
{
    //
    // Clear the FEN bit
    //
    HW_WR_REG16(base + CSL_SDFM_SDDFPARM1 +
        ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET),
        HW_RD_REG16(base + CSL_SDFM_SDDFPARM1 +
        ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET)) &
        ~CSL_SDFM_SDDFPARM1_FEN_MASK);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
SDFM_enableFIFOBuffer(uint32_t base, uint32_t filterNumber)
{
    //
    // Set the FFEN bit
    //
    HW_WR_REG16(base + CSL_SDFM_SDFIFOCTL1 +
        ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET),
        HW_RD_REG16(base + CSL_SDFM_SDFIFOCTL1 +
        ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET)) |
        CSL_SDFM_SDFIFOCTL1_FFEN_MASK);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
SDFM_disableFIFOBuffer(uint32_t base, uint32_t filterNumber)
{
    //
    // Clear the FFEN bit
    //
    HW_WR_REG16(base + CSL_SDFM_SDFIFOCTL1 +
        ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET),
        HW_RD_REG16(base + CSL_SDFM_SDFIFOCTL1 +
        ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET)) &
        ~CSL_SDFM_SDFIFOCTL1_FFEN_MASK);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline bool
SDFM_getZeroCrossTripStatus(uint32_t base, uint32_t filterNumber)
{
    return(((HW_RD_REG16(base + CSL_SDFM_SDSTATUS) >> (uint16_t)filterNumber) &
            0x1U) == 1U);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
SDFM_clearZeroCrossTripStatus(uint32_t base, uint32_t filterNumber)
{
    //
    // Set SDCTL MIE bit
    //
    HW_WR_REG16((base + CSL_SDFM_SDCTL),
        HW_RD_REG16(base + CSL_SDFM_SDCTL) | (1U << filterNumber));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
SDFM_enableComparator(uint32_t base, uint32_t filterNumber)
{
    //
    // Set CEN bit
    //
    HW_WR_REG16((base + CSL_SDFM_SDCPARM1 +
        ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET)),
        HW_RD_REG16(base + CSL_SDFM_SDCPARM1 +
        ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET)) |
        CSL_SDFM_SDCPARM1_CEN_MASK);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
SDFM_disableComparator(uint32_t base, uint32_t filterNumber)
{
    //
    // Clear CEN bit
    //
    HW_WR_REG16((base + CSL_SDFM_SDCPARM1 +
        ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET)),
        HW_RD_REG16(base + CSL_SDFM_SDCPARM1 +
        ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET)) &
        ~CSL_SDFM_SDCPARM1_CEN_MASK);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
SDFM_selectCompEventSource(uint32_t base, uint32_t filterNumber,
                           uint32_t compEventNum,
                           uint32_t compEventSource)
{
    uint32_t address;
    address = base + CSL_SDFM_SDCPARM1 + ((uint32_t)filterNumber *
                                         SDFM_SDFIL_OFFSET);
 
    //
    // Select source for selected comparator event
    //
    HW_WR_REG16(address,
        (HW_RD_REG16(address) & ~((uint16_t)0x2U << compEventNum)) |
        ((uint16_t)compEventSource << compEventNum) );
}
 
//*****************************************************************************
//
//*****************************************************************************
static inline void
SDFM_setFilterType(uint32_t base, uint32_t filterNumber,
                   uint32_t filterType)
{
    uint32_t address;
 
    address = base + CSL_SDFM_SDDFPARM1 + ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET);
 
    //
    // Write to SST bits
    //
    HW_WR_REG16(address,
        (HW_RD_REG16(address) & (~CSL_SDFM_SDDFPARM1_SST_MASK)) |
        ((uint16_t)filterType << 6U));
}
 
//*****************************************************************************
//
//*****************************************************************************
static inline void
SDFM_setFilterOverSamplingRatio(uint32_t base, uint32_t filterNumber,
                                uint16_t overSamplingRatio)
{
    uint32_t address;
 
    DebugP_assert(overSamplingRatio < 256U);
 
    address = base + CSL_SDFM_SDDFPARM1 + ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET);
 
    //
    // Write to DOSR bits
    //
    HW_WR_REG16(address,
        (HW_RD_REG16(address) & (~CSL_SDFM_SDDFPARM1_DOSR_MASK)) | overSamplingRatio);
}
 
//*****************************************************************************
//
//*****************************************************************************
static inline void
SDFM_setupModulatorClock(uint32_t base, uint32_t filterNumber,
                         uint32_t clockMode)
{
    uint32_t address;
 
    address = base + CSL_SDFM_SDCTLPARM1 + ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET);
 
    //
    // Write to MOD bits
    //
    HW_WR_REG16(address, (HW_RD_REG16(address) & (~CSL_SDFM_SDCTLPARM1_MOD_MASK)) |
                      (uint16_t)clockMode);
 
    //
    // Enable data and clock synchronizer
    //
    HW_WR_REG16(base + CSL_SDFM_SDCTLPARM1 +
        ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET),
        HW_RD_REG16(base + CSL_SDFM_SDCTLPARM1 +
        ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET)) |
        (SDFM_CLOCK_SYNCHRONIZER | SDFM_DATA_SYNCHRONIZER));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
SDFM_setOutputDataFormat(uint32_t base, uint32_t filterNumber,
                         uint32_t dataFormat)
{
    uint32_t address;
 
    address = base + CSL_SDFM_SDDPARM1 + ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET);
 
    //
    // Write to DR bit
    //
    HW_WR_REG16(address, (HW_RD_REG16(address) & (~CSL_SDFM_SDDPARM1_DR_MASK)) |
                      ((uint16_t)dataFormat << 10U));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
SDFM_setDataShiftValue(uint32_t base, uint32_t filterNumber,
                       uint16_t shiftValue)
{
    uint32_t address;
 
    DebugP_assert(shiftValue < 32U);
 
    address = base + CSL_SDFM_SDDPARM1 + ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET);
 
    //
    // Write to SH bit
    //
    HW_WR_REG16(address, (HW_RD_REG16(address) & (~CSL_SDFM_SDDPARM1_SH_MASK)) |
                      (shiftValue << CSL_SDFM_SDDPARM1_SH_SHIFT));
}
 
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
SDFM_setCompFilterHighThreshold(uint32_t base, uint32_t filterNumber,
                                uint32_t highThreshold)
{
    uint32_t address;
 
    DebugP_assert((uint16_t)highThreshold <= CSL_SDFM_SDFLT1CMPH1_HLT_MASK);
    DebugP_assert((uint16_t)(highThreshold >> 16U) <= CSL_SDFM_SDFLT1CMPH2_HLT2_MASK);
 
    address = base + CSL_SDFM_SDFLT1CMPH1 +
              ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET);
 
    //
    // Write to HLT bit
    //
    HW_WR_REG16(address,
        (HW_RD_REG16(address) & ~CSL_SDFM_SDFLT1CMPH1_HLT_MASK) |
        (uint16_t)highThreshold);
    HW_WR_REG16(address + SDFM_SDFLT1CMPHx_OFFSET,
        (HW_RD_REG16(address + SDFM_SDFLT1CMPHx_OFFSET) &
        ~CSL_SDFM_SDFLT1CMPH2_HLT2_MASK) | (uint16_t)(highThreshold >> 16U));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
SDFM_setCompFilterLowThreshold(uint32_t base, uint32_t filterNumber,
                               uint32_t lowThreshold)
{
    uint32_t address;
 
    DebugP_assert((uint16_t)lowThreshold <= CSL_SDFM_SDFLT1CMPL1_LLT_MASK);
    DebugP_assert((uint16_t)(lowThreshold >> 16U) <= CSL_SDFM_SDFLT1CMPL2_LLT2_MASK);
 
    address = base + CSL_SDFM_SDFLT1CMPL1 +
              ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET);
 
    //
    // Write to LLT bit.
    //
    HW_WR_REG16(address, (HW_RD_REG16(address) & ~CSL_SDFM_SDFLT1CMPL1_LLT_MASK) |
                      (uint16_t)lowThreshold);
    HW_WR_REG16(address + SDFM_SDFLT1CMPLx_OFFSET,
        (HW_RD_REG16(address + SDFM_SDFLT1CMPLx_OFFSET) &
        ~CSL_SDFM_SDFLT1CMPL2_LLT2_MASK) | (uint16_t)(lowThreshold >> 16U));
}
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
SDFM_setCompFilterZeroCrossThreshold(uint32_t base,
                                     uint32_t filterNumber,
                                     uint16_t zeroCrossThreshold)
{
    uint32_t address;
 
    DebugP_assert(zeroCrossThreshold < 0x7FFFU);
 
    address = base + CSL_SDFM_SDFLT1CMPHZ + ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET);
 
    //
    // Write to ZCT bit
    //
    HW_WR_REG16(address,
        (HW_RD_REG16(address) & ~CSL_SDFM_SDFLT1CMPHZ_HLTZ_MASK) | zeroCrossThreshold);
 
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
SDFM_enableZeroCrossEdgeDetect(uint32_t base, uint32_t filterNumber)
{
    //
    // Set ZCEN bit
    //
    HW_WR_REG16(base + CSL_SDFM_SDCPARM1 +
        ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET),
        HW_RD_REG16(base + CSL_SDFM_SDCPARM1 +
        ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET)) |
        CSL_SDFM_SDCPARM1_HZEN_MASK);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
SDFM_disableZeroCrossEdgeDetect(uint32_t base, uint32_t filterNumber)
{
    //
    // Clear ZCEN bit
    //
    HW_WR_REG16(base + CSL_SDFM_SDCPARM1 +
        ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET),
        HW_RD_REG16(base + CSL_SDFM_SDCPARM1 +
        ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET)) &
        ~CSL_SDFM_SDCPARM1_HZEN_MASK);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
SDFM_enableInterrupt(uint32_t base, uint32_t filterNumber,
                     uint16_t intFlags)
{
    uint16_t offset;
 
    offset = (uint16_t)filterNumber * SDFM_SDFIL_OFFSET;
 
    //
    // Low, high threshold, Modulator failure
    //
    if((intFlags & (SDFM_MODULATOR_FAILURE_INTERRUPT |
                    SDFM_CEVT2_INTERRUPT |
                    SDFM_CEVT1_INTERRUPT)) != 0U)
    {
        //
        // Set IEL or IEH or MFIE bit of CSL_SDFM_SDCPARMx
        //
        HW_WR_REG16(base + CSL_SDFM_SDCPARM1 + offset,
            HW_RD_REG16(base + CSL_SDFM_SDCPARM1 + offset) |
            (intFlags & (SDFM_MODULATOR_FAILURE_INTERRUPT |
            SDFM_CEVT2_INTERRUPT |
            SDFM_CEVT1_INTERRUPT)));
    }
 
    //
    // Data filter acknowledge interrupt
    //
    if((intFlags & SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT) != 0U)
    {
        HW_WR_REG16(base + CSL_SDFM_SDDFPARM1 + offset,
            HW_RD_REG16(base + CSL_SDFM_SDDFPARM1 + offset) |
            CSL_SDFM_SDDFPARM1_AE_MASK);
    }
 
    //
    // FIFO , FIFO overflow interrupt
    //
    if((intFlags & (SDFM_FIFO_INTERRUPT | SDFM_FIFO_OVERFLOW_INTERRUPT)) != 0U)
    {
        //
        // Set OVFIEN or FFIEN bits of CSL_SDFM_SDFIFOCTLx
        //
        HW_WR_REG16(base + CSL_SDFM_SDFIFOCTL1 + offset,
            HW_RD_REG16(base + CSL_SDFM_SDFIFOCTL1 + offset) |
            (intFlags & (SDFM_FIFO_INTERRUPT | SDFM_FIFO_OVERFLOW_INTERRUPT)));
    }
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
SDFM_disableInterrupt(uint32_t base, uint32_t filterNumber,
                      uint16_t intFlags)
{
    uint16_t offset;
 
    offset = (uint16_t)filterNumber * SDFM_SDFIL_OFFSET;
 
    //
    // Low, high threshold, modulator failure interrupts
    //
    if((intFlags & (SDFM_MODULATOR_FAILURE_INTERRUPT |
                    SDFM_CEVT2_INTERRUPT |
                    SDFM_CEVT1_INTERRUPT)) != 0U)
    {
        //
        // Set IEL or IEH or MFIE bit of CSL_SDFM_SDCPARMx
        //
        HW_WR_REG16(base + CSL_SDFM_SDCPARM1 + offset,
            HW_RD_REG16(base + CSL_SDFM_SDCPARM1 + offset) &
            ~(intFlags & (SDFM_MODULATOR_FAILURE_INTERRUPT |
            SDFM_CEVT2_INTERRUPT |
            SDFM_CEVT1_INTERRUPT)));
    }
 
    //
    // Data filter acknowledge interrupt
    //
    if((intFlags & SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT) != 0U)
    {
        HW_WR_REG16(base + CSL_SDFM_SDDFPARM1 + offset,
            HW_RD_REG16(base + CSL_SDFM_SDDFPARM1 + offset) &
            ~CSL_SDFM_SDDFPARM1_AE_MASK);
    }
 
    //
    // FIFO , FIFO overflow interrupt
    //
    if((intFlags & (SDFM_FIFO_INTERRUPT | SDFM_FIFO_OVERFLOW_INTERRUPT)) != 0U)
    {
         //
         // Set OVFIEN or FFIEN bits of CSL_SDFM_SDFIFOCTLx
         //
         HW_WR_REG16(base + CSL_SDFM_SDFIFOCTL1 + offset,
            HW_RD_REG16(base + CSL_SDFM_SDFIFOCTL1 + offset) &
            ~(intFlags & (SDFM_FIFO_INTERRUPT | SDFM_FIFO_OVERFLOW_INTERRUPT)));
    }
}
 
//*****************************************************************************
//
//*****************************************************************************
static inline void
SDFM_setComparatorFilterType(uint32_t base, uint32_t filterNumber,
                             uint32_t filterType)
{
    uint32_t address;
 
    address = base + CSL_SDFM_SDCPARM1 + ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET);
 
    //
    // Write to CS1_CS0 bits
    //
    HW_WR_REG16(address,
        (HW_RD_REG16(address) & (~CSL_SDFM_SDCPARM1_CS1_CS0_MASK)) |
        ((uint16_t)filterType << 3U));
}
 
//*****************************************************************************
//
//*****************************************************************************
static inline void
SDFM_setCompFilterOverSamplingRatio(uint32_t base,
                                    uint32_t filterNumber,
                                    uint16_t overSamplingRatio)
{
    uint32_t address;
 
    DebugP_assert(overSamplingRatio < 32U);
 
    address = base + CSL_SDFM_SDCPARM1 + ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET);
 
    //
    // Write to COSR bits
    //
    HW_WR_REG16(address,
        (HW_RD_REG16(address) & (~CSL_SDFM_SDCPARM1_COSR_MASK)) |
        overSamplingRatio);
}
 
//*****************************************************************************
//
//*****************************************************************************
static inline uint32_t
SDFM_getFilterData(uint32_t base, uint32_t filterNumber)
{
    //
    // Read SDDATA bits
    //
    return(HW_RD_REG32(base + CSL_SDFM_SDDATA1 +
        ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET)));
}
 
//*****************************************************************************
//
//*****************************************************************************
static inline uint32_t
SDFM_getThresholdStatus(uint32_t base, uint32_t filterNumber)
{
    //
    // Read SDIFLG high/low threshold bits
    //
    return((uint32_t)((HW_RD_REG32(base + CSL_SDFM_SDIFLG) >>
            (2U * (uint16_t)filterNumber)) & 0x3U));
}
 
//*****************************************************************************
//
//*****************************************************************************
static inline bool
SDFM_getModulatorStatus(uint32_t base, uint32_t filterNumber)
{
    //
    // Read SDIFLG MF1, MF2, MF3 OR MF4 bits
    //
    return(((HW_RD_REG32(base + CSL_SDFM_SDIFLG) >>
          ((uint16_t)filterNumber + 8U)) & 0x1U) != 0x1U);
}
 
//*****************************************************************************
//
//*****************************************************************************
static inline bool
SDFM_getNewFilterDataStatus(uint32_t base, uint32_t filterNumber)
{
    //
    // Read SDIFLG AF1, AF2, AF3 OR AF4 bits
    //
    return(((HW_RD_REG32(base + CSL_SDFM_SDIFLG) >>
          ((uint16_t)filterNumber + 12U)) & 0x1U) == 0x1U);
}
 
//*****************************************************************************
//
//*****************************************************************************
static inline bool
SDFM_getFIFOOverflowStatus(uint32_t base, uint32_t filterNumber)
{
    //
    // Read SDIFLG SDFFOVF1, SDFFOVF2, SDFFOVF3 OR SDFFOVF4 bits
    //
    return(((HW_RD_REG32(base + CSL_SDFM_SDIFLG) >>
          ((uint16_t)filterNumber + 16U)) & 0x1U) == 0x1U);
}
 
//*****************************************************************************
//
//*****************************************************************************
static inline bool
SDFM_getFIFOISRStatus(uint32_t base, uint32_t filterNumber)
{
    //
    // Read SDIFLG SDFFINT1, SDFFINT2, SDFFINT3 OR SDFFINT4 bits
    //
    return(((HW_RD_REG32(base + CSL_SDFM_SDIFLG) >>
          ((uint16_t)filterNumber + 20U)) & 0x1U) == 0x1U);
}
 
//*****************************************************************************
//
//*****************************************************************************
static inline bool
SDFM_getIsrStatus(uint32_t base)
{
    //
    // Read SDIFLG MIF
    //
    return((HW_RD_REG32(base + CSL_SDFM_SDIFLG) >> 31U) == 0x1U);
}
 
//*****************************************************************************
//
//*****************************************************************************
static inline void
SDFM_clearInterruptFlag(uint32_t base, uint32_t flag)
{
    DebugP_assert((flag & 0x80FFFFFFU) == flag);
 
    //
    // Write to  SDIFLGCLR register
    //
    HW_WR_REG32((base + CSL_SDFM_SDIFLGCLR),
        HW_RD_REG32(base + CSL_SDFM_SDIFLGCLR) | flag);
}
 
//*****************************************************************************
//
//*****************************************************************************
static inline void
SDFM_enableMasterInterrupt(uint32_t base)
{
    //
    // Set SDCTL MIE bit
    //
    HW_WR_REG16(base + CSL_SDFM_SDCTL,
        HW_RD_REG16(base + CSL_SDFM_SDCTL) | CSL_SDFM_SDCTL_MIE_MASK);
}
 
//*****************************************************************************
//
//*****************************************************************************
static inline void
SDFM_disableMasterInterrupt(uint32_t base)
{
    //
    // Clear SDCTL MIE bit
    //
    HW_WR_REG16(base + CSL_SDFM_SDCTL,
        HW_RD_REG16(base + CSL_SDFM_SDCTL) & ~CSL_SDFM_SDCTL_MIE_MASK);
}
 
//*****************************************************************************
//
//*****************************************************************************
static inline void
SDFM_enableMasterFilter(uint32_t base)
{
    //
    // Set SDMFILEN MFE bit
    //
    HW_WR_REG16(base + CSL_SDFM_SDMFILEN,
        HW_RD_REG16(base + CSL_SDFM_SDMFILEN) | CSL_SDFM_SDMFILEN_MFE_MASK);
}
 
//*****************************************************************************
//
//*****************************************************************************
static inline void
SDFM_disableMasterFilter(uint32_t base)
{
    //
    // Clear SDMFILEN MFE bit
    //
    HW_WR_REG16(base + CSL_SDFM_SDMFILEN,
        HW_RD_REG16(base + CSL_SDFM_SDMFILEN) & ~CSL_SDFM_SDMFILEN_MFE_MASK);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline uint16_t
SDFM_getFIFODataCount(uint32_t base, uint32_t filterNumber)
{
    //
    // Read SDFFST
    //
    return((HW_RD_REG16(base + CSL_SDFM_SDFIFOCTL1 +
        ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET)) &
        CSL_SDFM_SDFIFOCTL1_SDFFST_MASK) >> CSL_SDFM_SDFIFOCTL1_SDFFST_SHIFT);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline uint16_t
SDFM_getComparatorSincData(uint32_t base, uint32_t filterNumber)
{
    //
    // Read SDCDATA
    //
    return(HW_RD_REG16(base + CSL_SDFM_SDCDATA1 +
          ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET)));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline uint32_t
SDFM_getFIFOData(uint32_t base, uint32_t filterNumber)
{
    //
    // Read SDDATFIFO
    //
    return(HW_RD_REG32(base + CSL_SDFM_SDDATFIFO1 +
          ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET)));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
SDFM_setFIFOInterruptLevel(uint32_t base, uint32_t filterNumber,
                           uint16_t fifoLevel)
{
    uint32_t address;
 
    DebugP_assert(fifoLevel <= 16U);
 
    address = base + CSL_SDFM_SDFIFOCTL1 + ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET);
 
    //
    // Write to SDFFIL bit
    //
    HW_WR_REG16(address,
        ((HW_RD_REG16(address) & (~CSL_SDFM_SDFIFOCTL1_SDFFIL_MASK)) | fifoLevel));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
SDFM_setDataReadyInterruptSource(uint32_t base, uint32_t filterNumber,
                                 uint32_t dataReadySource)
{
    uint32_t address;
 
    address = base + CSL_SDFM_SDFIFOCTL1 + ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET);
 
    //
    // Write to DRINTSEL
    //
    HW_WR_REG16(address,
        (HW_RD_REG16(address) & ~CSL_SDFM_SDFIFOCTL1_DRINTSEL_MASK) |
        ((uint16_t)dataReadySource << 14U));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline bool
SDFM_getWaitForSyncStatus(uint32_t base, uint32_t filterNumber)
{
    //
    // Read WTSYNFLG bit
    //
    return(((HW_RD_REG16(base + CSL_SDFM_SDSYNC1 +
        ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET)) &
        CSL_SDFM_SDSYNC1_WTSYNFLG_MASK) >> 7U) == 0x1U);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
SDFM_clearWaitForSyncFlag(uint32_t base, uint32_t filterNumber)
{
    //
    // Clear WTSYNCLR bit
    //
    HW_WR_REG16(base + CSL_SDFM_SDSYNC1 +
        ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET),
        HW_RD_REG16(base + CSL_SDFM_SDSYNC1 +
        ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET)) |
        CSL_SDFM_SDSYNC1_WTSYNCLR_MASK);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
SDFM_enableWaitForSync(uint32_t base, uint32_t filterNumber)
{
    //
    // Set WTSYNCEN bit
    //
    HW_WR_REG16(base + CSL_SDFM_SDSYNC1 +
        ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET),
        HW_RD_REG16(base + CSL_SDFM_SDSYNC1 +
        ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET)) |
        CSL_SDFM_SDSYNC1_WTSYNCEN_MASK);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
SDFM_disableWaitForSync(uint32_t base, uint32_t filterNumber)
{
    //
    // Clear WTSYNCEN bit
    //
    HW_WR_REG16(base + CSL_SDFM_SDSYNC1 +
        ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET),
        HW_RD_REG16(base + CSL_SDFM_SDSYNC1 +
        ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET)) &
        ~CSL_SDFM_SDSYNC1_WTSYNCEN_MASK);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
SDFM_setPWMSyncSource(uint32_t base, uint32_t filterNumber,
                      uint32_t syncSource)
{
    uint32_t address;
 
    address = base + CSL_SDFM_SDSYNC1 + ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET);
 
    //
    // Write to SYNCSEL bits
    //
    HW_WR_REG16(address,
        (HW_RD_REG16(address) & ~CSL_SDFM_SDSYNC1_SYNCSEL_MASK) |
        (uint16_t)syncSource);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
SDFM_setFIFOClearOnSyncMode(uint32_t base, uint32_t filterNumber,
                            uint32_t fifoClearSyncMode)
{
    uint32_t address;
 
    address = base + CSL_SDFM_SDSYNC1 + ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET);
 
    //
    // Write to FFSYNCCLREN bit
    //
    HW_WR_REG16(address,
        (HW_RD_REG16(address) & ~CSL_SDFM_SDSYNC1_FFSYNCCLREN_MASK) |
        ((uint16_t)fifoClearSyncMode << 9U));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
SDFM_setWaitForSyncClearMode(uint32_t base, uint32_t filterNumber,
                             uint32_t syncClearMode)
{
    uint32_t address;
 
    address = base + CSL_SDFM_SDSYNC1 + ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET);
 
    //
    // Write to WTSCLREN  bit
    //
    HW_WR_REG16(address,
        (HW_RD_REG16(address) & ~CSL_SDFM_SDSYNC1_WTSCLREN_MASK) |
        ((uint16_t)syncClearMode << 10U));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
SDFM_selectClockSource(uint32_t base, uint32_t filterNumber,
                       uint32_t clkSource)
{
    uint32_t address;
 
    address = base + CSL_SDFM_SDCTLPARM1 +
              ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET);
 
    //
    // Select SDFM clock source.
    //
    HW_WR_REG16(address,
        (HW_RD_REG16(address) & ~(CSL_SDFM_SDCTLPARM1_SDCLKSEL_MASK)) |
        (uint16_t)clkSource);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
SDFM_enableSynchronizer(uint32_t base, uint32_t filterNumber,
                        uint16_t syncConfig)
{
    //
    // Select SDFM clock source.
    //
    HW_WR_REG16(base + CSL_SDFM_SDCTLPARM1 +
        ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET),
        HW_RD_REG16(base + CSL_SDFM_SDCTLPARM1 +
        ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET)) | syncConfig);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
SDFM_disableSynchronizer(uint32_t base, uint32_t filterNumber,
                         uint16_t syncConfig)
{
    //
    // Select SDFM clock source.
    //
    HW_WR_REG16(base + CSL_SDFM_SDCTLPARM1 +
        ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET),
        HW_RD_REG16(base + CSL_SDFM_SDCTLPARM1 +
        ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET)) & ~syncConfig);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
SDFM_selectCompEventHighSource(uint32_t base, uint32_t filterNumber,
                               uint32_t source)
{
    uint32_t address;
    address = base + CSL_SDFM_SDCOMP1CTL +
              ((uint32_t)filterNumber * SDFM_DIGFIL_OFFSET);
 
    //
    // Set COMPHOUT source.
    //
    HW_WR_REG16(address,
        (HW_RD_REG16(address) & ~CSL_SDFM_SDCOMP1CTL_CEVT1DIGFILTSEL_MASK) |
        (uint16_t)source);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
SDFM_selectCompEventLowSource(uint32_t base, uint32_t filterNumber,
                              uint32_t source)
{
    uint32_t address;
    address = base + CSL_SDFM_SDCOMP1CTL +
              ((uint32_t)filterNumber * SDFM_DIGFIL_OFFSET);
 
    //
    // Set COMPLOUT source.
    //
    HW_WR_REG16(address,
        (HW_RD_REG16(address) & ~CSL_SDFM_SDCOMP1CTL_CEVT2DIGFILTSEL_MASK) |
        (uint16_t)source);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
SDFM_initCompEventLowFilter(uint32_t base, uint32_t filterNumber)
{
    //
    // Initialize comparator event low filter.
    //
    HW_WR_REG16(base + CSL_SDFM_SDCOMP1EVT2FLTCTL +
        ((uint32_t)filterNumber * SDFM_DIGFIL_OFFSET),
        HW_RD_REG16(base + CSL_SDFM_SDCOMP1EVT2FLTCTL +
        ((uint32_t)filterNumber * SDFM_DIGFIL_OFFSET)) |
        (uint16_t)CSL_SDFM_SDCOMP1EVT2FLTCTL_FILINIT_MASK);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
SDFM_initCompEventHighFilter(uint32_t base, uint32_t filterNumber)
{
    //
    // Initialize comparator event high filter.
    //
    HW_WR_REG16(base + CSL_SDFM_SDCOMP1EVT1FLTCTL +
        ((uint32_t)filterNumber * SDFM_DIGFIL_OFFSET),
        HW_RD_REG16(base + CSL_SDFM_SDCOMP1EVT1FLTCTL +
        ((uint32_t)filterNumber * SDFM_DIGFIL_OFFSET)) |
        (uint16_t)CSL_SDFM_SDCOMP1EVT1FLTCTL_FILINIT_MASK);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
SDFM_lockCompEventFilterConfig(uint32_t base, uint32_t filterNumber,
                               uint16_t lockConfig)
{
    //
    // Lock comparator event filter related configurations.
    //
    HW_WR_REG16(base + CSL_SDFM_SDCOMP1LOCK +
        ((uint32_t)filterNumber * SDFM_DIGFIL_OFFSET),
        HW_RD_REG16(base + CSL_SDFM_SDCOMP1LOCK +
        ((uint32_t)filterNumber * SDFM_DIGFIL_OFFSET)) | lockConfig);
}
 
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//*****************************************************************************
extern void
SDFM_configComparator(uint32_t base, uint16_t config1,
                      uint32_t config2, uint16_t config3);
 
//*****************************************************************************
//
//*****************************************************************************
extern void
SDFM_configEnhancedComparator(uint32_t base, uint16_t filterConfig,
                              uint32_t highLowThreshold1,
                              uint32_t highLowThreshold2,
                              uint16_t zeroCrossThreshold);
 
//*****************************************************************************
//
//*****************************************************************************
extern void
SDFM_configDataFilter(uint32_t base, uint16_t config1, uint16_t config2);
 
//*****************************************************************************
//
//*****************************************************************************
extern void
SDFM_configZeroCrossComparator(uint32_t base, uint16_t config1,
                               uint16_t config2);
 
//*****************************************************************************
//
//*****************************************************************************
extern void
SDFM_configDataFilterFIFO(uint32_t base, uint16_t config1, uint16_t config2);
 
//*****************************************************************************
//
//
//*****************************************************************************
extern void
SDFM_configCompEventLowFilter(uint32_t base, uint32_t filterNumber,
                              const SDFM_CompEventFilterConfig *config);
 
//*****************************************************************************
//
//
//*****************************************************************************
extern void
SDFM_configCompEventHighFilter(uint32_t base, uint32_t filterNumber,
                               const SDFM_CompEventFilterConfig *config);
 
//*****************************************************************************
//
// Close the Doxygen group.
//
//*****************************************************************************
 
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // SDFM_V0_H_