lin/v0/lin.h

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/*
 * Copyright (C) 2021 Texas Instruments Incorporated
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *   Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 *
 *   Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the
 *   distribution.
 *
 *   Neither the name of Texas Instruments Incorporated nor the names of
 *   its contributors may be used to endorse or promote products derived
 *   from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef LIN_V0_H_
#define LIN_V0_H_
 
/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */
 
#include <stdint.h>
#include <kernel/dpl/SystemP.h>
#include <kernel/dpl/SemaphoreP.h>
#include <kernel/dpl/HwiP.h>
#include <drivers/hw_include/cslr.h>
#include <drivers/hw_include/cslr_soc.h>
#include <drivers/hw_include/cslr_lin.h>
#include <drivers/hw_include/hw_types.h>
 
#ifdef __cplusplus
extern "C" {
#endif
 
/* ========================================================================== */
/*                             Macros & Typedefs                              */
/* ========================================================================== */
 
#define LIN_IO_DFT_KEY                      (0xAU)
 
#define LIN_WAKEUP_KEY                      (0xF0U)
 
#define LIN_ID0                             (0x1U)
#define LIN_ID1                             (0x2U)
#define LIN_ID2                             (0x4U)
#define LIN_ID3                             (0x8U)
#define LIN_ID4                             (0x10U)
#define LIN_ID5                             (0x20U)
 
#define LIN_INT_WAKEUP                      (0x00000002U) /* Wakeup */
#define LIN_INT_TO                          (0x00000010U) /* Time out */
#define LIN_INT_TOAWUS                      (0x00000040U) /* Time out after wakeup signal */
#define LIN_INT_TOA3WUS                     (0x00000080U) /* Time out after 3 wakeup signals */
#define LIN_INT_TX                          (0x00000100U) /* Transmit buffer ready */
#define LIN_INT_RX                          (0x00000200U) /* Receive buffer ready */
#define LIN_INT_ID                          (0x00002000U) /* Received matching identifier */
#define LIN_INT_PE                          (0x01000000U) /* Parity error */
#define LIN_INT_OE                          (0x02000000U) /* Overrun error */
#define LIN_INT_FE                          (0x04000000U) /* Framing error */
#define LIN_INT_NRE                         (0x08000000U) /* No response error */
#define LIN_INT_ISFE                        (0x10000000U) /* Inconsistent sync field error */
#define LIN_INT_CE                          (0x20000000U) /* Checksum error */
#define LIN_INT_PBE                         (0x40000000U) /* Physical bus error */
#define LIN_INT_BE                          (0x80000000U) /* Bit error */
#define LIN_INT_ALL                         (0xFF0023D2U) /* All interrupts */
 
#define LIN_FLAG_BREAK                      (CSL_LIN_SCIFLR_BRKDT_MASK)
#define LIN_FLAG_WAKEUP                     (CSL_LIN_SCIFLR_WAKEUP_MASK)
#define LIN_FLAG_IDLE                       (CSL_LIN_SCIFLR_IDLE_MASK)
#define LIN_FLAG_BUSY                       (CSL_LIN_SCIFLR_BUSY_MASK)
#define LIN_FLAG_TO                         (CSL_LIN_SCIFLR_TIMEOUT_MASK)
#define LIN_FLAG_TOAWUS                     (CSL_LIN_SCIFLR_TOAWUS_MASK)
#define LIN_FLAG_TOA3WUS                    (CSL_LIN_SCIFLR_TOA3WUS_MASK)
#define LIN_FLAG_TXRDY                      (CSL_LIN_SCIFLR_TXRDY_MASK)
#define LIN_FLAG_RXRDY                      (CSL_LIN_SCIFLR_RXRDY_MASK)
#define LIN_FLAG_TXWAKE                     (CSL_LIN_SCIFLR_TXWAKE_MASK)
#define LIN_FLAG_TXEMPTY                    (CSL_LIN_SCIFLR_TXEMPTY_MASK)
#define LIN_FLAG_RXWAKE                     (CSL_LIN_SCIFLR_RXWAKE_MASK)
#define LIN_FLAG_TXID                       (CSL_LIN_SCIFLR_IDTXFLAG_MASK)
#define LIN_FLAG_RXID                       (CSL_LIN_SCIFLR_IDRXFLAG_MASK)
#define LIN_FLAG_PE                         (CSL_LIN_SCIFLR_PE_MASK)
#define LIN_FLAG_OE                         (CSL_LIN_SCIFLR_OE_MASK)
#define LIN_FLAG_FE                         (CSL_LIN_SCIFLR_FE_MASK)
#define LIN_FLAG_NRE                        (CSL_LIN_SCIFLR_NRE_MASK)
#define LIN_FLAG_ISFE                       (CSL_LIN_SCIFLR_ISFE_MASK)
#define LIN_FLAG_CE                         (CSL_LIN_SCIFLR_CE_MASK)
#define LIN_FLAG_PBE                        (CSL_LIN_SCIFLR_PBE_MASK)
#define LIN_FLAG_BE                         (CSL_LIN_SCIFLR_BE_MASK)
 
#define LIN_VECT_NONE                       (0x00)
#define LIN_VECT_WAKEUP                     (0x01)
#define LIN_VECT_ISFE                       (0x02)
#define LIN_VECT_PE                         (0x03)
#define LIN_VECT_ID                         (0x04)
#define LIN_VECT_PBE                        (0x05)
#define LIN_VECT_FE                         (0x06)
#define LIN_VECT_BREAK                      (0x07)
#define LIN_VECT_CE                         (0x08)
#define LIN_VECT_OE                         (0x09)
#define LIN_VECT_BE                         (0x0A)
#define LIN_VECT_RX                         (0x0B)
#define LIN_VECT_TX                         (0x0C)
#define LIN_VECT_NRE                        (0x0D)
#define LIN_VECT_TOAWUS                     (0x0E)
#define LIN_VECT_TOA3WUS                    (0x0F)
#define LIN_VECT_TO                         (0x10)
 
#define LIN_ALL_ERRORS                      (0xF0000000U)
#define LIN_BIT_ERROR                       (0x80000000U)
#define LIN_BUS_ERROR                       (0x40000000U)
#define LIN_CHECKSUM_ERROR                  (0x20000000U)
#define LIN_ISF_ERROR                       (0x10000000U)
 
#define LIN_SCI_ALL_ERRORS                  (0x7000000U)
#define LIN_SCI_FRAME_ERROR                 (0x4000000U)
#define LIN_SCI_PARITY_ERROR                (0x2000000U)
#define LIN_SCI_BREAK_ERROR                 (0x1000000U)
 
#define LIN_SCI_INT_BREAK                   (0x1U)
#define LIN_SCI_INT_WAKEUP                  (0x2U)
#define LIN_SCI_INT_TX                      (0x100U)
#define LIN_SCI_INT_RX                      (0x200U)
#define LIN_SCI_INT_TX_DMA                  (0x10000U)
#define LIN_SCI_INT_RX_DMA                  (0x20000U)
#define LIN_SCI_INT_PARITY                  (0x1000000U)
#define LIN_SCI_INT_OVERRUN                 (0x2000000U)
#define LIN_SCI_INT_FRAME                   (0x4000000U)
#define LIN_SCI_INT_ALL                     (0x7000303U)
 
/* ========================================================================== */
/*                         Structures and Enums                               */
/* ========================================================================== */
 
typedef enum
{
    LIN_LOOPBACK_DIGITAL = 0U,    
    LIN_LOOPBACK_ANALOG  = 1U     
} LIN_LoopbackType;
 
typedef enum
{
    LIN_ANALOG_LOOP_NONE = 0U,    
    LIN_ANALOG_LOOP_TX   = 0U,    
    LIN_ANALOG_LOOP_RX   = 1U     
} LIN_AnalogLoopback;
 
typedef enum
{
    LIN_COMM_LIN_USELENGTHVAL = 0x0000U,
    LIN_COMM_LIN_ID4ID5LENCTL = 0x0001U
} LIN_CommMode;
 
typedef enum
{
    LIN_COMM_SCI_IDLELINE     = 0x0000U,
    LIN_COMM_SCI_ADDRBIT      = 0x0001U
} LIN_SCICommMode;
 
typedef enum
{
    LIN_MODE_LIN_SLAVE        = 0x0U,
    LIN_MODE_LIN_MASTER       = 0x1U
} LIN_LINMode;
 
typedef enum
{
    LIN_INTERRUPT_LINE0       = 0x0U,
    LIN_INTERRUPT_LINE1       = 0x1U
} LIN_InterruptLine;
 
typedef enum
{
    LIN_MSG_FILTER_IDBYTE  = 0x0U,
    LIN_MSG_FILTER_IDSLAVE = 0x1U
} LIN_MessageFilter;
 
typedef enum
{
    LIN_CHECKSUM_CLASSIC  = 0x0U,
    LIN_CHECKSUM_ENHANCED = 0x1U
} LIN_ChecksumType;
 
typedef enum
{
    LIN_DEBUG_FROZEN   = 0x0U,    
    LIN_DEBUG_COMPLETE = 0x1U     
} LIN_DebugMode;
 
typedef enum
{
    LIN_PINMASK_NONE         = 0x0U,
    LIN_PINMASK_CENTER       = 0x1U,
    LIN_PINMASK_CENTER_SCLK  = 0x2U,
    LIN_PINMASK_CENTER_2SCLK = 0x3U
} LIN_PinSampleMask;
 
typedef enum
{
    LIN_SCI_PAR_ODD   = 0x0U,
    LIN_SCI_PAR_EVEN  = 0x1U
} LIN_SCIParityType;
 
typedef enum
{
    LIN_SCI_STOP_ONE   = 0x0U,
    LIN_SCI_STOP_TWO   = 0x1U
} LIN_SCIStopBits;
 
typedef enum
{
    LIN_PINTYPE_TX = 0x4U,
    LIN_PINTYPE_RX = 0x2U
} LIN_PinType;
 
/* ========================================================================== */
/*                  Internal/Private Structure Declarations                   */
/* ========================================================================== */
 
/* None */
 
/* ========================================================================== */
/*                         Global Variables Declarations                      */
/* ========================================================================== */
 
/* None */
 
/* ========================================================================== */
/*                          Function Declarations                             */
/* ========================================================================== */
 
void LIN_initModule(uint32_t base);
 
void LIN_getData(uint32_t base, uint16_t * const data);
 
void LIN_sendData(uint32_t base, uint16_t *data);
 
/* ========================================================================== */
/*                       Static Function Definitions                          */
/* ========================================================================== */
 
static inline Bool
LIN_isBaseValid(uint32_t base)
{
    #if defined (SOC_AM263X)
    return(
           (base == CSL_LIN0_U_BASE) ||
           (base == CSL_LIN1_U_BASE) ||
           (base == CSL_LIN2_U_BASE) ||
           (base == CSL_LIN3_U_BASE) ||
           (base == CSL_LIN4_U_BASE)
          );
    #else
    return TRUE;
    #endif /* defined (SOC_AM263X) */
}
 
static inline void
LIN_setLINMode(uint32_t base, LIN_LINMode mode)
{
    /* Paramter Validation */
    DebugP_assert(LIN_isBaseValid(base));
 
    /* Program LIN Mode */
    HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_CLK_MASTER_MASK, CSL_LIN_SCIGCR1_CLK_MASTER_SHIFT, mode);
}
 
static inline void
LIN_setMaximumBaudRate(uint32_t base, uint32_t clock)
{
    /* Parameter Validation */
    DebugP_assert(LIN_isBaseValid(base));
 
    /* Calculate maximum baud rate prescaler */
    HW_WR_FIELD32_RAW((base + CSL_LIN_MBRSR), CSL_LIN_MBRSR_MBR_MASK, CSL_LIN_MBRSR_MBR_SHIFT, (clock / 20000U));
}
 
static inline void
LIN_setMessageFiltering(uint32_t base, LIN_MessageFilter type)
{
    /* Parameter Validation */
    DebugP_assert(LIN_isBaseValid(base));
 
    /* Sets the message filtering type */
    HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_HGENCTRL_MASK, CSL_LIN_SCIGCR1_HGENCTRL_SHIFT, type);
}
 
static inline void
LIN_enableParity(uint32_t base)
{
    /* Parameter Validation */
    DebugP_assert(LIN_isBaseValid(base));
 
    /* Enable the parity mode */
    HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_PARITYENA_MASK, CSL_LIN_SCIGCR1_PARITYENA_SHIFT, CSL_TRUE);
}
 
static inline void
LIN_disableParity(uint32_t base)
{
    /* Parameter Validation */
    DebugP_assert(LIN_isBaseValid(base));
 
    /* Enable the parity mode */
    HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_PARITYENA_MASK, CSL_LIN_SCIGCR1_PARITYENA_SHIFT, CSL_FALSE);
}
 
static inline uint16_t
LIN_generateParityID(uint16_t identifier)
{
    uint16_t p0, p1, parityIdentifier;
 
    /* Calculate parity bits and generate updated identifier */
    p0 = ((identifier & LIN_ID0) ^ ((identifier & LIN_ID1) >> 1U) ^
          ((identifier & LIN_ID2) >> 2U) ^ ((identifier & LIN_ID4) >> 4U));
    p1 = !(((identifier & LIN_ID1) >> 1U) ^ ((identifier & LIN_ID3) >> 3U) ^
           ((identifier & LIN_ID4) >> 4U) ^ ((identifier & LIN_ID5) >> 5U));
    parityIdentifier = identifier | ((p0 << 6U) | (p1 << 7U));
 
    return(parityIdentifier);
}
 
static inline void
LIN_setIDByte(uint32_t base, uint16_t identifier)
{
    /* Parameter Validation */
    DebugP_assert(LIN_isBaseValid(base));
 
    HW_WR_FIELD32_RAW((base + CSL_LIN_LINID), CSL_LIN_LINID_IDBYTE_MASK, CSL_LIN_LINID_IDBYTE_SHIFT, identifier);
}
 
static inline void
LIN_setIDSlaveTask(uint32_t base, uint16_t identifier)
{
    /* Parameter Validation */
    DebugP_assert(LIN_isBaseValid(base));
 
    HW_WR_FIELD32_RAW((base + CSL_LIN_LINID), CSL_LIN_LINID_IDSLAVETASKBYTE_MASK, CSL_LIN_LINID_IDSLAVETASKBYTE_SHIFT, identifier);
}
 
static inline void
LIN_sendWakeupSignal(uint32_t base)
{
    /* Parameter Validation */
    DebugP_assert(LIN_isBaseValid(base));
 
    /* Set key in Byte 0 (MSB) of transmit buffer 0 register */
    HW_WR_FIELD32_RAW((base + CSL_LIN_LINTD0), CSL_LIN_LINTD0_TD3_MASK, CSL_LIN_LINTD0_TD3_SHIFT, (uint16_t)LIN_WAKEUP_KEY);
 
    /* Transmit TDO for wakeup */
    HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR2), CSL_LIN_SCIGCR2_GENWU_MASK, CSL_LIN_SCIGCR2_GENWU_SHIFT, CSL_TRUE);
}
 
static inline void
LIN_enterSleep(uint32_t base)
{
    /* Parameter Validation */
    DebugP_assert(LIN_isBaseValid(base));
 
    /* Entering Powerdown */
    HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR2), CSL_LIN_SCIGCR2_POWERDOWN_MASK, CSL_LIN_SCIGCR2_POWERDOWN_SHIFT, CSL_TRUE);
}
 
static inline void
LIN_sendChecksum(uint32_t base)
{
    /* Parameter Validation */
    DebugP_assert(LIN_isBaseValid(base));
 
    /* Setting the Check Sum */
    HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR2), CSL_LIN_SCIGCR2_SC_MASK, CSL_LIN_SCIGCR2_SC_SHIFT, CSL_TRUE);
}
 
static inline void
LIN_triggerChecksumCompare(uint32_t base)
{
    /* Parameter Validation */
    DebugP_assert(LIN_isBaseValid(base));
 
    /* Comparing the Check Sum */
    HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR2), CSL_LIN_SCIGCR2_CC_MASK, CSL_LIN_SCIGCR2_CC_SHIFT, CSL_TRUE);
}
 
static inline Bool
LIN_isTxReady(uint32_t base)
{
    /* Parameter Validation */
    DebugP_assert(LIN_isBaseValid(base));
 
    /* Check TXRDY BIT */
    return((HW_RD_REG32_RAW(base + CSL_LIN_SCIFLR) & CSL_LIN_SCIFLR_TXRDY_MASK) ==
           CSL_LIN_SCIFLR_TXRDY_MASK);
}
 
static inline void
LIN_setFrameLength(uint32_t base, uint16_t length)
{
    /* Parameter Validation */
    DebugP_assert(LIN_isBaseValid(base));
    DebugP_assert((length > 0U) && (length < 9U));
 
    /* Clear and set frame length value */
    HW_WR_FIELD32_RAW((base + CSL_LIN_SCIFORMAT), CSL_LIN_SCIFORMAT_LENGTH_MASK, CSL_LIN_SCIFORMAT_LENGTH_SHIFT, ((uint32_t)length - (uint32_t)1U));
}
 
static inline void
LIN_setCommMode(uint32_t base, LIN_CommMode mode)
{
    /* Parameter Validation */
    DebugP_assert(LIN_isBaseValid(base));
 
    /* Write communication mode selection to the appropriate bit. */
    HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_COMMMODE_MASK, CSL_LIN_SCIGCR1_COMMMODE_SHIFT, (uint16_t)mode);
}
 
static inline void
LIN_setTxMask(uint32_t base, uint16_t mask)
{
    /* Parameter Validation */
    DebugP_assert(LIN_isBaseValid(base));
 
    /* Clear previous mask value and set new mask */
    HW_WR_FIELD32_RAW((base + CSL_LIN_LINMASK), CSL_LIN_LINMASK_TXIDMASK_MASK, CSL_LIN_LINMASK_TXIDMASK_SHIFT, mask);
}
 
static inline void
LIN_setRxMask(uint32_t base, uint16_t mask)
{
    /* Parameter Validation */
    DebugP_assert(LIN_isBaseValid(base));
 
    /* Clear previous mask value and set new mask */
    HW_WR_FIELD32_RAW((base + CSL_LIN_LINMASK), CSL_LIN_LINMASK_RXIDMASK_MASK, CSL_LIN_LINMASK_RXIDMASK_SHIFT, (uint32_t)mask);
}
 
static inline uint16_t
LIN_getTxMask(uint32_t base)
{
    /* Parameter Validation */
    DebugP_assert(LIN_isBaseValid(base));
 
    /* Get Tx Mask status */
    return(HW_RD_FIELD32_RAW((base + CSL_LIN_LINMASK), CSL_LIN_LINMASK_TXIDMASK_MASK, CSL_LIN_LINMASK_TXIDMASK_SHIFT));
}
 
static inline uint16_t
LIN_getRxMask(uint32_t base)
{
    /* Parameter Validation */
    DebugP_assert(LIN_isBaseValid(base));
 
    /* Get Tx Mask status */
    return(HW_RD_FIELD32_RAW((base + CSL_LIN_LINMASK), CSL_LIN_LINMASK_RXIDMASK_MASK, CSL_LIN_LINMASK_RXIDMASK_SHIFT));
}
 
static inline Bool
LIN_isRxReady(uint32_t base)
{
    /* Parameter Validation */
    DebugP_assert(LIN_isBaseValid(base));
 
    /* Ready Rx ready flag and return status */
    return(HW_RD_FIELD32_RAW((base + CSL_LIN_SCIFLR), CSL_LIN_SCIFLR_RXRDY_MASK, CSL_LIN_SCIFLR_RXRDY_SHIFT));
}
 
static inline uint16_t
LIN_getRxIdentifier(uint32_t base)
{
    /* Parameter Validation */
    DebugP_assert(LIN_isBaseValid(base));
 
    /* Ready Rx ready flag and return status */
    return(HW_RD_FIELD32_RAW((base + CSL_LIN_LINID), CSL_LIN_LINID_RECEIVEDID_MASK, CSL_LIN_LINID_RECEIVEDID_SHIFT));
}
 
static inline Bool
LIN_isTxMatch(uint32_t base)
{
    /* Parameter Validation */
    DebugP_assert(LIN_isBaseValid(base));
 
    /* Read Tx ID flag and return status */
    return(HW_RD_FIELD32_RAW((base + CSL_LIN_SCIFLR), CSL_LIN_SCIFLR_IDTXFLAG_MASK, CSL_LIN_SCIFLR_IDTXFLAG_SHIFT));
}
 
static inline Bool
LIN_isRxMatch(uint32_t base)
{
    /* Parameter Validation */
    DebugP_assert(LIN_isBaseValid(base));
 
    /* Read Tx ID flag and return status */
    return(HW_RD_FIELD32_RAW((base + CSL_LIN_SCIFLR), CSL_LIN_SCIFLR_IDRXFLAG_MASK, CSL_LIN_SCIFLR_IDRXFLAG_SHIFT));
}
 
static inline void
LIN_enableInterrupt(uint32_t base, uint32_t intFlags)
{
    /* Parameter Validation */
    DebugP_assert(LIN_isBaseValid(base));
 
    /* Set Interrupt Flags */
    HW_WR_REG32_RAW((base + CSL_LIN_SCISETINT), HW_RD_REG32_RAW(base + CSL_LIN_SCISETINT)|intFlags);
}
 
static inline void
LIN_disableInterrupt(uint32_t base, uint32_t intFlags)
{
    /* Parameter Validation */
    DebugP_assert(LIN_isBaseValid(base));
 
    /* Clear Interrupt Flags */
    HW_WR_REG32_RAW((base + CSL_LIN_SCICLEARINT), intFlags);
}
 
static inline void
LIN_clearInterruptStatus(uint32_t base, uint32_t intFlags)
{
    /* Parameter Validation */
    DebugP_assert(LIN_isBaseValid(base));
 
    /* Clear Status Flags */
    HW_WR_REG32_RAW((base + CSL_LIN_SCIFLR), intFlags);
}
 
static inline void
LIN_setInterruptLevel0(uint32_t base, uint32_t intFlags)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
 
    /* Clear Status Flags */
    HW_WR_REG32_RAW((base + CSL_LIN_SCICLEARINTLVL), intFlags);
}
 
static inline void
LIN_setInterruptLevel1(uint32_t base, uint32_t intFlags)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
 
    /* Set interrupt levels to 1 */
    HW_WR_REG32_RAW((base + CSL_LIN_SCISETINTLVL), HW_RD_REG32_RAW(base + CSL_LIN_SCISETINTLVL)|intFlags);
}
 
static inline void
LIN_enableModuleErrors(uint32_t base, uint32_t errors)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
 
    /* Clear the IO DFT Enable Key & Enable write access*/
    HW_WR_FIELD32_RAW((base + CSL_LIN_IODFTCTRL), CSL_LIN_IODFTCTRL_IODFTENA_MASK, CSL_LIN_IODFTCTRL_IODFTENA_SHIFT, (uint32_t)LIN_IO_DFT_KEY);
 
    /* Enable specified error bits */
    HW_WR_REG32_RAW((base + CSL_LIN_IODFTCTRL), HW_RD_REG32_RAW(base + CSL_LIN_IODFTCTRL)|errors);
 
    /* Clear the IO DFT Enable Key */
    HW_WR_FIELD32_RAW((base + CSL_LIN_IODFTCTRL), CSL_LIN_IODFTCTRL_IODFTENA_MASK, CSL_LIN_IODFTCTRL_IODFTENA_SHIFT, (uint32_t)CSL_FALSE);
}
 
static inline void
LIN_disableModuleErrors(uint32_t base, uint32_t errors)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
 
    /* Clear the IO DFT Enable Key & Enable write access */
    HW_WR_FIELD32_RAW((base + CSL_LIN_IODFTCTRL), CSL_LIN_IODFTCTRL_IODFTENA_MASK, CSL_LIN_IODFTCTRL_IODFTENA_SHIFT, (uint32_t)LIN_IO_DFT_KEY);
 
    /* Disable specified error bits */
    HW_WR_REG32_RAW((base + CSL_LIN_IODFTCTRL), HW_RD_REG32_RAW(base + CSL_LIN_IODFTCTRL)&~(errors));
 
    /* Clear the IO DFT Enable Key */
    HW_WR_FIELD32_RAW((base + CSL_LIN_IODFTCTRL), CSL_LIN_IODFTCTRL_IODFTENA_MASK, CSL_LIN_IODFTCTRL_IODFTENA_SHIFT, (uint32_t)CSL_FALSE);
}
 
static inline void
LIN_enableAutomaticBaudrate(uint32_t base)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
 
    /* Specified error bits */
    HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_ADAPT_MASK, CSL_LIN_SCIGCR1_ADAPT_SHIFT, CSL_TRUE);
}
 
static inline void
LIN_disableAutomaticBaudrate(uint32_t base)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
 
    /* Specified error bits */
    HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_ADAPT_MASK, CSL_LIN_SCIGCR1_ADAPT_SHIFT, CSL_FALSE);
}
 
static inline void
LIN_stopExtendedFrame(uint32_t base)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
 
    /* Set stop bit. */
    HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_STOPEXTFRAME_MASK, CSL_LIN_SCIGCR1_STOPEXTFRAME_SHIFT, CSL_TRUE);
}
 
static inline void
LIN_setChecksumType(uint32_t base, LIN_ChecksumType type)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
 
    /* Set stop bit. */
    HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_STOPEXTFRAME_MASK, CSL_LIN_SCIGCR1_STOPEXTFRAME_SHIFT, type);
}
 
static inline void
LIN_setSyncFields(uint32_t base, uint16_t syncBreak, uint16_t delimiter)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
    DebugP_assert(syncBreak < 8U);
    DebugP_assert((delimiter >= 1U) && (delimiter < 5U));
 
    /* Clear sync values and set new values */
    HW_WR_FIELD32_RAW((base + CSL_LIN_LINCOMP), (CSL_LIN_LINCOMP_SDEL_MASK|CSL_LIN_LINCOMP_SBREAK_MASK),
                        CSL_LIN_LINCOMP_SDEL_SHIFT, (syncBreak | (delimiter - 1U)));
}
 
static inline void
LIN_enableSCIMode(uint32_t base)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
 
    HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_LINMODE_MASK,
                        CSL_LIN_SCIGCR1_LINMODE_SHIFT, CSL_FALSE);
 
    HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_CLK_MASTER_MASK,
                        CSL_LIN_SCIGCR1_CLK_MASTER_SHIFT, CSL_TRUE);
 
    HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_TIMINGMODE_MASK,
                    CSL_LIN_SCIGCR1_TIMINGMODE_SHIFT, CSL_TRUE);
}
 
static inline void
LIN_disableSCIMode(uint32_t base)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
 
    /* Disable SCI communications mode */
    HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_CLK_MASTER_MASK,
                        CSL_LIN_SCIGCR1_CLK_MASTER_SHIFT, CSL_FALSE);
 
    HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_TIMINGMODE_MASK,
                    CSL_LIN_SCIGCR1_TIMINGMODE_SHIFT, CSL_FALSE);
 
    HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_LINMODE_MASK,
                        CSL_LIN_SCIGCR1_LINMODE_SHIFT, CSL_TRUE);
}
 
static inline void
LIN_setSCICommMode(uint32_t base, LIN_SCICommMode mode)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
    DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
           0U);
 
    HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_COMMMODE_MASK,
                    CSL_LIN_SCIGCR1_COMMMODE_SHIFT, mode);
}
 
static inline void
LIN_enableSCIParity(uint32_t base, LIN_SCIParityType parity)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
    DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
           0U);
 
    HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_PARITYENA_MASK,
                    CSL_LIN_SCIGCR1_PARITYENA_SHIFT, 1U);
 
    HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_PARITY_MASK,
                CSL_LIN_SCIGCR1_PARITY_SHIFT, parity);
}
 
static inline void
LIN_disableSCIParity(uint32_t base)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
    DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
           0U);
 
    HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_PARITYENA_MASK,
                    CSL_LIN_SCIGCR1_PARITYENA_SHIFT, 0U);
}
 
static inline void
LIN_setSCIStopBits(uint32_t base, LIN_SCIStopBits number)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
    DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
           0U);
 
    HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_STOP_MASK,
                    CSL_LIN_SCIGCR1_STOP_SHIFT, number);
}
 
static inline void
LIN_enableSCISleepMode(uint32_t base)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
    DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
           0U);
 
    HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_SLEEP_MASK,
                    CSL_LIN_SCIGCR1_SLEEP_SHIFT, CSL_TRUE);
}
 
static inline void
LIN_disableSCISleepMode(uint32_t base)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
    DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
           0U);
 
    HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_SLEEP_MASK,
                    CSL_LIN_SCIGCR1_SLEEP_SHIFT, CSL_FALSE);
}
 
static inline void
LIN_enterSCILowPower(uint32_t base)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
    DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
           0U);
 
    HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR2), CSL_LIN_SCIGCR2_POWERDOWN_MASK,
                    CSL_LIN_SCIGCR2_POWERDOWN_SHIFT, CSL_TRUE);
}
 
static inline void
LIN_exitSCILowPower(uint32_t base)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
    DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
           0U);
 
    HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR2), CSL_LIN_SCIGCR2_POWERDOWN_MASK,
                    CSL_LIN_SCIGCR2_POWERDOWN_SHIFT, CSL_FALSE);
}
 
static inline void
LIN_setSCICharLength(uint32_t base, uint16_t numBits)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
    DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
           0U);
    DebugP_assert((numBits > 0U) && (numBits < 9U));
 
    HW_WR_FIELD32_RAW((base + CSL_LIN_SCIFORMAT), CSL_LIN_SCIFORMAT_CHAR_MASK,
                    CSL_LIN_SCIFORMAT_CHAR_SHIFT, (uint32_t)(numBits - 1U));
}
 
static inline void
LIN_setSCIFrameLength(uint32_t base, uint16_t length)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
    DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
           0U);
    DebugP_assert((length > 0U) && (length < 9U));
 
    HW_WR_FIELD32_RAW((base + CSL_LIN_SCIFORMAT), CSL_LIN_SCIFORMAT_LENGTH_MASK,
                    CSL_LIN_SCIFORMAT_LENGTH_SHIFT, (uint32_t)(length - 1U));
}
 
static inline Bool
LIN_isSCIDataAvailable(uint32_t base)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
    DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
           0U);
 
    return((HW_RD_REG32_RAW(base + CSL_LIN_SCIFLR) & CSL_LIN_SCIFLR_RXRDY_MASK) == CSL_LIN_SCIFLR_RXRDY_MASK);
}
 
static inline Bool
LIN_isSCISpaceAvailable(uint32_t base)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
    DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
           0U);
 
    return((HW_RD_REG32_RAW(base + CSL_LIN_SCIFLR) & CSL_LIN_SCIFLR_TXRDY_MASK) == CSL_LIN_SCIFLR_TXRDY_MASK);
}
 
static inline uint16_t
LIN_readSCICharNonBlocking(uint32_t base, Bool emulation)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
    DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
           0U);
 
    /* Read specific data register */
    return(emulation ? (HW_RD_REG32_RAW(base + CSL_LIN_SCIED) & CSL_LIN_SCIED_ED_MASK) :
            (HW_RD_REG32_RAW(base + CSL_LIN_SCIRD) & CSL_LIN_SCIRD_RD_MASK));
}
 
static inline uint16_t
LIN_readSCICharBlocking(uint32_t base, Bool emulation)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
    DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
           0U);
 
    /* Wait until a character is available in buffer. */
    while(!LIN_isSCIDataAvailable(base))
    {
    }
 
    /* Read specific data register */
    return(emulation ? (HW_RD_REG32_RAW(base + CSL_LIN_SCIED) & CSL_LIN_SCIED_ED_MASK) :
            (HW_RD_REG32_RAW(base + CSL_LIN_SCIRD) & CSL_LIN_SCIRD_RD_MASK));
}
 
static inline void
LIN_writeSCICharNonBlocking(uint32_t base, uint16_t data)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
    DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
           0U);
    DebugP_assert(data <= CSL_LIN_SCITD_TD_MASK);
 
    /* Set the Tx Data */
    HW_WR_FIELD32_RAW((base + CSL_LIN_SCITD), CSL_LIN_SCITD_TD_MASK, CSL_LIN_SCITD_TD_SHIFT, data);
}
 
static inline void
LIN_writeSCICharBlocking(uint32_t base, uint16_t data)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
    DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
           0U);
    DebugP_assert(data <= CSL_LIN_SCITD_TD_MASK);
 
    /* Wait until space is available in the transmit buffer. */
    while(!LIN_isSCISpaceAvailable(base))
    {
    }
 
    /* Set the Tx Data */
    HW_WR_FIELD32_RAW((base + CSL_LIN_SCITD), CSL_LIN_SCITD_TD_MASK, CSL_LIN_SCITD_TD_SHIFT, data);
}
 
static inline void
LIN_enableSCIModuleErrors(uint32_t base, uint32_t errors)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
    DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
           0U);
 
    /* Clear the IO DFT Enable Key & Enable write access */
    HW_WR_FIELD32_RAW((base + CSL_LIN_IODFTCTRL), CSL_LIN_IODFTCTRL_IODFTENA_MASK, CSL_LIN_IODFTCTRL_IODFTENA_SHIFT, LIN_IO_DFT_KEY);
 
    /* Enable specified error bits */
    HW_WR_REG32_RAW((base + CSL_LIN_IODFTCTRL), (HW_RD_REG32_RAW(base + CSL_LIN_IODFTCTRL)|errors));
 
    /* Clear the IO DFT Enable Key & Enable write access */
    HW_WR_FIELD32_RAW((base + CSL_LIN_IODFTCTRL), CSL_LIN_IODFTCTRL_IODFTENA_MASK, CSL_LIN_IODFTCTRL_IODFTENA_SHIFT, CSL_FALSE);
}
 
static inline void
LIN_disableSCIModuleErrors(uint32_t base, uint32_t errors)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
    DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
           0U);
 
    /* Clear the IO DFT Enable Key & Enable write access */
    HW_WR_FIELD32_RAW((base + CSL_LIN_IODFTCTRL), CSL_LIN_IODFTCTRL_IODFTENA_MASK, CSL_LIN_IODFTCTRL_IODFTENA_SHIFT, LIN_IO_DFT_KEY);
 
    /* Disable specified error bits */
    HW_WR_FIELD32_RAW((base + CSL_LIN_IODFTCTRL), errors, 0U, CSL_FALSE);
 
    /* Clear the IO DFT Enable Key & Enable write access */
    HW_WR_FIELD32_RAW((base + CSL_LIN_IODFTCTRL), CSL_LIN_IODFTCTRL_IODFTENA_MASK, CSL_LIN_IODFTCTRL_IODFTENA_SHIFT, CSL_FALSE);
}
 
static inline void
LIN_enableSCIInterrupt(uint32_t base, uint32_t intFlags)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
    DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
           0U);
 
    /* Set specified interrupts */
    HW_WR_REG32_RAW((base + CSL_LIN_SCISETINT), (HW_RD_REG32_RAW(base + CSL_LIN_SCISETINT)|intFlags));
}
 
static inline void
LIN_disableSCIInterrupt(uint32_t base, uint32_t intFlags)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
    DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
           0U);
 
    /* Set specified interrupts */
    HW_WR_REG32_RAW((base + CSL_LIN_SCICLEARINT), (HW_RD_REG32_RAW(base + CSL_LIN_SCICLEARINT)|intFlags));
}
 
static inline void
LIN_clearSCIInterruptStatus(uint32_t base, uint32_t intFlags)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
    DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
           0U);
 
    /* Set specified interrupts */
    HW_WR_REG32_RAW((base + CSL_LIN_SCIFLR), (HW_RD_REG32_RAW(base + CSL_LIN_SCIFLR)|intFlags));
}
 
static inline void
LIN_setSCIInterruptLevel0(uint32_t base, uint32_t intFlags)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
    DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
           0U);
 
    /* Clear Status Flags */
    HW_WR_REG32_RAW((base + CSL_LIN_SCICLEARINTLVL), (HW_RD_REG32_RAW(base + CSL_LIN_SCICLEARINTLVL)|intFlags));
}
 
static inline void
LIN_setSCIInterruptLevel1(uint32_t base, uint32_t intFlags)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
    DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
           0U);
 
    /* Set interrupt levels to 1 */
    HW_WR_REG32_RAW((base + CSL_LIN_SCISETINTLVL), HW_RD_REG32_RAW(base + CSL_LIN_SCISETINTLVL)|intFlags);
}
 
static inline Bool
LIN_isSCIReceiverIdle(uint32_t base)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
    DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
           0U);
 
    /* Read Rx Idle flag and return status */
    return((HW_RD_REG32_RAW(base + CSL_LIN_SCIFLR) & CSL_LIN_SCIFLR_IDLE_MASK) == 0U);
}
 
static inline Bool
LIN_getSCITxFrameType(uint32_t base)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
    DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
           0U);
 
    /* Read Rx Idle flag and return status */
    return((HW_RD_REG32_RAW(base + CSL_LIN_SCIFLR) & CSL_LIN_SCIFLR_WAKEUP_MASK) == CSL_LIN_SCIFLR_WAKEUP_MASK);
}
 
static inline Bool
LIN_getSCIRxFrameType(uint32_t base)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
    DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
           0U);
 
    /* Read Rx Idle flag and return status */
    return((HW_RD_REG32_RAW(base + CSL_LIN_SCIFLR) & CSL_LIN_SCIFLR_RXWAKE_MASK) == CSL_LIN_SCIFLR_RXWAKE_MASK);
}
 
static inline Bool
LIN_isSCIBreakDetected(uint32_t base)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
    DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
           0U);
 
    /* Read Rx Idle flag and return status */
    return((HW_RD_REG32_RAW(base + CSL_LIN_SCIFLR) & CSL_LIN_SCIFLR_BRKDT_MASK) == CSL_LIN_SCIFLR_BRKDT_MASK);
}
 
static inline void
LIN_enableModule(uint32_t base)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
 
    /* Set reset bit. */
    HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR0), CSL_LIN_SCIGCR0_RESET_MASK, CSL_LIN_SCIGCR0_RESET_SHIFT, CSL_TRUE);
 
    /* Enable TX and RX pin control functionality. */
    HW_WR_FIELD32_RAW((base + CSL_LIN_SCIPIO0), CSL_LIN_SCIPIO0_RXFUNC_MASK, CSL_LIN_SCIPIO0_RXFUNC_SHIFT, CSL_TRUE);
    HW_WR_FIELD32_RAW((base + CSL_LIN_SCIPIO0), CSL_LIN_SCIPIO0_TXFUNC_MASK, CSL_LIN_SCIPIO0_TXFUNC_SHIFT, CSL_TRUE);
}
 
static inline void
LIN_disableModule(uint32_t base)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
 
    /* Disable TX and RX pin control functionality. */
    HW_WR_FIELD32_RAW((base + CSL_LIN_SCIPIO0), CSL_LIN_SCIPIO0_RXFUNC_MASK, CSL_LIN_SCIPIO0_RXFUNC_SHIFT, CSL_FALSE);
    HW_WR_FIELD32_RAW((base + CSL_LIN_SCIPIO0), CSL_LIN_SCIPIO0_TXFUNC_MASK, CSL_LIN_SCIPIO0_TXFUNC_SHIFT, CSL_FALSE);
 
    /* Reset reset bit. */
    HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR0), CSL_LIN_SCIGCR0_RESET_MASK, CSL_LIN_SCIGCR0_RESET_SHIFT, CSL_FALSE);
}
 
static inline void
LIN_setBaudRatePrescaler(uint32_t base, uint32_t prescaler,
                         uint32_t divider)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
    DebugP_assert(prescaler <= (CSL_LIN_BRSR_SCI_LIN_PSL_MASK | CSL_LIN_BRSR_SCI_LIN_PSH_MASK));
    DebugP_assert(divider <= (CSL_LIN_BRSR_M_MASK >> CSL_LIN_BRSR_M_SHIFT));
 
    /* Set baud rate prescaler and divider. */
    HW_WR_REG32_RAW((base + CSL_LIN_BRSR), (prescaler | (divider << CSL_LIN_BRSR_M_SHIFT)));
}
 
static inline void
LIN_enableDataTransmitter(uint32_t base)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
 
    /* Enable transmit bit. */
    HW_WR_REG32_RAW((base + CSL_LIN_SCIGCR1), HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1)|CSL_LIN_SCIGCR1_TXENA_MASK);
}
 
static inline void
LIN_disableDataTransmitter(uint32_t base)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
 
    /* Enable transmit bit. */
    HW_WR_REG32_RAW((base + CSL_LIN_SCIGCR1), HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1)&~(CSL_LIN_SCIGCR1_TXENA_MASK));
}
 
static inline void
LIN_enableDataReceiver(uint32_t base)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
 
    /* Enable receive bit. */
    HW_WR_REG32_RAW((base + CSL_LIN_SCIGCR1), HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1)|CSL_LIN_SCIGCR1_RXENA_MASK);
}
 
static inline void
LIN_disableDataReceiver(uint32_t base)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
 
    /* Disable receive bit. */
    HW_WR_REG32_RAW((base + CSL_LIN_SCIGCR1), HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1)&~(CSL_LIN_SCIGCR1_RXENA_MASK));
}
 
static inline void
LIN_performSoftwareReset(uint32_t base)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
 
    HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_SWNRST_MASK, CSL_LIN_SCIGCR1_SWNRST_SHIFT, CSL_TRUE);
}
 
static inline void
LIN_enterSoftwareReset(uint32_t base)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
 
    HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_SWNRST_MASK, CSL_LIN_SCIGCR1_SWNRST_SHIFT, CSL_FALSE);
}
 
static inline void
LIN_exitSoftwareReset(uint32_t base)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
 
    HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_SWNRST_MASK, CSL_LIN_SCIGCR1_SWNRST_SHIFT, CSL_TRUE);
}
 
static inline Bool
LIN_isBusBusy(uint32_t base)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
 
    return((HW_RD_REG32_RAW(base + CSL_LIN_SCIFLR) & CSL_LIN_SCIFLR_BUSY_MASK) == CSL_LIN_SCIFLR_BUSY_MASK);
}
 
static inline Bool
LIN_isTxBufferEmpty(uint32_t base)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
 
    return((HW_RD_REG32_RAW(base + CSL_LIN_SCIFLR) & CSL_LIN_SCIFLR_TXEMPTY_MASK) == CSL_LIN_SCIFLR_TXEMPTY_MASK);
}
 
static inline void
LIN_enableExtLoopback(uint32_t base, LIN_LoopbackType loopbackType,
                      LIN_AnalogLoopback path)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
 
    /* Clear the IO DFT Enable Key */
    HW_WR_FIELD32_RAW((base + CSL_LIN_IODFTCTRL), CSL_LIN_IODFTCTRL_IODFTENA_MASK, CSL_LIN_IODFTCTRL_IODFTENA_SHIFT, LIN_IO_DFT_KEY);
 
    /* Set loopback Type */
    HW_WR_FIELD32_RAW((base + CSL_LIN_IODFTCTRL), CSL_LIN_IODFTCTRL_LPBENA_MASK, CSL_LIN_IODFTCTRL_LPBENA_SHIFT, loopbackType);
 
    /* Set Analog Loopback Path */
    HW_WR_FIELD32_RAW((base + CSL_LIN_IODFTCTRL), CSL_LIN_IODFTCTRL_RXPENA_MASK, CSL_LIN_IODFTCTRL_RXPENA_SHIFT, path);
}
 
static inline void
LIN_disableExtLoopback(uint32_t base)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
 
    /* Set loopback Type */
    HW_WR_FIELD32_RAW((base + CSL_LIN_IODFTCTRL), CSL_LIN_IODFTCTRL_LPBENA_MASK, CSL_LIN_IODFTCTRL_LPBENA_SHIFT, CSL_FALSE);
 
    /* Set Analog Loopback Path */
    HW_WR_FIELD32_RAW((base + CSL_LIN_IODFTCTRL), CSL_LIN_IODFTCTRL_RXPENA_MASK, CSL_LIN_IODFTCTRL_RXPENA_SHIFT, CSL_FALSE);
}
 
static inline void
LIN_enableIntLoopback(uint32_t base)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
 
    /* Set loopback Type */
    HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_LOOPBACK_MASK, CSL_LIN_SCIGCR1_LOOPBACK_SHIFT, CSL_TRUE);
}
 
static inline void
LIN_disableIntLoopback(uint32_t base)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
 
    /* Set loopback Type */
    HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_LOOPBACK_MASK, CSL_LIN_SCIGCR1_LOOPBACK_SHIFT, CSL_FALSE);
}
 
static inline uint32_t
LIN_getInterruptStatus(uint32_t base)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
 
    /* Read and return the flag register */
    return(HW_RD_REG32_RAW(base + CSL_LIN_SCIFLR));
}
 
static inline uint32_t
LIN_getInterruptLevel(uint32_t base)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
 
    /* Read and return the flag register */
    return(HW_RD_REG32_RAW(base + CSL_LIN_SCISETINTLVL));
}
 
static inline uint16_t
LIN_getInterruptLine0Offset(uint32_t base)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
 
    /* Read and return the flag register */
    return(HW_RD_REG32_RAW(base + CSL_LIN_SCIINTVECT0) & CSL_LIN_SCIINTVECT0_INTVECT0_MASK);
}
 
static inline uint16_t
LIN_getInterruptLine1Offset(uint32_t base)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
 
    /* Read and return the flag register */
    return(HW_RD_REG32_RAW(base + CSL_LIN_SCIINTVECT1) & CSL_LIN_SCIINTVECT1_INTVECT1_MASK);
}
 
static inline void
LIN_enableMultibufferMode(uint32_t base)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
 
    /* Read and return the flag register */
    HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_MBUFMODE_MASK, CSL_LIN_SCIGCR1_MBUFMODE_SHIFT, CSL_TRUE);
}
 
static inline void
LIN_disableMultibufferMode(uint32_t base)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
 
    /* Read and return the flag register */
    HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_MBUFMODE_MASK, CSL_LIN_SCIGCR1_MBUFMODE_SHIFT, CSL_FALSE);
}
 
static inline void
LIN_setTransmitDelay(uint32_t base, uint16_t delay)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
    DebugP_assert(delay < 8U);
 
    /* Clear and Set the IO DFT Enable Key */
    HW_WR_FIELD32_RAW((base + CSL_LIN_IODFTCTRL), CSL_LIN_IODFTCTRL_IODFTENA_MASK, CSL_LIN_IODFTCTRL_IODFTENA_SHIFT, LIN_IO_DFT_KEY);
 
    /* Set the delay value */
    HW_WR_FIELD32_RAW((base + CSL_LIN_IODFTCTRL), CSL_LIN_IODFTCTRL_TXSHIFT_MASK, CSL_LIN_IODFTCTRL_TXSHIFT_SHIFT, delay);
 
    /* Clear the IO DFT Enable Key */
    HW_WR_FIELD32_RAW((base + CSL_LIN_IODFTCTRL), CSL_LIN_IODFTCTRL_IODFTENA_MASK, CSL_LIN_IODFTCTRL_IODFTENA_SHIFT, CSL_FALSE);
}
 
static inline void
LIN_setPinSampleMask(uint32_t base, LIN_PinSampleMask mask)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
 
    /* Clear and Set the IO DFT Enable Key */
    HW_WR_FIELD32_RAW((base + CSL_LIN_IODFTCTRL), CSL_LIN_IODFTCTRL_IODFTENA_MASK, CSL_LIN_IODFTCTRL_IODFTENA_SHIFT, LIN_IO_DFT_KEY);
 
    /* Set the delay value */
    HW_WR_FIELD32_RAW((base + CSL_LIN_IODFTCTRL), CSL_LIN_IODFTCTRL_PINSAMPLEMASK_MASK, CSL_LIN_IODFTCTRL_PINSAMPLEMASK_SHIFT, mask);
 
    /* Clear the IO DFT Enable Key */
    HW_WR_FIELD32_RAW((base + CSL_LIN_IODFTCTRL), CSL_LIN_IODFTCTRL_IODFTENA_MASK, CSL_LIN_IODFTCTRL_IODFTENA_SHIFT, CSL_FALSE);
}
 
static inline void
LIN_setDebugSuspendMode(uint32_t base, LIN_DebugMode mode)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
 
    /* Clear and Set the IO DFT Enable Key */
    HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_CONT_MASK, CSL_LIN_SCIGCR1_CONT_SHIFT, mode);
}
 
static inline void
LIN_enableGlobalInterrupt(uint32_t base, LIN_InterruptLine line)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
 
    HW_WR_REG32_RAW((base + CSL_LIN_LIN_GLB_INT_EN), HW_RD_REG32_RAW(base + CSL_LIN_LIN_GLB_INT_EN)|(CSL_LIN_LIN_GLB_INT_FLG_INT0_FLG_MASK<<(uint16_t)line));
}
 
static inline void
LIN_disableGlobalInterrupt(uint32_t base, LIN_InterruptLine line)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
 
    HW_WR_REG32_RAW((base + CSL_LIN_LIN_GLB_INT_EN), HW_RD_REG32_RAW(base + CSL_LIN_LIN_GLB_INT_EN)&(~(CSL_LIN_LIN_GLB_INT_FLG_INT0_FLG_MASK<<(uint16_t)line)));
}
 
static inline void
LIN_clearGlobalInterruptStatus(uint32_t base, LIN_InterruptLine line)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
 
    HW_WR_REG32_RAW((base + CSL_LIN_LIN_GLB_INT_CLR), (CSL_LIN_LIN_GLB_INT_FLG_INT0_FLG_MASK<<(uint16_t)line));
}
 
static inline Bool
LIN_getGlobalInterruptStatus(uint32_t base, LIN_InterruptLine line)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
 
    return((HW_RD_REG32_RAW(base + CSL_LIN_LIN_GLB_INT_FLG) & (CSL_LIN_LIN_GLB_INT_FLG_INT0_FLG_MASK<<(uint16_t)line))
                                                        == (CSL_LIN_LIN_GLB_INT_FLG_INT0_FLG_MASK<<(uint16_t)line));
}
 
static inline Bool
LIN_getPinStatus(uint32_t base, LIN_PinType pin)
{
    /* Check the arguments. */
    DebugP_assert(LIN_isBaseValid(base));
 
    return((HW_RD_REG32_RAW(base + CSL_LIN_SCIPIO2) & pin) == pin);
}
 
#ifdef __cplusplus
}
#endif
 
#endif  /* #ifndef LIN_V0_H_ */