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AM263x MCU+ SDK
08.05.00
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63 #include <drivers/hw_include/hw_types.h>
64 #include <drivers/hw_include/cslr_soc.h>
66 #include <drivers/hw_include/cslr_epwm.h>
79 #define EPWM_SYNC_OUT_SOURCE_M ((uint16_t)CSL_EPWM_EPWMSYNCOUTEN_SWEN_MASK |\
80 (uint16_t)CSL_EPWM_EPWMSYNCOUTEN_ZEROEN_MASK |\
81 (uint16_t)CSL_EPWM_EPWMSYNCOUTEN_CMPBEN_MASK |\
82 (uint16_t)CSL_EPWM_EPWMSYNCOUTEN_CMPCEN_MASK |\
83 (uint16_t)CSL_EPWM_EPWMSYNCOUTEN_CMPDEN_MASK |\
84 (uint16_t)CSL_EPWM_EPWMSYNCOUTEN_DCAEVT1EN_MASK |\
85 (uint16_t)CSL_EPWM_EPWMSYNCOUTEN_DCBEVT1EN_MASK)
94 #define EPWM_SYNC_OUT_PULSE_ON_SOFTWARE CSL_EPWM_EPWMSYNCOUTEN_SWEN_MASK
95 #define EPWM_SYNC_OUT_PULSE_ON_CNTR_ZERO CSL_EPWM_EPWMSYNCOUTEN_ZEROEN_MASK
97 #define EPWM_SYNC_OUT_PULSE_ON_CNTR_COMPARE_B CSL_EPWM_EPWMSYNCOUTEN_CMPBEN_MASK
99 #define EPWM_SYNC_OUT_PULSE_ON_CNTR_COMPARE_C CSL_EPWM_EPWMSYNCOUTEN_CMPCEN_MASK
101 #define EPWM_SYNC_OUT_PULSE_ON_CNTR_COMPARE_D CSL_EPWM_EPWMSYNCOUTEN_CMPDEN_MASK
103 #define EPWM_SYNC_OUT_PULSE_ON_DCA_EVT1_SYNC CSL_EPWM_EPWMSYNCOUTEN_DCAEVT1EN_MASK
105 #define EPWM_SYNC_OUT_PULSE_ON_DCB_EVT1_SYNC CSL_EPWM_EPWMSYNCOUTEN_DCBEVT1EN_MASK
107 #define EPWM_SYNC_OUT_PULSE_ON_ALL EPWM_SYNC_OUT_SOURCE_M
376 #define EPWM_TIME_BASE_STATUS_COUNT_DOWN (0U)
377 #define EPWM_TIME_BASE_STATUS_COUNT_UP (1U)
780 #define EPWM_DB_INPUT_EPWMA (0U)
781 #define EPWM_DB_INPUT_EPWMB (1U)
783 #define EPWM_DB_INPUT_DB_RED (2U)
864 #define EPWM_TZ_SIGNAL_CBC1 (0x1U)
865 #define EPWM_TZ_SIGNAL_CBC2 (0x2U)
867 #define EPWM_TZ_SIGNAL_CBC3 (0x4U)
869 #define EPWM_TZ_SIGNAL_CBC4 (0x8U)
871 #define EPWM_TZ_SIGNAL_CBC5 (0x10U)
873 #define EPWM_TZ_SIGNAL_CBC6 (0x20U)
875 #define EPWM_TZ_SIGNAL_DCAEVT2 (0x40U)
877 #define EPWM_TZ_SIGNAL_DCBEVT2 (0x80U)
879 #define EPWM_TZ_SIGNAL_OSHT1 (0x100U)
881 #define EPWM_TZ_SIGNAL_OSHT2 (0x200U)
883 #define EPWM_TZ_SIGNAL_OSHT3 (0x400U)
885 #define EPWM_TZ_SIGNAL_OSHT4 (0x800U)
887 #define EPWM_TZ_SIGNAL_OSHT5 (0x1000U)
889 #define EPWM_TZ_SIGNAL_OSHT6 (0x2000U)
891 #define EPWM_TZ_SIGNAL_DCAEVT1 (0x4000U)
893 #define EPWM_TZ_SIGNAL_DCBEVT1 (0x8000U)
895 #define EPWM_TZ_SIGNAL_CAPEVT_OST (0x10000U)
897 #define EPWM_TZ_SIGNAL_CAPEVT_CBC (0x1000000U)
1020 #define EPWM_TZ_INTERRUPT_CBC (0x2U)
1021 #define EPWM_TZ_INTERRUPT_OST (0x4U)
1023 #define EPWM_TZ_INTERRUPT_DCAEVT1 (0x8U)
1025 #define EPWM_TZ_INTERRUPT_DCAEVT2 (0x10U)
1027 #define EPWM_TZ_INTERRUPT_DCBEVT1 (0x20U)
1029 #define EPWM_TZ_INTERRUPT_DCBEVT2 (0x40U)
1031 #define EPWM_TZ_INTERRUPT_CAPEVT (0x80U)
1040 #define EPWM_TZ_FLAG_CBC (0x2U)
1041 #define EPWM_TZ_FLAG_OST (0x4U)
1043 #define EPWM_TZ_FLAG_DCAEVT1 (0x8U)
1045 #define EPWM_TZ_FLAG_DCAEVT2 (0x10U)
1047 #define EPWM_TZ_FLAG_DCBEVT1 (0x20U)
1049 #define EPWM_TZ_FLAG_DCBEVT2 (0x40U)
1051 #define EPWM_TZ_FLAG_CAPEVT (0x80U)
1061 #define EPWM_TZ_INTERRUPT (0x1U)
1071 #define EPWM_TZ_CBC_FLAG_1 (0x1U)
1072 #define EPWM_TZ_CBC_FLAG_2 (0x2U)
1074 #define EPWM_TZ_CBC_FLAG_3 (0x4U)
1076 #define EPWM_TZ_CBC_FLAG_4 (0x8U)
1078 #define EPWM_TZ_CBC_FLAG_5 (0x10U)
1080 #define EPWM_TZ_CBC_FLAG_6 (0x20U)
1082 #define EPWM_TZ_CBC_FLAG_DCAEVT2 (0x40U)
1084 #define EPWM_TZ_CBC_FLAG_DCBEVT2 (0x80U)
1086 #define EPWM_TZ_CBC_FLAG_CAPEVT (0x100U)
1097 #define EPWM_TZ_OST_FLAG_OST1 (0x1U)
1098 #define EPWM_TZ_OST_FLAG_OST2 (0x2U)
1100 #define EPWM_TZ_OST_FLAG_OST3 (0x4U)
1102 #define EPWM_TZ_OST_FLAG_OST4 (0x8U)
1104 #define EPWM_TZ_OST_FLAG_OST5 (0x10U)
1106 #define EPWM_TZ_OST_FLAG_OST6 (0x20U)
1108 #define EPWM_TZ_OST_FLAG_DCAEVT1 (0x40U)
1110 #define EPWM_TZ_OST_FLAG_DCBEVT1 (0x80U)
1112 #define EPWM_TZ_OST_FLAG_CAPEVT (0x100U)
1138 #define EPWM_TZ_FORCE_EVENT_CBC (0x2U)
1139 #define EPWM_TZ_FORCE_EVENT_OST (0x4U)
1141 #define EPWM_TZ_FORCE_EVENT_DCAEVT1 (0x8U)
1143 #define EPWM_TZ_FORCE_EVENT_DCAEVT2 (0x10U)
1145 #define EPWM_TZ_FORCE_EVENT_DCBEVT1 (0x20U)
1147 #define EPWM_TZ_FORCE_EVENT_DCBEVT2 (0x40U)
1149 #define EPWM_TZ_FORCE_EVENT_CAPEVT (0x80U)
1159 #define EPWM_TZ_SELECT_TRIPOUT_OST (0x1)
1160 #define EPWM_TZ_SELECT_TRIPOUT_CBC (0x2)
1162 #define EPWM_TZ_SELECT_TRIPOUT_TZ1 (0x4)
1164 #define EPWM_TZ_SELECT_TRIPOUT_TZ2 (0x8)
1166 #define EPWM_TZ_SELECT_TRIPOUT_TZ3 (0x10)
1168 #define EPWM_TZ_SELECT_TRIPOUT_TZ4 (0x20)
1170 #define EPWM_TZ_SELECT_TRIPOUT_TZ5 (0x40)
1172 #define EPWM_TZ_SELECT_TRIPOUT_TZ6 (0x80)
1174 #define EPWM_TZ_SELECT_TRIPOUT_DCAEVT1 (0x100)
1176 #define EPWM_TZ_SELECT_TRIPOUT_DCAEVT2 (0x200)
1178 #define EPWM_TZ_SELECT_TRIPOUT_DCBEVT1 (0x400)
1180 #define EPWM_TZ_SELECT_TRIPOUT_DCBEVT2 (0x800)
1182 #define EPWM_TZ_SELECT_TRIPOUT_CAPEVT (0x1000)
1192 #define EPWM_INT_TBCTR_ZERO (1U)
1193 #define EPWM_INT_TBCTR_PERIOD (2U)
1195 #define EPWM_INT_TBCTR_ETINTMIX (3U)
1197 #define EPWM_INT_TBCTR_U_CMPA (4U)
1199 #define EPWM_INT_TBCTR_U_CMPC (8U)
1201 #define EPWM_INT_TBCTR_D_CMPA (5U)
1203 #define EPWM_INT_TBCTR_D_CMPC (10U)
1205 #define EPWM_INT_TBCTR_U_CMPB (6U)
1207 #define EPWM_INT_TBCTR_U_CMPD (12U)
1209 #define EPWM_INT_TBCTR_D_CMPB (7U)
1211 #define EPWM_INT_TBCTR_D_CMPD (14U)
1221 #define EPWM_INT_MIX_TBCTR_ZERO (0x1)
1222 #define EPWM_INT_MIX_TBCTR_PERIOD (0x2)
1224 #define EPWM_INT_MIX_TBCTR_U_CMPA (0x4)
1226 #define EPWM_INT_MIX_TBCTR_D_CMPA (0x8)
1228 #define EPWM_INT_MIX_TBCTR_U_CMPB (0x10)
1230 #define EPWM_INT_MIX_TBCTR_D_CMPB (0x20)
1232 #define EPWM_INT_MIX_TBCTR_U_CMPC (0x40)
1234 #define EPWM_INT_MIX_TBCTR_D_CMPC (0x80)
1236 #define EPWM_INT_MIX_TBCTR_U_CMPD (0x100)
1238 #define EPWM_INT_MIX_TBCTR_D_CMPD (0x200)
1240 #define EPWM_INT_MIX_DCAEVT1 (0x400)
1348 #define EPWM_DC_COMBINATIONAL_TRIPIN1 (0x1U)
1349 #define EPWM_DC_COMBINATIONAL_TRIPIN2 (0x2U)
1351 #define EPWM_DC_COMBINATIONAL_TRIPIN3 (0x4U)
1353 #define EPWM_DC_COMBINATIONAL_TRIPIN4 (0x8U)
1355 #define EPWM_DC_COMBINATIONAL_TRIPIN5 (0x10U)
1357 #define EPWM_DC_COMBINATIONAL_TRIPIN6 (0x20U)
1359 #define EPWM_DC_COMBINATIONAL_TRIPIN7 (0x40U)
1361 #define EPWM_DC_COMBINATIONAL_TRIPIN8 (0x80U)
1363 #define EPWM_DC_COMBINATIONAL_TRIPIN9 (0x100U)
1365 #define EPWM_DC_COMBINATIONAL_TRIPIN10 (0x200U)
1367 #define EPWM_DC_COMBINATIONAL_TRIPIN11 (0x400U)
1369 #define EPWM_DC_COMBINATIONAL_TRIPIN12 (0x800U)
1371 #define EPWM_DC_COMBINATIONAL_TRIPIN13 (0x1000U)
1373 #define EPWM_DC_COMBINATIONAL_TRIPIN14 (0x2000U)
1375 #define EPWM_DC_COMBINATIONAL_TRIPIN15 (0x4000U)
1403 #define EPWM_DC_TBCTR_ZERO (0x1)
1404 #define EPWM_DC_TBCTR_PERIOD (0x2)
1406 #define EPWM_DC_TBCTR_U_CMPA (0x4)
1408 #define EPWM_DC_TBCTR_D_CMPA (0x8)
1410 #define EPWM_DC_TBCTR_U_CMPB (0x10)
1412 #define EPWM_DC_TBCTR_D_CMPB (0x20)
1414 #define EPWM_DC_TBCTR_U_CMPC (0x40)
1416 #define EPWM_DC_TBCTR_D_CMPC (0x80)
1418 #define EPWM_DC_TBCTR_U_CMPD (0x100)
1420 #define EPWM_DC_TBCTR_D_CMPD (0x200)
1567 #define EPWM_GL_REGISTER_TBPRD_TBPRDHR (0x1U)
1568 #define EPWM_GL_REGISTER_CMPA_CMPAHR (0x2U)
1570 #define EPWM_GL_REGISTER_CMPB_CMPBHR (0x4U)
1572 #define EPWM_GL_REGISTER_CMPC (0x8U)
1574 #define EPWM_GL_REGISTER_CMPD (0x10U)
1576 #define EPWM_GL_REGISTER_DBRED_DBREDHR (0x20U)
1578 #define EPWM_GL_REGISTER_DBFED_DBFEDHR (0x40U)
1580 #define EPWM_GL_REGISTER_DBCTL (0x80U)
1582 #define EPWM_GL_REGISTER_AQCTLA_AQCTLA2 (0x100U)
1584 #define EPWM_GL_REGISTER_AQCTLB_AQCTLB2 (0x200U)
1586 #define EPWM_GL_REGISTER_AQCSFRC (0x400U)
1720 #define EPWM_MINDB_BLOCK_A (0x0)
1721 #define EPWM_MINDB_BLOCK_B (0x1)
1730 #define EPWM_MINDB_NO_INVERT (0x0)
1731 #define EPWM_MINDB_INVERT (0x1)
1740 #define EPWM_MINDB_INVERT_LOGICAL_AND (0x0)
1741 #define EPWM_MINDB_LOGICAL_OR (0x1)
1750 #define EPWM_MINDB_PWMB (0x0)
1751 #define EPWM_MINDB_PWM_OUTXBAR_OUT1 (0x1)
1753 #define EPWM_MINDB_PWM_OUTXBAR_OUT2 (0x2)
1755 #define EPWM_MINDB_PWM_OUTXBAR_OUT3 (0x3)
1757 #define EPWM_MINDB_PWM_OUTXBAR_OUT4 (0x4)
1759 #define EPWM_MINDB_PWM_OUTXBAR_OUT5 (0x5)
1761 #define EPWM_MINDB_PWM_OUTXBAR_OUT6 (0x6)
1763 #define EPWM_MINDB_PWM_OUTXBAR_OUT7 (0x7)
1765 #define EPWM_MINDB_PWM_OUTXBAR_OUT8 (0x8)
1767 #define EPWM_MINDB_PWM_OUTXBAR_OUT9 (0x9)
1769 #define EPWM_MINDB_PWM_OUTXBAR_OUT10 (0xA)
1771 #define EPWM_MINDB_PWM_OUTXBAR_OUT11 (0xB)
1773 #define EPWM_MINDB_PWM_OUTXBAR_OUT12 (0xC)
1775 #define EPWM_MINDB_PWM_OUTXBAR_OUT13 (0xD)
1777 #define EPWM_MINDB_PWM_OUTXBAR_OUT14 (0xE)
1779 #define EPWM_MINDB_PWM_OUTXBAR_OUT15 (0xF)
1788 #define EPWM_MINDB_BLOCKING_SIGNAL_SAME (0x0)
1789 #define EPWM_MINDB_BLOCKING_SIGNAL_DIFF (0x1)
1798 #define EPWM_MINDB_ICSS_XBAR_OUT0 (0x0)
1799 #define EPWM_MINDB_ICSS_XBAR_OUT1 (0x1)
1801 #define EPWM_MINDB_ICSS_XBAR_OUT2 (0x2)
1803 #define EPWM_MINDB_ICSS_XBAR_OUT3 (0x3)
1805 #define EPWM_MINDB_ICSS_XBAR_OUT4 (0x4)
1807 #define EPWM_MINDB_ICSS_XBAR_OUT5 (0x5)
1809 #define EPWM_MINDB_ICSS_XBAR_OUT6 (0x6)
1811 #define EPWM_MINDB_ICSS_XBAR_OUT7 (0x7)
1813 #define EPWM_MINDB_ICSS_XBAR_OUT8 (0x8)
1815 #define EPWM_MINDB_ICSS_XBAR_OUT9 (0x9)
1817 #define EPWM_MINDB_ICSS_XBAR_OUT10 (0xA)
1819 #define EPWM_MINDB_ICSS_XBAR_OUT11 (0xB)
1821 #define EPWM_MINDB_ICSS_XBAR_OUT12 (0xC)
1823 #define EPWM_MINDB_ICSS_XBAR_OUT13 (0xD)
1825 #define EPWM_MINDB_ICSS_XBAR_OUT14 (0xE)
1827 #define EPWM_MINDB_ICSS_XBAR_OUT15 (0xF)
2061 #define EPWM_XCMP_ACTIVE (0x0)
2062 #define EPWM_XCMP_SHADOW1 (0x1)
2064 #define EPWM_XCMP_SHADOW2 (0x2)
2066 #define EPWM_XCMP_SHADOW3 (0x3)
2435 #define EPWM_DE_CHANNEL_A (0x0)
2436 #define EPWM_DE_CHANNEL_B (0x1)
2446 #define EPWM_DE_COUNT_UP (0x0)
2447 #define EPWM_DE_COUNT_DOWN (0x1)
2457 #define EPWM_DE_TRIPL (0x1)
2458 #define EPWM_DE_TRIPH (0x0)
2468 #define EPWM_DCxCTL_STEP (CSL_EPWM_DCBCTL - CSL_EPWM_DCACTL)
2469 #define EPWM_DCxxTRIPSEL (CSL_EPWM_DCALTRIPSEL - CSL_EPWM_DCAHTRIPSEL)
2470 #define EPWM_XREGSHDWxSTS_STEP (CSL_EPWM_XREGSHDW2STS-CSL_EPWM_XREGSHDW1STS)
2471 #define EPWM_XCMPx_ACTIVE_STEP (CSL_EPWM_XCMP2_ACTIVE-CSL_EPWM_XCMP1_ACTIVE)
2472 #define EPWM_XCMPx_STEP (CSL_EPWM_XCMP1_SHDW2-CSL_EPWM_XCMP1_SHDW1)
2473 #define EPWM_XCMPx_SHDWx_STEP (CSL_EPWM_XCMP2_SHDW1-CSL_EPWM_XCMP1_SHDW1)
2474 #define EPWM_LOCK_KEY (0xA5A50000U)
2515 HW_WR_REG16(base + CSL_EPWM_TBCTR, count);
2542 HW_WR_REG16(base + CSL_EPWM_TBCTL,
2543 (HW_RD_REG16(base + CSL_EPWM_TBCTL) |
2544 CSL_EPWM_TBCTL_PHSDIR_MASK));
2551 HW_WR_REG16(base + CSL_EPWM_TBCTL,
2552 (HW_RD_REG16(base + CSL_EPWM_TBCTL) &
2553 ~CSL_EPWM_TBCTL_PHSDIR_MASK));
2587 HW_WR_REG16(base + CSL_EPWM_TBCTL,
2588 ((HW_RD_REG16(base + CSL_EPWM_TBCTL) &
2589 ~(CSL_EPWM_TBCTL_CLKDIV_MASK | CSL_EPWM_TBCTL_HSPCLKDIV_MASK)) |
2590 (((uint16_t)prescaler << CSL_EPWM_TBCTL_CLKDIV_SHIFT) |
2591 ((uint16_t)highSpeedPrescaler << CSL_EPWM_TBCTL_HSPCLKDIV_SHIFT))));
2613 HW_WR_REG16(base + CSL_EPWM_TBCTL,
2614 HW_RD_REG16(base + CSL_EPWM_TBCTL) | CSL_EPWM_TBCTL_SWFSYNC_MASK);
2653 HW_WR_REG16(base + CSL_EPWM_EPWMSYNCINSEL,
2654 ((HW_RD_REG16(base + CSL_EPWM_EPWMSYNCINSEL) &
2655 (~CSL_EPWM_EPWMSYNCINSEL_SEL_MASK)) |
2656 ((uint16_t)source & CSL_EPWM_EPWMSYNCINSEL_SEL_MASK)));
2705 HW_WR_REG16(base + CSL_EPWM_EPWMSYNCOUTEN,
2706 (HW_RD_REG16(base + CSL_EPWM_EPWMSYNCOUTEN) |
2750 HW_WR_REG16(base + CSL_EPWM_EPWMSYNCOUTEN,
2751 (HW_RD_REG16(base + CSL_EPWM_EPWMSYNCOUTEN) &
2752 ~((uint16_t)source)));
2779 HW_WR_REG16(base + CSL_EPWM_TBCTL3,
2780 ((HW_RD_REG16(base + CSL_EPWM_TBCTL3) &
2781 ~(CSL_EPWM_TBCTL3_OSSFRCEN_MASK)) |
2782 (uint16_t)trigger));
2809 HW_WR_REG16(base + CSL_EPWM_TBCTL,
2810 (HW_RD_REG16(base + CSL_EPWM_TBCTL) & ~CSL_EPWM_TBCTL_PRDLD_MASK));
2817 HW_WR_REG16(base + CSL_EPWM_TBCTL,
2818 (HW_RD_REG16(base + CSL_EPWM_TBCTL) | CSL_EPWM_TBCTL_PRDLD_MASK));
2840 HW_WR_REG16(base + CSL_EPWM_TBCTL,
2841 (HW_RD_REG16(base + CSL_EPWM_TBCTL) | CSL_EPWM_TBCTL_PHSEN_MASK));
2861 HW_WR_REG16(base + CSL_EPWM_TBCTL,
2862 (HW_RD_REG16(base + CSL_EPWM_TBCTL) & ~CSL_EPWM_TBCTL_PHSEN_MASK));
2888 HW_WR_REG16(base + CSL_EPWM_TBCTL,
2889 ((HW_RD_REG16(base + CSL_EPWM_TBCTL) &
2890 ~(CSL_EPWM_TBCTL_CTRMODE_MASK)) | ((uint16_t)counterMode)));
2920 HW_WR_REG16(base + CSL_EPWM_TBCTL2,
2921 ((HW_RD_REG16(base + CSL_EPWM_TBCTL2) &
2922 ~(CSL_EPWM_TBCTL2_PRDLDSYNC_MASK)) |
2923 ((uint16_t)shadowLoadMode << CSL_EPWM_TBCTL2_PRDLDSYNC_SHIFT)));
2942 HW_WR_REG16(base + CSL_EPWM_TBCTL2,
2943 (HW_RD_REG16(base + CSL_EPWM_TBCTL2) |
2944 CSL_EPWM_TBCTL2_OSHTSYNCMODE_MASK));
2964 HW_WR_REG16(base + CSL_EPWM_TBCTL2,
2965 (HW_RD_REG16(base + CSL_EPWM_TBCTL2) &
2966 ~CSL_EPWM_TBCTL2_OSHTSYNCMODE_MASK));
2986 HW_WR_REG16(base + CSL_EPWM_TBCTL2,
2987 (HW_RD_REG16(base + CSL_EPWM_TBCTL2) | CSL_EPWM_TBCTL2_OSHTSYNC_MASK));
3001 static inline uint16_t
3007 return(HW_RD_REG16(base + CSL_EPWM_TBCTR));
3028 return(((HW_RD_REG16(base + CSL_EPWM_TBSTS) &
3029 CSL_EPWM_TBSTS_CTRMAX_MASK) ==
3030 CSL_EPWM_TBSTS_CTRMAX_MASK) ?
true :
false);
3051 HW_WR_REG16(base + CSL_EPWM_TBSTS,
3052 (HW_RD_REG16(base + CSL_EPWM_TBSTS) | CSL_EPWM_TBSTS_CTRMAX_MASK));
3073 return(((HW_RD_REG16(base + CSL_EPWM_TBSTS) & CSL_EPWM_TBSTS_SYNCI_MASK) ==
3074 CSL_EPWM_TBSTS_SYNCI_MASK) ?
true :
false);
3094 HW_WR_REG16(base + CSL_EPWM_TBSTS,
3095 (HW_RD_REG16(base + CSL_EPWM_TBSTS) | CSL_EPWM_TBSTS_SYNCI_MASK));
3111 static inline uint16_t
3117 return(HW_RD_REG16(base + CSL_EPWM_TBSTS) & CSL_EPWM_TBSTS_CTRDIR_MASK);
3141 HW_WR_REG32(base + CSL_EPWM_TBPHS,
3142 ((HW_RD_REG32(base + CSL_EPWM_TBPHS) &
3143 ~((uint32_t)CSL_EPWM_TBPHS_TBPHS_MASK)) |
3144 ((uint32_t)phaseCount << CSL_EPWM_TBPHS_TBPHS_SHIFT)));
3170 HW_WR_REG16(base + CSL_EPWM_TBPRD, periodCount);
3184 static inline uint16_t
3190 return(HW_RD_REG16(base + CSL_EPWM_TBPRD));
3261 uint32_t registerOffset;
3265 registerOffset = base + CSL_EPWM_EPWMXLINK2;
3270 registerOffset = base + CSL_EPWM_EPWMXLINKXLOAD;
3275 registerOffset = base + CSL_EPWM_EPWMXLINK;
3281 HW_WR_REG32(registerOffset,
3282 ((HW_RD_REG32(registerOffset) &
3283 ~((uint32_t)CSL_EPWM_EPWMXLINK_TBPRDLINK_MASK << linkComp)) |
3284 ((uint32_t)epwmLink << linkComp)));
3322 uint16_t syncModeOffset;
3323 uint16_t loadModeOffset;
3324 uint16_t shadowModeOffset;
3325 uint32_t registerOffset;
3330 syncModeOffset = CSL_EPWM_CMPCTL_LOADASYNC_SHIFT;
3331 loadModeOffset = CSL_EPWM_CMPCTL_LOADAMODE_SHIFT;
3332 shadowModeOffset = CSL_EPWM_CMPCTL_SHDWAMODE_SHIFT;
3336 syncModeOffset = CSL_EPWM_CMPCTL_LOADBSYNC_SHIFT;
3337 loadModeOffset = CSL_EPWM_CMPCTL_LOADBMODE_SHIFT;
3338 shadowModeOffset = CSL_EPWM_CMPCTL_SHDWBMODE_SHIFT;
3348 registerOffset = base + CSL_EPWM_CMPCTL;
3352 registerOffset = base + CSL_EPWM_CMPCTL2;
3359 HW_WR_REG16(registerOffset,
3360 ((HW_RD_REG16(registerOffset) &
3361 ~((CSL_EPWM_CMPCTL_LOADASYNC_MAX << syncModeOffset) |
3362 (CSL_EPWM_CMPCTL_LOADAMODE_MAX << loadModeOffset) |
3363 (CSL_EPWM_CMPCTL_SHDWAMODE_MAX << shadowModeOffset))) |
3364 ((((uint16_t)loadMode >> 2U) << syncModeOffset) |
3365 (((uint16_t)loadMode & CSL_EPWM_CMPCTL_LOADASYNC_MAX) <<
3391 uint16_t shadowModeOffset;
3392 uint32_t registerOffset;
3397 shadowModeOffset = CSL_EPWM_CMPCTL_SHDWAMODE_SHIFT;
3401 shadowModeOffset = CSL_EPWM_CMPCTL_SHDWBMODE_SHIFT;
3411 registerOffset = base + CSL_EPWM_CMPCTL;
3415 registerOffset = base + CSL_EPWM_CMPCTL2;
3421 HW_WR_REG16(registerOffset,
3422 (HW_RD_REG16(registerOffset) |
3423 (CSL_EPWM_CMPCTL_SHDWAMODE_MAX << shadowModeOffset)));
3449 uint32_t registerOffset;
3454 registerOffset = base + CSL_EPWM_CMPA + (uint16_t)compModule;
3465 HW_WR_REG16(registerOffset + 0x2U, compCount);
3472 HW_WR_REG16(registerOffset, compCount);
3493 static inline uint16_t
3496 uint32_t registerOffset;
3502 registerOffset = base + CSL_EPWM_CMPA + (uint16_t)compModule;
3513 compCount = (uint16_t)((HW_RD_REG32(registerOffset) &
3514 (uint32_t)CSL_EPWM_CMPA_CMPA_MASK) >>
3515 CSL_EPWM_CMPA_CMPA_SHIFT);
3522 compCount = HW_RD_REG16(registerOffset);
3556 return((((HW_RD_REG32(base + CSL_EPWM_CMPCTL) >>
3557 ((((uint16_t)compModule >> 1U) & 0x2U) +
3558 CSL_EPWM_CMPCTL_SHDWAFULL_SHIFT)) &
3559 0x1U) == 0x1U) ?
true:
false);
3600 uint16_t syncModeOffset;
3601 uint16_t shadowModeOffset;
3603 syncModeOffset = CSL_EPWM_AQCTL_LDAQASYNC_SHIFT + (uint16_t)aqModule;
3604 shadowModeOffset = CSL_EPWM_AQCTL_SHDWAQAMODE_SHIFT + (uint16_t)aqModule;
3610 HW_WR_REG16(base + CSL_EPWM_AQCTL,
3611 ((HW_RD_REG16(base + CSL_EPWM_AQCTL) &
3612 (~((CSL_EPWM_AQCTL_LDAQAMODE_MASK << (uint16_t)aqModule) |
3613 (CSL_EPWM_AQCTL_LDAQASYNC_MAX << (uint16_t)syncModeOffset))) |
3614 (CSL_EPWM_AQCTL_SHDWAQAMODE_MAX << shadowModeOffset)) |
3615 ((((uint16_t)loadMode >> 2U) << syncModeOffset) |
3616 (((uint16_t)loadMode & CSL_EPWM_AQCTL_LDAQAMODE_MASK) <<
3617 (uint16_t)aqModule))));
3640 uint16_t shadowModeOffset;
3642 shadowModeOffset = CSL_EPWM_AQCTL_SHDWAQAMODE_SHIFT + (uint16_t)aqModule;
3648 HW_WR_REG16(base + CSL_EPWM_AQCTL,
3649 (HW_RD_REG16(base + CSL_EPWM_AQCTL) &
3650 ~(CSL_EPWM_AQCTL_SHDWAQAMODE_MAX << shadowModeOffset)));
3682 HW_WR_REG16(base + CSL_EPWM_AQTSRCSEL,
3683 ((HW_RD_REG16(base + CSL_EPWM_AQTSRCSEL) &
3684 (~CSL_EPWM_AQTSRCSEL_T1SEL_MASK)) |
3685 ((uint16_t)trigger)));
3717 HW_WR_REG16(base + CSL_EPWM_AQTSRCSEL,
3718 ((HW_RD_REG16(base + CSL_EPWM_AQTSRCSEL) &
3719 (~CSL_EPWM_AQTSRCSEL_T2SEL_MASK)) |
3720 ((uint16_t)trigger << CSL_EPWM_AQTSRCSEL_T2SEL_SHIFT)));
3771 uint32_t registerOffset;
3772 uint32_t registerTOffset;
3777 registerOffset = CSL_EPWM_AQCTLA + (uint16_t)epwmOutput;
3778 registerTOffset = CSL_EPWM_AQCTLA2 + (uint16_t)epwmOutput;
3783 if(((uint16_t)
event & 0x1U) == 1U)
3788 HW_WR_REG16(base + registerTOffset,
3789 ((HW_RD_REG16(base + registerTOffset) &
3790 ~(CSL_EPWM_AQCTLA_ZRO_MAX << ((uint16_t)event - 1U))) |
3791 ((uint16_t)output << ((uint16_t)event - 1U))));
3798 HW_WR_REG16(base + registerOffset,
3799 ((HW_RD_REG16(base + registerOffset) &
3800 ~(CSL_EPWM_AQCTLA_ZRO_MAX << (uint16_t)event)) |
3801 ((uint16_t)output << (uint16_t)event)));
3894 uint32_t registerOffset;
3899 registerOffset = CSL_EPWM_AQCTLA + (uint16_t)epwmOutput;
3904 HW_WR_REG16(base + registerOffset, action);
3973 uint32_t registerTOffset;
3978 registerTOffset = CSL_EPWM_AQCTLA2 + (uint16_t)epwmOutput;
3983 HW_WR_REG16(base + registerTOffset, action);
4016 HW_WR_REG16(base + CSL_EPWM_AQSFRC,
4017 ((HW_RD_REG16(base + CSL_EPWM_AQSFRC) &
4018 ~CSL_EPWM_AQSFRC_RLDCSF_MASK) |
4019 ((uint16_t)mode << CSL_EPWM_AQSFRC_RLDCSF_SHIFT)));
4054 HW_WR_REG16(base + CSL_EPWM_AQCSFRC,
4055 ((HW_RD_REG16(base + CSL_EPWM_AQCSFRC) &
4056 ~CSL_EPWM_AQCSFRC_CSFA_MASK) |
4057 ((uint16_t)output)));
4061 HW_WR_REG16(base + CSL_EPWM_AQCSFRC,
4062 ((HW_RD_REG16(base + CSL_EPWM_AQCSFRC) &
4063 ~CSL_EPWM_AQCSFRC_CSFB_MASK) |
4064 ((uint16_t)output << CSL_EPWM_AQCSFRC_CSFB_SHIFT)));
4102 HW_WR_REG16(base + CSL_EPWM_AQSFRC,
4103 ((HW_RD_REG16(base + CSL_EPWM_AQSFRC) &
4104 ~CSL_EPWM_AQSFRC_ACTSFA_MASK) |
4105 ((uint16_t)output)));
4109 HW_WR_REG16(base + CSL_EPWM_AQSFRC,
4110 ((HW_RD_REG16(base + CSL_EPWM_AQSFRC) &
4111 ~CSL_EPWM_AQSFRC_ACTSFB_MASK) |
4112 ((uint16_t)output << CSL_EPWM_AQSFRC_ACTSFB_SHIFT)));
4141 HW_WR_REG16(base + CSL_EPWM_AQSFRC,
4142 (HW_RD_REG16(base + CSL_EPWM_AQSFRC) |
4143 CSL_EPWM_AQSFRC_OTSFA_MASK));
4147 HW_WR_REG16(base + CSL_EPWM_AQSFRC,
4148 (HW_RD_REG16(base + CSL_EPWM_AQSFRC) |
4149 CSL_EPWM_AQSFRC_OTSFB_MASK));
4180 bool enableSwapMode)
4184 mask = (uint16_t)1U << ((uint16_t)output + CSL_EPWM_DBCTL_OUTSWAP_SHIFT);
4191 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4192 (HW_RD_REG16(base + CSL_EPWM_DBCTL) | mask));
4199 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4200 (HW_RD_REG16(base + CSL_EPWM_DBCTL) & ~mask));
4228 bool enableDelayMode)
4232 mask = 1U << ((uint16_t)(delayMode + CSL_EPWM_DBCTL_OUT_MODE_SHIFT));
4239 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4240 (HW_RD_REG16(base + CSL_EPWM_DBCTL) | mask));
4247 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4248 (HW_RD_REG16(base + CSL_EPWM_DBCTL) & ~mask));
4280 shift = (((uint16_t)delayMode ^ 0x1U) + CSL_EPWM_DBCTL_POLSEL_SHIFT);
4285 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4286 ((HW_RD_REG16(base + CSL_EPWM_DBCTL) & ~ (1U << shift)) |
4287 ((uint16_t)polarity << shift)));
4319 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4320 ((HW_RD_REG16(base + CSL_EPWM_DBCTL) &
4321 ~(1U << (CSL_EPWM_DBCTL_IN_MODE_SHIFT))) |
4322 (input << CSL_EPWM_DBCTL_IN_MODE_SHIFT)));
4360 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4361 (HW_RD_REG16(base + CSL_EPWM_DBCTL) |
4362 CSL_EPWM_DBCTL_DEDB_MODE_MASK));
4369 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4370 (HW_RD_REG16(base + CSL_EPWM_DBCTL) &
4371 ~CSL_EPWM_DBCTL_DEDB_MODE_MASK));
4376 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4377 ((HW_RD_REG16(base + CSL_EPWM_DBCTL) &
4378 ~(1U << (CSL_EPWM_DBCTL_IN_MODE_SHIFT + 1U))) |
4379 (input << (CSL_EPWM_DBCTL_IN_MODE_SHIFT + 1U))));
4409 HW_WR_REG16(base + CSL_EPWM_DBCTL2,
4410 ((HW_RD_REG16(base + CSL_EPWM_DBCTL2) &
4411 ~CSL_EPWM_DBCTL2_LOADDBCTLMODE_MASK) |
4412 (CSL_EPWM_DBCTL2_LOADDBCTLMODE_MASK | (uint16_t)loadMode)));
4433 HW_WR_REG16(base + CSL_EPWM_DBCTL2,
4434 (HW_RD_REG16(base + CSL_EPWM_DBCTL2) &
4435 ~CSL_EPWM_DBCTL2_SHDWDBCTLMODE_MASK));
4463 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4464 ((HW_RD_REG16(base + CSL_EPWM_DBCTL) &
4465 ~CSL_EPWM_DBCTL_LOADREDMODE_MASK) |
4466 ((uint16_t)CSL_EPWM_DBCTL_SHDWDBREDMODE_MASK |
4467 ((uint16_t)loadMode << CSL_EPWM_DBCTL_LOADREDMODE_SHIFT))));
4488 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4489 (HW_RD_REG16(base + CSL_EPWM_DBCTL) &
4490 ~CSL_EPWM_DBCTL_SHDWDBREDMODE_MASK));
4518 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4519 ((HW_RD_REG16(base + CSL_EPWM_DBCTL) &
4520 ~CSL_EPWM_DBCTL_LOADFEDMODE_MASK) |
4521 (CSL_EPWM_DBCTL_SHDWDBFEDMODE_MASK |
4522 ((uint16_t)loadMode << CSL_EPWM_DBCTL_LOADFEDMODE_SHIFT))));
4543 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4544 (HW_RD_REG16(base + CSL_EPWM_DBCTL) &
4545 ~CSL_EPWM_DBCTL_SHDWDBFEDMODE_MASK));
4573 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4574 ((HW_RD_REG16(base + CSL_EPWM_DBCTL) &
4575 ~CSL_EPWM_DBCTL_HALFCYCLE_MASK) |
4576 ((uint16_t)clockMode << CSL_EPWM_DBCTL_HALFCYCLE_SHIFT)));
4603 HW_WR_REG16(base + CSL_EPWM_DBRED, redCount);
4630 HW_WR_REG16(base + CSL_EPWM_DBFED, fedCount);
4653 HW_WR_REG16(base + CSL_EPWM_PCCTL,
4654 (HW_RD_REG16(base + CSL_EPWM_PCCTL) | CSL_EPWM_PCCTL_CHPEN_MASK));
4674 HW_WR_REG16(base + CSL_EPWM_PCCTL,
4675 (HW_RD_REG16(base + CSL_EPWM_PCCTL) & ~CSL_EPWM_PCCTL_CHPEN_MASK));
4704 HW_WR_REG16(base + CSL_EPWM_PCCTL,
4705 ((HW_RD_REG16(base + CSL_EPWM_PCCTL) & ~CSL_EPWM_PCCTL_CHPDUTY_MASK) |
4706 (dutyCycleCount << CSL_EPWM_PCCTL_CHPDUTY_SHIFT)));
4735 HW_WR_REG16(base + CSL_EPWM_PCCTL,
4736 ((HW_RD_REG16(base + CSL_EPWM_PCCTL) &
4737 ~(uint16_t)CSL_EPWM_PCCTL_CHPFREQ_MASK) |
4738 (freqDiv << CSL_EPWM_PCCTL_CHPFREQ_SHIFT)));
4762 DebugP_assert(firstPulseWidth <= CSL_EPWM_PCCTL_OSHTWTH_MAX);
4767 HW_WR_REG16(base + CSL_EPWM_PCCTL,
4768 ((HW_RD_REG16(base + CSL_EPWM_PCCTL) &
4769 ~(uint16_t)CSL_EPWM_PCCTL_OSHTWTH_MASK) |
4770 (firstPulseWidth << CSL_EPWM_PCCTL_OSHTWTH_SHIFT)));
4815 HW_WR_REG32(base + CSL_EPWM_TZSEL,
4816 (HW_RD_REG32(base + CSL_EPWM_TZSEL) | tzSignal));
4858 HW_WR_REG32(base + CSL_EPWM_TZSEL,
4859 (HW_RD_REG32(base + CSL_EPWM_TZSEL) & ~tzSignal));
4902 HW_WR_REG16(base + CSL_EPWM_TZDCSEL,
4903 ((HW_RD_REG16(base + CSL_EPWM_TZDCSEL) &
4904 ~(CSL_EPWM_TZDCSEL_DCAEVT1_MASK << (uint16_t)dcType)) |
4905 ((uint16_t)dcEvent << (uint16_t)dcType)));
4927 HW_WR_REG16(base + CSL_EPWM_TZCTL2,
4928 (HW_RD_REG16(base + CSL_EPWM_TZCTL2) | CSL_EPWM_TZCTL2_ETZE_MASK));
4948 HW_WR_REG16(base + CSL_EPWM_TZCTL2,
4949 (HW_RD_REG16(base + CSL_EPWM_TZCTL2) & ~CSL_EPWM_TZCTL2_ETZE_MASK));
4991 HW_WR_REG16(base + CSL_EPWM_TZCTL,
4992 ((HW_RD_REG16(base + CSL_EPWM_TZCTL) &
4993 ~(CSL_EPWM_TZCTL_TZA_MASK << (uint16_t)tzEvent)) |
4994 ((uint16_t)tzAction << (uint16_t)tzEvent)));
5042 HW_WR_REG16(base + CSL_EPWM_TZCTL2,
5043 ((HW_RD_REG16(base + CSL_EPWM_TZCTL2) &
5044 ~(CSL_EPWM_TZCTL2_TZAU_MASK << (uint16_t)tzAdvEvent)) |
5045 ((uint16_t)tzAdvAction << (uint16_t)tzAdvEvent)));
5047 HW_WR_REG16(base + CSL_EPWM_TZCTL2,
5048 (HW_RD_REG16(base + CSL_EPWM_TZCTL2) | CSL_EPWM_TZCTL2_ETZE_MASK));
5094 HW_WR_REG16(base + CSL_EPWM_TZCTLDCA,
5095 ((HW_RD_REG16(base + CSL_EPWM_TZCTLDCA) &
5096 ~(CSL_EPWM_TZCTLDCA_DCAEVT1U_MASK << (uint16_t)tzAdvDCEvent)) |
5097 ((uint16_t)tzAdvDCAction << (uint16_t)tzAdvDCEvent)));
5099 HW_WR_REG16(base + CSL_EPWM_TZCTL2,
5100 (HW_RD_REG16(base + CSL_EPWM_TZCTL2) | CSL_EPWM_TZCTL2_ETZE_MASK));
5145 HW_WR_REG16(base + CSL_EPWM_TZCTLDCB,
5146 ((HW_RD_REG16(base + CSL_EPWM_TZCTLDCB) &
5147 ~(CSL_EPWM_TZCTLDCB_DCBEVT1U_MASK << (uint16_t)tzAdvDCEvent)) |
5148 ((uint16_t)tzAdvDCAction << (uint16_t)tzAdvDCEvent)));
5150 HW_WR_REG16(base + CSL_EPWM_TZCTL2,
5151 (HW_RD_REG16(base + CSL_EPWM_TZCTL2) | CSL_EPWM_TZCTL2_ETZE_MASK));
5182 DebugP_assert((tzInterrupt >= 0U) && (tzInterrupt < 0x80U));
5187 HW_WR_REG16(base + CSL_EPWM_TZEINT,
5188 (HW_RD_REG16(base + CSL_EPWM_TZEINT) | tzInterrupt));
5224 HW_WR_REG16(base + CSL_EPWM_TZEINT,
5225 (HW_RD_REG16(base + CSL_EPWM_TZEINT) & ~tzInterrupt));
5248 static inline uint16_t
5254 return(HW_RD_REG16(base + CSL_EPWM_TZFLG) & 0xFFU);
5280 static inline uint16_t
5286 return(HW_RD_REG16(base + CSL_EPWM_TZCBCFLG) & 0x1FFU);
5310 static inline uint16_t
5316 return(HW_RD_REG16(base + CSL_EPWM_TZOSTFLG) & 0x1FFU);
5346 HW_WR_REG16(base + CSL_EPWM_TZCLR,
5347 ((HW_RD_REG16(base + CSL_EPWM_TZCLR) &
5348 ~CSL_EPWM_TZCLR_CBCPULSE_MASK) |
5349 ((uint16_t)clearEvent << CSL_EPWM_TZCLR_CBCPULSE_SHIFT)));
5386 HW_WR_REG16(base + CSL_EPWM_TZCLR,
5387 (HW_RD_REG16(base + CSL_EPWM_TZCLR) | tzFlags));
5424 HW_WR_REG16(base + CSL_EPWM_TZCBCCLR,
5425 (HW_RD_REG16(base + CSL_EPWM_TZCBCCLR) | tzCBCFlags));
5461 HW_WR_REG16(base + CSL_EPWM_TZOSTCLR,
5462 (HW_RD_REG16(base + CSL_EPWM_TZOSTCLR) | tzOSTFlags));
5495 HW_WR_REG16(base + CSL_EPWM_TZFRC,
5496 (HW_RD_REG16(base + CSL_EPWM_TZFRC) | tzForceEvent));
5522 HW_WR_REG16(base + CSL_EPWM_TZTRIPOUTSEL,
5523 (HW_RD_REG16(base + CSL_EPWM_TZTRIPOUTSEL) | tzOutput));
5549 HW_WR_REG16(base + CSL_EPWM_TZTRIPOUTSEL,
5550 (HW_RD_REG16(base + CSL_EPWM_TZTRIPOUTSEL) & ~tzOutput));
5573 HW_WR_REG16(base + CSL_EPWM_ETSEL,
5574 (HW_RD_REG16(base + CSL_EPWM_ETSEL) | CSL_EPWM_ETSEL_INTEN_MASK));
5594 HW_WR_REG16(base + CSL_EPWM_ETSEL,
5595 (HW_RD_REG16(base + CSL_EPWM_ETSEL) & ~CSL_EPWM_ETSEL_INTEN_MASK));
5626 uint16_t mixedSource)
5633 DebugP_assert(((interruptSource > 0U) && (interruptSource < 9U)) ||
5634 (interruptSource == 10U) || (interruptSource == 12U) ||
5635 (interruptSource == 14U));
5645 intSource = interruptSource >> 1U;
5650 HW_WR_REG16(base + CSL_EPWM_ETSEL,
5651 (HW_RD_REG16(base + CSL_EPWM_ETSEL) |
5652 CSL_EPWM_ETSEL_INTSELCMP_MASK));
5659 intSource = interruptSource;
5664 HW_WR_REG16(base + CSL_EPWM_ETSEL,
5665 (HW_RD_REG16(base + CSL_EPWM_ETSEL) &
5666 ~CSL_EPWM_ETSEL_INTSELCMP_MASK));
5670 intSource = interruptSource;
5675 HW_WR_REG16(base + CSL_EPWM_ETINTMIXEN, mixedSource);
5679 intSource = interruptSource;
5685 HW_WR_REG16(base + CSL_EPWM_ETSEL,
5686 ((HW_RD_REG16(base + CSL_EPWM_ETSEL) &
5687 ~CSL_EPWM_ETSEL_INTSEL_MASK) | intSource));
5715 HW_WR_REG16(base + CSL_EPWM_ETPS,
5716 (HW_RD_REG16(base + CSL_EPWM_ETPS) | CSL_EPWM_ETPS_INTPSSEL_MASK));
5718 HW_WR_REG16(base + CSL_EPWM_ETINTPS,
5719 ((HW_RD_REG16(base + CSL_EPWM_ETINTPS) &
5720 ~CSL_EPWM_ETINTPS_INTPRD2_MASK) | eventCount));
5742 return(((HW_RD_REG16(base + CSL_EPWM_ETFLG) & 0x1U) ==
5743 0x1U) ?
true :
false);
5763 HW_WR_REG16(base + CSL_EPWM_ETCLR,
5764 (HW_RD_REG16(base + CSL_EPWM_ETCLR) | CSL_EPWM_ETCLR_INT_MASK));
5787 HW_WR_REG16(base + CSL_EPWM_ETCNTINITCTL,
5788 (HW_RD_REG16(base + CSL_EPWM_ETCNTINITCTL) |
5789 CSL_EPWM_ETCNTINITCTL_INTINITEN_MASK));
5810 HW_WR_REG16(base + CSL_EPWM_ETCNTINITCTL,
5811 (HW_RD_REG16(base + CSL_EPWM_ETCNTINITCTL) &
5812 ~CSL_EPWM_ETCNTINITCTL_INTINITEN_MASK));
5836 HW_WR_REG16(base + CSL_EPWM_ETCNTINITCTL,
5837 (HW_RD_REG16(base + CSL_EPWM_ETCNTINITCTL) |
5838 CSL_EPWM_ETCNTINITCTL_INTINITFRC_MASK));
5861 DebugP_assert(eventCount <= CSL_EPWM_ETCNTINIT_INTINIT_MAX);
5866 HW_WR_REG16(base + CSL_EPWM_ETCNTINIT,
5867 ((HW_RD_REG16(base + CSL_EPWM_ETCNTINIT) &
5868 ~CSL_EPWM_ETCNTINIT_INTINIT_MASK) |
5869 (uint16_t)(eventCount & CSL_EPWM_ETCNTINIT_INTINIT_MASK)));
5883 static inline uint16_t
5889 return(((HW_RD_REG16(base + CSL_EPWM_ETINTPS) &
5890 CSL_EPWM_ETINTPS_INTCNT2_MASK) >>
5891 CSL_EPWM_ETINTPS_INTCNT2_SHIFT));
5911 HW_WR_REG16(base + CSL_EPWM_ETFRC,
5912 (HW_RD_REG16(base + CSL_EPWM_ETFRC) | CSL_EPWM_ETFRC_INT_MASK));
5941 HW_WR_REG16(base + CSL_EPWM_ETSEL,
5942 (HW_RD_REG16(base + CSL_EPWM_ETSEL) | CSL_EPWM_ETSEL_SOCAEN_MASK));
5946 HW_WR_REG16(base + CSL_EPWM_ETSEL,
5947 (HW_RD_REG16(base + CSL_EPWM_ETSEL) | CSL_EPWM_ETSEL_SOCBEN_MASK));
5974 HW_WR_REG16(base + CSL_EPWM_ETSEL,
5975 (HW_RD_REG16(base + CSL_EPWM_ETSEL) & ~CSL_EPWM_ETSEL_SOCAEN_MASK));
5979 HW_WR_REG16(base + CSL_EPWM_ETSEL,
5980 (HW_RD_REG16(base + CSL_EPWM_ETSEL) & ~CSL_EPWM_ETSEL_SOCBEN_MASK));
6020 uint16_t mixedSource)
6029 source = (uint16_t)socSource >> 1U;
6033 source = (uint16_t)socSource;
6041 HW_WR_REG16(base + CSL_EPWM_ETSEL,
6042 ((HW_RD_REG16(base + CSL_EPWM_ETSEL) &
6043 ~CSL_EPWM_ETSEL_SOCASEL_MASK) |
6044 (source << CSL_EPWM_ETSEL_SOCASEL_SHIFT)));
6057 HW_WR_REG16(base + CSL_EPWM_ETSEL,
6058 (HW_RD_REG16(base + CSL_EPWM_ETSEL) &
6059 ~CSL_EPWM_ETSEL_SOCASELCMP_MASK));
6069 HW_WR_REG16(base + CSL_EPWM_ETSEL,
6070 (HW_RD_REG16(base + CSL_EPWM_ETSEL) |
6071 CSL_EPWM_ETSEL_SOCASELCMP_MASK));
6078 HW_WR_REG16(base + CSL_EPWM_ETSOCAMIXEN, mixedSource);
6092 HW_WR_REG16(base + CSL_EPWM_ETSEL,
6093 ((HW_RD_REG16(base + CSL_EPWM_ETSEL) &
6094 ~CSL_EPWM_ETSEL_SOCBSEL_MASK) |
6095 (source << CSL_EPWM_ETSEL_SOCBSEL_SHIFT)));
6108 HW_WR_REG16(base + CSL_EPWM_ETSEL,
6109 (HW_RD_REG16(base + CSL_EPWM_ETSEL) &
6110 ~CSL_EPWM_ETSEL_SOCBSELCMP_MASK));
6120 HW_WR_REG16(base + CSL_EPWM_ETSEL,
6121 (HW_RD_REG16(base + CSL_EPWM_ETSEL) |
6122 CSL_EPWM_ETSEL_SOCBSELCMP_MASK));
6129 HW_WR_REG16(base + CSL_EPWM_ETSOCBMIXEN, mixedSource);
6166 uint16_t preScaleCount)
6171 DebugP_assert(preScaleCount <= CSL_EPWM_ETSOCPS_SOCAPRD2_MAX);
6176 HW_WR_REG16(base + CSL_EPWM_ETPS,
6177 (HW_RD_REG16(base + CSL_EPWM_ETPS) |
6178 CSL_EPWM_ETPS_SOCPSSEL_MASK));
6185 HW_WR_REG16(base + CSL_EPWM_ETSOCPS,
6186 ((HW_RD_REG16(base + CSL_EPWM_ETSOCPS) &
6187 ~CSL_EPWM_ETSOCPS_SOCAPRD2_MASK) |
6195 HW_WR_REG16(base + CSL_EPWM_ETSOCPS,
6196 ((HW_RD_REG16(base + CSL_EPWM_ETSOCPS) &
6197 ~CSL_EPWM_ETSOCPS_SOCBPRD2_MASK) |
6198 (preScaleCount << CSL_EPWM_ETSOCPS_SOCBPRD2_SHIFT)));
6225 return((((HW_RD_REG16(base + CSL_EPWM_ETFLG) >>
6226 ((uint16_t)adcSOCType + CSL_EPWM_ETFLG_SOCA_SHIFT)) &
6227 0x1U) == 0x1U) ?
true :
false);
6252 HW_WR_REG16(base + CSL_EPWM_ETCLR,
6253 (HW_RD_REG16(base + CSL_EPWM_ETCLR) |
6254 1U << ((uint16_t)adcSOCType + CSL_EPWM_ETCLR_SOCA_SHIFT)));
6283 HW_WR_REG16(base + CSL_EPWM_ETCNTINITCTL,
6284 (HW_RD_REG16(base + CSL_EPWM_ETCNTINITCTL) | 1U <<
6285 ((uint16_t)adcSOCType + CSL_EPWM_ETCNTINITCTL_SOCAINITEN_SHIFT)));
6313 HW_WR_REG16(base + CSL_EPWM_ETCNTINITCTL,
6314 (HW_RD_REG16(base + CSL_EPWM_ETCNTINITCTL) &
6315 ~(1U << ((uint16_t)adcSOCType +
6316 CSL_EPWM_ETCNTINITCTL_SOCAINITEN_SHIFT))));
6342 HW_WR_REG16(base + CSL_EPWM_ETCNTINITCTL,
6343 (HW_RD_REG16(base + CSL_EPWM_ETCNTINITCTL) |
6344 1U << ((uint16_t)adcSOCType +
6345 CSL_EPWM_ETCNTINITCTL_SOCAINITFRC_SHIFT)));
6368 uint16_t eventCount)
6373 DebugP_assert(eventCount <= CSL_EPWM_ETCNTINIT_SOCAINIT_MAX);
6380 HW_WR_REG16(base + CSL_EPWM_ETCNTINIT,
6381 ((HW_RD_REG16(base + CSL_EPWM_ETCNTINIT) &
6382 ~CSL_EPWM_ETCNTINIT_SOCAINIT_MASK) |
6383 (uint16_t)(eventCount << CSL_EPWM_ETCNTINIT_SOCAINIT_SHIFT)));
6387 HW_WR_REG16(base + CSL_EPWM_ETCNTINIT,
6388 ((HW_RD_REG16(base + CSL_EPWM_ETCNTINIT) &
6389 ~CSL_EPWM_ETCNTINIT_SOCBINIT_MASK) |
6390 (eventCount << CSL_EPWM_ETCNTINIT_SOCBINIT_SHIFT)));
6409 static inline uint16_t
6413 uint16_t eventCount;
6420 eventCount = (HW_RD_REG16(base + CSL_EPWM_ETSOCPS) >>
6421 CSL_EPWM_ETSOCPS_SOCACNT2_SHIFT) &
6422 CSL_EPWM_ETSOCPS_SOCACNT2_MAX;
6426 eventCount = (HW_RD_REG16(base + CSL_EPWM_ETSOCPS) >>
6427 CSL_EPWM_ETSOCPS_SOCBCNT2_SHIFT) &
6428 CSL_EPWM_ETSOCPS_SOCBCNT2_MAX;
6455 HW_WR_REG16(base + CSL_EPWM_ETFRC,
6456 (HW_RD_REG16(base + CSL_EPWM_ETFRC) |
6457 1U << ((uint16_t)adcSOCType + CSL_EPWM_ETFRC_SOCA_SHIFT)));
6496 HW_WR_REG16(base + CSL_EPWM_DCTRIPSEL,
6497 ((HW_RD_REG16(base + CSL_EPWM_DCTRIPSEL) &
6498 ~(CSL_EPWM_DCTRIPSEL_DCAHCOMPSEL_MASK <<
6499 ((uint16_t)dcType << 2U))) |
6500 ((uint16_t)tripSource << ((uint16_t)dcType << 2U))));
6523 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6524 (HW_RD_REG16(base + CSL_EPWM_DCFCTL) | CSL_EPWM_DCFCTL_BLANKE_MASK));
6544 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6545 (HW_RD_REG16(base + CSL_EPWM_DCFCTL) & ~CSL_EPWM_DCFCTL_BLANKE_MASK));
6566 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6567 (HW_RD_REG16(base + CSL_EPWM_DCFCTL) | CSL_EPWM_DCFCTL_BLANKINV_MASK));
6587 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6588 (HW_RD_REG16(base + CSL_EPWM_DCFCTL) &
6589 ~CSL_EPWM_DCFCTL_BLANKINV_MASK));
6614 uint16_t mixedSource)
6621 HW_WR_REG16(base + CSL_EPWM_BLANKPULSEMIXSEL, mixedSource);
6627 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6628 ((HW_RD_REG16(base + CSL_EPWM_DCFCTL) &
6629 ~CSL_EPWM_DCFCTL_PULSESEL_MASK) |
6630 ((uint16_t)((uint32_t)blankingPulse <<
6631 CSL_EPWM_DCFCTL_PULSESEL_SHIFT))));
6659 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6660 ((HW_RD_REG16(base + CSL_EPWM_DCFCTL) & ~CSL_EPWM_DCFCTL_SRCSEL_MASK) |
6661 ((uint16_t)filterInput)));
6685 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6686 (HW_RD_REG16(base + CSL_EPWM_DCFCTL) |
6687 CSL_EPWM_DCFCTL_EDGEFILTSEL_MASK));
6707 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6708 (HW_RD_REG16(base + CSL_EPWM_DCFCTL) &
6709 ~CSL_EPWM_DCFCTL_EDGEFILTSEL_MASK));
6735 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6736 (HW_RD_REG16(base + CSL_EPWM_DCFCTL) &
6737 ~CSL_EPWM_DCFCTL_EDGEMODE_MASK) |
6738 (edgeMode << CSL_EPWM_DCFCTL_EDGEMODE_SHIFT));
6769 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6770 (HW_RD_REG16(base + CSL_EPWM_DCFCTL) &
6771 ~CSL_EPWM_DCFCTL_EDGECOUNT_MASK) |
6772 (edgeCount << CSL_EPWM_DCFCTL_EDGECOUNT_SHIFT));
6787 static inline uint16_t
6793 return((HW_RD_REG16(base + CSL_EPWM_DCFCTL) &
6794 CSL_EPWM_DCFCTL_EDGECOUNT_MASK) >>
6795 CSL_EPWM_DCFCTL_EDGECOUNT_SHIFT);
6810 static inline uint16_t
6816 return((HW_RD_REG16(base + CSL_EPWM_DCFCTL) &
6817 CSL_EPWM_DCFCTL_EDGESTATUS_MASK) >>
6818 CSL_EPWM_DCFCTL_EDGESTATUS_SHIFT);
6841 HW_WR_REG16(base + CSL_EPWM_DCFOFFSET, windowOffsetCount);
6863 HW_WR_REG16(base + CSL_EPWM_DCFWINDOW, windowLengthCount);
6877 static inline uint16_t
6883 return(HW_RD_REG16(base + CSL_EPWM_DCFOFFSETCNT));
6897 static inline uint16_t
6903 return(HW_RD_REG16(base + CSL_EPWM_DCFWINDOWCNT));
6941 uint32_t registerOffset;
6950 HW_WR_REG16(base + registerOffset,
6951 ((HW_RD_REG16(base + registerOffset) &
6952 ~CSL_EPWM_DCACTL_EVT1SRCSEL_MASK) |
6953 (uint16_t)dcEventSource));
6957 HW_WR_REG16(base + registerOffset,
6958 ((HW_RD_REG16(base + registerOffset) &
6959 ~CSL_EPWM_DCACTL_EVT2SRCSEL_MASK) |
6960 ((uint16_t)dcEventSource << CSL_EPWM_DCACTL_EVT2SRCSEL_SHIFT)));
6996 uint32_t registerOffset;
7005 HW_WR_REG16(base + registerOffset,
7006 ((HW_RD_REG16(base + registerOffset) &
7007 ~CSL_EPWM_DCACTL_EVT1FRCSYNCSEL_MASK) |
7008 ((uint16_t)syncMode << CSL_EPWM_DCACTL_EVT1FRCSYNCSEL_SHIFT)));
7012 HW_WR_REG16(base + registerOffset,
7013 ((HW_RD_REG16(base + registerOffset) &
7014 ~CSL_EPWM_DCACTL_EVT2FRCSYNCSEL_MASK) |
7015 ((uint16_t)syncMode << CSL_EPWM_DCACTL_EVT2FRCSYNCSEL_SHIFT)));
7039 uint32_t registerOffset;
7046 HW_WR_REG16(base + registerOffset,
7047 (HW_RD_REG16(base + registerOffset) | CSL_EPWM_DCACTL_EVT1SOCE_MASK));
7070 uint32_t registerOffset;
7077 HW_WR_REG16(base + registerOffset,
7078 (HW_RD_REG16(base + registerOffset) & ~CSL_EPWM_DCACTL_EVT1SOCE_MASK));
7101 uint32_t registerOffset;
7108 HW_WR_REG16(base + registerOffset,
7109 (HW_RD_REG16(base + registerOffset) | CSL_EPWM_DCACTL_EVT1SYNCE_MASK));
7132 uint32_t registerOffset;
7139 HW_WR_REG16(base + registerOffset,
7140 (HW_RD_REG16(base + registerOffset) &
7141 ~CSL_EPWM_DCACTL_EVT1SYNCE_MASK));
7174 uint32_t registerOffset;
7183 HW_WR_REG16(base + registerOffset,
7184 ((HW_RD_REG16(base + registerOffset) &
7185 ~CSL_EPWM_DCACTL_EVT1LATSEL_MASK) |
7186 ((uint16_t)latchMode << CSL_EPWM_DCACTL_EVT1LATSEL_SHIFT)));
7190 HW_WR_REG16(base + registerOffset,
7191 ((HW_RD_REG16(base + registerOffset) &
7192 ~CSL_EPWM_DCACTL_EVT2LATSEL_MASK) |
7193 ((uint16_t)latchMode << CSL_EPWM_DCACTL_EVT2LATSEL_SHIFT)));
7232 uint32_t registerOffset;
7241 HW_WR_REG16(base + registerOffset,
7242 ((HW_RD_REG16(base + registerOffset) &
7243 ~CSL_EPWM_DCACTL_EVT1LATCLRSEL_MASK) |
7244 ((uint16_t)clearEvent << CSL_EPWM_DCACTL_EVT1LATCLRSEL_SHIFT)));
7248 HW_WR_REG16(base + registerOffset,
7249 ((HW_RD_REG16(base + registerOffset) &
7250 ~CSL_EPWM_DCACTL_EVT2LATCLRSEL_MASK) |
7251 ((uint16_t)clearEvent << CSL_EPWM_DCACTL_EVT2LATCLRSEL_SHIFT)));
7283 uint32_t registerOffset;
7293 status = HW_RD_REG16(base + registerOffset) &
7294 CSL_EPWM_DCACTL_EVT1LAT_MASK;
7298 status = HW_RD_REG16(base + registerOffset) &
7299 CSL_EPWM_DCACTL_EVT2LAT_MASK;
7302 return(status != 0U);
7325 HW_WR_REG16(base + CSL_EPWM_DCCAPCTL,
7326 (HW_RD_REG16(base + CSL_EPWM_DCCAPCTL) | CSL_EPWM_DCCAPCTL_CAPE_MASK));
7346 HW_WR_REG16(base + CSL_EPWM_DCCAPCTL,
7347 (HW_RD_REG16(base + CSL_EPWM_DCCAPCTL) &
7348 ~CSL_EPWM_DCCAPCTL_CAPE_MASK));
7369 if(enableShadowMode)
7374 HW_WR_REG16(base + CSL_EPWM_DCCAPCTL,
7375 (HW_RD_REG16(base + CSL_EPWM_DCCAPCTL) &
7376 ~CSL_EPWM_DCCAPCTL_SHDWMODE_MASK));
7383 HW_WR_REG16(base + CSL_EPWM_DCCAPCTL,
7384 (HW_RD_REG16(base + CSL_EPWM_DCCAPCTL) |
7385 CSL_EPWM_DCCAPCTL_SHDWMODE_MASK));
7409 return((HW_RD_REG16(base + CSL_EPWM_DCCAPCTL) &
7410 CSL_EPWM_DCCAPCTL_CAPSTS_MASK) == CSL_EPWM_DCCAPCTL_CAPSTS_MASK);
7426 static inline uint16_t
7432 return(HW_RD_REG16(base + CSL_EPWM_DCCAP));
7461 uint32_t registerOffset;
7467 registerOffset = CSL_EPWM_DCAHTRIPSEL +
7473 HW_WR_REG16(base + registerOffset,
7474 (HW_RD_REG16(base + registerOffset) | tripInput));
7479 HW_WR_REG16(base + CSL_EPWM_DCTRIPSEL,
7480 (HW_RD_REG16(base + CSL_EPWM_DCTRIPSEL) |
7481 (CSL_EPWM_DCTRIPSEL_DCAHCOMPSEL_MASK << ((uint16_t)dcType << 2U))));
7510 uint32_t registerOffset;
7516 registerOffset = CSL_EPWM_DCAHTRIPSEL +
7522 HW_WR_REG16(base + registerOffset,
7523 (HW_RD_REG16(base + registerOffset) & ~tripInput));
7546 HW_WR_REG16(base + CSL_EPWM_VCAPCTL,
7547 (HW_RD_REG16(base + CSL_EPWM_VCAPCTL) | CSL_EPWM_VCAPCTL_VCAPE_MASK));
7567 HW_WR_REG16(base + CSL_EPWM_VCAPCTL,
7568 (HW_RD_REG16(base + CSL_EPWM_VCAPCTL) & ~CSL_EPWM_VCAPCTL_VCAPE_MASK));
7592 HW_WR_REG16(base + CSL_EPWM_VCAPCTL,
7593 (HW_RD_REG16(base + CSL_EPWM_VCAPCTL) |
7594 CSL_EPWM_VCAPCTL_VCAPSTART_MASK));
7618 HW_WR_REG16(base + CSL_EPWM_VCAPCTL,
7619 ((HW_RD_REG16(base + CSL_EPWM_VCAPCTL) &
7620 ~CSL_EPWM_VCAPCTL_TRIGSEL_MASK) |
7621 ((uint16_t)trigger << CSL_EPWM_VCAPCTL_TRIGSEL_SHIFT)));
7656 HW_WR_REG16(base + CSL_EPWM_VCNTCFG,
7657 ((HW_RD_REG16(base + CSL_EPWM_VCNTCFG) &
7658 ~(CSL_EPWM_VCNTCFG_STARTEDGE_MASK | CSL_EPWM_VCNTCFG_STOPEDGE_MASK)) |
7659 (startCount | (stopCount << CSL_EPWM_VCNTCFG_STOPEDGE_SHIFT))));
7679 HW_WR_REG16(base + CSL_EPWM_VCAPCTL,
7680 (HW_RD_REG16(base + CSL_EPWM_VCAPCTL) |
7681 CSL_EPWM_VCAPCTL_EDGEFILTDLYSEL_MASK));
7701 HW_WR_REG16(base + CSL_EPWM_VCAPCTL,
7702 (HW_RD_REG16(base + CSL_EPWM_VCAPCTL) &
7703 ~CSL_EPWM_VCAPCTL_EDGEFILTDLYSEL_MASK));
7724 HW_WR_REG16(base + CSL_EPWM_SWVDELVAL, delayOffsetValue);
7745 HW_WR_REG16(base + CSL_EPWM_VCAPCTL,
7746 ((HW_RD_REG16(base + CSL_EPWM_VCAPCTL) &
7747 ~CSL_EPWM_VCAPCTL_VDELAYDIV_MASK) |
7748 ((uint16_t)delayMode << CSL_EPWM_VCAPCTL_VDELAYDIV_SHIFT)));
7775 return(((HW_RD_REG16(base + CSL_EPWM_VCNTCFG) &
7776 CSL_EPWM_VCNTCFG_STARTEDGESTS_MASK) ==
7777 CSL_EPWM_VCNTCFG_STARTEDGESTS_MASK) ?
true :
false);
7784 return(((HW_RD_REG16(base + CSL_EPWM_VCNTCFG) &
7785 CSL_EPWM_VCNTCFG_STOPEDGESTS_MASK) ==
7786 CSL_EPWM_VCNTCFG_STOPEDGESTS_MASK) ?
true :
false);
7804 static inline uint16_t
7810 return(HW_RD_REG16(base + CSL_EPWM_VCNTVAL));
7824 static inline uint16_t
7830 return(HW_RD_REG16(base + CSL_EPWM_HWVDELVAL));
7852 HW_WR_REG16(base + CSL_EPWM_GLDCTL,
7853 (HW_RD_REG16(base + CSL_EPWM_GLDCTL) | CSL_EPWM_GLDCTL_GLD_MASK));
7874 HW_WR_REG16(base + CSL_EPWM_GLDCTL,
7875 (HW_RD_REG16(base + CSL_EPWM_GLDCTL) & ~CSL_EPWM_GLDCTL_GLD_MASK));
7913 HW_WR_REG16(base + CSL_EPWM_GLDCTL,
7914 ((HW_RD_REG16(base + CSL_EPWM_GLDCTL) &
7915 ~CSL_EPWM_GLDCTL_GLDMODE_MASK) |
7916 ((uint16_t)loadTrigger << CSL_EPWM_GLDCTL_GLDMODE_SHIFT)));
7946 HW_WR_REG16(base + CSL_EPWM_GLDCTL,
7947 ((HW_RD_REG16(base + CSL_EPWM_GLDCTL) & ~CSL_EPWM_GLDCTL_GLDPRD_MASK) |
7948 (prescalePulseCount << CSL_EPWM_GLDCTL_GLDPRD_SHIFT)));
7964 static inline uint16_t
7970 return((HW_RD_REG16(base + CSL_EPWM_GLDCTL) >>
7971 CSL_EPWM_GLDCTL_GLDCNT_SHIFT) & CSL_EPWM_GLDCTL_GLDCNT_MAX);
7993 HW_WR_REG16(base + CSL_EPWM_GLDCTL,
7994 (HW_RD_REG16(base + CSL_EPWM_GLDCTL) &
7995 ~CSL_EPWM_GLDCTL_OSHTMODE_MASK));
8017 HW_WR_REG16(base + CSL_EPWM_GLDCTL,
8018 (HW_RD_REG16(base + CSL_EPWM_GLDCTL) | CSL_EPWM_GLDCTL_OSHTMODE_MASK));
8040 HW_WR_REG16(base + CSL_EPWM_GLDCTL2,
8041 (HW_RD_REG16(base + CSL_EPWM_GLDCTL2) | CSL_EPWM_GLDCTL2_OSHTLD_MASK));
8062 HW_WR_REG16(base + CSL_EPWM_GLDCTL2,
8063 (HW_RD_REG16(base + CSL_EPWM_GLDCTL2) | CSL_EPWM_GLDCTL2_GFRCLD_MASK));
8097 DebugP_assert((loadRegister > 0x0000U) && (loadRegister < 0x0800U));
8102 HW_WR_REG16(base + CSL_EPWM_GLDCFG,
8103 (HW_RD_REG16(base + CSL_EPWM_GLDCFG) | loadRegister));
8138 DebugP_assert((loadRegister > 0x0000U) && (loadRegister < 0x0800U));
8144 HW_WR_REG16(base + CSL_EPWM_GLDCFG,
8145 (HW_RD_REG16(base + CSL_EPWM_GLDCFG) & ~loadRegister));
8167 HW_WR_REG32(base + CSL_EPWM_EPWMLOCK,
8191 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8192 (HW_RD_REG32(base + CSL_EPWM_MINDBCFG) |
8193 CSL_EPWM_MINDBCFG_ENABLEA_MASK));
8197 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8198 (HW_RD_REG32(base + CSL_EPWM_MINDBCFG) |
8199 CSL_EPWM_MINDBCFG_ENABLEB_MASK));
8220 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8221 (HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
8222 ~CSL_EPWM_MINDBCFG_ENABLEA_MASK));
8226 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8227 (HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
8228 ~CSL_EPWM_MINDBCFG_ENABLEB_MASK));
8252 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8253 ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
8254 ~CSL_EPWM_MINDBCFG_INVERTA_MASK) |
8255 (invert<<CSL_EPWM_MINDBCFG_INVERTA_SHIFT)));
8259 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8260 ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
8261 ~CSL_EPWM_MINDBCFG_INVERTB_MASK) |
8262 (invert<<CSL_EPWM_MINDBCFG_INVERTB_SHIFT)));
8283 uint32_t referenceSignal)
8287 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8288 ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
8289 ~CSL_EPWM_MINDBCFG_POLSELA_MASK) |
8290 (referenceSignal<<CSL_EPWM_MINDBCFG_POLSELA_SHIFT)));
8294 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8295 ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
8296 ~CSL_EPWM_MINDBCFG_POLSELB_MASK) |
8297 (referenceSignal<<CSL_EPWM_MINDBCFG_POLSELB_SHIFT)));
8317 uint32_t blockingSignal)
8321 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8322 ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
8323 ~CSL_EPWM_MINDBCFG_SELBLOCKA_MASK) |
8324 (blockingSignal<<CSL_EPWM_MINDBCFG_SELBLOCKA_SHIFT)));
8328 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8329 ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
8330 ~CSL_EPWM_MINDBCFG_SELBLOCKB_MASK) |
8331 (blockingSignal<<CSL_EPWM_MINDBCFG_SELBLOCKB_SHIFT)));
8350 uint32_t referenceSignal)
8354 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8355 ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
8356 ~CSL_EPWM_MINDBCFG_SELA_MASK) |
8357 (referenceSignal<<CSL_EPWM_MINDBCFG_SELA_SHIFT)));
8361 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8362 ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
8363 ~CSL_EPWM_MINDBCFG_SELB_MASK) |
8364 (referenceSignal<<CSL_EPWM_MINDBCFG_SELB_SHIFT)));
8380 static inline uint32_t
8387 retval = (HW_RD_REG32(base + CSL_EPWM_MINDBDLY) &
8388 CSL_EPWM_MINDBDLY_DELAYA_MASK);
8392 retval = (HW_RD_REG32(base + CSL_EPWM_MINDBDLY) &
8393 CSL_EPWM_MINDBDLY_DELAYB_MASK);
8418 HW_WR_REG32(base + CSL_EPWM_MINDBDLY,
8419 ((HW_RD_REG32(base + CSL_EPWM_MINDBDLY) &
8420 ~CSL_EPWM_MINDBDLY_DELAYA_MASK) |
8421 (delay<<CSL_EPWM_MINDBDLY_DELAYA_SHIFT)));
8425 HW_WR_REG32(base + CSL_EPWM_MINDBDLY,
8426 ((HW_RD_REG32(base + CSL_EPWM_MINDBDLY) &
8427 ~CSL_EPWM_MINDBDLY_DELAYB_MASK) |
8428 (delay<<CSL_EPWM_MINDBDLY_DELAYB_SHIFT)));
8452 HW_WR_REG32(base + CSL_EPWM_LUTCTLA,
8453 (HW_RD_REG32(base + CSL_EPWM_LUTCTLA) &
8454 ~CSL_EPWM_LUTCTLA_BYPASS_MASK));
8458 HW_WR_REG32(base + CSL_EPWM_LUTCTLB,
8459 (HW_RD_REG32(base + CSL_EPWM_LUTCTLB) &
8460 ~CSL_EPWM_LUTCTLB_BYPASS_MASK));
8481 HW_WR_REG32(base + CSL_EPWM_LUTCTLA,
8482 (HW_RD_REG32(base + CSL_EPWM_LUTCTLA) |
8483 CSL_EPWM_LUTCTLA_BYPASS_MASK));
8487 HW_WR_REG32(base + CSL_EPWM_LUTCTLB,
8488 (HW_RD_REG32(base + CSL_EPWM_LUTCTLB) |
8489 CSL_EPWM_LUTCTLB_BYPASS_MASK));
8511 HW_WR_REG32(base + CSL_EPWM_LUTCTLA,
8512 ((HW_RD_REG32(base + CSL_EPWM_LUTCTLA) &
8513 ~CSL_EPWM_LUTCTLA_SELXBAR_MASK) |
8514 (xbarInput<<CSL_EPWM_LUTCTLA_SELXBAR_SHIFT)));
8518 HW_WR_REG32(base + CSL_EPWM_LUTCTLB,
8519 ((HW_RD_REG32(base + CSL_EPWM_LUTCTLB) &
8520 ~CSL_EPWM_LUTCTLB_SELXBAR_MASK) |
8521 (xbarInput<<CSL_EPWM_LUTCTLB_SELXBAR_SHIFT)));
8545 HW_WR_REG32(base + CSL_EPWM_LUTCTLA,
8546 ((HW_RD_REG32(base + CSL_EPWM_LUTCTLA) &
8547 ~(CSL_EPWM_LUTCTLA_LUTDEC0_MAX <<
8548 (CSL_EPWM_LUTCTLA_LUTDEC0_SHIFT+decx))) |
8549 (force<<(CSL_EPWM_LUTCTLA_LUTDEC0_SHIFT+decx))));
8553 HW_WR_REG32(base + CSL_EPWM_LUTCTLB,
8554 ((HW_RD_REG32(base + CSL_EPWM_LUTCTLB) &
8555 ~(CSL_EPWM_LUTCTLB_LUTDEC0_MAX <<
8556 (CSL_EPWM_LUTCTLB_LUTDEC0_SHIFT+decx))) |
8557 (force<<(CSL_EPWM_LUTCTLB_LUTDEC0_SHIFT+decx))));
8592 HW_WR_REG32(base + CSL_EPWM_TBPHS, phaseCount<<8U);
8622 HW_WR_REG32(base + CSL_EPWM_TBPHS,
8623 ((HW_RD_REG32(base + CSL_EPWM_TBPHS) &
8624 ~((uint32_t)CSL_EPWM_TBPHS_TBPHSHR_MASK)) |
8625 ((uint32_t)hrPhaseCount << (CSL_EPWM_TBPHS_TBPHSHR_SHIFT + 8U))));
8652 DebugP_assert(hrPeriodCount <= CSL_EPWM_TBPRDHR_TBPRDHR_MAX);
8657 HW_WR_REG16(base + CSL_EPWM_TBPRDHR, hrPeriodCount << 8);
8671 static inline uint16_t
8677 return(HW_RD_REG16(base + CSL_EPWM_TBPRDHR) >> 8U);
8713 HW_WR_REG16(base + CSL_EPWM_HRCNFG,
8714 ((HW_RD_REG16(base + CSL_EPWM_HRCNFG) &
8715 ~(CSL_EPWM_HRCNFG_EDGMODE_MAX << (uint16_t)channel)) |
8716 ((uint16_t)mepEdgeMode << (uint16_t)channel)));
8750 HW_WR_REG16(base + CSL_EPWM_HRCNFG,
8751 ((HW_RD_REG16(base + CSL_EPWM_HRCNFG) &
8752 ~(CSL_EPWM_HRCNFG_CTLMODE_MAX << ((uint16_t)channel + 2U))) |
8753 ((uint16_t)mepCtrlMode << ((uint16_t)channel + 2U))));
8788 HW_WR_REG16(base + CSL_EPWM_HRCNFG,
8789 ((HW_RD_REG16(base + CSL_EPWM_HRCNFG) &
8790 ~(CSL_EPWM_HRCNFG_HRLOAD_MAX << ((uint16_t)channel + 3U))) |
8791 ((uint16_t)loadEvent << ((uint16_t)channel + 3U))));
8814 if(enableOutputSwap)
8816 HW_WR_REG16(base + CSL_EPWM_HRCNFG,
8817 HW_RD_REG16(base + CSL_EPWM_HRCNFG) | CSL_EPWM_HRCNFG_SWAPAB_MASK);
8821 HW_WR_REG16(base + CSL_EPWM_HRCNFG,
8822 HW_RD_REG16(base + CSL_EPWM_HRCNFG) & ~CSL_EPWM_HRCNFG_SWAPAB_MASK);
8847 HW_WR_REG16(base + CSL_EPWM_HRCNFG,
8848 ((HW_RD_REG16(base + CSL_EPWM_HRCNFG) & ~(CSL_EPWM_HRCNFG_SELOUTB_MASK)) |
8849 ((uint16_t)outputOnB << CSL_EPWM_HRCNFG_SELOUTB_SHIFT)));
8870 HW_WR_REG16(base + CSL_EPWM_HRCNFG,
8871 HW_RD_REG16(base + CSL_EPWM_HRCNFG) | CSL_EPWM_HRCNFG_AUTOCONV_MASK);
8892 HW_WR_REG16(base + CSL_EPWM_HRCNFG,
8893 HW_RD_REG16(base + CSL_EPWM_HRCNFG) & ~CSL_EPWM_HRCNFG_AUTOCONV_MASK);
8913 HW_WR_REG16(base + CSL_EPWM_HRPCTL,
8914 HW_RD_REG16(base + CSL_EPWM_HRPCTL) | CSL_EPWM_HRPCTL_HRPE_MASK);
8934 HW_WR_REG16(base + CSL_EPWM_HRPCTL,
8935 HW_RD_REG16(base + CSL_EPWM_HRPCTL) & ~CSL_EPWM_HRPCTL_HRPE_MASK);
8956 HW_WR_REG16(base + CSL_EPWM_HRPCTL,
8957 HW_RD_REG16(base + CSL_EPWM_HRPCTL) | CSL_EPWM_HRPCTL_TBPHSHRLOADE_MASK);
8977 HW_WR_REG16(base + CSL_EPWM_HRPCTL,
8978 HW_RD_REG16(base + CSL_EPWM_HRPCTL) & ~CSL_EPWM_HRPCTL_TBPHSHRLOADE_MASK);
9017 HW_WR_REG16(base + CSL_EPWM_HRPCTL,
9018 ((HW_RD_REG16(base + CSL_EPWM_HRPCTL) &
9019 ~(CSL_EPWM_HRPCTL_PWMSYNCSELX_MASK | CSL_EPWM_HRPCTL_PWMSYNCSEL_MASK)) |
9020 ((uint16_t)syncPulseSource << 1U)));
9024 HW_WR_REG16(base + CSL_EPWM_HRPCTL,
9025 ((HW_RD_REG16(base + CSL_EPWM_HRPCTL) & ~CSL_EPWM_HRPCTL_PWMSYNCSELX_MASK) |
9026 ((uint16_t)syncPulseSource << CSL_EPWM_HRPCTL_PWMSYNCSELX_SHIFT)));
9053 HW_WR_REG16(base + CSL_EPWM_TRREM, trremVal & CSL_EPWM_TRREM_TRREM_MASK);
9095 HW_WR_REG32(base + CSL_EPWM_CMPA, compCount << 8);
9102 HW_WR_REG32(base + CSL_EPWM_CMPB, compCount << 8);
9123 static inline uint32_t
9137 compCount = HW_RD_REG32(base + CSL_EPWM_CMPA);
9144 compCount = HW_RD_REG32(base + CSL_EPWM_CMPB);
9147 return(compCount>>8U);
9172 uint16_t hrCompCount)
9187 HW_WR_REG32(base + CSL_EPWM_CMPA,
9188 HW_RD_REG32(base + CSL_EPWM_CMPA) | ((hrCompCount & CSL_EPWM_CMPA_CMPAHR_MASK) << 8U));
9195 HW_WR_REG32(base + CSL_EPWM_CMPB,
9196 HW_RD_REG32(base + CSL_EPWM_CMPB) | ((hrCompCount & CSL_EPWM_CMPB_CMPBHR_MASK) << 8U));
9216 static inline uint16_t
9220 uint16_t hrCompCount;
9230 hrCompCount = (HW_RD_REG16(base + CSL_EPWM_CMPA) & CSL_EPWM_CMPA_CMPAHR_MASK);
9237 hrCompCount = (HW_RD_REG16(base + CSL_EPWM_CMPB) & CSL_EPWM_CMPB_CMPBHR_MASK);
9240 return(hrCompCount >> 8U);
9270 HW_WR_REG16(base + CSL_EPWM_DBREDHR,
9271 HW_RD_REG16(base + CSL_EPWM_DBREDHR) |
9272 (hrRedCount << CSL_EPWM_DBREDHR_DBREDHR_SHIFT));
9301 HW_WR_REG16(base + CSL_EPWM_DBFEDHR,
9302 HW_RD_REG16(base + CSL_EPWM_DBFEDHR) &
9303 ~CSL_EPWM_DBFEDHR_DBFEDHR_MASK |
9304 (hrFedCount << CSL_EPWM_DBFEDHR_DBFEDHR_SHIFT));
9332 HW_WR_REG16(base + CSL_OTTOCAL_HRMSTEP,
9333 ((HW_RD_REG16(base + CSL_OTTOCAL_HRMSTEP) & ~CSL_OTTOCAL_HRMSTEP_HRMSTEP_MASK) |
9334 mepCount << CSL_OTTOCAL_HRMSTEP_HRMSTEP_SHIFT));
9365 HW_WR_REG16(base + CSL_EPWM_HRCNFG2,
9366 ((HW_RD_REG16(base + CSL_EPWM_HRCNFG2) & ~CSL_EPWM_HRCNFG2_EDGMODEDB_MASK) |
9367 ((uint16_t)mepDBEdge << CSL_EPWM_HRCNFG2_EDGMODEDB_SHIFT)));
9395 HW_WR_REG16(base + CSL_EPWM_HRCNFG2,
9396 ((HW_RD_REG16(base + CSL_EPWM_HRCNFG2) & ~CSL_EPWM_HRCNFG2_CTLMODEDBRED_MASK) |
9397 ((uint16_t)loadEvent << CSL_EPWM_HRCNFG2_CTLMODEDBRED_SHIFT)));
9424 HW_WR_REG16(base + CSL_EPWM_HRCNFG2,
9425 ((HW_RD_REG16(base + CSL_EPWM_HRCNFG2) & ~CSL_EPWM_HRCNFG2_CTLMODEDBFED_MASK) |
9426 ((uint16_t)loadEvent << CSL_EPWM_HRCNFG2_CTLMODEDBFED_SHIFT)));
9450 uint32_t registerOffset;
9455 registerOffset = base + CSL_EPWM_XCMP1_ACTIVE + (uint16_t)xcmpReg;
9460 HW_WR_REG16(registerOffset, xcmpvalue);
9480 uint32_t registerOffset = base + CSL_EPWM_XCMPCTL1;
9482 HW_WR_REG32(registerOffset,
9483 (HW_RD_REG32(registerOffset) | CSL_EPWM_XCMPCTL1_XCMPEN_MAX ));
9500 uint32_t registerOffset = base + CSL_EPWM_XCMPCTL1;
9502 HW_WR_REG32(registerOffset,
9503 (HW_RD_REG32(registerOffset) & ~CSL_EPWM_XCMPCTL1_XCMPEN_MAX ));
9522 uint32_t registerOffset = base + CSL_EPWM_XCMPCTL1;
9523 uint32_t offset = CSL_EPWM_XCMPCTL1_XCMPSPLIT_SHIFT;
9525 HW_WR_REG32(registerOffset,
9526 (HW_RD_REG32(registerOffset) | ( CSL_EPWM_XCMPCTL1_XCMPSPLIT_MAX << offset )));
9544 uint32_t registerOffset = base + CSL_EPWM_XCMPCTL1;
9545 uint32_t offset = CSL_EPWM_XCMPCTL1_XCMPSPLIT_SHIFT;
9547 HW_WR_REG32(registerOffset,
9548 (HW_RD_REG32(registerOffset) & ~( CSL_EPWM_XCMPCTL1_XCMPSPLIT_MAX << offset )));
9577 uint32_t registerOffset = base + CSL_EPWM_XCMPCTL1;
9578 uint32_t offset = CSL_EPWM_XCMPCTL1_XCMPA_ALLOC_SHIFT;
9580 HW_WR_REG32(registerOffset,
9581 ( (HW_RD_REG32(registerOffset) & ~CSL_EPWM_XCMPCTL1_XCMPA_ALLOC_MASK) | ( alloctype << offset )));
9604 uint32_t registerOffset = base + CSL_EPWM_XCMPCTL1;
9605 uint32_t offset = CSL_EPWM_XCMPCTL1_XCMPB_ALLOC_SHIFT;
9607 HW_WR_REG32(registerOffset,
9608 ( (HW_RD_REG32(registerOffset) & ~CSL_EPWM_XCMPCTL1_XCMPB_ALLOC_MASK) | ( alloctype << offset )));
9637 uint32_t registerOffset;
9642 registerOffset = base + CSL_EPWM_XCMP1_ACTIVE + (uint16_t)xcmpReg;
9647 HW_WR_REG16(registerOffset + 0x2U, xcmpvalue);
9695 uint32_t registerOffset;
9703 registerOffset = CSL_EPWM_XAQCTLA_ACTIVE + (uint16_t)(epwmOutput/2);
9705 HW_WR_REG16(base + registerOffset,
9706 ((HW_RD_REG16(base + registerOffset) &
9707 ~(CSL_EPWM_XAQCTLA_ACTIVE_XCMP1_MAX << (uint16_t)event)) |
9708 ((uint16_t)output << (uint16_t)event)));
9712 registerOffset = CSL_EPWM_XAQCTLA_SHDW1 + (uint16_t)(epwmOutput/2);
9714 HW_WR_REG16(base + registerOffset,
9715 ((HW_RD_REG16(base + registerOffset) &
9716 ~(CSL_EPWM_XAQCTLA_SHDW1_XCMP1_MAX << (uint16_t)event)) |
9717 ((uint16_t)output << (uint16_t)event)));
9721 registerOffset = CSL_EPWM_XAQCTLA_SHDW2 + (uint16_t)(epwmOutput/2);
9723 HW_WR_REG16(base + registerOffset,
9724 ((HW_RD_REG16(base + registerOffset) &
9725 ~(CSL_EPWM_XAQCTLA_SHDW2_XCMP1_MAX << (uint16_t)event)) |
9726 ((uint16_t)output << (uint16_t)event)));
9730 registerOffset = CSL_EPWM_XAQCTLA_SHDW3 + (uint16_t)(epwmOutput/2);
9732 HW_WR_REG16(base + registerOffset,
9733 ((HW_RD_REG16(base + registerOffset) &
9734 ~(CSL_EPWM_XAQCTLA_SHDW3_XCMP1_MAX << (uint16_t)event)) |
9735 ((uint16_t)output << (uint16_t)event)));
9755 uint32_t registerOffset = base + CSL_EPWM_XLOAD;
9757 HW_WR_REG32(registerOffset,
9758 (HW_RD_REG32(registerOffset) | CSL_EPWM_XLOAD_STARTLD_MASK ));
9775 uint32_t registerOffset = base + CSL_EPWM_XLOAD;
9777 HW_WR_REG32(registerOffset,
9778 (HW_RD_REG32(registerOffset) & ~CSL_EPWM_XLOAD_STARTLD_MASK ));
9799 uint32_t registerOffset;
9804 registerOffset = base + CSL_EPWM_XLOADCTL;
9808 HW_WR_REG32(registerOffset,
9809 (HW_RD_REG32(registerOffset) & ~CSL_EPWM_XLOADCTL_LOADMODE_MASK));
9813 HW_WR_REG32(registerOffset,
9814 (HW_RD_REG32(registerOffset) | CSL_EPWM_XLOADCTL_LOADMODE_MASK));
9837 uint32_t registerOffset;
9842 registerOffset = base + CSL_EPWM_XLOADCTL;
9844 HW_WR_REG32(registerOffset,
9845 ((HW_RD_REG32(registerOffset) & ~CSL_EPWM_XLOADCTL_SHDWLEVEL_MASK) |
9846 ((uint16_t)level << CSL_EPWM_XLOADCTL_SHDWLEVEL_SHIFT)));
9868 uint32_t registerOffset;
9873 registerOffset = base + CSL_EPWM_XLOADCTL;
9875 HW_WR_REG32(registerOffset,
9876 ((HW_RD_REG32(registerOffset) & ~CSL_EPWM_XLOADCTL_SHDWBUFPTR_LOADONCE_MASK) |
9877 ((uint16_t)ptr << CSL_EPWM_XLOADCTL_SHDWBUFPTR_LOADONCE_SHIFT)));
9901 uint32_t registerOffset;
9905 registerOffset = base + CSL_EPWM_XLOADCTL;
9909 HW_WR_REG32(registerOffset,
9910 ((HW_RD_REG32(registerOffset) & ~(CSL_EPWM_XLOADCTL_RPTBUF2PRD_MASK))
9911 | (count<<CSL_EPWM_XLOADCTL_RPTBUF2PRD_SHIFT)) );
9915 HW_WR_REG32(registerOffset,
9916 ((HW_RD_REG32(registerOffset) & ~(CSL_EPWM_XLOADCTL_RPTBUF3PRD_MASK))
9917 | (count<<CSL_EPWM_XLOADCTL_RPTBUF3PRD_SHIFT)) );
9941 uint32_t registerOffset;
9945 registerOffset = base + CSL_EPWM_DECTL;
9947 HW_WR_REG32(registerOffset,
9948 (HW_RD_REG32(registerOffset) | CSL_EPWM_DECTL_ENABLE_MAX ));
9967 uint32_t registerOffset;
9971 registerOffset = base + CSL_EPWM_DECTL;
9973 HW_WR_REG32(registerOffset,
9974 (HW_RD_REG32(registerOffset) & ~CSL_EPWM_DECTL_ENABLE_MAX ));
9999 uint32_t registerOffset;
10004 registerOffset = base + CSL_EPWM_DECTL;
10008 HW_WR_REG32(registerOffset,
10009 (HW_RD_REG32(registerOffset) & ~CSL_EPWM_DECTL_MODE_MASK));
10013 HW_WR_REG32(registerOffset,
10014 (HW_RD_REG32(registerOffset) | CSL_EPWM_DECTL_MODE_MASK));
10035 uint32_t registerOffset;
10039 registerOffset = base + CSL_EPWM_DECTL;
10041 HW_WR_REG32(registerOffset,
10042 ((HW_RD_REG32(registerOffset) & ~(CSL_EPWM_DECTL_REENTRYDLY_MASK))
10043 | (delay<<CSL_EPWM_DECTL_REENTRYDLY_SHIFT)) );
10069 uint32_t registerOffset;
10073 registerOffset = base + CSL_EPWM_DECOMPSEL;
10077 HW_WR_REG32(registerOffset,
10078 ((HW_RD_REG32(registerOffset) &
10079 ~CSL_EPWM_DECOMPSEL_TRIPL_MASK) |
10080 (source<<CSL_EPWM_DECOMPSEL_TRIPL_SHIFT)));
10084 HW_WR_REG32(registerOffset,
10085 ((HW_RD_REG32(registerOffset) &
10086 ~CSL_EPWM_DECOMPSEL_TRIPH_MASK) |
10087 (source<<CSL_EPWM_DECOMPSEL_TRIPH_SHIFT)));
10116 uint32_t registerOffset;
10120 registerOffset = base + CSL_EPWM_DEACTCTL;
10124 HW_WR_REG32(registerOffset,
10125 ((HW_RD_REG32(registerOffset) &
10126 ~CSL_EPWM_DEACTCTL_PWMA_MASK) |
10127 (signal<<CSL_EPWM_DEACTCTL_PWMA_SHIFT)));
10131 HW_WR_REG32(registerOffset,
10132 ((HW_RD_REG32(registerOffset) &
10133 ~CSL_EPWM_DEACTCTL_PWMB_MASK) |
10134 (signal<<CSL_EPWM_DEACTCTL_PWMB_SHIFT)));
10160 uint32_t registerOffset;
10164 registerOffset = base + CSL_EPWM_DEACTCTL;
10168 HW_WR_REG32(registerOffset,
10169 ((HW_RD_REG32(registerOffset) &
10170 ~CSL_EPWM_DEACTCTL_TRIPSELA_MASK) |
10171 (signal<<CSL_EPWM_DEACTCTL_TRIPSELA_SHIFT)));
10175 HW_WR_REG32(registerOffset,
10176 ((HW_RD_REG32(registerOffset) &
10177 ~CSL_EPWM_DEACTCTL_TRIPSELB_MASK) |
10178 (signal<<CSL_EPWM_DEACTCTL_TRIPSELB_SHIFT)));
10194 uint32_t registerOffset;
10198 registerOffset = base + CSL_EPWM_DEACTCTL;
10200 HW_WR_REG32(registerOffset,
10201 (HW_RD_REG32(registerOffset) &
10202 ~(CSL_EPWM_DEACTCTL_TRIPENABLE_MAX << CSL_EPWM_DEACTCTL_TRIPENABLE_SHIFT)));
10218 uint32_t registerOffset;
10222 registerOffset = base + CSL_EPWM_DEACTCTL;
10224 HW_WR_REG32(registerOffset,
10225 (HW_RD_REG32(registerOffset) |
10226 (CSL_EPWM_DEACTCTL_TRIPENABLE_MAX << CSL_EPWM_DEACTCTL_TRIPENABLE_SHIFT)));
10242 uint32_t registerOffset;
10246 registerOffset = base + CSL_EPWM_DEFRC;
10248 HW_WR_REG32(registerOffset,
10249 (HW_RD_REG32(registerOffset) | CSL_EPWM_DEFRC_DEACTIVE_MASK));
10265 uint32_t registerOffset;
10269 registerOffset = base + CSL_EPWM_DECLR;
10271 HW_WR_REG32(registerOffset,
10272 (HW_RD_REG32(registerOffset) | CSL_EPWM_DECLR_DEACTIVE_MASK));
10288 uint32_t registerOffset;
10292 registerOffset = base + CSL_EPWM_DEMONCTL;
10294 HW_WR_REG32(registerOffset,
10295 (HW_RD_REG32(registerOffset) |
10296 (CSL_EPWM_DEMONCTL_ENABLE_MAX << CSL_EPWM_DEMONCTL_ENABLE_SHIFT)));
10311 uint32_t registerOffset;
10315 registerOffset = base + CSL_EPWM_DEMONCTL;
10317 HW_WR_REG32(registerOffset,
10318 (HW_RD_REG32(registerOffset) &
10319 ~(CSL_EPWM_DEMONCTL_ENABLE_MAX << CSL_EPWM_DEMONCTL_ENABLE_SHIFT)));
10341 uint32_t registerOffset;
10345 registerOffset = base + CSL_EPWM_DEMONSTEP;
10349 HW_WR_REG32(registerOffset,
10350 (HW_RD_REG32(registerOffset) & ~CSL_EPWM_DEMONSTEP_INCSTEP_MASK)
10351 | (stepsize<<CSL_EPWM_DEMONSTEP_INCSTEP_SHIFT));
10355 HW_WR_REG32(registerOffset,
10356 ((HW_RD_REG32(registerOffset) &
10357 ~CSL_EPWM_DEMONSTEP_DECSTEP_MASK) |
10358 (stepsize<<CSL_EPWM_DEMONSTEP_DECSTEP_SHIFT)));
10375 uint32_t registerOffset;
10379 registerOffset = base + CSL_EPWM_DEMONTHRES;
10381 HW_WR_REG32(registerOffset,
10382 ((HW_RD_REG32(registerOffset) & ~(CSL_EPWM_DEMONTHRES_THRESHOLD_MASK))
10383 | (threshold<<CSL_EPWM_DEMONTHRES_THRESHOLD_SHIFT)) );
10438 #endif // EPWM_V1_H_
@ EPWM_TZ_ACTION_HIGH
high voltage state
Definition: etpwm.h:955
@ HRPWM_LOAD_ON_CNTR_ZERO_PERIOD
load when counter equals zero or period
Definition: etpwm.h:1889
static void EPWM_disableInterruptEventCountInit(uint32_t base)
Definition: etpwm.h:5805
static void EPWM_setDeadBandOutputSwapMode(uint32_t base, EPWM_DeadBandOutput output, bool enableSwapMode)
Definition: etpwm.h:4179
@ HRPWM_XCMP6_SHADOW3
XCMP6_SHADOW3.
Definition: etpwm.h:2043
static void EPWM_enableADCTriggerEventCountInit(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
Definition: etpwm.h:6277
@ EPWM_AQ_OUTPUT_HIGH_UP_T1
T1 event on count up and set output pins to high.
Definition: etpwm.h:675
static uint16_t EPWM_getValleyHWDelay(uint32_t base)
Definition: etpwm.h:7825
static uint16_t EPWM_getDigitalCompareEdgeFilterEdgeStatus(uint32_t base)
Definition: etpwm.h:6811
EPWM_TimeBaseCountMode
Definition: etpwm.h:346
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT22
Trip source is INPUTXBAR out22 signal.
Definition: etpwm.h:2355
@ HRPWM_XCMP1_SHADOW2
XCMP1_SHADOW2.
Definition: etpwm.h:2010
@ EPWM_TZ_ACTION_LOW
low voltage state
Definition: etpwm.h:956
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM8
Sync-in source is EPWM8 sync-out signal.
Definition: etpwm.h:204
static uint16_t EPWM_getCycleByCycleTripZoneFlagStatus(uint32_t base)
Definition: etpwm.h:5281
EPWM_ActionQualifierLoadMode
Definition: etpwm.h:508
@ EPWM_LINK_WITH_EPWM_5
link current ePWM with ePWM5
Definition: etpwm.h:393
@ HRPWM_XTBPRD_ACTIVE
XTBPRD_ACTIVE.
Definition: etpwm.h:1984
static void EPWM_setFallingEdgeDelayCountShadowLoadMode(uint32_t base, EPWM_FallingEdgeDelayLoadMode loadMode)
Definition: etpwm.h:4512
static void EPWM_selectPeriodLoadEvent(uint32_t base, EPWM_PeriodShadowLoadMode shadowLoadMode)
Definition: etpwm.h:2914
@ EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO_PERIOD
Clear CBC pulse when counter equals zero or period.
Definition: etpwm.h:1128
static void EPWM_setupEPWMLinks(uint32_t base, EPWM_CurrentLink epwmLink, EPWM_LinkComponent linkComp)
Definition: etpwm.h:3258
EPWM_XCMP_XLOADCTL_SHDWLEVEL
Definition: etpwm.h:2256
static void HRPWM_setMEPEdgeSelect(uint32_t base, HRPWM_Channel channel, HRPWM_MEPEdgeMode mepEdgeMode)
Definition: etpwm.h:8707
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX2_RX_TRIG2
Sync-in source is FSI-RX2 RX Trigger 2 signal.
Definition: etpwm.h:300
@ EPWM_SOC_A
SOC A.
Definition: etpwm.h:1257
@ EPWM_DC_EVENT_1
Digital Compare Event number 1.
Definition: etpwm.h:1464
@ EPWM_AQ_LOAD_ON_CNTR_ZERO_PERIOD
load when counter equals zero or period
Definition: etpwm.h:514
@ EPWM_AQ_SW_OUTPUT_HIGH
Set output pins to High.
Definition: etpwm.h:600
@ EPWM_DC_WINDOW_START_TBCTR_ZERO_PERIOD
Time base counter equals zero or period.
Definition: etpwm.h:1391
@ EPWM_DE_TRIP_SRC_CMPSSB1
Trip source is CMPSSB1 signal.
Definition: etpwm.h:2397
@ EPWM_HSCLOCK_DIVIDER_2
Divide clock by 2.
Definition: etpwm.h:168
@ EPWM_LINK_WITH_EPWM_9
link current ePWM with ePWM9
Definition: etpwm.h:397
static void HRPWM_setMEPStep(uint32_t base, uint16_t mepCount)
Definition: etpwm.h:9322
@ HRPWM_XTBPRD_SHADOW1
XTBPRD_SHADOW1.
Definition: etpwm.h:2003
static void EPWM_startValleyCapture(uint32_t base)
Definition: etpwm.h:7587
static void EPWM_setXCMPShadowRepeatBufxCount(uint32_t base, uint32_t bufferset, uint8_t count)
Definition: etpwm.h:9899
static void EPWM_disableOneShotSync(uint32_t base)
Definition: etpwm.h:2959
@ EPWM_XCMP2_SHADOW3
XCMP2_SHADOW3.
Definition: etpwm.h:2143
@ EPWM_GL_LOAD_PULSE_CNTR_CMPC_U
load when counter is equal to cmpc and cmpc is incrementing
Definition: etpwm.h:1549
static void EPWM_enableValleyHWDelay(uint32_t base)
Definition: etpwm.h:7674
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT18
Trip source is INPUTXBAR out18 signal.
Definition: etpwm.h:2347
static void EPWM_selectCycleByCycleTripZoneClearEvent(uint32_t base, EPWM_CycleByCycleTripZoneClearMode clearEvent)
Definition: etpwm.h:5340
static void EPWM_setChopperFreq(uint32_t base, uint16_t freqDiv)
Definition: etpwm.h:4725
@ EPWM_SYNC_IN_PULSE_SRC_C2K_TIMESYNC_XBAR_PWM_OUT1
Sync-in source is C2K Timesync xbar sync pwm out1 signal.
Definition: etpwm.h:278
static void EPWM_enableTripZoneOutput(uint32_t base, uint16_t tzOutput)
Definition: etpwm.h:5517
@ EPWM_SHADOW_LOAD_MODE_COUNTER_ZERO
shadow to active load occurs when time base counter reaches 0.
Definition: etpwm.h:362
@ EPWM_DE_TRIP_SRC_CMPSSB0
Trip source is CMPSSB0 signal.
Definition: etpwm.h:2395
@ EPWM_REGISTER_GROUP_TRIP_ZONE
Trip zone register group.
Definition: etpwm.h:1706
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM24
Sync-in source is EPWM24 sync-out signal.
Definition: etpwm.h:236
@ EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_U
Digital Compare event A/B 1 while counting up.
Definition: etpwm.h:1004
static void EPWM_forceDiodeEmulationActive(uint32_t base)
Definition: etpwm.h:10240
@ EPWM_COMP_LOAD_ON_CNTR_ZERO
load when counter equals zero
Definition: etpwm.h:469
EPWM_ActionQualifierContForce
Definition: etpwm.h:726
@ EPWM_DE_SYNC_INV_TRIPHorL
synchronized and inverted version of TRIPH or TRIPL signal
Definition: etpwm.h:2422
static uint16_t EPWM_getTimeBaseCounterValue(uint32_t base)
Definition: etpwm.h:3002
static uint16_t EPWM_getADCTriggerEventCount(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
Definition: etpwm.h:6410
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT16
Trip source is INPUTXBAR out16 signal.
Definition: etpwm.h:2343
@ EPWM_DE_HIGH
a constant high signal
Definition: etpwm.h:2426
static void EPWM_enableTripZoneAdvAction(uint32_t base)
Definition: etpwm.h:4922
@ HRPWM_PWMSYNC_SOURCE_ZERO
Counter equals zero.
Definition: etpwm.h:1919
@ HRPWM_PWMSYNC_SOURCE_COMPD_UP
Counter equals COMPD when counting up.
Definition: etpwm.h:1925
static void HRPWM_setHiResFallingEdgeDelayOnly(uint32_t base, uint16_t hrFedCount)
Definition: etpwm.h:9291
static void EPWM_setActionQualifierActionComplete(uint32_t base, EPWM_ActionQualifierOutputModule epwmOutput, EPWM_ActionQualifierEventAction action)
Definition: etpwm.h:3890
@ EPWM_DC_CBC_LATCH_CLR_ON_CNTR_ZERO_PERIOD
Clear CBC latch when counter equals zero or period.
Definition: etpwm.h:1523
@ EPWM_CLOCK_DIVIDER_32
Divide clock by 32.
Definition: etpwm.h:154
static void EPWM_setFallingEdgeDelayCount(uint32_t base, uint16_t fedCount)
Definition: etpwm.h:4620
@ EPWM_XCMP_4_CMPA
Allocate XCMP1 - XCMP4 registers to CMPA.
Definition: etpwm.h:2205
#define EPWM_XCMP_SHADOW1
XCMP set = Shadow 2.
Definition: etpwm.h:2063
@ EPWM_COMP_LOAD_FREEZE
Freeze shadow to active load.
Definition: etpwm.h:475
@ EPWM_SYNC_IN_PULSE_SRC_C2K_TIMESYNC_XBAR_PWM_OUT0
Sync-in source is C2K Timesync xbar sync pwm out0 signal.
Definition: etpwm.h:276
@ EPWM_DE_TRIP_SRC_CMPSSB2
Trip source is CMPSSB2 signal.
Definition: etpwm.h:2399
@ EPWM_DC_EDGEFILT_EDGECNT_6
Digital Compare Edge filter edge count = 7.
Definition: etpwm.h:1691
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT12
Trip source is INPUTXBAR out12 signal.
Definition: etpwm.h:2335
Float32 dutyValA
Desired ePWMxA Signal Duty.
Definition: etpwm.h:2485
@ EPWM_AQ_LOAD_ON_SYNC_CNTR_ZERO
load on sync or when counter equals zero
Definition: etpwm.h:518
HRPWM_XCMPReg
Definition: etpwm.h:1966
static void EPWM_forceActionQualifierSWAction(uint32_t base, EPWM_ActionQualifierOutputModule epwmOutput)
Definition: etpwm.h:4133
@ EPWM_XCMP2_ACTIVE
XCMP2_ACTIVE.
Definition: etpwm.h:2080
@ EPWM_DC_CBC_LATCH_CLR_CNTR_ZERO
Clear CBC latch when counter equals zero.
Definition: etpwm.h:1519
@ EPWM_LINK_WITH_EPWM_22
link current ePWM with ePWM22
Definition: etpwm.h:410
@ EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_T1
T1 event on count down and no change in the output pins.
Definition: etpwm.h:679
void EPWM_setEmulationMode(uint32_t base, EPWM_EmulationMode emulationMode)
@ HRPWM_XCMP6_SHADOW1
XCMP6_SHADOW1.
Definition: etpwm.h:1997
@ EPWM_LINK_WITH_EPWM_16
link current ePWM with ePWM16
Definition: etpwm.h:404
@ HRPWM_CMPD_SHADOW1
CMPD_SHADOW1.
Definition: etpwm.h:2007
EPWM_DigitalCompareEdgeFilterEdgeCount
Definition: etpwm.h:1677
@ EPWM_AQ_OUTPUT_HIGH_DOWN_CMPA
Time base counter down equals COMPA and set output pins to high.
Definition: etpwm.h:640
static void EPWM_selectDigitalCompareTripInput(uint32_t base, EPWM_DigitalCompareTripInput tripSource, EPWM_DigitalCompareType dcType)
Definition: etpwm.h:6489
EPWM_TripZoneDigitalCompareOutput
Definition: etpwm.h:907
EPWM_TripZoneAdvancedEvent
Definition: etpwm.h:967
@ EPWM_XCMP5_SHADOW3
XCMP5_SHADOW3.
Definition: etpwm.h:2149
@ EPWM_FED_LOAD_ON_CNTR_PERIOD
load when counter equals period
Definition: etpwm.h:833
static void EPWM_clearADCTriggerFlag(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
Definition: etpwm.h:6246
@ EPWM_COMP_LOAD_ON_CNTR_ZERO_PERIOD
load when counter equals zero or period
Definition: etpwm.h:473
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP9
Sync-in source is ECAP9 sync-out signal.
Definition: etpwm.h:270
@ EPWM_XCMP1_SHADOW1
XCMP1_SHADOW1.
Definition: etpwm.h:2099
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP0
Sync-in source is ECAP0 sync-out signal.
Definition: etpwm.h:252
@ EPWM_XMINMAX_SHADOW1
XMINMAX_SHADOW1.
Definition: etpwm.h:2117
#define EPWM_XCMP_ACTIVE
< XCMP set = Active
Definition: etpwm.h:2061
static void HRPWM_setMEPControlMode(uint32_t base, HRPWM_Channel channel, HRPWM_MEPCtrlMode mepCtrlMode)
Definition: etpwm.h:8744
static void EPWM_setDigitalCompareEventSyncMode(uint32_t base, EPWM_DigitalCompareModule dcModule, EPWM_DigitalCompareEvent dcEvent, EPWM_DigitalCompareSyncMode syncMode)
Definition: etpwm.h:6991
@ EPWM_DB_POLARITY_ACTIVE_HIGH
DB polarity is not inverted.
Definition: etpwm.h:769
static void EPWM_setActionQualifierContSWForceShadowMode(uint32_t base, EPWM_ActionQualifierContForce mode)
Definition: etpwm.h:4009
@ EPWM_DB_RED
DB RED (Rising Edge Delay) mode.
Definition: etpwm.h:757
@ EPWM_LINK_WITH_EPWM_24
link current ePWM with ePWM24
Definition: etpwm.h:412
EPWM_ActionQualifierTriggerSource
Definition: etpwm.h:534
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP1
Time base counter equals XCMP1.
Definition: etpwm.h:2171
@ HRPWM_MEP_PHASE_CTRL
TBPHSHR controls MEP edge.
Definition: etpwm.h:1872
#define EPWM_SYNC_OUT_SOURCE_M
Definition: etpwm.h:79
@ EPWM_COUNTER_COMPARE_D
counter compare D
Definition: etpwm.h:457
@ EPWM_TZ_EVENT_DCXL_HIGH_DCXH_LOW
Event when DCxL high DCxH low.
Definition: etpwm.h:927
@ EPWM_LINK_TBPRD
link TBPRD:TBPRDHR registers
Definition: etpwm.h:430
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT29
Trip source is INPUTXBAR out29 signal.
Definition: etpwm.h:2369
#define EPWM_INT_TBCTR_D_CMPD
time-base counter equal to CMPD when the timer is decrementing
Definition: etpwm.h:1212
@ EPWM_TZ_ADV_ACTION_EVENT_TZA_U
TZ1 - TZ6, DCAEVT2, DCAEVT1 while counting up.
Definition: etpwm.h:975
@ EPWM_SOC_TBCTR_PERIOD
Time-base counter equal to period.
Definition: etpwm.h:1274
static uint16_t EPWM_getGlobalLoadEventCount(uint32_t base)
Definition: etpwm.h:7965
@ HRPWM_XCMP5_SHADOW1
XCMP5_SHADOW1.
Definition: etpwm.h:1995
static void EPWM_setTripZoneAdvDigitalCompareActionB(uint32_t base, EPWM_TripZoneAdvDigitalCompareEvent tzAdvDCEvent, EPWM_TripZoneAdvancedAction tzAdvDCAction)
Definition: etpwm.h:5138
@ HRPWM_XCMP3_SHADOW3
XCMP3_SHADOW3.
Definition: etpwm.h:2037
@ EPWM_AQ_OUTPUT_TOGGLE_ZERO
Time base counter equals zero and toggle the output pins.
Definition: etpwm.h:618
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM18
Sync-in source is EPWM18 sync-out signal.
Definition: etpwm.h:224
static void HRPWM_setDeadbandMEPEdgeSelect(uint32_t base, HRPWM_MEPDeadBandEdgeMode mepDBEdge)
Definition: etpwm.h:9359
@ EPWM_DE_TRIP_SRC_CMPSSB4
Trip source is CMPSSB4 signal.
Definition: etpwm.h:2403
@ EPWM_AQ_TRIGGER_EVENT_TRIG_DC_EVTFILT
Digital compare filter event.
Definition: etpwm.h:543
@ HRPWM_DB_MEP_CTRL_RED
MEP controls Rising Edge Delay.
Definition: etpwm.h:1953
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM0
Sync-in source is EPWM0 sync-out signal.
Definition: etpwm.h:188
@ EPWM_SOC_TBCTR_D_CMPC
time-base counter equal to CMPC when the timer is decrementing
Definition: etpwm.h:1284
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT14
Trip source is INPUTXBAR out14 signal.
Definition: etpwm.h:2339
static void EPWM_setOneShotSyncOutTrigger(uint32_t base, EPWM_OneShotSyncOutTrigger trigger)
Definition: etpwm.h:2773
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA
Time base counter down equals COMPA.
Definition: etpwm.h:561
EPWM_ActionQualifierEventAction
Definition: etpwm.h:610
static void EPWM_disableXCMPMode(uint32_t base)
Definition: etpwm.h:9498
static void EPWM_setDigitalCompareWindowOffset(uint32_t base, uint16_t windowOffsetCount)
Definition: etpwm.h:6836
@ EPWM_XCMP_6_CMPA
Allocate XCMP1 - XCMP6 registers to CMPA.
Definition: etpwm.h:2209
EPWM_ClockDivider tbClkDiv
Time Base Counter Clock Divider.
Definition: etpwm.h:2490
@ EPWM_AQ_OUTPUT_NO_CHANGE
No change in the output pins.
Definition: etpwm.h:584
@ EPWM_DE_TRIP_SRC_CMPSSA0
Trip source is CMPSSA0 signal.
Definition: etpwm.h:2375
@ EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_1
Digital compare event B 1.
Definition: etpwm.h:537
static void HRPWM_setHiResRisingEdgeDelay(uint32_t base, uint16_t hrRedCount)
Definition: etpwm.h:9260
@ EPWM_XTBPRD_SHADOW3
XTBPRD_SHADOW3.
Definition: etpwm.h:2157
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX1_RX_TRIG1
Sync-in source is FSI-RX1 RX Trigger 1 signal.
Definition: etpwm.h:290
@ HRPWM_LOAD_ON_CNTR_ZERO
load when counter equals zero
Definition: etpwm.h:1885
static void EPWM_setMinDeadBandDelay(uint32_t base, uint32_t block, uint32_t delay)
Definition: etpwm.h:8414
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM27
Sync-in source is EPWM27 sync-out signal.
Definition: etpwm.h:242
@ EPWM_XCMP3_SHADOW3
XCMP3_SHADOW3.
Definition: etpwm.h:2145
@ EPWM_LINK_WITH_EPWM_12
link current ePWM with ePWM12
Definition: etpwm.h:400
static void HRPWM_setChannelBOutputPath(uint32_t base, HRPWM_ChannelBOutput outputOnB)
Definition: etpwm.h:8842
static void EPWM_enableInterrupt(uint32_t base)
Definition: etpwm.h:5568
static void EPWM_disableTripZoneAdvAction(uint32_t base)
Definition: etpwm.h:4943
static void EPWM_clearDiodeEmulationActive(uint32_t base)
Definition: etpwm.h:10263
#define EPWM_DB_INPUT_EPWMA
Input signal is ePWMA.
Definition: etpwm.h:780
@ HRPWM_XCMP5_ACTIVE
XCMP5_ACTIVE.
Definition: etpwm.h:1976
static void EPWM_setDeadBandCounterClock(uint32_t base, EPWM_DeadBandClockMode clockMode)
Definition: etpwm.h:4567
@ EPWM_OSHT_SYNC_OUT_TRIG_RELOAD
Trigger is OSHT reload.
Definition: etpwm.h:322
@ EPWM_AQ_OUTPUT_HIGH_ZERO
Time base counter equals zero and set output pins to high.
Definition: etpwm.h:616
@ EPWM_GL_LOAD_PULSE_SYNC_OR_CNTR_PERIOD
load on sync event or when counter is equal to period
Definition: etpwm.h:1545
HRPWM_ChannelBOutput
Definition: etpwm.h:1901
@ EPWM_LINK_WITH_EPWM_2
link current ePWM with ePWM2
Definition: etpwm.h:390
static void EPWM_enableIllegalComboLogic(uint32_t base, uint32_t block)
Definition: etpwm.h:8448
static void HRPWM_disablePeriodControl(uint32_t base)
Definition: etpwm.h:8929
@ EPWM_DB_OUTPUT_A
DB output is ePWMA.
Definition: etpwm.h:745
@ EPWM_TZ_CBC_PULSE_CLR_CNTR_PERIOD
Clear CBC pulse when counter equals period.
Definition: etpwm.h:1126
EPWM_TripZoneDigitalCompareOutputEvent
Definition: etpwm.h:921
@ EPWM_SHADOW_LOAD_MODE_SYNC
shadow to active load occurs only when a SYNC occurs
Definition: etpwm.h:367
static void EPWM_setTimeBaseCounterMode(uint32_t base, EPWM_TimeBaseCountMode counterMode)
Definition: etpwm.h:2883
EPWM_PeriodLoadMode
Definition: etpwm.h:332
Float32 sysClkInHz
SYSCLK Frequency(in Hz)
Definition: etpwm.h:2488
EPWM_CurrentLink
Definition: etpwm.h:387
static void EPWM_setDeadBandDelayPolarity(uint32_t base, EPWM_DeadBandDelayMode delayMode, EPWM_DeadBandPolarity polarity)
Definition: etpwm.h:4274
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM15
Sync-in source is EPWM15 sync-out signal.
Definition: etpwm.h:218
@ EPWM_HSCLOCK_DIVIDER_1
Divide clock by 1.
Definition: etpwm.h:167
static void EPWM_setChopperFirstPulseWidth(uint32_t base, uint16_t firstPulseWidth)
Definition: etpwm.h:4757
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM4
Sync-in source is EPWM4 sync-out signal.
Definition: etpwm.h:196
@ EPWM_HSCLOCK_DIVIDER_14
Divide clock by 14.
Definition: etpwm.h:174
@ EPWM_AQ_OUTPUT_LOW_DOWN_T2
T2 event on count down and set output pins to low.
Definition: etpwm.h:697
#define EPWM_DCxxTRIPSEL
Definition: etpwm.h:2469
HRPWM_MEPCtrlMode
Definition: etpwm.h:1868
EPWM_DiodeEmulationSignal
Definition: etpwm.h:2417
@ EPWM_REGISTER_GROUP_DIGITAL_COMPARE
Digital compare group.
Definition: etpwm.h:1708
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX3_RX_TRIG0
Sync-in source is FSI-RX3 RX Trigger 0 signal.
Definition: etpwm.h:304
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP8
Time base counter equals XCMP8.
Definition: etpwm.h:2185
@ EPWM_XCMP_7_CMPA
Allocate XCMP1 - XCMP7 registers to CMPA.
Definition: etpwm.h:2211
static void EPWM_disableFallingEdgeDelayCountShadowLoadMode(uint32_t base)
Definition: etpwm.h:4538
static void EPWM_clearEventTriggerInterruptFlag(uint32_t base)
Definition: etpwm.h:5758
EPWM_DigitalCompareTripInput
Definition: etpwm.h:1321
@ HRPWM_XCMP4_ACTIVE
XCMP4_ACTIVE.
Definition: etpwm.h:1974
@ EPWM_AQ_SW_OUTPUT_LOW
Set output pins to low.
Definition: etpwm.h:599
static void EPWM_enableDigitalCompareTripCombinationInput(uint32_t base, uint16_t tripInput, EPWM_DigitalCompareType dcType)
Definition: etpwm.h:7457
EPWM_SyncInPulseSource
Definition: etpwm.h:184
@ EPWM_AQ_OUTPUT_TOGGLE_DOWN_T2
T2 event on count down and toggle the output pins.
Definition: etpwm.h:701
static void EPWM_selectMinimumDeadBandReferenceSignal(uint32_t base, uint32_t block, uint32_t referenceSignal)
Definition: etpwm.h:8349
EPWM_DeadBandControlLoadMode
Definition: etpwm.h:793
EPWM_ActionQualifierSWOutput
Definition: etpwm.h:597
static void EPWM_setValleyDelayDivider(uint32_t base, EPWM_ValleyDelayMode delayMode)
Definition: etpwm.h:7740
@ EPWM_AQ_OUTPUT_ON_T1_COUNT_UP
T1 event on count up.
Definition: etpwm.h:567
static void EPWM_clearTripZoneFlag(uint32_t base, uint16_t tzFlags)
Definition: etpwm.h:5376
static void HRPWM_setFallingEdgeDelayLoadMode(uint32_t base, HRPWM_LoadMode loadEvent)
Definition: etpwm.h:9419
EPWM_ADCStartOfConversionType
Definition: etpwm.h:1256
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT28
Trip source is INPUTXBAR out28 signal.
Definition: etpwm.h:2367
@ EPWM_XCMP_2_CMPA
Allocate XCMP1 - XCMP2 registers to CMPA.
Definition: etpwm.h:2201
static void EPWM_setValleyTriggerSource(uint32_t base, EPWM_ValleyTriggerSource trigger)
Definition: etpwm.h:7613
@ EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SHIFT_1_SW_DELAY
Definition: etpwm.h:1642
static void EPWM_setCountModeAfterSync(uint32_t base, EPWM_SyncCountMode mode)
Definition: etpwm.h:2535
static void EPWM_setTripZoneAdvAction(uint32_t base, EPWM_TripZoneAdvancedEvent tzAdvEvent, EPWM_TripZoneAdvancedAction tzAdvAction)
Definition: etpwm.h:5036
@ EPWM_GL_LOAD_PULSE_SYNC
load on sync event
Definition: etpwm.h:1541
static void EPWM_disableDigitalCompareWindowInverseMode(uint32_t base)
Definition: etpwm.h:6582
@ EPWM_GL_LOAD_PULSE_SYNC_OR_CNTR_ZERO
load on sync event or when counter is equal to zero
Definition: etpwm.h:1543
static void EPWM_setChopperDutyCycle(uint32_t base, uint16_t dutyCycleCount)
Definition: etpwm.h:4694
#define EPWM_INT_TBCTR_ETINTMIX
Time-base counter based on mix events.
Definition: etpwm.h:1196
@ EPWM_XCMP5_SHADOW1
XCMP5_SHADOW1.
Definition: etpwm.h:2107
@ EPWM_LINK_WITH_EPWM_18
link current ePWM with ePWM18
Definition: etpwm.h:406
@ EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_CMPA
Time base counter down equals COMPA and no change in the output pins.
Definition: etpwm.h:636
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT25
Trip source is INPUTXBAR out25 signal.
Definition: etpwm.h:2361
@ EPWM_XCMP_XLOADCTL_SHDWLEVEL_0
Only Active register is available.
Definition: etpwm.h:2258
static void EPWM_setInterruptEventCount(uint32_t base, uint16_t eventCount)
Definition: etpwm.h:5705
static void EPWM_nobypassDiodeEmulationLogic(uint32_t base)
Definition: etpwm.h:10192
@ EPWM_CLOCK_DIVIDER_8
Divide clock by 8.
Definition: etpwm.h:152
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT3
Trip source is INPUTXBAR out3 signal.
Definition: etpwm.h:2317
@ EPWM_TZ_ADV_ACTION_EVENT_TZA_D
TZ1 - TZ6, DCAEVT2, DCAEVT1 while counting down.
Definition: etpwm.h:973
static bool EPWM_getSyncStatus(uint32_t base)
Definition: etpwm.h:3068
@ HRPWM_XCMP7_SHADOW2
XCMP7_SHADOW2.
Definition: etpwm.h:2022
@ HRPWM_XCMP8_SHADOW1
XCMP8_SHADOW1.
Definition: etpwm.h:2001
@ EPWM_TZ_ADV_ACTION_LOW
low voltage state
Definition: etpwm.h:989
@ EPWM_COMP_LOAD_ON_SYNC_CNTR_PERIOD
load when counter equals period
Definition: etpwm.h:479
@ EPWM_COUNTER_MODE_UP
Up - count mode.
Definition: etpwm.h:347
@ EPWM_SOC_TBCTR_U_CMPD
time-base counter equal to CMPD when the timer is incrementing
Definition: etpwm.h:1288
static void EPWM_setADCTriggerSource(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType, EPWM_ADCStartOfConversionSource socSource, uint16_t mixedSource)
Definition: etpwm.h:6017
static void EPWM_disableSplitXCMP(uint32_t base)
Definition: etpwm.h:9542
static void EPWM_enableMinimumDeadBand(uint32_t base, uint32_t block)
Definition: etpwm.h:8187
@ EPWM_HSCLOCK_DIVIDER_6
Divide clock by 6.
Definition: etpwm.h:170
@ EPWM_XCMP_1_CMPA
Allocate XCMP1 register to CMPA.
Definition: etpwm.h:2199
static uint16_t EPWM_getTripZoneFlagStatus(uint32_t base)
Definition: etpwm.h:5249
@ EPWM_REGISTER_GROUP_GLOBAL_LOAD
Global load register group.
Definition: etpwm.h:1705
@ EPWM_GL_LOAD_PULSE_CNTR_PERIOD
load when counter is equal to period
Definition: etpwm.h:1537
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP2
Time base counter equals XCMP2.
Definition: etpwm.h:2173
@ EPWM_AQ_OUTPUT_NO_CHANGE_UP_T2
T2 event on count up and no change in the output pins.
Definition: etpwm.h:687
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX0_RX_TRIG0
Sync-in source is FSI-RX0 RX Trigger 0 signal.
Definition: etpwm.h:280
static uint16_t EPWM_getTimeBasePeriod(uint32_t base)
Definition: etpwm.h:3185
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX0_RX_TRIG2
Sync-in source is FSI-RX0 RX Trigger 2 signal.
Definition: etpwm.h:284
static void EPWM_setValleySWDelayValue(uint32_t base, uint16_t delayOffsetValue)
Definition: etpwm.h:7719
@ EPWM_DC_MODULE_A
Digital Compare Module A.
Definition: etpwm.h:1449
@ EPWM_AQ_OUTPUT_A
ePWMxA output
Definition: etpwm.h:715
EPWM_GlobalLoadTrigger
Definition: etpwm.h:1533
@ EPWM_HSCLOCK_DIVIDER_10
Divide clock by 10.
Definition: etpwm.h:172
@ EPWM_LINK_WITH_EPWM_0
link current ePWM with ePWM0
Definition: etpwm.h:388
@ EPWM_COUNT_MODE_DOWN_AFTER_SYNC
Count down after sync event.
Definition: etpwm.h:137
@ EPWM_DC_WINDOW_START_TBCTR_ZERO
Time base counter equals zero.
Definition: etpwm.h:1389
@ EPWM_AQ_OUTPUT_TOGGLE
Toggle the output pins.
Definition: etpwm.h:587
EPWM_DigitalCompareCBCLatchClearEvent
Definition: etpwm.h:1517
@ EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_1
Digital compare event A 1.
Definition: etpwm.h:535
@ EPWM_XCMP_XLOADCTL_SHDWBUFPTR_TWO
Shadow buffer 2 is in use.
Definition: etpwm.h:2281
static void EPWM_disableDiodeEmulationMonitorModeControl(uint32_t base)
Definition: etpwm.h:10309
@ EPWM_AQ_OUTPUT_HIGH_DOWN_T1
T1 event on count down and set output pins to high.
Definition: etpwm.h:683
@ EPWM_XCMP3_SHADOW1
XCMP3_SHADOW1.
Definition: etpwm.h:2103
static bool EPWM_getDigitalCompareCaptureStatus(uint32_t base)
Definition: etpwm.h:7404
@ EPWM_VALLEY_TRIGGER_EVENT_SOFTWARE
Valley capture trigged by software.
Definition: etpwm.h:1598
static void EPWM_setGlobalLoadOneShotLatch(uint32_t base)
Definition: etpwm.h:8035
@ EPWM_AQ_SW_DISABLED
Software forcing disabled.
Definition: etpwm.h:598
@ HRPWM_XCMP3_SHADOW1
XCMP3_SHADOW1.
Definition: etpwm.h:1991
@ EPWM_XMINMAX_SHADOW2
XMINMAX_SHADOW2.
Definition: etpwm.h:2138
EPWM_ADCStartOfConversionSource
Definition: etpwm.h:1268
@ HRPWM_XCMP5_SHADOW3
XCMP5_SHADOW3.
Definition: etpwm.h:2041
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT23
Trip source is INPUTXBAR out23 signal.
Definition: etpwm.h:2357
static void EPWM_disableDigitalCompareTripCombinationInput(uint32_t base, uint16_t tripInput, EPWM_DigitalCompareType dcType)
Definition: etpwm.h:7506
@ HRPWM_PWMSYNC_SOURCE_COMPD_DOWN
Counter equals COMPD when counting down.
Definition: etpwm.h:1927
EPWM_EmulationMode
Definition: etpwm.h:120
@ EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_2
Trip zone 2.
Definition: etpwm.h:540
@ EPWM_DC_WINDOW_SOURCE_DCBEVT2
DC filter signal source is DCBEVT2.
Definition: etpwm.h:1434
#define EPWM_INT_TBCTR_U_CMPC
time-base counter equal to CMPC when the timer is incrementing
Definition: etpwm.h:1200
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM25
Sync-in source is EPWM25 sync-out signal.
Definition: etpwm.h:238
@ EPWM_DC_EDGEFILT_EDGECNT_2
Digital Compare Edge filter edge count = 3.
Definition: etpwm.h:1683
#define EPWM_INT_TBCTR_D_CMPB
time-base counter equal to CMPB when the timer is decrementing
Definition: etpwm.h:1210
EPWM_XCMP_ALLOC_CMPA
Values that can be passed to EPWM_allocAXCMP() as the alloctype parameter.
Definition: etpwm.h:2195
@ EPWM_LINK_WITH_EPWM_20
link current ePWM with ePWM20
Definition: etpwm.h:408
@ EPWM_RED_LOAD_ON_CNTR_ZERO_PERIOD
load when counter equals zero or period
Definition: etpwm.h:817
@ EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_2
Digital compare event A 2.
Definition: etpwm.h:536
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP6
Time base counter equals XCMP6.
Definition: etpwm.h:2181
@ HRPWM_XCMP3_SHADOW2
XCMP3_SHADOW2.
Definition: etpwm.h:2014
static void HRPWM_setSyncPulseSource(uint32_t base, HRPWM_SyncPulseSource syncPulseSource)
Definition: etpwm.h:9005
static void HRPWM_setHiResTimeBasePeriod(uint32_t base, uint16_t hrPeriodCount)
Definition: etpwm.h:8647
@ EPWM_LINK_WITH_EPWM_30
link current ePWM with ePWM30
Definition: etpwm.h:418
static void EPWM_enableDigitalCompareADCTrigger(uint32_t base, EPWM_DigitalCompareModule dcModule)
Definition: etpwm.h:7036
@ EPWM_DC_TYPE_DCAL
Digital Compare A Low.
Definition: etpwm.h:1309
EPWM_CounterCompareModule
Definition: etpwm.h:453
EPWM_HSClockDivider tbHSClkDiv
Time Base Counter HS Clock Divider.
Definition: etpwm.h:2491
@ EPWM_XTBPRD_SHADOW1
XTBPRD_SHADOW1.
Definition: etpwm.h:2115
@ EPWM_OSHT_SYNC_OUT_TRIG_SYNC
Trigger is OSHT sync.
Definition: etpwm.h:321
HRPWM_CounterCompareModule
Definition: etpwm.h:1937
@ EPWM_TZ_EVENT_DCXL_LOW
Event when DCxL low.
Definition: etpwm.h:925
@ EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_D
Digital Compare event A/B 1 while counting down.
Definition: etpwm.h:1006
static void HRPWM_setPhaseShift(uint32_t base, uint32_t phaseCount)
Definition: etpwm.h:8582
EPWM_DigitalCompareSyncMode
Definition: etpwm.h:1489
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT15
Trip source is INPUTXBAR out15 signal.
Definition: etpwm.h:2341
static void EPWM_setTimeBaseCounter(uint32_t base, uint16_t count)
Definition: etpwm.h:2510
@ EPWM_COUNTER_COMPARE_A
counter compare A
Definition: etpwm.h:454
@ EPWM_DC_EDGEFILT_MODE_BOTH
Definition: etpwm.h:1667
@ EPWM_LINK_WITH_EPWM_13
link current ePWM with ePWM13
Definition: etpwm.h:401
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM16
Sync-in source is EPWM16 sync-out signal.
Definition: etpwm.h:220
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB
Time base counter up equals COMPB.
Definition: etpwm.h:563
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP4
Sync-in source is ECAP4 sync-out signal.
Definition: etpwm.h:260
@ EPWM_XCMP1_SHADOW2
XCMP1_SHADOW2.
Definition: etpwm.h:2120
static void EPWM_enableTripZoneSignals(uint32_t base, uint32_t tzSignal)
Definition: etpwm.h:4810
@ EPWM_DC_TRIP_TRIPIN13
Trip 13.
Definition: etpwm.h:1334
@ HRPWM_XCMP7_SHADOW3
XCMP7_SHADOW3.
Definition: etpwm.h:2045
@ EPWM_DC_EDGEFILT_EDGECNT_7
Definition: etpwm.h:1693
@ HRPWM_XCMP2_SHADOW1
XCMP2_SHADOW1.
Definition: etpwm.h:1989
@ EPWM_AQ_OUTPUT_B
ePWMxB output
Definition: etpwm.h:716
@ EPWM_REGISTER_GROUP_TRIP_ZONE_CLEAR
Trip zone clear group.
Definition: etpwm.h:1707
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD
Time base counter equals period.
Definition: etpwm.h:557
static void EPWM_disableDigitalCompareBlankingWindow(uint32_t base)
Definition: etpwm.h:6539
@ EPWM_SOC_TBCTR_ZERO
Time-base counter equal to zero.
Definition: etpwm.h:1272
@ EPWM_LINK_WITH_EPWM_29
link current ePWM with ePWM29
Definition: etpwm.h:417
@ EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SHIFT_4_SW_DELAY
Definition: etpwm.h:1648
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT31
Trip source is INPUTXBAR out31 signal.
Definition: etpwm.h:2373
@ EPWM_LINK_WITH_EPWM_14
link current ePWM with ePWM14
Definition: etpwm.h:402
static void EPWM_setActionQualifierT1TriggerSource(uint32_t base, EPWM_ActionQualifierTriggerSource trigger)
Definition: etpwm.h:3676
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM17
Sync-in source is EPWM17 sync-out signal.
Definition: etpwm.h:222
#define EPWM_MINDB_BLOCK_A
Values that can be passed to.
Definition: etpwm.h:1720
EPWM_ActionQualifierOutputEvent
Definition: etpwm.h:553
@ EPWM_AQ_LOAD_ON_SYNC_CNTR_PERIOD
load on sync or when counter equals period
Definition: etpwm.h:520
@ EPWM_XCMP_XLOADCTL_LOADMODE_LOADMULTIPLE
Load mode is LOADMULTIPLE.
Definition: etpwm.h:2245
@ EPWM_DC_EDGEFILT_EDGECNT_0
Digital Compare Edge filter edge count = 0.
Definition: etpwm.h:1679
@ EPWM_AQ_LOAD_ON_CNTR_ZERO
load when counter equals zero
Definition: etpwm.h:510
@ EPWM_DC_TYPE_DCAH
Digital Compare A High.
Definition: etpwm.h:1308
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM1
Sync-in source is EPWM1 sync-out signal.
Definition: etpwm.h:190
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM31
Sync-in source is EPWM31 sync-out signal.
Definition: etpwm.h:250
@ EPWM_XCMP8_SHADOW3
XCMP8_SHADOW3.
Definition: etpwm.h:2155
@ HRPWM_OUTPUT_ON_B_INV_A
Definition: etpwm.h:1905
static void EPWM_setGlobalLoadTrigger(uint32_t base, EPWM_GlobalLoadTrigger loadTrigger)
Definition: etpwm.h:7908
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM3
Sync-in source is EPWM3 sync-out signal.
Definition: etpwm.h:194
@ EPWM_TZ_ACTION_EVENT_TZB
TZ1 - TZ6, DCBEVT2, DCBEVT1.
Definition: etpwm.h:939
static bool EPWM_getEventTriggerInterruptStatus(uint32_t base)
Definition: etpwm.h:5737
static void EPWM_setXCMPActionQualifierAction(uint32_t base, uint32_t shadowset, EPWM_ActionQualifierOutputModule epwmOutput, EPWM_ActionQualifierOutput output, EPWM_XCMPActionQualifierOutputEvent event)
Definition: etpwm.h:9690
@ EPWM_COMP_LOAD_ON_SYNC_CNTR_ZERO_PERIOD
load when counter equals zero or period
Definition: etpwm.h:481
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP4
Time base counter equals XCMP4.
Definition: etpwm.h:2177
@ EPWM_CLOCK_DIVIDER_64
Divide clock by 64.
Definition: etpwm.h:155
@ EPWM_AQ_OUTPUT_TOGGLE_UP_T1
T1 event on count up and toggle the output pins.
Definition: etpwm.h:677
static void EPWM_selectDiodeEmulationTripSignal(uint32_t base, uint32_t channel, uint32_t signal)
Definition: etpwm.h:10157
static void EPWM_allocAXCMP(uint32_t base, EPWM_XCMP_ALLOC_CMPA alloctype)
Definition: etpwm.h:9575
@ EPWM_LINK_WITH_EPWM_3
link current ePWM with ePWM3
Definition: etpwm.h:391
EPWM_TimeBaseCountMode tbCtrMode
Time Base Counter Mode.
Definition: etpwm.h:2489
static void EPWM_setPhaseShift(uint32_t base, uint16_t phaseCount)
Definition: etpwm.h:3136
static void EPWM_enableDiodeEmulationMode(uint32_t base)
Definition: etpwm.h:9939
EPWM_DigitalCompareType
Definition: etpwm.h:1307
@ EPWM_COMP_LOAD_ON_SYNC_ONLY
load on sync only
Definition: etpwm.h:483
@ EPWM_REGISTER_GROUP_HR
HRPWM register group.
Definition: etpwm.h:1704
@ EPWM_AQ_OUTPUT_TOGGLE_DOWN_CMPA
Time base counter down equals COMPA and toggle the output pins.
Definition: etpwm.h:642
@ EPWM_LINK_WITH_EPWM_21
link current ePWM with ePWM21
Definition: etpwm.h:409
static void EPWM_forceEventTriggerInterrupt(uint32_t base)
Definition: etpwm.h:5906
static void EPWM_selectXbarInput(uint32_t base, uint32_t block, uint32_t xbarInput)
Definition: etpwm.h:8507
static void EPWM_setDiodeEmulationMode(uint32_t base, EPWM_DiodeEmulationMode mode)
Definition: etpwm.h:9997
EPWM_DeadBandOutput
Definition: etpwm.h:744
@ EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_U
Digital Compare event A/B 2 while counting up.
Definition: etpwm.h:1008
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX0_RX_TRIG1
Sync-in source is FSI-RX0 RX Trigger 1 signal.
Definition: etpwm.h:282
@ EPWM_EMULATION_STOP_AFTER_FULL_CYCLE
Stop when counter completes whole cycle.
Definition: etpwm.h:124
@ EPWM_TZ_ADV_ACTION_EVENT_TZB_D
TZ1 - TZ6, DCBEVT2, DCBEVT1 while counting down.
Definition: etpwm.h:969
static void EPWM_disableValleyHWDelay(uint32_t base)
Definition: etpwm.h:7696
@ EPWM_SOC_TBCTR_MIXED_EVENT
Time-base counter equal to zero or period.
Definition: etpwm.h:1276
static void EPWM_setXCMPShadowBufPtrLoadOnce(uint32_t base, EPWM_XCMP_XLOADCTL_SHDWBUFPTR ptr)
Definition: etpwm.h:9866
static void EPWM_setClockPrescaler(uint32_t base, EPWM_ClockDivider prescaler, EPWM_HSClockDivider highSpeedPrescaler)
Definition: etpwm.h:2581
@ EPWM_AQ_OUTPUT_TOGGLE_UP_CMPB
Time base counter up equals COMPB and toggle the output pins.
Definition: etpwm.h:650
static uint16_t EPWM_getDigitalCompareBlankingWindowLengthCount(uint32_t base)
Definition: etpwm.h:6898
@ EPWM_AQ_OUTPUT_LOW_UP_CMPB
Time base counter up equals COMPB and set output pins to low.
Definition: etpwm.h:646
@ EPWM_RED_LOAD_ON_CNTR_ZERO
load when counter equals zero
Definition: etpwm.h:813
@ EPWM_HSCLOCK_DIVIDER_8
Divide clock by 8.
Definition: etpwm.h:171
@ EPWM_TZ_DC_OUTPUT_A2
Digital Compare output 2 A.
Definition: etpwm.h:909
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT13
Trip source is INPUTXBAR out13 signal.
Definition: etpwm.h:2337
Float32 dutyValB
Desired ePWMxB Signal Duty.
Definition: etpwm.h:2486
static void EPWM_lockRegisters(uint32_t base, EPWM_LockRegisterGroup registerGroup)
Definition: etpwm.h:8162
static void HRPWM_disableAutoConversion(uint32_t base)
Definition: etpwm.h:8887
@ EPWM_DE_TRIP_SRC_CMPSSA2
Trip source is CMPSSA2 signal.
Definition: etpwm.h:2379
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM12
Sync-in source is EPWM12 sync-out signal.
Definition: etpwm.h:212
@ HRPWM_XCMP2_ACTIVE
XCMP2_ACTIVE.
Definition: etpwm.h:1970
#define EPWM_INT_TBCTR_D_CMPC
time-base counter equal to CMPC when the timer is decrementing
Definition: etpwm.h:1204
@ EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_T2
T2 event on count down and no change in the output pins.
Definition: etpwm.h:695
@ EPWM_AQ_OUTPUT_TOGGLE_UP_T2
T2 event on count up and toggle the output pins.
Definition: etpwm.h:693
@ EPWM_XCMP8_ACTIVE
XCMP8_ACTIVE.
Definition: etpwm.h:2092
static void EPWM_enableXLoad(uint32_t base)
Definition: etpwm.h:9753
@ EPWM_TZ_ACTION_DISABLE
disable action
Definition: etpwm.h:957
@ EPWM_AQ_TRIGGER_EVENT_TRIG_EPWM_SYNCIN
ePWM sync
Definition: etpwm.h:542
static void EPWM_forceADCTriggerEventCountInit(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
Definition: etpwm.h:6336
static uint32_t EPWM_getMinDeadBandDelay(uint32_t base, uint32_t block)
Definition: etpwm.h:8381
@ HRPWM_XCMP6_ACTIVE
XCMP6_ACTIVE.
Definition: etpwm.h:1978
@ EPWM_XCMP_NONE_CMPA
Allocate 0 XCMP registers to CMPA.
Definition: etpwm.h:2197
static void EPWM_disableIllegalComboLogic(uint32_t base, uint32_t block)
Definition: etpwm.h:8477
@ EPWM_GL_LOAD_PULSE_SYNC_CNTR_ZERO_PERIOD
load on sync event or when counter is equal to period or zero
Definition: etpwm.h:1547
static void EPWM_disableActionQualifierShadowLoadMode(uint32_t base, EPWM_ActionQualifierModule aqModule)
Definition: etpwm.h:3637
static void EPWM_setADCTriggerEventPrescale(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType, uint16_t preScaleCount)
Definition: etpwm.h:6164
static void EPWM_enableInterruptEventCountInit(uint32_t base)
Definition: etpwm.h:5782
EPWM_DiodeEmulationTripSource
Definition: etpwm.h:2309
static void EPWM_enableDigitalCompareCounterCapture(uint32_t base)
Definition: etpwm.h:7320
@ EPWM_XCMP_XLOADCTL_SHDWBUFPTR_ONE
Shadow buffer 1 is in use.
Definition: etpwm.h:2279
@ EPWM_DC_WINDOW_SOURCE_DCAEVT1
DC filter signal source is DCAEVT1.
Definition: etpwm.h:1431
EPWM_DigitalCompareEvent
Definition: etpwm.h:1463
static void HRPWM_enableAutoConversion(uint32_t base)
Definition: etpwm.h:8865
@ EPWM_LINK_COMP_B
link COMPB registers
Definition: etpwm.h:432
@ EPWM_LINK_WITH_EPWM_6
link current ePWM with ePWM6
Definition: etpwm.h:394
static void EPWM_enableDigitalCompareWindowInverseMode(uint32_t base)
Definition: etpwm.h:6561
@ EPWM_XCMP4_SHADOW3
XCMP4_SHADOW3.
Definition: etpwm.h:2147
@ EPWM_LINK_WITH_EPWM_15
link current ePWM with ePWM15
Definition: etpwm.h:403
@ HRPWM_MEP_DUTY_PERIOD_CTRL
CMPAHR/CMPBHR or TBPRDHR controls MEP edge.
Definition: etpwm.h:1870
static void EPWM_disableDeadBandControlShadowLoadMode(uint32_t base)
Definition: etpwm.h:4428
@ EPWM_DE_TRIP_SRC_CMPSSA5
Trip source is CMPSSA5 signal.
Definition: etpwm.h:2385
@ EPWM_DB_POLARITY_ACTIVE_LOW
DB polarity is inverted.
Definition: etpwm.h:770
static void EPWM_setRisingEdgeDelayCountShadowLoadMode(uint32_t base, EPWM_RisingEdgeDelayLoadMode loadMode)
Definition: etpwm.h:4457
@ EPWM_TZ_ADV_ACTION_DISABLE
disable action
Definition: etpwm.h:991
@ EPWM_CLOCK_DIVIDER_4
Divide clock by 4.
Definition: etpwm.h:151
@ EPWM_DC_EVENT_INPUT_SYNCED
DC input signal is synced with TBCLK.
Definition: etpwm.h:1491
@ EPWM_AQ_OUTPUT_NO_CHANGE_PERIOD
Time base counter equals period and no change in the output pins.
Definition: etpwm.h:620
@ EPWM_LINK_DBRED
link DBRED registers
Definition: etpwm.h:436
EPWM_ValleyCounterEdge
Definition: etpwm.h:1622
EPWM_LockRegisterGroup
Definition: etpwm.h:1703
@ EPWM_SYNC_IN_PULSE_SRC_DISABLE
Disable Sync-in.
Definition: etpwm.h:186
static void EPWM_setFallingEdgeDeadBandDelayInput(uint32_t base, uint16_t input)
Definition: etpwm.h:4346
void EPWM_configureSignal(uint32_t base, const EPWM_SignalParams *signalParams)
@ EPWM_XCMP_XLOADCTL_SHDWBUFPTR_THREE
Shadow buffer 3 is in use.
Definition: etpwm.h:2283
EPWM_SyncCountMode
Definition: etpwm.h:136
@ EPWM_RED_LOAD_FREEZE
Freeze shadow to active load.
Definition: etpwm.h:819
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX1_RX_TRIG0
Sync-in source is FSI-RX1 RX Trigger 0 signal.
Definition: etpwm.h:288
@ EPWM_HSCLOCK_DIVIDER_12
Divide clock by 12.
Definition: etpwm.h:173
HRPWM_Channel
Definition: etpwm.h:1838
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM21
Sync-in source is EPWM21 sync-out signal.
Definition: etpwm.h:230
static void EPWM_setDeadBandControlShadowLoadMode(uint32_t base, EPWM_DeadBandControlLoadMode loadMode)
Definition: etpwm.h:4403
@ EPWM_DC_TRIP_TRIPIN4
Trip 4.
Definition: etpwm.h:1325
EPWM_HSClockDivider
Definition: etpwm.h:166
@ EPWM_RED_LOAD_ON_CNTR_PERIOD
load when counter equals period
Definition: etpwm.h:815
static void HRPWM_setOutputSwapMode(uint32_t base, bool enableOutputSwap)
Definition: etpwm.h:8809
@ EPWM_AQ_OUTPUT_LOW_DOWN_CMPA
Time base counter down equals COMPA and set output pins to low.
Definition: etpwm.h:638
@ HRPWM_MEP_CTRL_DISABLE
HRPWM is disabled.
Definition: etpwm.h:1852
@ EPWM_AQ_OUTPUT_NO_CHANGE_ZERO
Time base counter equals zero and no change in the output pins.
Definition: etpwm.h:612
@ EPWM_DE_TRIP_SRC_CMPSSA1
Trip source is CMPSSA1 signal.
Definition: etpwm.h:2377
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT19
Trip source is INPUTXBAR out19 signal.
Definition: etpwm.h:2349
@ EPWM_AQ_OUTPUT_LOW
Set output pins to low.
Definition: etpwm.h:585
@ EPWM_XCMP_1_CMPB
Allocate XCMP5 register to CMPB.
Definition: etpwm.h:2225
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT8
Trip source is INPUTXBAR out8 signal.
Definition: etpwm.h:2327
static uint16_t EPWM_getTimeBaseCounterDirection(uint32_t base)
Definition: etpwm.h:3112
HRPWM_LoadMode
Definition: etpwm.h:1883
@ EPWM_XCMP1_ACTIVE
XCMP1_ACTIVE.
Definition: etpwm.h:2078
static void EPWM_selectMinimumDeadBandAndOrLogic(uint32_t base, uint32_t block, uint32_t referenceSignal)
Definition: etpwm.h:8282
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM19
Sync-in source is EPWM19 sync-out signal.
Definition: etpwm.h:226
static uint16_t EPWM_getDigitalCompareCaptureCount(uint32_t base)
Definition: etpwm.h:7427
static void EPWM_setDigitalCompareBlankingEvent(uint32_t base, EPWM_DigitalCompareBlankingPulse blankingPulse, uint16_t mixedSource)
Definition: etpwm.h:6612
#define EPWM_INT_TBCTR_U_CMPD
time-base counter equal to CMPD when the timer is incrementing
Definition: etpwm.h:1208
@ EPWM_XCMP_XLOADCTL_LOADMODE_LOADONCE
Load mode is LOADONCE.
Definition: etpwm.h:2243
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX3_RX_TRIG1
Sync-in source is FSI-RX3 RX Trigger 1 signal.
Definition: etpwm.h:306
@ EPWM_LINK_XLOAD
link XLOAD registers
Definition: etpwm.h:438
@ EPWM_TZ_ADV_ACTION_EVENT_TZB_U
TZ1 - TZ6, DCBEVT2, DCBEVT1 while counting up.
Definition: etpwm.h:971
@ EPWM_TZ_EVENT_DC_DISABLED
Event is disabled.
Definition: etpwm.h:922
@ EPWM_XCMP_XLOADCTL_SHDWLEVEL_3
SHDW3, SHDW2, SHDW1 and Active registers are available.
Definition: etpwm.h:2264
static uint16_t EPWM_getInterruptEventCount(uint32_t base)
Definition: etpwm.h:5884
@ HRPWM_XCMP8_SHADOW2
XCMP8_SHADOW2.
Definition: etpwm.h:2024
static void EPWM_setDigitalCompareCounterShadowMode(uint32_t base, bool enableShadowMode)
Definition: etpwm.h:7367
Float32 freqInHz
Desired Signal Frequency(in Hz)
Definition: etpwm.h:2484
@ EPWM_ACTION_QUALIFIER_A
Action Qualifier A.
Definition: etpwm.h:497
#define EPWM_DE_TRIPH
Definition: etpwm.h:2459
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM11
Sync-in source is EPWM11 sync-out signal.
Definition: etpwm.h:210
@ EPWM_DE_TRIP_SRC_CMPSSB5
Trip source is CMPSSB5 signal.
Definition: etpwm.h:2405
@ EPWM_DE_TRIP_SRC_CMPSSA4
Trip source is CMPSSA4 signal.
Definition: etpwm.h:2383
#define EPWM_XCMP_SHADOW3
Definition: etpwm.h:2067
EPWM_TripZoneEvent
Definition: etpwm.h:937
@ HRPWM_XCMP5_SHADOW2
XCMP5_SHADOW2.
Definition: etpwm.h:2018
@ HRPWM_XCMP3_ACTIVE
XCMP3_ACTIVE.
Definition: etpwm.h:1972
@ EPWM_DC_TRIP_COMBINATION
All Trips (Trip1 - Trip 15) are selected.
Definition: etpwm.h:1337
@ EPWM_GL_LOAD_PULSE_GLOBAL_FORCE
load on global force
Definition: etpwm.h:1557
@ EPWM_DC_TRIP_TRIPIN15
Trip 15.
Definition: etpwm.h:1336
static void EPWM_disableGlobalLoadOneShotMode(uint32_t base)
Definition: etpwm.h:7988
#define EPWM_INT_TBCTR_D_CMPA
time-base counter equal to CMPA when the timer is decrementing
Definition: etpwm.h:1202
EPWM_DigitalCompareBlankingPulse
Definition: etpwm.h:1385
static uint16_t HRPWM_getHiResCounterCompareValueOnly(uint32_t base, HRPWM_CounterCompareModule compModule)
Definition: etpwm.h:9217
static void EPWM_forceSyncPulse(uint32_t base)
Definition: etpwm.h:2608
@ EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SHIFT_2_SW_DELAY
Definition: etpwm.h:1645
EPWM_ValleyDelayMode
Definition: etpwm.h:1634
@ EPWM_LINK_WITH_EPWM_11
link current ePWM with ePWM11
Definition: etpwm.h:399
@ EPWM_CLOCK_DIVIDER_1
Divide clock by 1.
Definition: etpwm.h:149
@ EPWM_AQ_OUTPUT_NO_CHANGE_UP_CMPA
Time base counter up equals COMPA and no change in the output pins.
Definition: etpwm.h:628
@ EPWM_XCMP_3_CMPA
Allocate XCMP1 - XCMP3 registers to CMPA.
Definition: etpwm.h:2203
static void EPWM_setSyncInPulseSource(uint32_t base, EPWM_SyncInPulseSource source)
Definition: etpwm.h:2648
@ EPWM_DE_TRIP_SRC_CMPSSB8
Trip source is CMPSSB8 signal.
Definition: etpwm.h:2411
@ EPWM_TZ_ACTION_HIGH_Z
high impedance output
Definition: etpwm.h:954
static void EPWM_allocBXCMP(uint32_t base, EPWM_XCMP_ALLOC_CMPB alloctype)
Definition: etpwm.h:9602
@ HRPWM_LOAD_ON_CNTR_PERIOD
load when counter equals period
Definition: etpwm.h:1887
static void EPWM_setTripZoneAdvDigitalCompareActionA(uint32_t base, EPWM_TripZoneAdvDigitalCompareEvent tzAdvDCEvent, EPWM_TripZoneAdvancedAction tzAdvDCAction)
Definition: etpwm.h:5087
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT6
Trip source is INPUTXBAR out6 signal.
Definition: etpwm.h:2323
static void EPWM_setDigitalCompareEdgeFilterMode(uint32_t base, EPWM_DigitalCompareEdgeFilterMode edgeMode)
Definition: etpwm.h:6729
@ EPWM_LINK_WITH_EPWM_23
link current ePWM with ePWM23
Definition: etpwm.h:411
@ EPWM_EMULATION_STOP_AFTER_NEXT_TB
Stop after next Time Base counter increment or decrement.
Definition: etpwm.h:122
@ EPWM_XMINMAX_SHADOW3
XMINMAX_SHADOW3.
Definition: etpwm.h:2159
static void EPWM_setGlobalLoadEventPrescale(uint32_t base, uint16_t prescalePulseCount)
Definition: etpwm.h:7935
@ EPWM_SOC_TBCTR_D_CMPA
time-base counter equal to CMPA when the timer is decrementing
Definition: etpwm.h:1282
@ EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL
signal source is unfiltered (DCAEVT1/2)
Definition: etpwm.h:1477
bool invertSignalB
Invert ePWMxB Signal if true.
Definition: etpwm.h:2487
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX1_RX_TRIG2
Sync-in source is FSI-RX1 RX Trigger 2 signal.
Definition: etpwm.h:292
@ EPWM_AQ_OUTPUT_ON_T2_COUNT_DOWN
T2 event on count down.
Definition: etpwm.h:573
static void EPWM_setActionQualifierAction(uint32_t base, EPWM_ActionQualifierOutputModule epwmOutput, EPWM_ActionQualifierOutput output, EPWM_ActionQualifierOutputEvent event)
Definition: etpwm.h:3766
@ EPWM_DB_FED
DB FED (Falling Edge Delay) mode.
Definition: etpwm.h:758
static void EPWM_disableMinimumDeadBand(uint32_t base, uint32_t block)
Definition: etpwm.h:8216
@ EPWM_TZ_DC_OUTPUT_B2
Digital Compare output 2 B.
Definition: etpwm.h:911
static void EPWM_setCounterCompareValue(uint32_t base, EPWM_CounterCompareModule compModule, uint16_t compCount)
Definition: etpwm.h:3446
@ EPWM_TZ_ADV_ACTION_HIGH_Z
high impedance output
Definition: etpwm.h:987
static uint16_t EPWM_getDigitalCompareBlankingWindowOffsetCount(uint32_t base)
Definition: etpwm.h:6878
static void EPWM_invertMinimumDeadBandSignal(uint32_t base, uint32_t block, uint32_t invert)
Definition: etpwm.h:8247
@ EPWM_DE_TRIP_SRC_CMPSSA8
Trip source is CMPSSA8 signal.
Definition: etpwm.h:2391
@ EPWM_DC_TYPE_DCBL
Digital Compare B Low.
Definition: etpwm.h:1311
@ EPWM_CLOCK_DIVIDER_2
Divide clock by 2.
Definition: etpwm.h:150
EPWM_DeadBandDelayMode
Definition: etpwm.h:756
static void EPWM_enableDigitalCompareEdgeFilter(uint32_t base)
Definition: etpwm.h:6680
@ HRPWM_XCMP4_SHADOW1
XCMP4_SHADOW1.
Definition: etpwm.h:1993
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM26
Sync-in source is EPWM26 sync-out signal.
Definition: etpwm.h:240
@ EPWM_DC_EDGEFILT_EDGECNT_3
Digital Compare Edge filter edge count = 4.
Definition: etpwm.h:1685
@ HRPWM_LOAD_ON_CMPB_EQ
load on translater event CMPB-3
Definition: etpwm.h:1891
#define EPWM_INT_TBCTR_U_CMPA
time-base counter equal to CMPA when the timer is incrementing
Definition: etpwm.h:1198
static void EPWM_setCounterCompareShadowLoadMode(uint32_t base, EPWM_CounterCompareModule compModule, EPWM_CounterCompareLoadMode loadMode)
Definition: etpwm.h:3318
EPWM_OneShotSyncOutTrigger
Definition: etpwm.h:320
static void EPWM_setXCMPRegValue(uint32_t base, EPWM_XCMPReg xcmpReg, uint16_t xcmpvalue)
Definition: etpwm.h:9634
static void EPWM_setRisingEdgeDelayCount(uint32_t base, uint16_t redCount)
Definition: etpwm.h:4593
static void EPWM_enableSplitXCMP(uint32_t base)
Definition: etpwm.h:9520
@ EPWM_TZ_EVENT_DCXH_HIGH
Event when DCxH high.
Definition: etpwm.h:924
@ EPWM_CLOCK_DIVIDER_16
Divide clock by 16.
Definition: etpwm.h:153
@ EPWM_DC_TRIP_TRIPIN12
Trip 12.
Definition: etpwm.h:1333
@ EPWM_XCMP_2_CMPB
Allocate XCMP5 - XCMP6 registers to CMPB.
Definition: etpwm.h:2227
static void EPWM_disableDiodeEmulationMode(uint32_t base)
Definition: etpwm.h:9965
@ EPWM_XCMP5_SHADOW2
XCMP5_SHADOW2.
Definition: etpwm.h:2128
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT5
Trip source is INPUTXBAR out5 signal.
Definition: etpwm.h:2321
@ EPWM_LINK_WITH_EPWM_10
link current ePWM with ePWM10
Definition: etpwm.h:398
static void EPWM_enableADCTrigger(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
Definition: etpwm.h:5934
@ EPWM_DC_TRIP_TRIPIN10
Trip 10.
Definition: etpwm.h:1331
@ HRPWM_XCMP8_SHADOW3
XCMP8_SHADOW3.
Definition: etpwm.h:2047
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP2
Sync-in source is ECAP2 sync-out signal.
Definition: etpwm.h:256
static void EPWM_setADCTriggerEventCountInitValue(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType, uint16_t eventCount)
Definition: etpwm.h:6366
HRPWM_MEPDeadBandEdgeMode
Definition: etpwm.h:1949
@ EPWM_SOC_TBCTR_U_CMPC
time-base counter equal to CMPC when the timer is incrementing
Definition: etpwm.h:1280
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT4
Trip source is INPUTXBAR out4 signal.
Definition: etpwm.h:2319
@ EPWM_VALLEY_COUNT_STOP_EDGE
Valley count stop edge.
Definition: etpwm.h:1624
@ EPWM_COUNTER_MODE_STOP_FREEZE
Stop - Freeze counter.
Definition: etpwm.h:350
@ EPWM_LINK_WITH_EPWM_17
link current ePWM with ePWM17
Definition: etpwm.h:405
static void EPWM_setDigitalCompareCBCLatchMode(uint32_t base, EPWM_DigitalCompareModule dcModule, EPWM_DigitalCompareEvent dcEvent, EPWM_DigitalCompareCBCLatchMode latchMode)
Definition: etpwm.h:7169
static void EPWM_forceGlobalLoadOneShotEvent(uint32_t base)
Definition: etpwm.h:8057
static bool EPWM_getValleyEdgeStatus(uint32_t base, EPWM_ValleyCounterEdge edge)
Definition: etpwm.h:7768
EPWM_ActionQualifierOutput
Definition: etpwm.h:583
@ EPWM_DC_EDGEFILT_MODE_RISING
Digital Compare Edge filter low to high edge mode.
Definition: etpwm.h:1663
@ EPWM_TZ_ACTION_EVENT_DCBEVT2
DCBEVT2 (Digital Compare B event 2)
Definition: etpwm.h:943
@ EPWM_AQ_OUTPUT_LOW_UP_T1
T1 event on count up and set output pins to low.
Definition: etpwm.h:673
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM14
Sync-in source is EPWM14 sync-out signal.
Definition: etpwm.h:216
@ EPWM_XCMP2_SHADOW1
XCMP2_SHADOW1.
Definition: etpwm.h:2101
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT7
Trip source is INPUTXBAR out7 signal.
Definition: etpwm.h:2325
@ HRPWM_PWMSYNC_SOURCE_COMPC_DOWN
Counter equals COMPC when counting down.
Definition: etpwm.h:1923
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM10
Sync-in source is EPWM10 sync-out signal.
Definition: etpwm.h:208
EPWM_ClockDivider
Definition: etpwm.h:148
#define EPWM_DB_INPUT_DB_RED
Input signal is the output of Rising Edge delay.
Definition: etpwm.h:784
EPWM_LinkComponent
Definition: etpwm.h:429
static void EPWM_disableSyncOutPulseSource(uint32_t base, uint16_t source)
Definition: etpwm.h:2740
static void EPWM_disableADCTriggerEventCountInit(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
Definition: etpwm.h:6307
@ EPWM_GL_LOAD_PULSE_CNTR_CMPD_D
load when counter is equal to cmpd and cmpd is decrementing
Definition: etpwm.h:1555
HRPWM_SyncPulseSource
Definition: etpwm.h:1915
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT17
Trip source is INPUTXBAR out17 signal.
Definition: etpwm.h:2345
@ EPWM_VALLEY_TRIGGER_EVENT_CNTR_ZERO
Valley capture trigged by when counter is equal to zero.
Definition: etpwm.h:1600
@ EPWM_AQ_OUTPUT_LOW_DOWN_CMPB
Time base counter down equals COMPB and set output pins to low.
Definition: etpwm.h:654
EPWM_DigitalCompareModule
Definition: etpwm.h:1448
static bool EPWM_getADCTriggerFlagStatus(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
Definition: etpwm.h:6219
@ EPWM_FED_LOAD_FREEZE
Freeze shadow to active load.
Definition: etpwm.h:837
EPWM_DigitalCompareCBCLatchMode
Definition: etpwm.h:1503
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX1_RX_TRIG3
Sync-in source is FSI-RX1 RX Trigger 3 signal.
Definition: etpwm.h:294
@ EPWM_SOC_B
SOC B.
Definition: etpwm.h:1258
@ HRPWM_XCMP7_ACTIVE
XCMP7_ACTIVE.
Definition: etpwm.h:1980
@ EPWM_PERIOD_SHADOW_LOAD
PWM Period register access is through shadow register.
Definition: etpwm.h:334
@ EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_D
Digital Compare event A/B 2 while counting down.
Definition: etpwm.h:1010
@ EPWM_DC_EDGEFILT_EDGECNT_1
Digital Compare Edge filter edge count = 2.
Definition: etpwm.h:1681
static void HRPWM_setHiResCounterCompareValue(uint32_t base, HRPWM_CounterCompareModule compModule, uint16_t hrCompCount)
Definition: etpwm.h:9170
@ EPWM_DC_EVENT_SOURCE_FILT_SIGNAL
signal source is filtered (DCEVTFILT)
Definition: etpwm.h:1479
@ EPWM_DE_TRIP_SRC_CMPSSA3
Trip source is CMPSSA3 signal.
Definition: etpwm.h:2381
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM23
Sync-in source is EPWM23 sync-out signal.
Definition: etpwm.h:234
@ EPWM_LINK_WITH_EPWM_8
link current ePWM with ePWM8
Definition: etpwm.h:396
@ EPWM_AQ_OUTPUT_HIGH_UP_CMPB
Time base counter up equals COMPB and set output pins to high.
Definition: etpwm.h:648
static bool EPWM_getTimeBaseCounterOverflowStatus(uint32_t base)
Definition: etpwm.h:3023
@ EPWM_DE_TRIP_SRC_CMPSSA9
Trip source is CMPSSA9 signal.
Definition: etpwm.h:2393
@ EPWM_COUNTER_COMPARE_B
counter compare B
Definition: etpwm.h:455
@ EPWM_SOC_DCxEVT1
Event is based on DCxEVT1.
Definition: etpwm.h:1270
@ EPWM_AQ_OUTPUT_NO_CHANGE_UP_T1
T1 event on count up and no change in the output pins.
Definition: etpwm.h:671
@ EPWM_DC_CBC_LATCH_ENABLED
DC cycle-by-cycle(CBC) latch is enabled.
Definition: etpwm.h:1507
@ EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_1
Trip zone 1.
Definition: etpwm.h:539
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM28
Sync-in source is EPWM28 sync-out signal.
Definition: etpwm.h:244
EPWM_ValleyTriggerSource
Definition: etpwm.h:1596
@ EPWM_DC_TRIP_TRIPIN6
Trip 6.
Definition: etpwm.h:1327
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP5
Sync-in source is ECAP5 sync-out signal.
Definition: etpwm.h:262
@ HRPWM_CMPC_SHADOW3
CMPC_SHADOW3.
Definition: etpwm.h:2051
@ EPWM_TZ_ADV_ACTION_TOGGLE
toggle the output
Definition: etpwm.h:990
@ EPWM_LINK_COMP_A
link COMPA registers
Definition: etpwm.h:431
static void EPWM_enableGlobalLoad(uint32_t base)
Definition: etpwm.h:7847
static void EPWM_disableValleyCapture(uint32_t base)
Definition: etpwm.h:7562
@ EPWM_TZ_ADV_ACTION_HIGH
high voltage state
Definition: etpwm.h:988
@ EPWM_VALLEY_TRIGGER_EVENT_DCBEVT1
Valley capture trigged by DCBEVT1 (Digital Compare B event 1)
Definition: etpwm.h:1610
EPWM_AdditionalActionQualifierEventAction
Definition: etpwm.h:669
static void EPWM_configureDiodeEmulationTripSources(uint32_t base, EPWM_DiodeEmulationTripSource source, uint32_t tripLorH)
Definition: etpwm.h:10066
@ EPWM_XCMP7_SHADOW2
XCMP7_SHADOW2.
Definition: etpwm.h:2132
static void EPWM_enableChopper(uint32_t base)
Definition: etpwm.h:4648
@ HRPWM_XTBPRD_SHADOW2
XTBPRD_SHADOW2.
Definition: etpwm.h:2026
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO
Time base counter equals zero.
Definition: etpwm.h:555
@ EPWM_DC_TRIP_TRIPIN3
Trip 3.
Definition: etpwm.h:1324
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX2_RX_TRIG1
Sync-in source is FSI-RX2 RX Trigger 1 signal.
Definition: etpwm.h:298
static void EPWM_enablePhaseShiftLoad(uint32_t base)
Definition: etpwm.h:2835
static void EPWM_setTripZoneDigitalCompareEventCondition(uint32_t base, EPWM_TripZoneDigitalCompareOutput dcType, EPWM_TripZoneDigitalCompareOutputEvent dcEvent)
Definition: etpwm.h:4895
@ EPWM_AQ_SW_IMMEDIATE_LOAD
No shadow load mode. Immediate mode only.
Definition: etpwm.h:734
@ EPWM_DC_WINDOW_SOURCE_DCBEVT1
DC filter signal source is DCBEVT1.
Definition: etpwm.h:1433
static void EPWM_clearTimeBaseCounterOverflowEvent(uint32_t base)
Definition: etpwm.h:3046
EPWM_DeadBandPolarity
Definition: etpwm.h:768
@ EPWM_DC_TRIP_TRIPIN7
Trip 7.
Definition: etpwm.h:1328
@ EPWM_LINK_WITH_EPWM_28
link current ePWM with ePWM28
Definition: etpwm.h:416
HRPWM_MEPEdgeMode
Definition: etpwm.h:1850
static void EPWM_disableADCTrigger(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
Definition: etpwm.h:5967
@ EPWM_DB_LOAD_FREEZE
Freeze shadow to active load.
Definition: etpwm.h:801
static void HRPWM_setCounterCompareShadowLoadEvent(uint32_t base, HRPWM_Channel channel, HRPWM_LoadMode loadEvent)
Definition: etpwm.h:8782
@ EPWM_XCMP7_SHADOW3
XCMP7_SHADOW3.
Definition: etpwm.h:2153
static void EPWM_enableDiodeEmulationMonitorModeControl(uint32_t base)
Definition: etpwm.h:10286
@ EPWM_XCMP_XLOADCTL_SHDWBUFPTR_NULL
No Shadow buffer is in use.
Definition: etpwm.h:2277
static void EPWM_enableDigitalCompareBlankingWindow(uint32_t base)
Definition: etpwm.h:6518
@ EPWM_DC_WINDOW_START_TBCTR_PERIOD
Time base counter equals period.
Definition: etpwm.h:1387
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT11
Trip source is INPUTXBAR out11 signal.
Definition: etpwm.h:2333
EPWM_TripZoneAdvancedAction
Definition: etpwm.h:986
@ EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SW_DELAY
Definition: etpwm.h:1639
@ HRPWM_MEP_CTRL_RISING_EDGE
MEP controls rising edge.
Definition: etpwm.h:1854
@ EPWM_DC_TRIP_TRIPIN14
Trip 14.
Definition: etpwm.h:1335
#define EPWM_DE_CHANNEL_A
< Diode emulation channel A
Definition: etpwm.h:2435
static void HRPWM_disablePhaseShiftLoad(uint32_t base)
Definition: etpwm.h:8972
static void EPWM_disableTripZoneOutput(uint32_t base, uint16_t tzOutput)
Definition: etpwm.h:5544
@ EPWM_XCMP_8_CMPA
Allocate XCMP1 - XCMP8 registers to CMPA.
Definition: etpwm.h:2213
@ EPWM_XCMP6_SHADOW3
XCMP6_SHADOW3.
Definition: etpwm.h:2151
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT26
Trip source is INPUTXBAR out26 signal.
Definition: etpwm.h:2363
@ EPWM_AQ_OUTPUT_TOGGLE_PERIOD
Time base counter equals period and toggle the output pins.
Definition: etpwm.h:626
@ EPWM_VALLEY_TRIGGER_EVENT_CNTR_ZERO_PERIOD
Valley capture trigged when counter is equal to zero or period.
Definition: etpwm.h:1604
static void EPWM_setActionQualifierSWAction(uint32_t base, EPWM_ActionQualifierOutputModule epwmOutput, EPWM_ActionQualifierOutput output)
Definition: etpwm.h:4093
static void EPWM_disableGlobalLoadRegisters(uint32_t base, uint16_t loadRegister)
Definition: etpwm.h:8133
@ EPWM_COUNTER_MODE_UP_DOWN
Up - down - count mode.
Definition: etpwm.h:349
@ EPWM_DC_TRIP_TRIPIN11
Trip 11.
Definition: etpwm.h:1332
static void EPWM_enableOneShotSync(uint32_t base)
Definition: etpwm.h:2937
static void EPWM_enableSyncOutPulseSource(uint32_t base, uint16_t source)
Definition: etpwm.h:2695
static void EPWM_setAdditionalActionQualifierActionComplete(uint32_t base, EPWM_ActionQualifierOutputModule epwmOutput, EPWM_AdditionalActionQualifierEventAction action)
Definition: etpwm.h:3969
EPWM_TripZoneAction
Definition: etpwm.h:953
@ HRPWM_DB_MEP_CTRL_RED_FED
MEP controls both Falling and Rising edge delay.
Definition: etpwm.h:1957
@ EPWM_XCMP6_ACTIVE
XCMP6_ACTIVE.
Definition: etpwm.h:2088
#define EPWM_LOCK_KEY
Definition: etpwm.h:2474
@ HRPWM_MEP_CTRL_FALLING_EDGE
MEP controls falling edge.
Definition: etpwm.h:1856
@ EPWM_DE_TRIP_SRC_CMPSSB3
Trip source is CMPSSB3 signal.
Definition: etpwm.h:2401
@ EPWM_DE_TRIP_SRC_CMPSSB6
Trip source is CMPSSB6 signal.
Definition: etpwm.h:2407
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP8
Sync-in source is ECAP8 sync-out signal.
Definition: etpwm.h:268
@ EPWM_DC_CBC_LATCH_DISABLED
DC cycle-by-cycle(CBC) latch is disabled.
Definition: etpwm.h:1505
@ EPWM_LINK_GLDCTL2
link GLDCTL2 registers
Definition: etpwm.h:435
@ EPWM_VALLEY_TRIGGER_EVENT_CNTR_PERIOD
Valley capture trigged by when counter is equal period.
Definition: etpwm.h:1602
EPWM_TripZoneAdvDigitalCompareEvent
Definition: etpwm.h:1002
@ HRPWM_CMPC_SHADOW2
CMPC_SHADOW2.
Definition: etpwm.h:2028
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT9
Trip source is INPUTXBAR out9 signal.
Definition: etpwm.h:2329
static void EPWM_selectMinimumDeadBandBlockingSignal(uint32_t base, uint32_t block, uint32_t blockingSignal)
Definition: etpwm.h:8316
EPWM_DigitalCompareEventSource
Definition: etpwm.h:1475
@ EPWM_SHADOW_LOAD_MODE_COUNTER_SYNC
Definition: etpwm.h:365
static void EPWM_setDiodeEmulationMonitorCounterThreshold(uint32_t base, uint16_t threshold)
Definition: etpwm.h:10373
EPWM_XCMP_ALLOC_CMPB
Values that can be passed to EPWM_allocBXCMP() as the alloctype parameter.
Definition: etpwm.h:2223
@ EPWM_AQ_OUTPUT_ON_T2_COUNT_UP
T2 event on count up.
Definition: etpwm.h:571
static uint16_t EPWM_getOneShotTripZoneFlagStatus(uint32_t base)
Definition: etpwm.h:5311
@ EPWM_AQ_OUTPUT_TOGGLE_DOWN_CMPB
Time base counter down equals COMPB and toggle the output pins.
Definition: etpwm.h:658
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP7
Time base counter equals XCMP7.
Definition: etpwm.h:2183
@ HRPWM_OUTPUT_ON_B_NORMAL
ePWMxB output is normal.
Definition: etpwm.h:1903
static void EPWM_setTripZoneAction(uint32_t base, EPWM_TripZoneEvent tzEvent, EPWM_TripZoneAction tzAction)
Definition: etpwm.h:4985
@ EPWM_FED_LOAD_ON_CNTR_ZERO
load when counter equals zero
Definition: etpwm.h:831
EPWM_DigitalCompareEdgeFilterMode
Definition: etpwm.h:1661
@ HRPWM_XCMP6_SHADOW2
XCMP6_SHADOW2.
Definition: etpwm.h:2020
@ EPWM_LINK_WITH_EPWM_7
link current ePWM with ePWM7
Definition: etpwm.h:395
@ EPWM_AQ_OUTPUT_NO_CHANGE_UP_CMPB
Time base counter up equals COMPB and no change in the output pins.
Definition: etpwm.h:644
static void EPWM_setDigitalCompareFilterInput(uint32_t base, EPWM_DigitalCompareFilterInput filterInput)
Definition: etpwm.h:6653
@ HRPWM_XCMP1_ACTIVE
XCMP1_ACTIVE.
Definition: etpwm.h:1968
@ EPWM_AQ_OUTPUT_LOW_DOWN_T1
T1 event on count down and set output pins to low.
Definition: etpwm.h:681
#define EPWM_INT_TBCTR_U_CMPB
time-base counter equal to CMPB when the timer is incrementing
Definition: etpwm.h:1206
@ EPWM_DC_EDGEFILT_EDGECNT_5
Digital Compare Edge filter edge count = 6.
Definition: etpwm.h:1689
@ EPWM_FED_LOAD_ON_CNTR_ZERO_PERIOD
load when counter equals zero or period
Definition: etpwm.h:835
@ EPWM_TZ_EVENT_DCXL_HIGH
Event when DCxL high.
Definition: etpwm.h:926
@ EPWM_TZ_ACTION_EVENT_DCAEVT1
DCAEVT1 (Digital Compare A event 1)
Definition: etpwm.h:940
@ EPWM_TZ_EVENT_DCXH_LOW
Event when DCxH low.
Definition: etpwm.h:923
@ EPWM_AQ_OUTPUT_HIGH_UP_CMPA
Time base counter up equals COMPA and set output pins to high.
Definition: etpwm.h:632
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX0_RX_TRIG3
Sync-in source is FSI-RX0 RX Trigger 3 signal.
Definition: etpwm.h:286
static void EPWM_forceInterruptEventCountInit(uint32_t base)
Definition: etpwm.h:5831
static uint16_t EPWM_getDigitalCompareEdgeFilterEdgeCount(uint32_t base)
Definition: etpwm.h:6788
@ EPWM_COMP_LOAD_ON_SYNC_CNTR_ZERO
load when counter equals zero
Definition: etpwm.h:477
@ EPWM_AQ_OUTPUT_HIGH
Set output pins to High.
Definition: etpwm.h:586
@ EPWM_GL_LOAD_PULSE_CNTR_ZERO_PERIOD
load when counter is equal to zero or period
Definition: etpwm.h:1539
@ HRPWM_DB_MEP_CTRL_DISABLE
HRPWM is disabled.
Definition: etpwm.h:1951
@ EPWM_DC_TRIP_TRIPIN9
Trip 9.
Definition: etpwm.h:1330
@ EPWM_XCMP3_ACTIVE
XCMP3_ACTIVE.
Definition: etpwm.h:2082
static void EPWM_enableGlobalLoadOneShotMode(uint32_t base)
Definition: etpwm.h:8012
EPWM_RisingEdgeDelayLoadMode
Definition: etpwm.h:811
@ EPWM_SOC_TBCTR_D_CMPB
time-base counter equal to CMPB when the timer is decrementing
Definition: etpwm.h:1290
EPWM_CycleByCycleTripZoneClearMode
Definition: etpwm.h:1122
#define EPWM_DE_COUNT_UP
Values that can be passed to EPWM_setDiodeEmulationMonitorModeStep()
Definition: etpwm.h:2446
@ EPWM_AQ_SW_SH_LOAD_ON_CNTR_PERIOD
shadow mode load when counter equals period
Definition: etpwm.h:730
@ EPWM_VALLEY_COUNT_START_EDGE
Valley count start edge.
Definition: etpwm.h:1623
EPWM_XCMPActionQualifierOutputEvent
Values that can be passed to EPWM_setXCMPActionQualifierAction() as the event parameter.
Definition: etpwm.h:2169
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT2
Trip source is INPUTXBAR out2 signal.
Definition: etpwm.h:2315
@ EPWM_DE_TRIP_SRC_CMPSSA7
Trip source is CMPSSA7 signal.
Definition: etpwm.h:2389
@ EPWM_LINK_WITH_EPWM_27
link current ePWM with ePWM27
Definition: etpwm.h:415
@ EPWM_DC_EDGEFILT_MODE_FALLING
Digital Compare Edge filter both edges mode.
Definition: etpwm.h:1665
@ EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO_PERIOD
shadow mode load when counter equals zero or period
Definition: etpwm.h:732
@ EPWM_XCMP8_SHADOW2
XCMP8_SHADOW2.
Definition: etpwm.h:2134
static void HRPWM_setHiResPhaseShift(uint32_t base, uint16_t hrPhaseCount)
Definition: etpwm.h:8612
@ EPWM_XCMP3_SHADOW2
XCMP3_SHADOW2.
Definition: etpwm.h:2124
@ EPWM_DC_EVENT_2
Digital Compare Event number 2.
Definition: etpwm.h:1465
@ HRPWM_XCMP2_SHADOW2
XCMP2_SHADOW2.
Definition: etpwm.h:2012
@ EPWM_COUNTER_COMPARE_C
counter compare C
Definition: etpwm.h:456
static void EPWM_disableDigitalCompareCounterCapture(uint32_t base)
Definition: etpwm.h:7341
@ HRPWM_CMPD_SHADOW2
CMPD_SHADOW2.
Definition: etpwm.h:2030
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP6
Sync-in source is ECAP6 sync-out signal.
Definition: etpwm.h:264
static void EPWM_enableTripZoneInterrupt(uint32_t base, uint16_t tzInterrupt)
Definition: etpwm.h:5177
static void EPWM_setLutDecX(uint32_t base, uint32_t block, uint32_t decx, uint32_t force)
Definition: etpwm.h:8541
@ EPWM_LINK_WITH_EPWM_19
link current ePWM with ePWM19
Definition: etpwm.h:407
@ EPWM_AQ_OUTPUT_LOW_PERIOD
Time base counter equals period and set output pins to low.
Definition: etpwm.h:622
EPWM_DiodeEmulationMode
Definition: etpwm.h:2295
@ EPWM_XCMP1_SHADOW3
XCMP1_SHADOW3.
Definition: etpwm.h:2141
@ EPWM_XCMP4_SHADOW1
XCMP4_SHADOW1.
Definition: etpwm.h:2105
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP7
Sync-in source is ECAP7 sync-out signal.
Definition: etpwm.h:266
static void EPWM_setDigitalCompareWindowLength(uint32_t base, uint16_t windowLengthCount)
Definition: etpwm.h:6858
static void EPWM_setDiodeEmulationReentryDelay(uint32_t base, uint8_t delay)
Definition: etpwm.h:10033
static void EPWM_disableRisingEdgeDelayCountShadowLoadMode(uint32_t base)
Definition: etpwm.h:4483
@ HRPWM_CMPC_SHADOW1
CMPC_SHADOW1.
Definition: etpwm.h:2005
@ EPWM_DB_COUNTER_CLOCK_HALF_CYCLE
Dead band counter runs at 2*TBCLK rate.
Definition: etpwm.h:851
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM5
Sync-in source is EPWM5 sync-out signal.
Definition: etpwm.h:198
@ EPWM_DC_TRIP_TRIPIN2
Trip 2.
Definition: etpwm.h:1323
@ EPWM_XCMP_4_CMPB
Allocate XCMP5 - XCMP8 registers to CMPB.
Definition: etpwm.h:2231
static bool EPWM_getCounterCompareShadowStatus(uint32_t base, EPWM_CounterCompareModule compModule)
Definition: etpwm.h:3544
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP3
Time base counter equals XCMP3.
Definition: etpwm.h:2175
static void EPWM_setPeriodLoadMode(uint32_t base, EPWM_PeriodLoadMode loadMode)
Definition: etpwm.h:2802
@ EPWM_AQ_OUTPUT_HIGH_DOWN_T2
T2 event on count down and set output pins to high.
Definition: etpwm.h:699
static void EPWM_setActionQualifierShadowLoadMode(uint32_t base, EPWM_ActionQualifierModule aqModule, EPWM_ActionQualifierLoadMode loadMode)
Definition: etpwm.h:3596
static void EPWM_setActionQualifierContSWForceAction(uint32_t base, EPWM_ActionQualifierOutputModule epwmOutput, EPWM_ActionQualifierSWOutput output)
Definition: etpwm.h:4045
@ HRPWM_XCMP1_SHADOW1
XCMP1_SHADOW1.
Definition: etpwm.h:1987
@ EPWM_SOC_TBCTR_U_CMPB
time-base counter equal to CMPB when the timer is incrementing
Definition: etpwm.h:1286
static void EPWM_selectDiodeEmulationPWMsignal(uint32_t base, uint32_t channel, EPWM_DiodeEmulationSignal signal)
Definition: etpwm.h:10113
@ HRPWM_XCMP1_SHADOW3
XCMP1_SHADOW3.
Definition: etpwm.h:2033
EPWM_FallingEdgeDelayLoadMode
Definition: etpwm.h:829
static void EPWM_disablePhaseShiftLoad(uint32_t base)
Definition: etpwm.h:2856
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB
Time base counter down equals COMPB.
Definition: etpwm.h:565
@ EPWM_DE_LOW
a constant low signal
Definition: etpwm.h:2424
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT0
Trip source is INPUTXBAR out0 signal.
Definition: etpwm.h:2311
static void EPWM_clearOneShotTripZoneFlag(uint32_t base, uint16_t tzOSTFlags)
Definition: etpwm.h:5451
@ EPWM_DB_OUTPUT_B
DB output is ePWMB.
Definition: etpwm.h:746
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT20
Trip source is INPUTXBAR out20 signal.
Definition: etpwm.h:2351
@ EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO
Clear CBC pulse when counter equals zero.
Definition: etpwm.h:1124
@ EPWM_GL_LOAD_PULSE_CNTR_CMPD_U
load when counter is equal to cmpd and cmpd is incrementing
Definition: etpwm.h:1553
static void EPWM_setXCMPShadowLevel(uint32_t base, EPWM_XCMP_XLOADCTL_SHDWLEVEL level)
Definition: etpwm.h:9835
@ HRPWM_COUNTER_COMPARE_A
counter compare A
Definition: etpwm.h:1938
@ EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO
shadow mode load when counter equals zero
Definition: etpwm.h:728
@ EPWM_AQ_OUTPUT_TOGGLE_DOWN_T1
T1 event on count down and toggle the output pins.
Definition: etpwm.h:685
@ EPWM_AQ_LOAD_ON_SYNC_ONLY
load on sync only
Definition: etpwm.h:524
@ HRPWM_XCMP4_SHADOW3
XCMP4_SHADOW3.
Definition: etpwm.h:2039
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM13
Sync-in source is EPWM13 sync-out signal.
Definition: etpwm.h:214
@ EPWM_LINK_COMP_D
link COMPD registers
Definition: etpwm.h:434
@ EPWM_COUNT_MODE_UP_AFTER_SYNC
Count up after sync event.
Definition: etpwm.h:138
@ EPWM_DC_EDGEFILT_EDGECNT_4
Digital Compare Edge filter edge count = 5.
Definition: etpwm.h:1687
static void EPWM_enableValleyCapture(uint32_t base)
Definition: etpwm.h:7541
static void EPWM_setDeadBandDelayMode(uint32_t base, EPWM_DeadBandDelayMode delayMode, bool enableDelayMode)
Definition: etpwm.h:4227
@ EPWM_DE_TRIP_SRC_CMPSSB7
Trip source is CMPSSB7 signal.
Definition: etpwm.h:2409
@ EPWM_AQ_OUTPUT_HIGH_UP_T2
T2 event on count up and set output pins to high.
Definition: etpwm.h:691
@ EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_CMPB
Time base counter down equals COMPB and no change in the output pins.
Definition: etpwm.h:652
static void EPWM_setActionQualifierT2TriggerSource(uint32_t base, EPWM_ActionQualifierTriggerSource trigger)
Definition: etpwm.h:3711
static void EPWM_disableTripZoneSignals(uint32_t base, uint32_t tzSignal)
Definition: etpwm.h:4853
@ EPWM_AQ_OUTPUT_TOGGLE_UP_CMPA
Time base counter up equals COMPA and toggle the output pins.
Definition: etpwm.h:634
static void HRPWM_setXCMPRegValue(uint32_t base, HRPWM_XCMPReg xcmpReg, uint16_t xcmpvalue)
Definition: etpwm.h:9447
@ EPWM_DC_TRIP_TRIPIN8
Trip 8.
Definition: etpwm.h:1329
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM30
Sync-in source is EPWM30 sync-out signal.
Definition: etpwm.h:248
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX3_RX_TRIG2
Sync-in source is FSI-RX3 RX Trigger 2 signal.
Definition: etpwm.h:308
@ EPWM_XCMP8_SHADOW1
XCMP8_SHADOW1.
Definition: etpwm.h:2113
#define EPWM_DB_INPUT_EPWMB
Input signal is ePWMB.
Definition: etpwm.h:782
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP5
Time base counter equals XCMP5.
Definition: etpwm.h:2179
@ EPWM_SOC_TBCTR_U_CMPA
time-base counter equal to CMPA when the timer is incrementing
Definition: etpwm.h:1278
@ EPWM_LINK_WITH_EPWM_26
link current ePWM with ePWM26
Definition: etpwm.h:414
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT1
Trip source is INPUTXBAR out1 signal.
Definition: etpwm.h:2313
@ EPWM_DE_TRIP_SRC_CMPSSA6
Trip source is CMPSSA6 signal.
Definition: etpwm.h:2387
@ EPWM_XCMP_5_CMPA
Allocate XCMP1 - XCMP5 registers to CMPA.
Definition: etpwm.h:2207
static void EPWM_clearCycleByCycleTripZoneFlag(uint32_t base, uint16_t tzCBCFlags)
Definition: etpwm.h:5414
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT24
Trip source is INPUTXBAR out24 signal.
Definition: etpwm.h:2359
@ EPWM_ACTION_QUALIFIER_B
Action Qualifier B.
Definition: etpwm.h:498
@ HRPWM_XCMP8_ACTIVE
XCMP8_ACTIVE.
Definition: etpwm.h:1982
@ EPWM_DC_MODULE_B
Digital Compare Module B.
Definition: etpwm.h:1450
@ EPWM_DB_LOAD_ON_CNTR_PERIOD
load when counter equals period
Definition: etpwm.h:797
@ EPWM_VALLEY_TRIGGER_EVENT_DCAEVT1
Valley capture trigged by DCAEVT1 (Digital Compare A event 1)
Definition: etpwm.h:1606
@ EPWM_PERIOD_DIRECT_LOAD
PWM Period register access is directly.
Definition: etpwm.h:336
#define EPWM_DCxCTL_STEP
Defines to be used by the driver.
Definition: etpwm.h:2468
EPWM_XCMPReg
Definition: etpwm.h:2076
@ EPWM_LINK_DBFED
link DBFED registers
Definition: etpwm.h:437
@ EPWM_AQ_OUTPUT_ON_T1_COUNT_DOWN
T1 event on count down.
Definition: etpwm.h:569
@ HRPWM_MEP_CTRL_RISING_AND_FALLING_EDGE
MEP controls both rising and falling edge.
Definition: etpwm.h:1858
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP1
Sync-in source is ECAP1 sync-out signal.
Definition: etpwm.h:254
#define DebugP_assert(expression)
Function to call for assert check.
Definition: DebugP.h:159
@ HRPWM_CMPD_SHADOW3
CMPD_SHADOW3.
Definition: etpwm.h:2053
EPWM_ActionQualifierModule
Definition: etpwm.h:496
EPWM_ActionQualifierOutputModule
Definition: etpwm.h:714
@ EPWM_LINK_WITH_EPWM_25
link current ePWM with ePWM25
Definition: etpwm.h:413
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT30
Trip source is INPUTXBAR out30 signal.
Definition: etpwm.h:2371
static void EPWM_forceADCTrigger(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
Definition: etpwm.h:6450
@ EPWM_DC_EVENT_INPUT_NOT_SYNCED
DC input signal is not synced with TBCLK.
Definition: etpwm.h:1493
static void EPWM_setDiodeEmulationMonitorModeStep(uint32_t base, uint32_t direction, uint8_t stepsize)
Definition: etpwm.h:10338
@ EPWM_XMINMAX_ACTIVE
XMINMAX_ACTIVE.
Definition: etpwm.h:2096
@ EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_2
Digital compare event B 2.
Definition: etpwm.h:538
@ HRPWM_XCMP2_SHADOW3
XCMP2_SHADOW3.
Definition: etpwm.h:2035
EPWM_DigitalCompareFilterInput
Definition: etpwm.h:1430
static void EPWM_setXCMPLoadMode(uint32_t base, EPWM_XCMPXloadCtlLoadMode mode)
Definition: etpwm.h:9797
@ EPWM_TZ_DC_OUTPUT_B1
Digital Compare output 1 B.
Definition: etpwm.h:910
@ EPWM_AQ_OUTPUT_LOW_UP_CMPA
Time base counter up equals COMPA and set output pins to low.
Definition: etpwm.h:630
@ EPWM_AQ_LOAD_ON_SYNC_CNTR_ZERO_PERIOD
load on sync or when counter equals zero or period
Definition: etpwm.h:522
@ EPWM_LINK_WITH_EPWM_1
link current ePWM with ePWM1
Definition: etpwm.h:389
@ EPWM_VALLEY_TRIGGER_EVENT_DCBEVT2
Valley capture trigged by DCBEVT2 (Digital Compare B event 2)
Definition: etpwm.h:1612
@ EPWM_LINK_WITH_EPWM_4
link current ePWM with ePWM4
Definition: etpwm.h:392
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX2_RX_TRIG0
Sync-in source is FSI-RX2 RX Trigger 0 signal.
Definition: etpwm.h:296
@ EPWM_DB_LOAD_ON_CNTR_ZERO_PERIOD
load when counter equals zero or period
Definition: etpwm.h:799
static void EPWM_disableXLoad(uint32_t base)
Definition: etpwm.h:9773
@ EPWM_AQ_OUTPUT_LOW_UP_T2
T2 event on count up and set output pins to low.
Definition: etpwm.h:689
static uint16_t EPWM_getValleyCount(uint32_t base)
Definition: etpwm.h:7805
@ EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_3
Trip zone 3.
Definition: etpwm.h:541
static void EPWM_disableDigitalCompareEdgeFilter(uint32_t base)
Definition: etpwm.h:6702
@ EPWM_COUNTER_MODE_DOWN
Down - count mode.
Definition: etpwm.h:348
static void HRPWM_enablePhaseShiftLoad(uint32_t base)
Definition: etpwm.h:8951
@ EPWM_DE_TRIP_SRC_CMPSSB9
Trip source is CMPSSB9 signal.
Definition: etpwm.h:2413
@ EPWM_SOC_TBCTR_D_CMPD
time-base counter equal to CMPD when the timer is decrementing
Definition: etpwm.h:1292
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM20
Sync-in source is EPWM20 sync-out signal.
Definition: etpwm.h:228
static void EPWM_enableXCMPMode(uint32_t base)
Definition: etpwm.h:9478
@ EPWM_DIODE_EMULATION_OST
Diode Emulation mode is One Shot.
Definition: etpwm.h:2299
@ HRPWM_CHANNEL_B
HRPWM B.
Definition: etpwm.h:1840
static void EPWM_disableCounterCompareShadowLoadMode(uint32_t base, EPWM_CounterCompareModule compModule)
Definition: etpwm.h:3388
static void HRPWM_enablePeriodControl(uint32_t base)
Definition: etpwm.h:8908
@ EPWM_XCMP4_SHADOW2
XCMP4_SHADOW2.
Definition: etpwm.h:2126
@ EPWM_DE_SYNC_TRIPHorL
synchronized version of TRIPH or TRIPL signal
Definition: etpwm.h:2420
@ EPWM_TZ_ACTION_EVENT_DCBEVT1
DCBEVT1 (Digital Compare B event 1)
Definition: etpwm.h:942
@ EPWM_DC_CBC_LATCH_CLR_ON_CNTR_PERIOD
Clear CBC latch when counter equals period.
Definition: etpwm.h:1521
@ EPWM_GL_LOAD_PULSE_CNTR_ZERO
load when counter is equal to zero
Definition: etpwm.h:1535
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM9
Sync-in source is EPWM9 sync-out signal.
Definition: etpwm.h:206
@ EPWM_DIODE_EMULATION_CBC
Diode Emulation mode is Cycle by Cycle.
Definition: etpwm.h:2297
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT21
Trip source is INPUTXBAR out21 signal.
Definition: etpwm.h:2353
static void EPWM_disableInterrupt(uint32_t base)
Definition: etpwm.h:5589
static void EPWM_disableGlobalLoad(uint32_t base)
Definition: etpwm.h:7869
static void EPWM_setRisingEdgeDeadBandDelayInput(uint32_t base, uint16_t input)
Definition: etpwm.h:4308
#define EPWM_XCMP_SHADOW2
XCMP set = Shadow 3.
Definition: etpwm.h:2065
static void EPWM_selectDigitalCompareCBCLatchClearEvent(uint32_t base, EPWM_DigitalCompareModule dcModule, EPWM_DigitalCompareEvent dcEvent, EPWM_DigitalCompareCBCLatchClearEvent clearEvent)
Definition: etpwm.h:7227
@ HRPWM_COUNTER_COMPARE_B
counter compare B
Definition: etpwm.h:1939
static void HRPWM_setCounterCompareValue(uint32_t base, HRPWM_CounterCompareModule compModule, uint32_t compCount)
Definition: etpwm.h:9078
static void EPWM_setValleyTriggerEdgeCounts(uint32_t base, uint16_t startCount, uint16_t stopCount)
Definition: etpwm.h:7645
@ EPWM_SYNC_IN_PULSE_SRC_INPUTXBAR_OUT4
Sync-in source is Input XBAR out4 signal.
Definition: etpwm.h:272
@ EPWM_XCMP6_SHADOW2
XCMP6_SHADOW2.
Definition: etpwm.h:2130
static void EPWM_disableChopper(uint32_t base)
Definition: etpwm.h:4669
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX2_RX_TRIG3
Sync-in source is FSI-RX2 RX Trigger 3 signal.
Definition: etpwm.h:302
static void EPWM_disableDigitalCompareSyncEvent(uint32_t base, EPWM_DigitalCompareModule dcModule)
Definition: etpwm.h:7129
@ EPWM_LINK_COMP_C
link COMPC registers
Definition: etpwm.h:433
static void EPWM_disableDigitalCompareADCTrigger(uint32_t base, EPWM_DigitalCompareModule dcModule)
Definition: etpwm.h:7067
@ HRPWM_XCMP7_SHADOW1
XCMP7_SHADOW1.
Definition: etpwm.h:1999
@ EPWM_COMP_LOAD_ON_CNTR_PERIOD
load when counter equals period
Definition: etpwm.h:471
@ EPWM_HSCLOCK_DIVIDER_4
Divide clock by 4.
Definition: etpwm.h:169
@ EPWM_XCMP_3_CMPB
Allocate XCMP5 - XCMP7 registers to CMPB.
Definition: etpwm.h:2229
@ HRPWM_DB_MEP_CTRL_FED
MEP controls Falling Edge Delay.
Definition: etpwm.h:1955
static uint16_t EPWM_getCounterCompareValue(uint32_t base, EPWM_CounterCompareModule compModule)
Definition: etpwm.h:3494
static void EPWM_bypassDiodeEmulationLogic(uint32_t base)
Definition: etpwm.h:10216
static void EPWM_startOneShotSync(uint32_t base)
Definition: etpwm.h:2981
@ EPWM_AQ_OUTPUT_LOW_ZERO
Time base counter equals zero and set output pins to low.
Definition: etpwm.h:614
#define EPWM_MINDB_BLOCK_B
Definition: etpwm.h:1722
static void HRPWM_setTranslatorRemainder(uint32_t base, uint16_t trremVal)
Definition: etpwm.h:9043
@ HRPWM_XCMP4_SHADOW2
XCMP4_SHADOW2.
Definition: etpwm.h:2016
@ EPWM_XTBPRD_ACTIVE
XTBPRD_ACTIVE.
Definition: etpwm.h:2094
EPWM_PeriodShadowLoadMode
Definition: etpwm.h:360
#define EPWM_DE_TRIPL
Values that can be passed to EPWM_configureDiodeEmulationTripSources()
Definition: etpwm.h:2457
static void EPWM_enableGlobalLoadRegisters(uint32_t base, uint16_t loadRegister)
Definition: etpwm.h:8092
@ EPWM_AQ_OUTPUT_HIGH_PERIOD
Time base counter equals period and set output pins to high.
Definition: etpwm.h:624
@ EPWM_CLOCK_DIVIDER_128
Divide clock by 128.
Definition: etpwm.h:156
EPWM_CounterCompareLoadMode
Definition: etpwm.h:467
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM6
Sync-in source is EPWM6 sync-out signal.
Definition: etpwm.h:200
@ EPWM_TZ_ACTION_EVENT_TZA
TZ1 - TZ6, DCAEVT2, DCAEVT1.
Definition: etpwm.h:938
static void HRPWM_setRisingEdgeDelayLoadMode(uint32_t base, HRPWM_LoadMode loadEvent)
Definition: etpwm.h:9389
static void EPWM_setDigitalCompareEventSource(uint32_t base, EPWM_DigitalCompareModule dcModule, EPWM_DigitalCompareEvent dcEvent, EPWM_DigitalCompareEventSource dcEventSource)
Definition: etpwm.h:6936
@ HRPWM_XTBPRD_SHADOW3
XTBPRD_SHADOW3.
Definition: etpwm.h:2049
@ EPWM_XCMP6_SHADOW1
XCMP6_SHADOW1.
Definition: etpwm.h:2109
@ EPWM_AQ_LOAD_ON_CNTR_PERIOD
load when counter equals period
Definition: etpwm.h:512
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM7
Sync-in source is EPWM7 sync-out signal.
Definition: etpwm.h:202
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP3
Sync-in source is ECAP3 sync-out signal.
Definition: etpwm.h:258
static void EPWM_disableTripZoneInterrupt(uint32_t base, uint16_t tzInterrupt)
Definition: etpwm.h:5214
@ EPWM_DC_WINDOW_START_TBCTR_BLANK_PULSE_MIX
Time base counter blank pulse mix.
Definition: etpwm.h:1393
EPWM_DeadBandClockMode
Definition: etpwm.h:847
@ EPWM_VALLEY_TRIGGER_EVENT_DCAEVT2
Valley capture trigged by DCAEVT2 (Digital Compare A event 2)
Definition: etpwm.h:1608
EPWM_XCMPXloadCtlLoadMode
Definition: etpwm.h:2241
@ EPWM_XCMP4_ACTIVE
XCMP4_ACTIVE.
Definition: etpwm.h:2084
static void EPWM_forceTripZoneEvent(uint32_t base, uint16_t tzForceEvent)
Definition: etpwm.h:5485
static void EPWM_setInterruptEventCountInitValue(uint32_t base, uint16_t eventCount)
Definition: etpwm.h:5856
@ HRPWM_PWMSYNC_SOURCE_PERIOD
Counter equals Period.
Definition: etpwm.h:1917
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX3_RX_TRIG3
Sync-in source is FSI-RX3 RX Trigger 3 signal.
Definition: etpwm.h:310
static uint16_t HRPWM_getHiResTimeBasePeriod(uint32_t base)
Definition: etpwm.h:8672
@ EPWM_GL_LOAD_PULSE_CNTR_CMPC_D
load when counter is equal to cmpc and cmpc is decrementing
Definition: etpwm.h:1551
#define EPWM_DE_COUNT_DOWN
Definition: etpwm.h:2448
@ EPWM_TZ_ACTION_EVENT_DCAEVT2
DCAEVT2 (Digital Compare A event 2)
Definition: etpwm.h:941
static void EPWM_setInterruptSource(uint32_t base, uint16_t interruptSource, uint16_t mixedSource)
Definition: etpwm.h:5625
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM2
Sync-in source is EPWM2 sync-out signal.
Definition: etpwm.h:192
@ EPWM_DC_TYPE_DCBH
Digital Compare B High.
Definition: etpwm.h:1310
static void EPWM_enableDigitalCompareSyncEvent(uint32_t base, EPWM_DigitalCompareModule dcModule)
Definition: etpwm.h:7098
static void EPWM_clearSyncEvent(uint32_t base)
Definition: etpwm.h:3089
@ EPWM_XCMP_XLOADCTL_SHDWLEVEL_2
SHDW2, SHDW1 and Active registers are available.
Definition: etpwm.h:2262
@ EPWM_EMULATION_FREE_RUN
Free run.
Definition: etpwm.h:126
static bool EPWM_getDigitalCompareCBCLatchStatus(uint32_t base, EPWM_DigitalCompareModule dcModule, EPWM_DigitalCompareEvent dcEvent)
Definition: etpwm.h:7279
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM22
Sync-in source is EPWM22 sync-out signal.
Definition: etpwm.h:232
static void EPWM_setDigitalCompareEdgeFilterEdgeCount(uint32_t base, EPWM_DigitalCompareEdgeFilterEdgeCount edgeCount)
Definition: etpwm.h:6763
@ EPWM_XCMP_XLOADCTL_SHDWLEVEL_1
SHDW1 and Active registers are available.
Definition: etpwm.h:2260
@ EPWM_AQ_LOAD_FREEZE
Freeze shadow to active load.
Definition: etpwm.h:516
@ EPWM_XCMP7_ACTIVE
XCMP7_ACTIVE.
Definition: etpwm.h:2090
@ EPWM_DC_TRIP_TRIPIN5
Trip 5.
Definition: etpwm.h:1326
@ HRPWM_PWMSYNC_SOURCE_COMPC_UP
Counter equals COMPC when counting up.
Definition: etpwm.h:1921
@ EPWM_VALLEY_DELAY_MODE_SW_DELAY
Delay value equals the offset value defines by software.
Definition: etpwm.h:1636
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT10
Trip source is INPUTXBAR out10 signal.
Definition: etpwm.h:2331
@ EPWM_XTBPRD_SHADOW2
XTBPRD_SHADOW2.
Definition: etpwm.h:2136
@ EPWM_XCMP2_SHADOW2
XCMP2_SHADOW2.
Definition: etpwm.h:2122
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT27
Trip source is INPUTXBAR out27 signal.
Definition: etpwm.h:2365
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA
Time base counter up equals COMPA.
Definition: etpwm.h:559
@ EPWM_XCMP7_SHADOW1
XCMP7_SHADOW1.
Definition: etpwm.h:2111
@ EPWM_XCMP5_ACTIVE
XCMP5_ACTIVE.
Definition: etpwm.h:2086
static void EPWM_setTimeBasePeriod(uint32_t base, uint16_t periodCount)
Definition: etpwm.h:3165
@ HRPWM_CHANNEL_A
HRPWM A.
Definition: etpwm.h:1839
@ EPWM_DB_COUNTER_CLOCK_FULL_CYCLE
Dead band counter runs at TBCLK rate.
Definition: etpwm.h:849
@ EPWM_SYNC_IN_PULSE_SRC_INPUTXBAR_OUT20
Sync-in source is Input XBAR out20 signal.
Definition: etpwm.h:274
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM29
Sync-in source is EPWM29 sync-out signal.
Definition: etpwm.h:246
EPWM_XCMP_XLOADCTL_SHDWBUFPTR
Definition: etpwm.h:2275
@ EPWM_DC_WINDOW_SOURCE_DCAEVT2
DC filter signal source is DCAEVT2.
Definition: etpwm.h:1432
@ EPWM_LINK_WITH_EPWM_31
link current ePWM with ePWM31
Definition: etpwm.h:419
static uint32_t HRPWM_getCounterCompareValue(uint32_t base, HRPWM_CounterCompareModule compModule)
Definition: etpwm.h:9124
@ EPWM_DC_TRIP_TRIPIN1
Trip 1.
Definition: etpwm.h:1322
@ EPWM_DB_LOAD_ON_CNTR_ZERO
load when counter equals zero
Definition: etpwm.h:795
@ EPWM_TZ_DC_OUTPUT_A1
Digital Compare output 1 A.
Definition: etpwm.h:908
@ EPWM_AQ_OUTPUT_HIGH_DOWN_CMPB
Time base counter down equals COMPB and set output pins to high.
Definition: etpwm.h:656