eqep/v1/eqep.h

Go to the documentation of this file.

/*
 * Copyright (C) 2021 Texas Instruments Incorporated
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *   Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 *
 *   Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the
 *   distribution.
 *
 *   Neither the name of Texas Instruments Incorporated nor the names of
 *   its contributors may be used to endorse or promote products derived
 *   from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef EQEP_V1_H_
#define EQEP_V1_H_
 
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
 
//*****************************************************************************
//
//
//*****************************************************************************
 
#include <stdbool.h>
#include <stdint.h>
#include <drivers/hw_include/hw_types.h>
#include <drivers/hw_include/cslr_soc.h>
#include <kernel/dpl/DebugP.h>
#include <drivers/hw_include/cslr_eqep.h>
 
//*****************************************************************************
//
// Values that can be passed to EQEP_setDecoderConfig() as the config
// parameter.
//
//*****************************************************************************
 
//
// Operation Mode
//
#define EQEP_CONFIG_QUADRATURE  (0x0000U)
#define EQEP_CONFIG_CLOCK_DIR  (0x4000U)
#define EQEP_CONFIG_UP_COUNT  (0x8000U)
#define EQEP_CONFIG_DOWN_COUNT  (0xC000U)
 
//
// Resolution
//
#define EQEP_CONFIG_2X_RESOLUTION  (0x0000U)
#define EQEP_CONFIG_1X_RESOLUTION  (0x0800U)
 
//
// Swap QEPA and QEPB
//
#define EQEP_CONFIG_NO_SWAP  (0x0000U)
#define EQEP_CONFIG_SWAP  (0x0400U)
 
//*****************************************************************************
 
//
// Values that can be passed to EQEP_setCompareConfig() as the config
// parameter.
//
//*****************************************************************************
 
//
// Sync pulse pin
//
#define EQEP_COMPARE_NO_SYNC_OUT  (0x0000U)
#define EQEP_COMPARE_IDX_SYNC_OUT  (0x2000U)
#define EQEP_COMPARE_STROBE_SYNC_OUT  (0x3000U)
 
//
// Shadow register use
//
#define EQEP_COMPARE_NO_SHADOW  (0x0000U)
#define EQEP_COMPARE_LOAD_ON_ZERO  (0x8000U)
#define EQEP_COMPARE_LOAD_ON_MATCH  (0xC000U)
 
//*****************************************************************************
//
// Values that can be passed to EQEP_enableInterrupt(),
// EQEP_disableInterrupt(), and EQEP_clearInterruptStatus() as the
// intFlags parameter and returned by EQEP_clearInterruptStatus().
//
//*****************************************************************************
#define EQEP_INT_GLOBAL  (0x0001U)  
#define EQEP_INT_POS_CNT_ERROR  (0x0002U)  
#define EQEP_INT_PHASE_ERROR  (0x0004U)  
#define EQEP_INT_DIR_CHANGE  (0x0008U)  
#define EQEP_INT_WATCHDOG  (0x0010U)  
#define EQEP_INT_UNDERFLOW  (0x0020U)  
#define EQEP_INT_OVERFLOW  (0x0040U)  
#define EQEP_INT_POS_COMP_READY  (0x0080U)  
#define EQEP_INT_POS_COMP_MATCH  (0x0100U)  
#define EQEP_INT_STROBE_EVNT_LATCH  (0x0200U)  
#define EQEP_INT_INDEX_EVNT_LATCH  (0x0400U)  
#define EQEP_INT_UNIT_TIME_OUT  (0x0800U)  
#define EQEP_INT_QMA_ERROR  (0x1000U)  
 
//*****************************************************************************
//
// Values that can be returned by EQEP_getStatus().
//
//*****************************************************************************
#define EQEP_STS_UNIT_POS_EVNT  (0x0080U)
#define EQEP_STS_DIR_ON_1ST_IDX  (0x0040U)
#define EQEP_STS_DIR_FLAG  (0x0020U)
#define EQEP_STS_DIR_LATCH  (0x0010U)
#define EQEP_STS_CAP_OVRFLW_ERROR  (0x0008U)
#define EQEP_STS_CAP_DIR_ERROR  (0x0004U)
#define EQEP_STS_1ST_IDX_FLAG  (0x0002U)
#define EQEP_STS_POS_CNT_ERROR  (0x0001U)
 
//*****************************************************************************
//
// Values that can be passed to EQEP_setLatchMode() as the latchMode parameter.
//
//*****************************************************************************
 
//
// Position counter latch event
//
#define EQEP_LATCH_CNT_READ_BY_CPU  (0x0000U) 
#define EQEP_LATCH_UNIT_TIME_OUT  (0x0004U) 
 
//
// Strobe position counter latch event
//
#define EQEP_LATCH_RISING_STROBE  (0x0000U)
#define EQEP_LATCH_EDGE_DIR_STROBE  (0x0040U)
 
//
// Index position counter latch event
//
#define EQEP_LATCH_RISING_INDEX  (0x0010U)  
#define EQEP_LATCH_FALLING_INDEX  (0x0020U)  
#define EQEP_LATCH_SW_INDEX_MARKER  (0x0030U) 
 
//*****************************************************************************
//
// Values that can be passed to EQEP_setPositionInitMode() as the initMode
// parameter.
//
//*****************************************************************************
#define EQEP_INIT_DO_NOTHING  (0x0000U) 
 
//
// Strobe events
//
#define EQEP_INIT_RISING_STROBE  (0x0800U)
#define EQEP_INIT_EDGE_DIR_STROBE  (0x0C00U)
 
//
// Index events
//
#define EQEP_INIT_RISING_INDEX  (0x0200U)  
#define EQEP_INIT_FALLING_INDEX  (0x0300U)  
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EQEP_POSITION_RESET_IDX = 0x0000,
    EQEP_POSITION_RESET_MAX_POS = 0x1000,
    EQEP_POSITION_RESET_1ST_IDX = 0x2000,
    EQEP_POSITION_RESET_UNIT_TIME_OUT = 0x3000
} EQEP_PositionResetMode;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EQEP_CAPTURE_CLK_DIV_1 = 0x00,  
    EQEP_CAPTURE_CLK_DIV_2 = 0x10,  
    EQEP_CAPTURE_CLK_DIV_4 = 0x20,  
    EQEP_CAPTURE_CLK_DIV_8 = 0x30,  
    EQEP_CAPTURE_CLK_DIV_16 = 0x40,  
    EQEP_CAPTURE_CLK_DIV_32 = 0x50,  
    EQEP_CAPTURE_CLK_DIV_64 = 0x60,  
    EQEP_CAPTURE_CLK_DIV_128 = 0x70   
} EQEP_CAPCLKPrescale;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EQEP_UNIT_POS_EVNT_DIV_1 = 0,  
    EQEP_UNIT_POS_EVNT_DIV_2 = 1,  
    EQEP_UNIT_POS_EVNT_DIV_4 = 2,  
    EQEP_UNIT_POS_EVNT_DIV_8 = 3,  
    EQEP_UNIT_POS_EVNT_DIV_16 = 4,  
    EQEP_UNIT_POS_EVNT_DIV_32 = 5,  
    EQEP_UNIT_POS_EVNT_DIV_64 = 6,  
    EQEP_UNIT_POS_EVNT_DIV_128 = 7,  
    EQEP_UNIT_POS_EVNT_DIV_256 = 8,  
    EQEP_UNIT_POS_EVNT_DIV_512 = 9,  
    EQEP_UNIT_POS_EVNT_DIV_1024 = 10,  
    EQEP_UNIT_POS_EVNT_DIV_2048 = 11  
} EQEP_UPEVNTPrescale;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EQEP_STROBE_FROM_GPIO = 0,  
} EQEP_StrobeSource;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EQEP_QMA_MODE_BYPASS = 0,  
    EQEP_QMA_MODE_1 = 1,  
    EQEP_QMA_MODE_2 = 2  
} EQEP_QMAMode;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    EQEP_SOURCE_ZERO = 0x0000U, 
    EQEP_SOURCE_DEVICE_PIN = 0x0001U, 
    EQEP_SOURCE_PWMXBAROUT0 = 0x0002U, 
    EQEP_SOURCE_PWMXBAROUT1 = 0x0003U, 
    EQEP_SOURCE_PWMXBAROUT2 = 0x0004U, 
    EQEP_SOURCE_PWMXBAROUT3 = 0x0005U, 
    EQEP_SOURCE_PWMXBAROUT4 = 0x0006U, 
    EQEP_SOURCE_PWMXBAROUT5 = 0x0007U, 
    EQEP_SOURCE_PWMXBAROUT6 = 0x0008U, 
    EQEP_SOURCE_PWMXBAROUT7 = 0x0009U, 
    EQEP_SOURCE_PWMXBAROUT8 = 0x000AU, 
    EQEP_SOURCE_PWMXBAROUT9 = 0x000BU, 
    EQEP_SOURCE_PWMXBAROUT10 = 0x000CU, 
    EQEP_SOURCE_PWMXBAROUT11 = 0x000DU, 
    EQEP_SOURCE_PWMXBAROUT12 = 0x000EU, 
    EQEP_SOURCE_PWMXBAROUT13 = 0x000FU, 
    EQEP_SOURCE_PWMXBAROUT14 = 0x0010U, 
    EQEP_SOURCE_PWMXBAROUT15 = 0x0011U, 
    EQEP_SOURCE_PWMXBAROUT16 = 0x0012U, 
    EQEP_SOURCE_PWMXBAROUT17 = 0x0013U, 
    EQEP_SOURCE_PWMXBAROUT18 = 0x0014U, 
    EQEP_SOURCE_PWMXBAROUT19 = 0x0015U, 
    EQEP_SOURCE_PWMXBAROUT20 = 0x0016U, 
    EQEP_SOURCE_PWMXBAROUT21 = 0x0017U, 
    EQEP_SOURCE_PWMXBAROUT22 = 0x0018U, 
    EQEP_SOURCE_PWMXBAROUT23 = 0x0019U, 
    EQEP_SOURCE_PWMXBAROUT24 = 0x001AU, 
    EQEP_SOURCE_PWMXBAROUT25 = 0x001BU, 
    EQEP_SOURCE_PWMXBAROUT26 = 0x001CU, 
    EQEP_SOURCE_PWMXBAROUT27 = 0x001DU, 
    EQEP_SOURCE_PWMXBAROUT28 = 0x001EU, 
    EQEP_SOURCE_PWMXBAROUT29 = 0x001FU 
} EQEP_Source;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef struct {
    EQEP_Source sourceA;
    EQEP_Source sourceB;
    EQEP_Source sourceIndex;
}EQEP_SourceSelect;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
  EQEP_EMULATIONMODE_STOPIMMEDIATELY = 0,  
  EQEP_EMULATIONMODE_STOPATROLLOVER = 1,  
  EQEP_EMULATIONMODE_RUNFREE = 2  
}EQEP_EmulationMode;
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EQEP_enableModule(uint32_t base)
{
    //
    // Enable the eQEP module.
    //
    HW_WR_REG16(base + CSL_EQEP_QEPCTL,
        (HW_RD_REG16(base + CSL_EQEP_QEPCTL) | CSL_EQEP_QEPCTL_QPEN_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EQEP_disableModule(uint32_t base)
{
    //
    // Disable the eQEP module.
    //
    HW_WR_REG16(base + CSL_EQEP_QEPCTL,
        (HW_RD_REG16(base + CSL_EQEP_QEPCTL) & ~CSL_EQEP_QEPCTL_QPEN_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EQEP_setDecoderConfig(uint32_t base, uint16_t config)
{
    //
    // Write the new decoder configuration to the hardware.
    //
    HW_WR_REG16(base + CSL_EQEP_QDECCTL,
        ((HW_RD_REG16(base + CSL_EQEP_QDECCTL) & ~(CSL_EQEP_QDECCTL_SWAP_MASK |
        CSL_EQEP_QDECCTL_XCR_MASK | CSL_EQEP_QDECCTL_QSRC_MASK)) | config));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EQEP_setPositionCounterConfig(uint32_t base, EQEP_PositionResetMode mode,
                              uint32_t maxPosition)
{
    //
    // Write the position counter reset configuration to the hardware.
    //
    HW_WR_REG16(base + CSL_EQEP_QEPCTL,
        ((HW_RD_REG16(base + CSL_EQEP_QEPCTL) & ~CSL_EQEP_QEPCTL_PCRM_MASK) |
        (uint16_t)mode));
 
    //
    // Set the maximum position.
    //
    HW_WR_REG32(base + CSL_EQEP_QPOSMAX, maxPosition);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline uint32_t
EQEP_getPosition(uint32_t base)
{
    //
    // Return the current position counter.
    //
    return(HW_RD_REG32(base + CSL_EQEP_QPOSCNT));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EQEP_setPosition(uint32_t base, uint32_t position)
{
    //
    // Set the position counter.
    //
    HW_WR_REG32(base + CSL_EQEP_QPOSCNT, position);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline int16_t
EQEP_getDirection(uint32_t base)
{
    int16_t direction;
 
    //
    // Return the direction of rotation.
    //
    if((HW_RD_REG16(base + CSL_EQEP_QEPSTS) & CSL_EQEP_QEPSTS_QDF_MASK) != 0U)
    {
        direction = 1;
    }
    else
    {
        direction = -1;
    }
 
    return(direction);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EQEP_enableInterrupt(uint32_t base, uint16_t intFlags)
{
    //
    // Enable the specified interrupts.
    //.
    HW_WR_REG16(base + CSL_EQEP_QEINT,
        (HW_RD_REG16(base + CSL_EQEP_QEINT) | intFlags));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EQEP_disableInterrupt(uint32_t base, uint16_t intFlags)
{
    //
    // Disable the specified interrupts.
    //
    HW_WR_REG16(base + CSL_EQEP_QEINT,
        (HW_RD_REG16(base + CSL_EQEP_QEINT) & ~intFlags));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline uint16_t
EQEP_getInterruptStatus(uint32_t base)
{
    //
    // Return Interrupt Status
    //
    return(HW_RD_REG16(base + CSL_EQEP_QFLG));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EQEP_clearInterruptStatus(uint32_t base, uint16_t intFlags)
{
    //
    // Clear the requested interrupt sources.
    //
    HW_WR_REG16(base + CSL_EQEP_QCLR, intFlags);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EQEP_forceInterrupt(uint32_t base, uint16_t intFlags)
{
    //
    // Force the specified interrupts.
    //
    HW_WR_REG16(base + CSL_EQEP_QFRC,
        (HW_RD_REG16(base + CSL_EQEP_QFRC) | intFlags));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline bool
EQEP_getError(uint32_t base)
{
    //
    // Return the error indicator.
    //
    return((HW_RD_REG16(base + CSL_EQEP_QFLG) & CSL_EQEP_QFLG_PHE_MASK) != 0U);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline uint16_t
EQEP_getStatus(uint32_t base)
{
    //
    // Return the status register.
    //
    return(HW_RD_REG16(base + CSL_EQEP_QEPSTS) & 0x00FFU);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EQEP_clearStatus(uint32_t base, uint16_t statusFlags)
{
    //
    // Clear the requested interrupt sources.
    //
    HW_WR_REG16(base + CSL_EQEP_QEPSTS, statusFlags);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EQEP_setCaptureConfig(uint32_t base, EQEP_CAPCLKPrescale capPrescale,
                      EQEP_UPEVNTPrescale evntPrescale)
{
    //
    // Write new prescaler configurations to the appropriate registers.
    //
    HW_WR_REG16(base + CSL_EQEP_QCAPCTL,
        ((HW_RD_REG16(base + CSL_EQEP_QCAPCTL) & ~(CSL_EQEP_QCAPCTL_UPPS_MASK |
        CSL_EQEP_QCAPCTL_CCPS_MASK)) | ((uint16_t)evntPrescale |
        (uint16_t)capPrescale)));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EQEP_enableCapture(uint32_t base)
{
    //
    // Enable edge capture.
    //
    HW_WR_REG16(base + CSL_EQEP_QCAPCTL,
        (HW_RD_REG16(base + CSL_EQEP_QCAPCTL) | CSL_EQEP_QCAPCTL_CEN_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EQEP_disableCapture(uint32_t base)
{
    //
    // Disable edge capture.
    //
    HW_WR_REG16(base + CSL_EQEP_QCAPCTL,
        (HW_RD_REG16(base + CSL_EQEP_QCAPCTL) & ~CSL_EQEP_QCAPCTL_CEN_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline uint16_t
EQEP_getCapturePeriod(uint32_t base)
{
    //
    // Return the capture period.
    //
    return(HW_RD_REG16(base + CSL_EQEP_QCPRD));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline uint16_t
EQEP_getCaptureTimer(uint32_t base)
{
    //
    // Return the capture timer value.
    //
    return(HW_RD_REG16(base + CSL_EQEP_QCTMR));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EQEP_enableCompare(uint32_t base)
{
    //
    // Enable position compare.
    //
    HW_WR_REG16(base + CSL_EQEP_QPOSCTL,
        (HW_RD_REG16(base + CSL_EQEP_QPOSCTL) | CSL_EQEP_QPOSCTL_PCE_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EQEP_disableCompare(uint32_t base)
{
    //
    // Disable position compare.
    //
    HW_WR_REG16(base + CSL_EQEP_QPOSCTL,
        (HW_RD_REG16(base + CSL_EQEP_QPOSCTL) & ~CSL_EQEP_QPOSCTL_PCE_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EQEP_setComparePulseWidth(uint32_t base, uint16_t cycles)
{
    //
    // Check the arguments.
    //
    DebugP_assert(cycles <= (CSL_EQEP_QPOSCTL_PCSPW_MASK + 1U));
 
    //
    // Set the pulse width.
    //
    HW_WR_REG16(base + CSL_EQEP_QPOSCTL,
        ((HW_RD_REG16(base + CSL_EQEP_QPOSCTL) &
        ~(uint16_t)CSL_EQEP_QPOSCTL_PCSPW_MASK) | (cycles - 1U)));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EQEP_loadUnitTimer(uint32_t base, uint32_t period)
{
    //
    // Set the period of the unit timer.
    //
    HW_WR_REG32(base + CSL_EQEP_QUPRD, period);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EQEP_enableUnitTimer(uint32_t base, uint32_t period)
{
    //
    // Set the period of the unit timer.
    //
    HW_WR_REG32(base + CSL_EQEP_QUPRD, period);
 
    //
    // Enable peripheral unit timer.
    //
    HW_WR_REG16(base + CSL_EQEP_QEPCTL,
        (HW_RD_REG16(base + CSL_EQEP_QEPCTL) | CSL_EQEP_QEPCTL_UTE_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EQEP_disableUnitTimer(uint32_t base)
{
    //
    // Disable peripheral unit timer.
    //
    HW_WR_REG16(base + CSL_EQEP_QEPCTL,
        (HW_RD_REG16(base + CSL_EQEP_QEPCTL) & ~CSL_EQEP_QEPCTL_UTE_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EQEP_enableWatchdog(uint32_t base, uint16_t period)
{
    //
    // Set the timeout count for the eQEP peripheral watchdog timer.
    //
    HW_WR_REG16(base + CSL_EQEP_QWDPRD, period);
 
    //
    // Enable peripheral watchdog.
    //
    HW_WR_REG16(base + CSL_EQEP_QEPCTL,
        (HW_RD_REG16(base + CSL_EQEP_QEPCTL) | CSL_EQEP_QEPCTL_WDE_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EQEP_disableWatchdog(uint32_t base)
{
    //
    // Disable peripheral watchdog.
    //
    HW_WR_REG16(base + CSL_EQEP_QEPCTL,
        (HW_RD_REG16(base + CSL_EQEP_QEPCTL) & ~CSL_EQEP_QEPCTL_WDE_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EQEP_setWatchdogTimerValue(uint32_t base, uint16_t value)
{
    //
    // Write the value to the watchdog timer register.
    //
    HW_WR_REG16(base + CSL_EQEP_QWDTMR, value);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline uint16_t
EQEP_getWatchdogTimerValue(uint32_t base)
{
    //
    // Read the value from the watchdog timer register.
    //
    return(HW_RD_REG16(base + CSL_EQEP_QWDTMR));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EQEP_setPositionInitMode(uint32_t base, uint16_t initMode)
{
    //
    // Set the init mode in the QEP Control register.
    //
    HW_WR_REG16(base + CSL_EQEP_QEPCTL,
        ((HW_RD_REG16(base + CSL_EQEP_QEPCTL) & ~(CSL_EQEP_QEPCTL_IEI_MASK |
        CSL_EQEP_QEPCTL_SEI_MASK)) | initMode));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EQEP_setSWPositionInit(uint32_t base, bool initialize)
{
    //
    // Set or clear the software initialization bit.
    //
    if(initialize)
    {
        HW_WR_REG16(base + CSL_EQEP_QEPCTL,
            (HW_RD_REG16(base + CSL_EQEP_QEPCTL) | CSL_EQEP_QEPCTL_SWI_MASK));
    }
    else
    {
        HW_WR_REG16(base + CSL_EQEP_QEPCTL,
            (HW_RD_REG16(base + CSL_EQEP_QEPCTL) & ~CSL_EQEP_QEPCTL_SWI_MASK));
    }
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EQEP_setInitialPosition(uint32_t base, uint32_t position)
{
    //
    // Write position to position counter init register
    //
    HW_WR_REG32(base + CSL_EQEP_QPOSINIT, position);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EQEP_setLatchMode(uint32_t base, uint32_t latchMode)
{
    //
    // Set the latch mode in the QEP Control register.
    //
    HW_WR_REG16(base + CSL_EQEP_QEPCTL,
    ((HW_RD_REG16(base + CSL_EQEP_QEPCTL) & ~(CSL_EQEP_QEPCTL_QCLM_MASK |
    CSL_EQEP_QEPCTL_IEL_MASK | CSL_EQEP_QEPCTL_SEL_MASK)) | latchMode));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline uint32_t
EQEP_getIndexPositionLatch(uint32_t base)
{
    //
    // Return the current position counter.
    //
    return(HW_RD_REG32(base + CSL_EQEP_QPOSILAT));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline uint32_t
EQEP_getStrobePositionLatch(uint32_t base)
{
    //
    // Return the current position counter.
    //
    return(HW_RD_REG32(base + CSL_EQEP_QPOSSLAT));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline uint32_t
EQEP_getPositionLatch(uint32_t base)
{
    //
    // Return the current position counter.
    //
    return(HW_RD_REG32(base + CSL_EQEP_QPOSLAT));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline uint16_t
EQEP_getCaptureTimerLatch(uint32_t base)
{
    //
    // Return the current position counter.
    //
    return(HW_RD_REG16(base + CSL_EQEP_QCTMRLAT));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline uint16_t
EQEP_getCapturePeriodLatch(uint32_t base)
{
    //
    // Return the current position counter.
    //
    return(HW_RD_REG16(base + CSL_EQEP_QCPRDLAT));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EQEP_setQMAModuleMode(uint32_t base, EQEP_QMAMode qmaMode)
{
    //
    // Write the QMA module mode into the appropriate register.
    //
    HW_WR_REG16(base + CSL_EQEP_QMACTRL,
        ((HW_RD_REG16(base + CSL_EQEP_QMACTRL) & ~CSL_EQEP_QMACTRL_MODE_MASK) |
        (uint16_t)qmaMode));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EQEP_setStrobeSource(uint32_t base, EQEP_StrobeSource strobeSrc)
{
    //
    // Write the strobe source selection into the appropriate register.
    //
    HW_WR_REG16(base + CSL_EQEP_QEPSTROBESEL,
        ((HW_RD_REG16(base + CSL_EQEP_QEPSTROBESEL) &
        ~CSL_EQEP_QEPSTROBESEL_STROBESEL_MASK) | (uint16_t)strobeSrc));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EQEP_enableDirectionChangeDuringIndex(uint32_t base)
{
    //
    //Sets the index direction enhancement bit
    //
    HW_WR_REG16(base + CSL_EQEP_QDECCTL,
        (HW_RD_REG16(base + CSL_EQEP_QDECCTL) | CSL_EQEP_QDECCTL_QIDIRE_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EQEP_disableDirectionChangeDuringIndex(uint32_t base)
{
    //
    //Clears the index direction enhancement bit
    //
    HW_WR_REG16(base + CSL_EQEP_QDECCTL,
        (HW_RD_REG16(base + CSL_EQEP_QDECCTL) & ~CSL_EQEP_QDECCTL_QIDIRE_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EQEP_selectSource(uint32_t base, EQEP_SourceSelect sourceConfig )
{
    //
    // Selecting sources for eQEP signals
    //
    HW_WR_REG32(base + CSL_EQEP_QEPSRCSEL,
        ((HW_RD_REG32(base + CSL_EQEP_QEPSRCSEL) &
        ~(CSL_EQEP_QEPSRCSEL_QEPASEL_MASK | CSL_EQEP_QEPSRCSEL_QEPBSEL_MASK |
        CSL_EQEP_QEPSRCSEL_QEPISEL_MASK)) |
        ((uint32_t)((uint32_t)(sourceConfig.sourceA) <<
        CSL_EQEP_QEPSRCSEL_QEPASEL_SHIFT) |
        (uint32_t)((uint32_t)(sourceConfig.sourceB) <<
        CSL_EQEP_QEPSRCSEL_QEPBSEL_SHIFT) |
        (uint32_t)((uint32_t)(sourceConfig.sourceIndex) <<
        CSL_EQEP_QEPSRCSEL_QEPISEL_SHIFT))));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
EQEP_setEmulationMode(uint32_t base, EQEP_EmulationMode emuMode)
{
    //
    // Write the emulation mode to the FREE_SOFT bits.
    //
    HW_WR_REG16(base + CSL_EQEP_QEPCTL,
        ((HW_RD_REG16(base + CSL_EQEP_QEPCTL) &
        ~CSL_EQEP_QEPSRCSEL_QEPISEL_SHIFT) |
        ((uint16_t)emuMode << CSL_EQEP_QEPCTL_FREE_SOFT_SHIFT)));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
extern void
EQEP_setCompareConfig(uint32_t base, uint16_t config, uint32_t compareValue,
                      uint16_t cycles);
 
//*****************************************************************************
//
//
//*****************************************************************************
extern void
EQEP_setInputPolarity(uint32_t base, bool invertQEPA, bool invertQEPB,
                      bool invertIndex, bool invertStrobe);
 
//*****************************************************************************
//
// Close the Doxygen group.
//
//*****************************************************************************
 
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
 
#endif // EQEP_V1_H_