ecap/v1/ecap.h

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/*
 * Copyright (C) 2021 Texas Instruments Incorporated
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *   Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 *
 *   Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the
 *   distribution.
 *
 *   Neither the name of Texas Instruments Incorporated nor the names of
 *   its contributors may be used to endorse or promote products derived
 *   from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef ECAP_V1_H_
#define ECAP_V1_H_
 
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
 
//*****************************************************************************
//
//
//*****************************************************************************
#include <stdint.h>
#include <stdbool.h>
#include <drivers/hw_include/hw_types.h>
#include <drivers/hw_include/cslr_soc.h>
#include <kernel/dpl/DebugP.h>
#include <drivers/hw_include/cslr_ecap.h>
 
//*****************************************************************************
//
// eCAP minimum and maximum values
//
//*****************************************************************************
#define ECAP_MAX_PRESCALER_VALUE    (32U)  // Maximum Pre-scaler value
 
//*****************************************************************************
//
// Values that can be passed to ECAP_enableInterrupt(),
// ECAP_disableInterrupt(), ECAP_clearInterrupt() and ECAP_forceInterrupt() as
// the intFlags parameter and returned by ECAP_getInterruptSource().
//
//*****************************************************************************
#define ECAP_ISR_SOURCE_CAPTURE_EVENT_1    (0x2U)
#define ECAP_ISR_SOURCE_CAPTURE_EVENT_2    (0x4U)
#define ECAP_ISR_SOURCE_CAPTURE_EVENT_3    (0x8U)
#define ECAP_ISR_SOURCE_CAPTURE_EVENT_4    (0x10U)
#define ECAP_ISR_SOURCE_COUNTER_OVERFLOW    (0x20U)
#define ECAP_ISR_SOURCE_COUNTER_PERIOD    (0x40U)
#define ECAP_ISR_SOURCE_COUNTER_COMPARE    (0x80U)
#define ECAP_ISR_SOURCE_HR_ERROR    (0x100U)
#define ECAP_ISR_SOURCE_ALL    (ECAP_ISR_SOURCE_CAPTURE_EVENT_1  |\
                                ECAP_ISR_SOURCE_CAPTURE_EVENT_2  |\
                                ECAP_ISR_SOURCE_CAPTURE_EVENT_3  |\
                                ECAP_ISR_SOURCE_CAPTURE_EVENT_4  |\
                                ECAP_ISR_SOURCE_COUNTER_OVERFLOW |\
                                ECAP_ISR_SOURCE_COUNTER_PERIOD   |\
                                ECAP_ISR_SOURCE_COUNTER_COMPARE  |\
                                ECAP_ISR_SOURCE_HR_ERROR)
 
//*****************************************************************************
//
// Values that can be passed to HRCAP_enableCalibrationInterrupt(),
// HRCAP_disableCalibrationInterrupt() as the intFlags parameter and
// HRCAP_clearCalibrationFlags() and HRCAP_forceCalibrationFlags() as the flags
// parameter and returned by HRCAP_getCalibrationFlags().
//
//*****************************************************************************
#define HRCAP_GLOBAL_CALIBRATION_INTERRUPT    (0x1U)
#define HRCAP_CALIBRATION_DONE    (0x2U)
#define HRCAP_CALIBRATION_PERIOD_OVERFLOW    (0x4U)
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    ECAP_EMULATION_STOP = 0x0U,
    ECAP_EMULATION_RUN_TO_ZERO = 0x1U,
    ECAP_EMULATION_FREE_RUN = 0x2U
}ECAP_EmulationMode;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    ECAP_CONTINUOUS_CAPTURE_MODE = 0U,
    ECAP_ONE_SHOT_CAPTURE_MODE = 1U
}ECAP_CaptureMode;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    ECAP_EVENT_1 = 0U,   
    ECAP_EVENT_2 = 1U,   
    ECAP_EVENT_3 = 2U,   
    ECAP_EVENT_4 = 3U    
}ECAP_Events;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    ECAP_SYNC_OUT_SYNCI = 0x00,
    ECAP_SYNC_OUT_COUNTER_PRD = 0x40,
    ECAP_SYNC_OUT_DISABLED = 0x80
}ECAP_SyncOutMode;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    ECAP_APWM_ACTIVE_HIGH = 0x000, 
    ECAP_APWM_ACTIVE_LOW = 0x400  
}ECAP_APWMPolarity;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    ECAP_EVNT_RISING_EDGE = 0U, 
    ECAP_EVNT_FALLING_EDGE = 1U  
}ECAP_EventPolarity;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    ECAP_INPUT_FSI_RX0_TRIG_0 = 0,
    ECAP_INPUT_FSI_RX0_TRIG_1 = 1,
    ECAP_INPUT_FSI_RX0_TRIG_2 = 2,
    ECAP_INPUT_FSI_RX0_TRIG_3 = 3,
    ECAP_INPUT_FSI_RX1_TRIG_0 = 4,
    ECAP_INPUT_FSI_RX1_TRIG_1 = 5,
    ECAP_INPUT_FSI_RX1_TRIG_2 = 6,
    ECAP_INPUT_FSI_RX1_TRIG_3 = 7,
    ECAP_INPUT_FSI_RX2_TRIG_0 = 8,
    ECAP_INPUT_FSI_RX2_TRIG_1 = 9,
    ECAP_INPUT_FSI_RX2_TRIG_2 = 10,
    ECAP_INPUT_FSI_RX2_TRIG_3 = 11,
    ECAP_INPUT_FSI_RX3_TRIG_0 = 12,
    ECAP_INPUT_FSI_RX3_TRIG_1 = 13,
    ECAP_INPUT_FSI_RX3_TRIG_2 = 14,
    ECAP_INPUT_FSI_RX3_TRIG_3 = 15,
    ECAP_INPUT_EQEP0_QI = 16,
    ECAP_INPUT_EQEP0_QS = 17,
    ECAP_INPUT_EQEP1_QI = 18,
    ECAP_INPUT_EQEP1_QS = 19,
    ECAP_INPUT_EQEP2_QI = 20,
    ECAP_INPUT_EQEP2_QS = 21,
    ECAP_INPUT_EPWM0_SOCA = 54,
    ECAP_INPUT_EPWM1_SOCA = 55,
    ECAP_INPUT_EPWM2_SOCA = 56,
    ECAP_INPUT_EPWM3_SOCA = 57,
    ECAP_INPUT_EPWM4_SOCA = 58,
    ECAP_INPUT_EPWM5_SOCA = 59,
    ECAP_INPUT_EPWM6_SOCA = 60,
    ECAP_INPUT_EPWM7_SOCA = 61,
    ECAP_INPUT_EPWM8_SOCA = 62,
    ECAP_INPUT_EPWM9_SOCA = 63,
    ECAP_INPUT_EPWM10_SOCA = 64,
    ECAP_INPUT_EPWM11_SOCA = 65,
    ECAP_INPUT_EPWM12_SOCA = 66,
    ECAP_INPUT_EPWM13_SOCA = 67,
    ECAP_INPUT_EPWM14_SOCA = 68,
    ECAP_INPUT_EPWM15_SOCA = 69,
    ECAP_INPUT_EPWM16_SOCA = 70,
    ECAP_INPUT_EPWM17_SOCA = 71,
    ECAP_INPUT_EPWM18_SOCA = 72,
    ECAP_INPUT_EPWM19_SOCA = 73,
    ECAP_INPUT_EPWM20_SOCA = 74,
    ECAP_INPUT_EPWM21_SOCA = 75,
    ECAP_INPUT_EPWM22_SOCA = 76,
    ECAP_INPUT_EPWM23_SOCA = 77,
    ECAP_INPUT_EPWM24_SOCA = 78,
    ECAP_INPUT_EPWM25_SOCA = 79,
    ECAP_INPUT_EPWM26_SOCA = 80,
    ECAP_INPUT_EPWM27_SOCA = 81,
    ECAP_INPUT_EPWM28_SOCA = 82,
    ECAP_INPUT_EPWM29_SOCA = 83,
    ECAP_INPUT_EPWM30_SOCA = 84,
    ECAP_INPUT_EPWM31_SOCA = 85,
    ECAP_INPUT_EPWM0_SOCB = 86,
    ECAP_INPUT_EPWM1_SOCB = 87,
    ECAP_INPUT_EPWM2_SOCB = 88,
    ECAP_INPUT_EPWM3_SOCB = 89,
    ECAP_INPUT_EPWM4_SOCB = 90,
    ECAP_INPUT_EPWM5_SOCB = 91,
    ECAP_INPUT_EPWM6_SOCB = 92,
    ECAP_INPUT_EPWM7_SOCB = 93,
    ECAP_INPUT_EPWM8_SOCB = 94,
    ECAP_INPUT_EPWM9_SOCB = 95,
    ECAP_INPUT_EPWM10_SOCB = 96,
    ECAP_INPUT_EPWM11_SOCB = 97,
    ECAP_INPUT_EPWM12_SOCB = 98,
    ECAP_INPUT_EPWM13_SOCB = 99,
    ECAP_INPUT_EPWM14_SOCB = 100,
    ECAP_INPUT_EPWM15_SOCB = 101,
    ECAP_INPUT_EPWM16_SOCB = 102,
    ECAP_INPUT_EPWM17_SOCB = 103,
    ECAP_INPUT_EPWM18_SOCB = 104,
    ECAP_INPUT_EPWM19_SOCB = 105,
    ECAP_INPUT_EPWM20_SOCB = 106,
    ECAP_INPUT_EPWM21_SOCB = 107,
    ECAP_INPUT_EPWM22_SOCB = 108,
    ECAP_INPUT_EPWM23_SOCB = 109,
    ECAP_INPUT_EPWM24_SOCB = 110,
    ECAP_INPUT_EPWM25_SOCB = 111,
    ECAP_INPUT_EPWM26_SOCB = 112,
    ECAP_INPUT_EPWM27_SOCB = 113,
    ECAP_INPUT_EPWM28_SOCB = 114,
    ECAP_INPUT_EPWM29_SOCB = 115,
    ECAP_INPUT_EPWM30_SOCB = 116,
    ECAP_INPUT_EPWM31_SOCB = 117,
    ECAP_INPUT_SDFM0_COMPARE1_HIGH = 118,
    ECAP_INPUT_SDFM0_COMPARE1_LOW = 119,
    ECAP_INPUT_SDFM0_COMPARE_Z1 = 120,
    ECAP_INPUT_SDFM0_COMPARE2_HIGH = 121,
    ECAP_INPUT_SDFM0_COMPARE2_LOW = 122,
    ECAP_INPUT_SDFM0_COMPARE_Z2 = 123,
    ECAP_INPUT_SDFM0_COMPARE3_HIGH = 124,
    ECAP_INPUT_SDFM0_COMPARE3_LOW = 125,
    ECAP_INPUT_SDFM0_COMPARE_Z3 = 126,
    ECAP_INPUT_SDFM0_COMPARE4_HIGH = 127,
    ECAP_INPUT_SDFM0_COMPARE4_LOW = 128,
    ECAP_INPUT_SDFM0_COMPARE_Z4 = 129,
    ECAP_INPUT_SDFM1_COMPARE1_HIGH = 130,
    ECAP_INPUT_SDFM1_COMPARE1_LOW = 131,
    ECAP_INPUT_SDFM1_COMPARE_Z1 = 132,
    ECAP_INPUT_SDFM1_COMPARE2_HIGH = 133,
    ECAP_INPUT_SDFM1_COMPARE2_LOW = 134,
    ECAP_INPUT_SDFM1_COMPARE_Z2 = 135,
    ECAP_INPUT_SDFM1_COMPARE3_HIGH = 136,
    ECAP_INPUT_SDFM1_COMPARE3_LOW = 137,
    ECAP_INPUT_SDFM1_COMPARE_Z3 = 138,
    ECAP_INPUT_SDFM1_COMPARE4_HIGH = 139,
    ECAP_INPUT_SDFM1_COMPARE4_LOW = 140,
    ECAP_INPUT_SDFM1_COMPARE_Z4 = 141,
    ECAP_INPUT_CMPSSA0_CTRIP_LOW = 142,
    ECAP_INPUT_CMPSSA0_CTRIP_HIGH = 143,
    ECAP_INPUT_CMPSSA1_CTRIP_LOW = 144,
    ECAP_INPUT_CMPSSA1_CTRIP_HIGH = 145,
    ECAP_INPUT_CMPSSA2_CTRIP_LOW = 146,
    ECAP_INPUT_CMPSSA2_CTRIP_HIGH = 147,
    ECAP_INPUT_CMPSSA3_CTRIP_LOW = 148,
    ECAP_INPUT_CMPSSA3_CTRIP_HIGH = 149,
    ECAP_INPUT_CMPSSA4_CTRIP_LOW = 150,
    ECAP_INPUT_CMPSSA4_CTRIP_HIGH = 151,
    ECAP_INPUT_CMPSSA5_CTRIP_LOW = 152,
    ECAP_INPUT_CMPSSA5_CTRIP_HIGH = 153,
    ECAP_INPUT_CMPSSA6_CTRIP_LOW = 154,
    ECAP_INPUT_CMPSSA6_CTRIP_HIGH = 155,
    ECAP_INPUT_CMPSSA7_CTRIP_LOW = 156,
    ECAP_INPUT_CMPSSA7_CTRIP_HIGH = 157,
    ECAP_INPUT_CMPSSA8_CTRIP_LOW = 158,
    ECAP_INPUT_CMPSSA8_CTRIP_HIGH = 159,
    ECAP_INPUT_CMPSSA9_CTRIP_LOW = 160,
    ECAP_INPUT_CMPSSA9_CTRIP_HIGH = 161,
    ECAP_INPUT_CMPSSB0_CTRIP_LOW = 162,
    ECAP_INPUT_CMPSSB0_CTRIP_HIGH = 163,
    ECAP_INPUT_CMPSSB1_CTRIP_LOW = 164,
    ECAP_INPUT_CMPSSB1_CTRIP_HIGH = 165,
    ECAP_INPUT_CMPSSB2_CTRIP_LOW = 166,
    ECAP_INPUT_CMPSSB2_CTRIP_HIGH = 167,
    ECAP_INPUT_CMPSSB3_CTRIP_LOW = 168,
    ECAP_INPUT_CMPSSB3_CTRIP_HIGH = 169,
    ECAP_INPUT_CMPSSB4_CTRIP_LOW = 170,
    ECAP_INPUT_CMPSSB4_CTRIP_HIGH = 171,
    ECAP_INPUT_CMPSSB5_CTRIP_LOW = 172,
    ECAP_INPUT_CMPSSB5_CTRIP_HIGH = 173,
    ECAP_INPUT_CMPSSB6_CTRIP_LOW = 174,
    ECAP_INPUT_CMPSSB6_CTRIP_HIGH = 175,
    ECAP_INPUT_CMPSSB7_CTRIP_LOW = 176,
    ECAP_INPUT_CMPSSB7_CTRIP_HIGH = 177,
    ECAP_INPUT_CMPSSB8_CTRIP_LOW = 178,
    ECAP_INPUT_CMPSSB8_CTRIP_HIGH = 179,
    ECAP_INPUT_CMPSSB9_CTRIP_LOW = 180,
    ECAP_INPUT_CMPSSB9_CTRIP_HIGH = 181,
    ECAP_INPUT_ADC0_EVT0 = 182,
    ECAP_INPUT_ADC0_EVT1 = 183,
    ECAP_INPUT_ADC0_EVT2 = 184,
    ECAP_INPUT_ADC0_EVT3 = 185,
    ECAP_INPUT_ADC1_EVT0 = 186,
    ECAP_INPUT_ADC1_EVT1 = 187,
    ECAP_INPUT_ADC1_EVT2 = 188,
    ECAP_INPUT_ADC1_EVT3 = 189,
    ECAP_INPUT_ADC2_EVT0 = 190,
    ECAP_INPUT_ADC2_EVT1 = 191,
    ECAP_INPUT_ADC2_EVT2 = 192,
    ECAP_INPUT_ADC2_EVT3 = 193,
    ECAP_INPUT_ADC3_EVT0 = 194,
    ECAP_INPUT_ADC3_EVT1 = 195,
    ECAP_INPUT_ADC3_EVT2 = 196,
    ECAP_INPUT_ADC3_EVT3 = 197,
    ECAP_INPUT_ADC4_EVT0 = 198,
    ECAP_INPUT_ADC4_EVT1 = 199,
    ECAP_INPUT_ADC4_EVT2 = 200,
    ECAP_INPUT_ADC4_EVT3 = 201,
    ECAP_INPUT_INPUTXBAR0 = 202,
    ECAP_INPUT_INPUTXBAR1 = 203,
    ECAP_INPUT_INPUTXBAR2 = 204,
    ECAP_INPUT_INPUTXBAR3 = 205,
    ECAP_INPUT_INPUTXBAR4 = 206,
    ECAP_INPUT_INPUTXBAR5 = 207,
    ECAP_INPUT_INPUTXBAR6 = 208,
    ECAP_INPUT_INPUTXBAR7 = 209,
    ECAP_INPUT_INPUTXBAR8 = 210,
    ECAP_INPUT_INPUTXBAR9 = 211,
    ECAP_INPUT_INPUTXBAR10 = 212,
    ECAP_INPUT_INPUTXBAR11 = 213,
    ECAP_INPUT_INPUTXBAR12 = 214,
    ECAP_INPUT_INPUTXBAR13 = 215,
    ECAP_INPUT_INPUTXBAR14 = 216,
    ECAP_INPUT_INPUTXBAR15 = 217,
    ECAP_INPUT_INPUTXBAR16 = 218,
    ECAP_INPUT_INPUTXBAR17 = 219,
    ECAP_INPUT_INPUTXBAR18 = 220,
    ECAP_INPUT_INPUTXBAR19 = 221,
    ECAP_INPUT_INPUTXBAR20 = 222,
    ECAP_INPUT_INPUTXBAR21 = 223,
    ECAP_INPUT_INPUTXBAR22 = 224,
    ECAP_INPUT_INPUTXBAR23 = 225,
    ECAP_INPUT_INPUTXBAR24 = 226,
    ECAP_INPUT_INPUTXBAR25 = 227,
    ECAP_INPUT_INPUTXBAR26 = 228,
    ECAP_INPUT_INPUTXBAR27 = 229,
    ECAP_INPUT_INPUTXBAR28 = 230,
    ECAP_INPUT_INPUTXBAR29 = 231,
    ECAP_INPUT_INPUTXBAR30 = 232,
    ECAP_INPUT_INPUTXBAR31 = 233
}ECAP_InputCaptureSignals;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    ECAP_CAP_MODE_SOC_TRIGGER_SRC_CEVT1 = 0,
    ECAP_CAP_MODE_SOC_TRIGGER_SRC_CEVT2 = 1,
    ECAP_CAP_MODE_SOC_TRIGGER_SRC_CEVT3 = 2,
    ECAP_CAP_MODE_SOC_TRIGGER_SRC_CEVT4 = 3,
    ECAP_APWM_MODE_SOC_TRIGGER_SRC_PRD = 4,
    ECAP_APWM_MODE_SOC_TRIGGER_SRC_CMP = 5,
    ECAP_APWM_MODE_SOC_TRIGGER_SRC_PRD_CMP = 6,
    ECAP_APWM_MODE_SOC_TRIGGER_SRC_DISABLED = 7
}ECAP_SocTriggerSource;
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    ECAP_SYNC_IN_PULSE_SRC_DISABLE = 0x0,
    ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM0 = 0x1,
    ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM1 = 0x2,
    ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM2 = 0x3,
    ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM3 = 0x4,
    ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM4 = 0x5,
    ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM5 = 0x6,
    ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM6 = 0x7,
    ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM7 = 0x8,
    ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM8 = 0x9,
    ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM9 = 0xA,
    ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM10 = 0xB,
    ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM11 = 0xC,
    ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM12 = 0xD,
    ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM13 = 0xE,
    ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM14 = 0xF,
    ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM15 = 0x10,
    ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM16 = 0x11,
    ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM17 = 0x12,
    ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM18 = 0x13,
    ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM19 = 0x14,
    ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM20 = 0x15,
    ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM21 = 0x16,
    ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM22 = 0x17,
    ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM23 = 0x18,
    ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM24 = 0x19,
    ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM25 = 0x1A,
    ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM26 = 0x1B,
    ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM27 = 0x1C,
    ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM28 = 0x1D,
    ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM29 = 0x1E,
    ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM30 = 0x1F,
    ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM31 = 0x20,
}ECAP_SyncInPulseSource;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    HRCAP_CALIBRATION_CLOCK_SYSCLK = 0x0,  
    HRCAP_CALIBRATION_CLOCK_HRCLK = 0x4  
}HRCAP_CalibrationClockSource;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    HRCAP_CONTINUOUS_CALIBRATION_DISABLED = 0x00,
    HRCAP_CONTINUOUS_CALIBRATION_ENABLED = 0x20
}HRCAP_ContinuousCalibrationMode;
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void ECAP_setEventPrescaler(uint32_t base,
                                          uint16_t preScalerValue)
{
    DebugP_assert(preScalerValue < ECAP_MAX_PRESCALER_VALUE);
 
    //
    // Write to PRESCALE bit
    //
    HW_WR_REG16(base + CSL_ECAP_ECCTL1,
        ((HW_RD_REG16(base + CSL_ECAP_ECCTL1) &
        (~CSL_ECAP_ECCTL1_PRESCALE_MASK)) |
        (preScalerValue << CSL_ECAP_ECCTL1_PRESCALE_SHIFT)));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void ECAP_setEventPolarity(uint32_t base,
                                         ECAP_Events event,
                                         ECAP_EventPolarity polarity)
{
 
    uint16_t shift;
 
    shift = ((uint16_t)event) << 1U;
 
    //
    // Write to CAP1POL, CAP2POL, CAP3POL or CAP4POL
    //
    HW_WR_REG16(base + CSL_ECAP_ECCTL1,
        ((HW_RD_REG16(base + CSL_ECAP_ECCTL1) & ~(1U << shift)) |
        ((uint16_t)polarity << shift)));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void ECAP_setCaptureMode(uint32_t base,
                                       ECAP_CaptureMode mode,
                                       ECAP_Events event)
{
    //
    // Write to CONT/ONESHT
    //
    HW_WR_REG16(base + CSL_ECAP_ECCTL2,
        ((HW_RD_REG16(base + CSL_ECAP_ECCTL2) &
        (~CSL_ECAP_ECCTL2_CONT_ONESHT_MASK)) | (uint16_t)mode));
 
    //
    // Write to STOP_WRAP
    //
    HW_WR_REG16(base + CSL_ECAP_ECCTL2,
        ((HW_RD_REG16(base + CSL_ECAP_ECCTL2) &
        (~CSL_ECAP_ECCTL2_STOP_WRAP_MASK)) |
        (((uint16_t)event) << CSL_ECAP_ECCTL2_STOP_WRAP_SHIFT )));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void ECAP_reArm(uint32_t base)
{
    //
    // Write to RE-ARM bit
    //
    HW_WR_REG16(base + CSL_ECAP_ECCTL2,
        (HW_RD_REG16(base + CSL_ECAP_ECCTL2) | CSL_ECAP_ECCTL2_REARM_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void ECAP_enableInterrupt(uint32_t base,
                                        uint16_t intFlags)
{
    DebugP_assert((intFlags & ~(ECAP_ISR_SOURCE_CAPTURE_EVENT_1 |
                   ECAP_ISR_SOURCE_CAPTURE_EVENT_2 |
                   ECAP_ISR_SOURCE_CAPTURE_EVENT_3 |
                   ECAP_ISR_SOURCE_CAPTURE_EVENT_4 |
                   ECAP_ISR_SOURCE_COUNTER_OVERFLOW |
                   ECAP_ISR_SOURCE_COUNTER_PERIOD |
                   ECAP_ISR_SOURCE_COUNTER_COMPARE |
                   ECAP_ISR_SOURCE_HR_ERROR)) == 0U);
 
    //
    // Set bits in ECEINT register
    //
    HW_WR_REG16(base + CSL_ECAP_ECEINT,
        (HW_RD_REG16(base + CSL_ECAP_ECEINT) | intFlags));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void ECAP_disableInterrupt(uint32_t base,
                                         uint16_t intFlags)
{
    DebugP_assert((intFlags & ~(ECAP_ISR_SOURCE_CAPTURE_EVENT_1 |
                   ECAP_ISR_SOURCE_CAPTURE_EVENT_2 |
                   ECAP_ISR_SOURCE_CAPTURE_EVENT_3 |
                   ECAP_ISR_SOURCE_CAPTURE_EVENT_4 |
                   ECAP_ISR_SOURCE_COUNTER_OVERFLOW |
                   ECAP_ISR_SOURCE_COUNTER_PERIOD |
                   ECAP_ISR_SOURCE_COUNTER_COMPARE |
                   ECAP_ISR_SOURCE_HR_ERROR)) == 0U);
 
    //
    // Clear bits in ECEINT register
    //
    HW_WR_REG16(base + CSL_ECAP_ECEINT,
        (HW_RD_REG16(base + CSL_ECAP_ECEINT) & ~intFlags));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline uint16_t ECAP_getInterruptSource(uint32_t base)
{
    //
    // Return contents of ECFLG register
    //
    return(HW_RD_REG16(base + CSL_ECAP_ECFLG) & 0xFEU);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline bool ECAP_getGlobalInterruptStatus(uint32_t base)
{
    //
    // Return contents of Global interrupt bit
    //
    return((HW_RD_REG16(base + CSL_ECAP_ECFLG) & 0x1U) == 0x1U);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void ECAP_clearInterrupt(uint32_t base,
                                       uint16_t intFlags)
{
    DebugP_assert((intFlags & ~(ECAP_ISR_SOURCE_CAPTURE_EVENT_1 |
                   ECAP_ISR_SOURCE_CAPTURE_EVENT_2 |
                   ECAP_ISR_SOURCE_CAPTURE_EVENT_3 |
                   ECAP_ISR_SOURCE_CAPTURE_EVENT_4 |
                   ECAP_ISR_SOURCE_COUNTER_OVERFLOW |
                   ECAP_ISR_SOURCE_COUNTER_PERIOD |
                   ECAP_ISR_SOURCE_COUNTER_COMPARE |
                   ECAP_ISR_SOURCE_HR_ERROR)) == 0U);
 
    //
    // Write to ECCLR register
    //
    HW_WR_REG16(base + CSL_ECAP_ECCLR,
        (HW_RD_REG16(base + CSL_ECAP_ECCLR) |
        (intFlags | CSL_ECAP_ECCLR_INT_MASK)));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void ECAP_clearGlobalInterrupt(uint32_t base)
{
    //
    // Write to INT bit
    //
    HW_WR_REG16(base + CSL_ECAP_ECCLR,
        (HW_RD_REG16(base + CSL_ECAP_ECCLR) | CSL_ECAP_ECCLR_INT_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void ECAP_forceInterrupt(uint32_t base,
                                       uint16_t intFlags)
{
    DebugP_assert((intFlags & ~(ECAP_ISR_SOURCE_CAPTURE_EVENT_1 |
                   ECAP_ISR_SOURCE_CAPTURE_EVENT_2 |
                   ECAP_ISR_SOURCE_CAPTURE_EVENT_3 |
                   ECAP_ISR_SOURCE_CAPTURE_EVENT_4 |
                   ECAP_ISR_SOURCE_COUNTER_OVERFLOW |
                   ECAP_ISR_SOURCE_COUNTER_PERIOD |
                   ECAP_ISR_SOURCE_COUNTER_COMPARE |
                   ECAP_ISR_SOURCE_HR_ERROR)) == 0U);
 
    //
    // Write to ECFRC register
    //
    HW_WR_REG16(base + CSL_ECAP_ECFRC,
        (HW_RD_REG16(base + CSL_ECAP_ECFRC) | intFlags));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void ECAP_enableCaptureMode(uint32_t base)
{
    //
    // Clear CAP/APWM bit
    //
    HW_WR_REG16(base + CSL_ECAP_ECCTL2,
        (HW_RD_REG16(base + CSL_ECAP_ECCTL2) &
        ~CSL_ECAP_ECCTL2_CAP_APWM_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void ECAP_enableAPWMMode(uint32_t base)
{
    //
    // Set CAP/APWM bit
    //
    HW_WR_REG16(base + CSL_ECAP_ECCTL2,
        (HW_RD_REG16(base + CSL_ECAP_ECCTL2) | CSL_ECAP_ECCTL2_CAP_APWM_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void ECAP_enableCounterResetOnEvent(uint32_t base,
                                                  ECAP_Events event)
{
    //
    // Set CTRRST1,CTRRST2,CTRRST3 or CTRRST4 bits
    //
    HW_WR_REG16(base + CSL_ECAP_ECCTL1,
        (HW_RD_REG16(base + CSL_ECAP_ECCTL1) |
        (1U << ((2U * (uint16_t)event) + 1U))));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void ECAP_disableCounterResetOnEvent(uint32_t base,
                                                   ECAP_Events event)
{
    DebugP_assert(((uint32_t) event >= 1U) || ((uint32_t) event <= 4U));
 
    //
    // Clear CTRRST1,CTRRST2,CTRRST3 or CTRRST4 bits
    //
    HW_WR_REG16(base + CSL_ECAP_ECCTL1,
        (HW_RD_REG16(base + CSL_ECAP_ECCTL1) &
        ~(1U << ((2U * (uint16_t)event) + 1U))));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void ECAP_enableTimeStampCapture(uint32_t base)
{
    //
    // Set CAPLDEN bit
    //
    HW_WR_REG16(base + CSL_ECAP_ECCTL1,
        (HW_RD_REG16(base + CSL_ECAP_ECCTL1) | CSL_ECAP_ECCTL1_CAPLDEN_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void ECAP_disableTimeStampCapture(uint32_t base)
{
    //
    // Clear CAPLDEN bit
    //
    HW_WR_REG16(base + CSL_ECAP_ECCTL1,
        (HW_RD_REG16(base + CSL_ECAP_ECCTL1) & ~CSL_ECAP_ECCTL1_CAPLDEN_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void ECAP_setPhaseShiftCount(uint32_t base, uint32_t shiftCount)
{
    //
    // Write to CTRPHS
    //
    HW_WR_REG32(base + CSL_ECAP_CTRPHS, shiftCount);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
ECAP_setSyncInPulseSource(uint32_t base, ECAP_SyncInPulseSource source)
{
    //
    // Set ECAP Sync-In Source Mode.
    //
    HW_WR_REG16(base + CSL_ECAP_ECAPSYNCINSEL,
        ((HW_RD_REG16(base + CSL_ECAP_ECAPSYNCINSEL) &
        (~CSL_ECAP_ECAPSYNCINSEL_SEL_MASK)) |
        ((uint16_t)source & CSL_ECAP_ECAPSYNCINSEL_SEL_MASK)));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void ECAP_enableLoadCounter(uint32_t base)
{
    //
    // Write to SYNCI_EN
    //
    HW_WR_REG16(base + CSL_ECAP_ECCTL2,
        (HW_RD_REG16(base + CSL_ECAP_ECCTL2) | CSL_ECAP_ECCTL2_SYNCI_EN_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void ECAP_disableLoadCounter(uint32_t base)
{
    //
    // Write to SYNCI_EN
    //
    HW_WR_REG16(base + CSL_ECAP_ECCTL2,
        (HW_RD_REG16(base + CSL_ECAP_ECCTL2) &
        ~CSL_ECAP_ECCTL2_SYNCI_EN_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void ECAP_loadCounter(uint32_t base)
{
    //
    // Write to SWSYNC
    //
    HW_WR_REG16(base + CSL_ECAP_ECCTL2,
        (HW_RD_REG16(base + CSL_ECAP_ECCTL2) | CSL_ECAP_ECCTL2_SWSYNC_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void ECAP_setSyncOutMode(uint32_t base,
                                       ECAP_SyncOutMode mode)
{
    //
    // Write to SYNCO_SEL
    //
    HW_WR_REG16(base + CSL_ECAP_ECCTL2,
        ((HW_RD_REG16(base + CSL_ECAP_ECCTL2) &
        (~CSL_ECAP_ECCTL2_SYNCO_SEL_MASK)) | (uint16_t)mode));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void ECAP_stopCounter(uint32_t base)
{
    //
    // Clear TSCTR
    //
    HW_WR_REG16(base + CSL_ECAP_ECCTL2,
        (HW_RD_REG16(base + CSL_ECAP_ECCTL2) &
        ~CSL_ECAP_ECCTL2_TSCTRSTOP_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void ECAP_startCounter(uint32_t base)
{
    //
    // Set TSCTR
    //
    HW_WR_REG16(base + CSL_ECAP_ECCTL2,
        (HW_RD_REG16(base + CSL_ECAP_ECCTL2) |
        CSL_ECAP_ECCTL2_TSCTRSTOP_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void ECAP_setAPWMPolarity(uint32_t base,
                                        ECAP_APWMPolarity polarity)
{
    HW_WR_REG16(base + CSL_ECAP_ECCTL2,
        ((HW_RD_REG16(base + CSL_ECAP_ECCTL2) &
        ~CSL_ECAP_ECCTL2_APWMPOL_MASK) | (uint16_t)polarity));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void ECAP_setAPWMPeriod(uint32_t base, uint32_t periodCount)
{
    //
    // Write to CAP1
    //
    HW_WR_REG32(base + CSL_ECAP_CAP1, periodCount);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void ECAP_setAPWMCompare(uint32_t base, uint32_t compareCount)
{
    //
    // Write to CAP2
    //
    HW_WR_REG32(base + CSL_ECAP_CAP2, compareCount);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void ECAP_setAPWMShadowPeriod(uint32_t base,
                                            uint32_t periodCount)
{
    //
    // Write to CAP3
    //
    HW_WR_REG32(base + CSL_ECAP_CAP3, periodCount);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void ECAP_setAPWMShadowCompare(uint32_t base,
                                             uint32_t compareCount)
{
    //
    // Write to CAP4
    //
    HW_WR_REG32(base + CSL_ECAP_CAP4, compareCount);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline uint32_t ECAP_getTimeBaseCounter(uint32_t base)
{
    //
    // Read the Time base counter value
    //
    return(HW_RD_REG32(base + CSL_ECAP_TSCTR));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline uint32_t ECAP_getEventTimeStamp(uint32_t base, ECAP_Events event)
{
    uint32_t count;
 
    switch(event)
    {
        case ECAP_EVENT_1:
 
            //
            // Read CAP1 register
            //
            count = HW_RD_REG32(base + CSL_ECAP_CAP1);
        break;
 
        case ECAP_EVENT_2:
            //
            // Read CAP2 register
            //
            count = HW_RD_REG32(base + CSL_ECAP_CAP2);
        break;
 
        case ECAP_EVENT_3:
 
            //
            // Read CAP3 register
            //
            count = HW_RD_REG32(base + CSL_ECAP_CAP3);
        break;
 
        case ECAP_EVENT_4:
 
            //
            // Read CAP4 register
            //
            count = HW_RD_REG32(base + CSL_ECAP_CAP4);
        break;
 
        default:
 
            //
            // Invalid event parameter
            //
            count = 0U;
        break;
    }
 
    return(count);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void ECAP_selectECAPInput(uint32_t base,
                                        ECAP_InputCaptureSignals input)
{
    //
    // Write to ECCTL0
    //
    HW_WR_REG16(base + CSL_ECAP_ECCTL0,
        ((HW_RD_REG16(base + CSL_ECAP_ECCTL0) &
        ~CSL_ECAP_ECCTL0_INPUTSEL_MASK) | (uint16_t)input));
}
//*****************************************************************************
//
//
//*****************************************************************************
static inline void ECAP_selectSocTriggerSource(uint32_t base,
                                        ECAP_SocTriggerSource triggersource)
{
    uint16_t source = (uint16_t)triggersource;
    //
    // Write to ECCTL0
    //
    if(source >= ECAP_APWM_MODE_SOC_TRIGGER_SRC_PRD)
        source-= (uint16_t)ECAP_APWM_MODE_SOC_TRIGGER_SRC_PRD;
 
    HW_WR_REG32(base + CSL_ECAP_ECCTL0,
        ((HW_RD_REG32(base + CSL_ECAP_ECCTL0) &
        ~CSL_ECAP_ECCTL0_SOCEVTSEL_MASK) | (source << CSL_ECAP_ECCTL0_SOCEVTSEL_SHIFT)));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void ECAP_resetCounters(uint32_t base)
{
    //
    // Write to ECCTL2
    //
    HW_WR_REG16(base + CSL_ECAP_ECCTL2,
        (HW_RD_REG16(base + CSL_ECAP_ECCTL2) |
        CSL_ECAP_ECCTL2_CTRFILTRESET_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void ECAP_setDMASource(uint32_t base, ECAP_Events event)
{
    //
    // Write to ECCTL2
    //
    HW_WR_REG16(base + CSL_ECAP_ECCTL2,
        ((HW_RD_REG16(base + CSL_ECAP_ECCTL2) &
        ~CSL_ECAP_ECCTL2_DMAEVTSEL_MASK) |
        ((uint16_t)event << CSL_ECAP_ECCTL2_DMAEVTSEL_SHIFT)));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline ECAP_Events ECAP_getModuloCounterStatus(uint32_t base)
{
    uint16_t counterStatusValue;
 
    counterStatusValue = (((HW_RD_REG32(base + CSL_ECAP_ECCTL2) &
                          CSL_ECAP_ECCTL2_MODCNTRSTS_MASK) >>
                          CSL_ECAP_ECCTL2_MODCNTRSTS_SHIFT));
 
    //
    // Read MODCNTRSTS bit
    //
    return((ECAP_Events)(counterStatusValue));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void HRCAP_enableHighResolution(uint32_t base)
{
    //
    // Set HRE bit.
    //
    HW_WR_REG16(base + CSL_ECAP_HRCTL,
        (HW_RD_REG16(base + CSL_ECAP_HRCTL) | CSL_ECAP_HRCTL_HRE_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void HRCAP_disableHighResolution(uint32_t base)
{
    //
    // Set HRE bit.
    //
    HW_WR_REG16(base + CSL_ECAP_HRCTL,
        (HW_RD_REG16(base + CSL_ECAP_HRCTL) & ~CSL_ECAP_HRCTL_HRE_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void HRCAP_enableHighResolutionClock(uint32_t base)
{
    //
    // Set HRCLKE bit.
    //
    HW_WR_REG16(base + CSL_ECAP_HRCTL,
        (HW_RD_REG16(base + CSL_ECAP_HRCTL) | CSL_ECAP_HRCTL_HRCLKE_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void HRCAP_disbleHighResolutionClock(uint32_t base)
{
    //
    // Clear HRCLKE bit.
    //
    HW_WR_REG16(base + CSL_ECAP_HRCTL,
        (HW_RD_REG16(base + CSL_ECAP_HRCTL) & ~CSL_ECAP_HRCTL_HRCLKE_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void HRCAP_startCalibration(uint32_t base)
{
    //
    // Set CALIBSTART bit.
    //
    HW_WR_REG16(base + CSL_ECAP_HRCTL,
        (HW_RD_REG16(base + CSL_ECAP_HRCTL) | CSL_ECAP_HRCTL_CALIBSTART_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void HRCAP_setCalibrationMode(uint32_t base)
{
    //
    // Write to CALIBSTS and CALIBCONT bits.
    //
    HW_WR_REG16(base + CSL_ECAP_HRCTL,
        (HW_RD_REG16(base + CSL_ECAP_HRCTL) | CSL_ECAP_HRCTL_CALIBCONT_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
HRCAP_enableCalibrationInterrupt(uint32_t base, uint16_t intFlags)
{
    DebugP_assert(intFlags & (HRCAP_CALIBRATION_DONE |
                  HRCAP_CALIBRATION_PERIOD_OVERFLOW));
 
    //
    // Set CALIBDONE or CALPRDCHKSTS.
    //
    HW_WR_REG16(base + CSL_ECAP_HRINTEN,
        (HW_RD_REG16(base + CSL_ECAP_HRINTEN) | intFlags));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
HRCAP_disableCalibrationInterrupt(uint32_t base, uint16_t intFlags)
{
    DebugP_assert(intFlags & (HRCAP_CALIBRATION_DONE |
                  HRCAP_CALIBRATION_PERIOD_OVERFLOW));
 
    //
    // Clear CALIBDONE or CALPRDCHKSTS.
    //
    HW_WR_REG16(base + CSL_ECAP_HRINTEN,
        (HW_RD_REG16(base + CSL_ECAP_HRINTEN) & ~intFlags));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline uint16_t HRCAP_getCalibrationFlags(uint32_t base)
{
    //
    // Return contents of HRFLG register.
    //
    return((uint16_t)(HW_RD_REG16(base + CSL_ECAP_HRFLG) & 0x7U));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void HRCAP_clearCalibrationFlags(uint32_t base, uint16_t flags)
{
    DebugP_assert((flags == (HRCAP_CALIBRATION_DONE |
                 HRCAP_GLOBAL_CALIBRATION_INTERRUPT)) ||
                 (flags == (HRCAP_CALIBRATION_PERIOD_OVERFLOW |
                 HRCAP_GLOBAL_CALIBRATION_INTERRUPT)) ||
                 (flags == (HRCAP_CALIBRATION_DONE |
                 HRCAP_GLOBAL_CALIBRATION_INTERRUPT |
                 HRCAP_CALIBRATION_PERIOD_OVERFLOW)));
 
    //
    // Write to HRCLR register.
    //
    HW_WR_REG16(base + CSL_ECAP_HRCLR,
        (HW_RD_REG16(base + CSL_ECAP_HRCLR) | flags));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline bool HRCAP_isCalibrationBusy(uint32_t base)
{
    //
    // Read CALIBSTS bit.
    //
    return((HW_RD_REG16(base + CSL_ECAP_HRCTL)
            & CSL_ECAP_HRCTL_CALIBSTS_MASK) == CSL_ECAP_HRCTL_CALIBSTS_MASK);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void HRCAP_forceCalibrationFlags(uint32_t base, uint16_t flag)
{
    DebugP_assert((flag & (HRCAP_CALIBRATION_DONE |
                   HRCAP_CALIBRATION_PERIOD_OVERFLOW)));
 
    //
    // Write to CALIBDONE or CALPRDCHKSTS bit.
    //
    HW_WR_REG16(base + CSL_ECAP_HRFRC,
        (HW_RD_REG16(base + CSL_ECAP_HRFRC) | flag));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void HRCAP_setCalibrationPeriod(uint32_t base, uint32_t sysclkHz)
{
    //
    // Write to HRCALPRD register
    //
    HW_WR_REG16(base + CSL_ECAP_HRCALPRD,
        (sysclkHz * 16U) / 10000U);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline uint32_t
HRCAP_getCalibrationClockPeriod(uint32_t base,
                               HRCAP_CalibrationClockSource clockSource)
{
    //
    // Return HRCAP_O_HRSYSCLKCAP or HRCAP_O_HRCLKCAP.
    //
    return(HW_RD_REG16(base + CSL_ECAP_HRSYSCLKCAP + (uint32_t)clockSource));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline Float32 HRCAP_getScaleFactor(uint32_t base)
{
    //
    // Calculate and return the scale factor.
    //
    return((Float32)HRCAP_getCalibrationClockPeriod(base,
                                            HRCAP_CALIBRATION_CLOCK_SYSCLK) /
           (Float32)HRCAP_getCalibrationClockPeriod(base,
                                            HRCAP_CALIBRATION_CLOCK_HRCLK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline Float32
HRCAP_convertEventTimeStampNanoseconds(uint32_t timeStamp,
                                       Float32 scaleFactor)
{
    //
    // Convert the raw count value to nanoseconds using the given scale factor.
    //
    return((Float32)timeStamp * scaleFactor * ((Float32)5.0 /
                                                 (Float32)128.0));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
extern void ECAP_setEmulationMode(uint32_t base, ECAP_EmulationMode mode);
 
//*****************************************************************************
//
// Close the Doxygen group.
//
//*****************************************************************************
 
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
 
#endif // ECAP_V1_H_