AM263x MCU+ SDK  08.05.00
EtherCAT SubDevice FWHAL

Table of Contents

Introduction

This software is designed for the TI SoCs with PRU-ICSS IP to enable customers add EtherCAT SubDevice protocol support to their system. It implements EtherCAT SubDevice Controller(ESC) Layer 2 functionality with two MII ports (one IN and one OUT port per PRU-ICSS) in accordance with ETG.1000.4 Data Link Layer protocol specification. This provides EtherCAT ASIC like functionality integrated into TI SoCs.

Software Architecture

EtherCAT firmware for PRU-ICSS is a black box product maintained by TI. EtherCAT SubDevice FWHAL(Firmware and Hardware Abstraction Layer) allows loading and running the EtherCAT firmware and acts as an interface with ESC firmware. FWHAL implements the key interface between EtherCAT SubDevice Controller Emulation firmware and EtherCAT stack.

SysConfig Features

Note
It is strongly recommend to use SysConfig where it is available instead of using direct SW API calls. This will help simplify the SW application and also catch common mistakes early in the development cycle.

SysConfig can be used to configure things mentioned below:

  • Selecting the PRU-ICSS instance
  • Configuring PINMUX needed for MII mode
  • Configuring ETHPHY for the two PHY ports of PRU-ICSS

PRU-ICSS EtherCAT SubDevice Firmware

Features Supported

  • All EtherCAT Commands (NOP, APRD, APWR, APRW, FPRD, FPWR, FPRW, BRD, BWR, BRW, LRD, LWR, LRW, ARMW and FRMW)
  • 8 FMMU support
  • 8 SM support
  • 59KB of Process Data RAM
  • Distributed clocks
    • 64-bit DC
    • SYNC0 out generation single shot and cyclic mode support
    • SYNC1 out generation - SYNC1 cycle time multiple of SYNC0 cycle time
    • Latch0 and Latch1 inputs
    • System Time PDI control
  • DL Loop Control
    • Using MII_RX_LINK (fast - depending on PHY link loss detection latency) - mandatory for cable redundancy support
    • Using PRU-ICSS MDIO state machine - not recommended for cable redundancy support
  • Interrupts - AL/ECAT events
    • SYNC0, SYNC1 and PDI interrupt events on external SOC pins
  • Watchdog - PDI and SM
  • Error Counters
    • RX Invalid Frame Counter Port 0/1
    • RX ERR Counter Port 0/1
    • Forwarded Error Counter Port 0/1
    • ECAT Processing Unit Error Counter
  • LED - Run, Error and Port0/1 activity
  • EEPROM Emulation for ESI EEPROM support
  • Management Interface for PHY over EtherCAT
  • PHY address configuration and host side API for PHY programming
  • Cable redundancy support
  • Firmware based on 200 MHz clock frequency for PRU-ICSS Core Clock and IEP Clock

Release Notes

MCU+ SDK Version 08.05.00

  • Firmware Version : x.5.12
  • Bug-fix for PINDSW-5384 : ESC DL Status register is not initialized correctly
  • Bug-fix for PINDSW-5385 : Next SYNC1 Pulse register is not updated correctly
  • Bug-fix for PINDSW-5401 : SYNC1 Pulse is generated one SYNC0 cycle time late
  • Bug-fix for PINDSW-5369 : Write to System Time Delay (0x0928) register works only once

MCU+ SDK Version 08.04.00

  • Firmware Version : x.5.6
  • No updates from MCU+ SDK Version 08.03.00

MCU+ SDK Version 08.03.00

  • Firmware Version : x.5.6
  • Added selection of 200 MHz or 333 MHz clock frequency for PRU-ICSS Core Clock and IEP Clock used by EtherCAT SubDevice Firmware using PRU Clock Frequency Selection Register (0x0E34)
  • Added PDI ISR Time Register (0x0E2C)
  • Changed default value of Bit 3 and Bit 7 in Sync/Latch PDI Configuration Register (0x0151) to 0
  • Bug-fixes in implementation of RX Error Counter

MCU+ SDK Version 08.02.00

  • Firmware Version : x.5.1
  • EtherCAT SubDevice Firmware based on 333 MHz (instead of 200 MHz) clock frequency for PRU-ICSS Core Clock and IEP Clock for better process path latency
  • Add PHY RX Error Counter Register (0x0E28) for improving RX Error Counter accuracy (See Register Exceptions for more details)
  • Bug-fixes for PINDSW-3120, PINDSW-5194, PINDSW-5229 and PINDSW-5267

Features Not Supported

  • EtherCAT SubDevice Controller
    • ECAT side register protection when using LRD command
    • APRW/FPRW/BRW for SM mapped area
  • EtherCAT G
  • Reset Isolation

Known Issues

Record ID Details Workaround
PINDSW-47 Multiple FMMU access in a single datagram to a SubDevice for process data using LRD/LWR commands Use LRW instead of LRD/LWR
PINDSW-72 PDI/PD watchdog counter incremented by 1 whenever PDI/PD watchdog is disabled None
PINDSW-74 LRD access on unused registers increment WKC - no register protection while using LRD None
PINDSW-141 LRW access to non-interleaved input and output process data of multiple SubDevices does not work. SOEM accesses S in LRW mode this way Use LRD/LWR for process data access or use more optimal interleaved access for process data access from MainDevice (TwinCAT way)
PINDSW-2204 Frames with no SFD not counted as errors if received on reverse path None
PINDSW-2360 System time of next Sync0 pulse register (0x990:0x993) is not instantaneous, resulting in read of incorrect value if read immediately after sync pulse None
PINDSW-5135 Read permissions and byte level write permissions for RW type commands are not checked None
PINDSW-5145 RX_ER counter does not count errors outside frame in MII RX_CLK units precisely Added PHY RX Error Counter Register (0x0E28) for improving RX Error Counter accuracy. Configuring this register will track RX_ERs within a frame precisely using PHY registers. Refer Register Exceptions for more details.
PINDSW-5414 Link Lost Counter is incorrectly incremented once for ports with polarity of RXLINK input as “Active Low” during initialization Use Active High Polarity for LED_LINK/SPEED connected to MII0/MII1 Receive Link (RXLINK) pin of PRU-ICSS

For more details, please see the EtherCAT SubDevice Errata document.

Important Files and Directory Structure

Folder/Files Description
${SDK_INSTALL_PATH}/examples/industrial_comms
ethercat_slave_beckhoff_ssc_demo EtherCAT SubDevice Example based on Beckhoff SSC
${SDK_INSTALL_PATH}/source/industrial_comms/ethercat_slave
icss_fwhal/firmware/m_v2.3 Firmware for the PRU cores in PRU-ICSS. Firmware Version : 5.5.12
icss_fwhal/lib/ FWHAL library for EtherCAT SubDevice
icss_fwhal/tiescbsp.h FWHAL interface file
beckhoff_stack/esi ESI XML file for Beckhoff SubDevice Stack Code(SSC) based example
beckhoff_stack/patch Patch file for Beckhoff SubDevice Stack Code(SSC) sources
beckhoff_stack/stack_hal Stack adaptation APIs for Beckhoff SubDevice Stack Code(SSC)
beckhoff_stack/stack_sources Folder where Beckhoff SubDevice Stack Code(SSC) sources should be copied. Stack sources are not packaged in the SDK

API Documentation

Please see APIs for Ethercat Slave FWHAL for API documentation.

It is recommended to use these FWHAL APIs in the stack adaptation files. For example, see ${SDK_INSTALL_PATH}/source/industrial_comms/ethercat_slave/beckhoff_stack/stack_hal, which contains the stack adaptation APIs for Beckhoff SubDevice Stack Code(SSC).

Procedure to kick-off the EtherCAT SubDevice Controller(ESC)

  • Initialize memories (register protection, register reset values, EEPROM cache) and PRU-ICSS INTC module. This is done by FWHAL(Firmware and Hardware Abstraction Layer).
  • Load firmware into PRUs of PRU-ICSS. This is done by FWHAL.
  • Enable the PRU cores. This is done by FWHAL.
  • Initialize the EtherCAT SubDevice stack.
  • Wait for AL Event Request and SYNC (in DC synchronous mode) interrupts from PRU and run EtherCAT stack main loop for handling mailbox and ESC state machine.
  • Handle the events as needed. Note that this is handled by the stack.

Interrupts

EtherCAT SubDevice Controller firmware generates the following interrupts.

8 Host Interrupts (Host Interrupts 2 through 9) are exported from the PRU_ICSSG internal INTC for signaling the device level interrupt controllers. PRU_EVTOUT0 to PRU_EVTOUT7 correspond to these eight interrupts in the following table. Please check PRUICSS Interrupt Controller section for more details.

Name Host Interrupt Description
DC SYNC0 OUT PRU_EVTOUT1 Used in DC mode for syncing the application
DC SYNC1 OUT PRU_EVTOUT2 Used in DC mode for syncing the application
PDI Interrupt PRU_EVTOUT3 AL event/PDI interrupt to host stack
ESC Command Acknowledgement PRU_EVTOUT4 ESC firmware command completion acknowledgement to Host

EtherCAT SubDevice Controller(ESC) Register List

TI EtherCAT SubDevice Controller Register List contains descriptions of the registers in TI's EtherCAT SubDevice Controller implementation.

EtherCAT SubDevice Controller(ESC) Exceptions

TI EtherCAT SubDevice Controller Exceptions lists the exceptions TI's EtherCAT SubDevice Controller implementation when compared with ET1100 ASIC. Please note that TI ESC is a 2 port EtherCAT SubDevice and it does not support E-bus interface and all the corresponding register fields are not implemented.

Additional References

Please refer to below documents to understand more about EtherCAT SubDevice on TI platforms and EtherCAT SubDevice protocol specifications.

Document Description
EtherCAT on Sitara Processors Application note by TI on the EtherCAT SubDevice implementation on TI's Sitara Processors.
PRU-ICSS EtherCAT SubDevice Troubleshooting Guide This troubleshooting guide is intended to provide guidance on how to set up and debug the EtherCAT SubDevice implemented on TI's Sitara processors.
EtherCAT ESC Datasheet Section 1 - Technology Section 1 of Beckhoff's EtherCAT SubDevice Controller (ESC) documentation which describes basic EtherCAT technology.
EtherCAT ESC Datasheet Section 2 - Register Description Section 2 of Beckhoff's EtherCAT SubDevice Controller (ESC) documentation which contains ESC register descriptions.
Application Note ET9300 (EtherCAT SubDevice Stack Code) This contains details on how to start EtherCAT SubDevice development with SubDevice Stack Code.
EtherCAT SubDevice Implementation Guide from EtherCAT Technology Group This contains information on how to develop an EtherCAT SubDevice implementation.
EtherCAT SubDevice Design Quick Guide from Beckhoff This contains information on modifying PDO when using Beckhoff SSC Tool for code generation.

See also