AM263x MCU+ SDK  08.03.00
uart/v0/uart.h
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1 /*
2  * Copyright (C) 2021 Texas Instruments Incorporated
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  *
8  * Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  *
11  * Redistributions in binary form must reproduce the above copyright
12  * notice, this list of conditions and the following disclaimer in the
13  * documentation and/or other materials provided with the
14  * distribution.
15  *
16  * Neither the name of Texas Instruments Incorporated nor the names of
17  * its contributors may be used to endorse or promote products derived
18  * from this software without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  */
32 
48 #ifndef UART_V0_H_
49 #define UART_V0_H_
50 
51 /* ========================================================================== */
52 /* Include Files */
53 /* ========================================================================== */
54 
55 #include <stdint.h>
56 #include <kernel/dpl/SystemP.h>
57 #include <kernel/dpl/SemaphoreP.h>
58 #include <kernel/dpl/HwiP.h>
59 #include <drivers/hw_include/cslr.h>
60 #include <drivers/hw_include/cslr_uart.h>
61 #include <drivers/hw_include/hw_types.h>
62 
63 #ifdef __cplusplus
64 extern "C" {
65 #endif
66 
67 /* ========================================================================== */
68 /* Macros & Typedefs */
69 /* ========================================================================== */
70 
72 #define UART_FIFO_SIZE (64U)
73 
79 #define UART_TRANSMITEMPTY_TRIALCOUNT (3000U)
80 
82 #define UART_ERROR_COUNT (0x00FFFFFFU)
83 
85 typedef void *UART_Handle;
86 
96 #define UART_TRANSFER_STATUS_SUCCESS (0U)
97 
98 #define UART_TRANSFER_STATUS_TIMEOUT (1U)
99 
100 #define UART_TRANSFER_STATUS_ERROR_BI (2U)
101 
102 #define UART_TRANSFER_STATUS_ERROR_FE (3U)
103 
104 #define UART_TRANSFER_STATUS_ERROR_PE (4U)
105 
106 #define UART_TRANSFER_STATUS_ERROR_OE (5U)
107 
108 #define UART_TRANSFER_STATUS_CANCELLED (6U)
109 
110 #define UART_TRANSFER_STATUS_STARTED (7U)
111 
112 #define UART_TRANSFER_STATUS_READ_TIMEOUT (8U)
113 
114 #define UART_TRANSFER_STATUS_ERROR_INUSE (9U)
115 
116 #define UART_TRANSFER_STATUS_ERROR_OTH (10U)
117 
138 #define UART_TRANSFER_MODE_BLOCKING (0U)
139 
143 #define UART_TRANSFER_MODE_CALLBACK (1U)
144 
166 #define UART_READ_RETURN_MODE_FULL (0U)
167 
170 #define UART_READ_RETURN_MODE_PARTIAL (1U)
171 
181 #define UART_LEN_5 (0U)
182 #define UART_LEN_6 (1U)
183 #define UART_LEN_7 (2U)
184 #define UART_LEN_8 (3U)
185 
195 #define UART_STOPBITS_1 (0U)
196 #define UART_STOPBITS_2 (1U)
197 
207 #define UART_PARITY_NONE (0x00U)
208 #define UART_PARITY_ODD (0x01U)
209 #define UART_PARITY_EVEN (0x03U)
210 #define UART_PARITY_FORCED0 (0x07U)
211 #define UART_PARITY_FORCED1 (0x05U)
212 
222 #define UART_FCTYPE_NONE (0x00U)
223 #define UART_FCTYPE_HW (0x02U)
224 
234 #define UART_FCPARAM_RXNONE (0x00U)
235 #define UART_FCPARAM_RXXONXOFF_2 (0x01U)
236 #define UART_FCPARAM_RXXONXOFF_1 (0x02U)
237 #define UART_FCPARAM_RXXONXOFF_12 (0x03U)
238 #define UART_FCPARAM_AUTO_RTS (0x40U)
239 
249 #define UART_FCPARAM_TXNONE (0x00U)
250 #define UART_FCPARAM_TXXONXOFF_2 (0x04U)
251 #define UART_FCPARAM_TXXONXOFF_1 (0x08U)
252 #define UART_FCPARAM_TXXONXOFF_12 (0x0CU)
253 #define UART_FCPARAM_AUTO_CTS (0x80U)
254 
264 #define UART_RXTRIGLVL_1 (1U)
265 #define UART_RXTRIGLVL_8 (8U)
266 #define UART_RXTRIGLVL_16 (16U)
267 #define UART_RXTRIGLVL_56 (56U)
268 #define UART_RXTRIGLVL_60 (60U)
269 
279 #define UART_TXTRIGLVL_1 (1U)
280 #define UART_TXTRIGLVL_8 (8U)
281 #define UART_TXTRIGLVL_16 (16U)
282 #define UART_TXTRIGLVL_32 (32U)
283 #define UART_TXTRIGLVL_56 (56U)
284 
294 #define UART_OPER_MODE_16X (0U)
295 #define UART_OPER_MODE_SIR (1U)
296 #define UART_OPER_MODE_16X_AUTO_BAUD (2U)
297 #define UART_OPER_MODE_13X (3U)
298 #define UART_OPER_MODE_MIR (4U)
299 #define UART_OPER_MODE_FIR (5U)
300 #define UART_OPER_MODE_CIR (6U)
301 #define UART_OPER_MODE_DISABLED (7U)
302 
313 #define UART_TX_FIFO_NOT_FULL ( \
314  UART_SSR_TX_FIFO_FULL_TX_FIFO_FULL_VALUE_0)
315 #define UART_TX_FIFO_FULL ( \
316  UART_SSR_TX_FIFO_FULL_TX_FIFO_FULL_VALUE_1)
317 
327 #define UART_INTID_MODEM_STAT (UART_IIR_IT_TYPE_IT_TYPE_VALUE_0 \
328  << \
329  UART_IIR_IT_TYPE_SHIFT)
330 #define UART_INTID_TX_THRES_REACH (UART_IIR_IT_TYPE_IT_TYPE_VALUE_1 \
331  << \
332  UART_IIR_IT_TYPE_SHIFT)
333 #define UART_INTID_RX_THRES_REACH (UART_IIR_IT_TYPE_IT_TYPE_VALUE_2 \
334  << \
335  UART_IIR_IT_TYPE_SHIFT)
336 #define UART_INTID_RX_LINE_STAT_ERROR (UART_IIR_IT_TYPE_IT_TYPE_VALUE_3 \
337  << \
338  UART_IIR_IT_TYPE_SHIFT)
339 #define UART_INTID_CHAR_TIMEOUT (UART_IIR_IT_TYPE_IT_TYPE_VALUE_6 \
340  << \
341  UART_IIR_IT_TYPE_SHIFT)
342 #define UART_INTID_XOFF_SPEC_CHAR_DETECT (UART_IIR_IT_TYPE_IT_TYPE_VALUE_8 \
343  << \
344  UART_IIR_IT_TYPE_SHIFT)
345 #define UART_INTID_MODEM_SIG_STATE_CHANGE (UART_IIR_IT_TYPE_IT_TYPE_VALUE_10 \
346  << \
347  UART_IIR_IT_TYPE_SHIFT)
348 
350 #define UART_INTR_PENDING (0U)
351 #define UART_N0_INTR_PENDING (1U)
352 
361 #define UART_INTR_CTS (UART_IER_CTS_IT_MASK)
362 #define UART_INTR_RTS (UART_IER_RTS_IT_MASK)
363 #define UART_INTR_XOFF (UART_IER_XOFF_IT_MASK)
364 #define UART_INTR_SLEEPMODE (UART_IER_SLEEP_MODE_MASK)
365 #define UART_INTR_MODEM_STAT (UART_IER_MODEM_STS_IT_MASK)
366 #define UART_INTR_LINE_STAT (UART_IER_LINE_STS_IT_MASK)
367 #define UART_INTR_THR (UART_IER_THR_IT_MASK)
368 #define UART_INTR_RHR_CTI (UART_IER_RHR_IT_MASK)
369 
370 #define UART_INTR2_RX_EMPTY (UART_IER2_EN_RXFIFO_EMPTY_MASK)
371 #define UART_INTR2_TX_EMPTY (UART_IER2_EN_TXFIFO_EMPTY_MASK)
372 
381 #define UART_FIFO_PE_FE_BI_DETECTED (UART_LSR_RX_FIFO_STS_MASK)
382 #define UART_BREAK_DETECTED_ERROR (UART_LSR_RX_BI_MASK)
383 #define UART_FRAMING_ERROR (UART_LSR_RX_FE_MASK)
384 #define UART_PARITY_ERROR (UART_LSR_RX_PE_MASK)
385 #define UART_OVERRUN_ERROR (UART_LSR_RX_OE_MASK)
386 
395 #define UART_REG_CONFIG_MODE_A ((uint32_t) 0x0080)
396 #define UART_REG_CONFIG_MODE_B ((uint32_t) 0x00BF)
397 #define UART_REG_OPERATIONAL_MODE ((uint32_t) 0x007F)
398 
409 #define UART_CONFIG_MODE_POLLED (0x00U)
410 #define UART_CONFIG_MODE_INTERRUPT (0x01U)
411 #define UART_CONFIG_MODE_USER_INTR (0x02U)
412 #define UART_CONFIG_MODE_DMA (0x03U)
413 
414 /* ========================================================================== */
415 /* Structures and Enums */
416 /* ========================================================================== */
417 
422 typedef struct
423 {
424  void *buf;
427  uint32_t count;
431  uint32_t timeout;
433  uint32_t status;
435  void *args;
437 } UART_Transaction;
438 
446 typedef void (*UART_CallbackFxn) (UART_Handle handle,
447  UART_Transaction *transaction);
448 
459 typedef struct
460 {
461  uint32_t baudRate;
463  uint32_t dataLength;
465  uint32_t stopBits;
467  uint32_t parityType;
469  uint32_t readMode;
471  uint32_t readReturnMode;
473  uint32_t writeMode;
475  UART_CallbackFxn readCallbackFxn;
477  UART_CallbackFxn writeCallbackFxn;
479  uint32_t hwFlowControl;
481  uint32_t hwFlowControlThr;
484  /*
485  * Driver configuration
486  */
487  uint32_t transferMode;
489  uint32_t intrNum;
491  uint8_t intrPriority;
493  uint32_t skipIntrReg;
495  int32_t uartDmaIndex;
500  /*
501  * UART configuration
502  */
503  uint32_t operMode;
505  uint32_t rxTrigLvl;
507  uint32_t txTrigLvl;
509  uint32_t rxEvtNum;
511  uint32_t txEvtNum;
513 } UART_Params;
514 
516 typedef struct
517 {
518  /*
519  * SOC configuration
520  */
521  uint32_t baseAddr;
523  uint32_t inputClkFreq;
525 } UART_Attrs;
526 
527 /* ========================================================================== */
528 /* Internal/Private Structure Declarations */
529 /* ========================================================================== */
530 
534 typedef struct
535 {
536  /*
537  * User parameters
538  */
539  UART_Handle handle;
541  UART_Params prms;
543  /*
544  * UART write variables
545  */
546  const void *writeBuf;
548  uint32_t writeCount;
550  uint32_t writeSizeRemaining;
552  /*
553  * UART receive variables
554  */
555  void *readBuf;
557  uint32_t readCount;
559  uint32_t readSizeRemaining;
561  uint32_t rxTimeoutCnt;
563  uint32_t readErrorCnt;
565  /*
566  * UART ransaction status variables
567  */
568  UART_Transaction *readTrans;
570  UART_Transaction *writeTrans;
572  /*
573  * State variables
574  */
575  uint32_t isOpen;
577  void *lock;
579  SemaphoreP_Object lockObj;
581  void *readTransferSem;
584  SemaphoreP_Object readTransferSemObj;
586  void *writeTransferSem;
589  SemaphoreP_Object writeTransferSemObj;
591  void *hwiHandle;
593  HwiP_Object hwiObj;
595  void* uartDmaHandle;
597 } UART_Object;
598 
605 typedef struct
606 {
607  UART_Attrs *attrs;
609  UART_Object *object;
611 } UART_Config;
612 
614 extern UART_Config gUartConfig[];
616 extern uint32_t gUartConfigNum;
617 
618 /* ========================================================================== */
619 /* Global Variables Declarations */
620 /* ========================================================================== */
621 
622 /* None */
623 
624 /* ========================================================================== */
625 /* Function Declarations */
626 /* ========================================================================== */
627 
631 void UART_init(void);
632 
636 void UART_deinit(void);
637 
654 UART_Handle UART_open(uint32_t index, const UART_Params *prms);
655 
665 void UART_close(UART_Handle handle);
666 
705 int32_t UART_write(UART_Handle handle, UART_Transaction *trans);
706 
741 int32_t UART_read(UART_Handle handle, UART_Transaction *trans);
742 
774 int32_t UART_writeCancel(UART_Handle handle, UART_Transaction *trans);
775 
807 int32_t UART_readCancel(UART_Handle handle, UART_Transaction *trans);
808 
817 UART_Handle UART_getHandle(uint32_t index);
818 
828 void UART_flushTxFifo(UART_Handle handle);
829 
835 static inline void UART_Params_init(UART_Params *prms);
836 
843 static inline void UART_Transaction_init(UART_Transaction *trans);
844 
845 /* ========================================================================== */
846 /* Static Function Definitions */
847 /* ========================================================================== */
848 
849 static inline void UART_Params_init(UART_Params *prms)
850 {
851  if(prms != NULL)
852  {
853  prms->baudRate = 115200U;
854  prms->dataLength = UART_LEN_8;
855  prms->stopBits = UART_STOPBITS_1;
856  prms->parityType = UART_PARITY_NONE;
857  prms->readMode = UART_TRANSFER_MODE_BLOCKING;
858  prms->readReturnMode = UART_READ_RETURN_MODE_FULL;
859  prms->writeMode = UART_TRANSFER_MODE_BLOCKING;
860  prms->readCallbackFxn = NULL;
861  prms->writeCallbackFxn = NULL;
862  prms->hwFlowControl = FALSE;
863  prms->hwFlowControlThr = UART_RXTRIGLVL_16;
864  prms->intrNum = 0xFFFF;
865  prms->transferMode = UART_CONFIG_MODE_INTERRUPT;
866  prms->intrPriority = 4U;
867  prms->skipIntrReg = FALSE;
868  prms->uartDmaIndex = -1;
869  prms->operMode = UART_OPER_MODE_16X;
870  prms->rxTrigLvl = UART_RXTRIGLVL_8;
871  prms->txTrigLvl = UART_TXTRIGLVL_32;
872  }
873 }
874 
875 static inline void UART_Transaction_init(UART_Transaction *trans)
876 {
877  if(trans != NULL)
878  {
879  trans->buf = NULL;
880  trans->count = 0U;
881  trans->timeout = SystemP_WAIT_FOREVER;
882  trans->status = UART_TRANSFER_STATUS_SUCCESS;
883  trans->args = NULL;
884  }
885 }
886 
887 /* ========================================================================== */
888 /* Advanced Function Declarations */
889 /* ========================================================================== */
898 uint32_t UART_getBaseAddr(UART_Handle handle);
899 
908 void UART_enableLoopbackMode(uint32_t baseAddr);
909 
918 void UART_disableLoopbackMode(uint32_t baseAddr);
919 
937 static inline void UART_putChar(uint32_t baseAddr, uint8_t byteTx);
938 
953 static inline uint32_t UART_getChar(uint32_t baseAddr, uint8_t *pChar);
954 
983 static inline void UART_intrEnable(uint32_t baseAddr, uint32_t intrFlag);
984 
1009 static inline void UART_intrDisable(uint32_t baseAddr, uint32_t intrFlag);
1010 
1029 static inline void UART_intr2Enable(uint32_t baseAddr, uint32_t intrFlag);
1030 
1048 static inline void UART_intr2Disable(uint32_t baseAddr, uint32_t intrFlag);
1049 
1075 static inline uint32_t UART_getIntrIdentityStatus(uint32_t baseAddr);
1076 
1089 static inline uint32_t UART_getIntr2Status(uint32_t baseAddr);
1090 
1105 static inline uint32_t UART_checkCharsAvailInFifo(uint32_t baseAddr);
1106 
1117 static inline uint32_t UART_readLineStatus(uint32_t baseAddr);
1118 
1132 static inline uint8_t UART_getCharFifo(uint32_t baseAddr, uint8_t *readBuf);
1133 /* ========================================================================== */
1134 /* Advanced Function Definitions */
1135 /* ========================================================================== */
1136 static inline void UART_putChar(uint32_t baseAddr, uint8_t byteTx)
1137 {
1138  /* Write the byte to the Transmit Holding Register(or TX FIFO). */
1139  HW_WR_REG32(baseAddr + UART_THR, (uint32_t) byteTx);
1140 }
1141 
1142 static inline uint32_t UART_getChar(uint32_t baseAddr, uint8_t *pChar)
1143 {
1144  uint32_t lcrRegValue = 0U;
1145  uint32_t retVal = FALSE;
1146 
1147  /* Preserving the current value of LCR. */
1148  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1149 
1150  /* Switching to Register Operational Mode of operation. */
1151  HW_WR_REG32(baseAddr + UART_LCR, HW_RD_REG32(baseAddr + UART_LCR)
1152  & 0x7FU);
1153 
1154  /* Checking if the RX FIFO(or RHR) has atleast one byte of data. */
1155  if ((uint32_t) UART_LSR_RX_FIFO_E_RX_FIFO_E_VALUE_0 !=
1156  (HW_RD_REG32(baseAddr + UART_LSR) &
1157  UART_LSR_RX_FIFO_E_MASK))
1158  {
1159  uint32_t tempRetVal = HW_RD_REG32(baseAddr + UART_RHR);
1160  *pChar = (uint8_t)tempRetVal;
1161  retVal = TRUE;
1162  }
1163 
1164  /* Restoring the value of LCR. */
1165  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1166 
1167  return retVal;
1168 }
1169 
1170 static inline void UART_intrEnable(uint32_t baseAddr, uint32_t intrFlag)
1171 {
1172  uint32_t enhanFnBitVal = 0U;
1173  uint32_t lcrRegValue = 0U;
1174 
1175  /* Switch to mode B only when the upper 4 bits of IER needs to be changed */
1176  if ((intrFlag & 0xF0U) > 0U)
1177  {
1178  /* Preserving the current value of LCR. */
1179  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1180  /* Switching to Register Configuration Mode B. */
1181  HW_WR_REG32(baseAddr + UART_LCR, UART_REG_CONFIG_MODE_B & 0xFFU);
1182 
1183  /* Collecting the current value of EFR[4] and later setting it. */
1184  enhanFnBitVal = HW_RD_FIELD32(baseAddr + UART_EFR, UART_EFR_ENHANCED_EN);
1185 
1186  HW_WR_FIELD32(baseAddr + UART_EFR, UART_EFR_ENHANCED_EN,
1187  UART_EFR_ENHANCED_EN_ENHANCED_EN_U_VALUE_1);
1188 
1189  /* Restoring the value of LCR. */
1190  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1191 
1192  /* Preserving the current value of LCR. */
1193  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1194 
1195  /* Switching to Register Operational Mode of operation. */
1196  HW_WR_REG32(baseAddr + UART_LCR, HW_RD_REG32(baseAddr + UART_LCR)
1197  & 0x7FU);
1198 
1199  /*
1200  ** It is suggested that the System Interrupts for UART in the
1201  ** Interrupt Controller are enabled after enabling the peripheral
1202  ** interrupts of the UART using this API. If done otherwise, there
1203  ** is a risk of LCR value not getting restored and illicit characters
1204  ** transmitted or received from/to the UART. The situation is explained
1205  ** below.
1206  ** The scene is that the system interrupt for UART is already enabled
1207  ** and the current API is invoked. On enabling the interrupts
1208  ** corresponding to IER[7:4] bits below, if any of those interrupt
1209  ** conditions already existed, there is a possibility that the control
1210  ** goes to Interrupt Service Routine (ISR) without executing the
1211  ** remaining statements in this API. Executing the remaining statements
1212  ** is critical in that the LCR value is restored in them.
1213  ** However, there seems to be no risk in this API for enabling
1214  ** interrupts corresponding to IER[3:0] because it is done at the end
1215  ** and no statements follow that.
1216  */
1217 
1218  /************* ATOMIC STATEMENTS START *************************/
1219 
1220  /* Programming the bits IER[7:4]. */
1221  HW_WR_REG32(baseAddr + UART_IER, intrFlag & 0xF0U);
1222 
1223  /* Restoring the value of LCR. */
1224  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1225 
1226  /* Preserving the current value of LCR. */
1227  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1228  /* Switching to Register Configuration Mode B. */
1229  HW_WR_REG32(baseAddr + UART_LCR, UART_REG_CONFIG_MODE_B & 0xFFU);
1230 
1231  /* Restoring the value of EFR[4] to its original value. */
1232  HW_WR_FIELD32(baseAddr + UART_EFR, UART_EFR_ENHANCED_EN, enhanFnBitVal);
1233 
1234  /* Restoring the value of LCR. */
1235  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1236 
1237  /************** ATOMIC STATEMENTS END *************************/
1238  }
1239 
1240  /* Programming the bits IER[3:0]. */
1241  HW_WR_REG32(baseAddr + UART_IER, HW_RD_REG32(baseAddr + UART_IER) |
1242  (intrFlag & 0x0FU));
1243 }
1244 
1245 static inline void UART_intrDisable(uint32_t baseAddr, uint32_t intrFlag)
1246 {
1247  uint32_t enhanFnBitVal;
1248  uint32_t lcrRegValue;
1249 
1250  /* Switch to mode B only when the upper 4 bits of IER needs to be changed */
1251  if((intrFlag & 0xF0U) > 0U)
1252  {
1253  /* Preserving the current value of LCR. */
1254  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1255  /* Switching to Register Configuration Mode B. */
1256  HW_WR_REG32(baseAddr + UART_LCR, UART_REG_CONFIG_MODE_B & 0xFFU);
1257 
1258  /* Collecting the current value of EFR[4] and later setting it. */
1259  enhanFnBitVal = HW_RD_FIELD32(baseAddr + UART_EFR, UART_EFR_ENHANCED_EN);
1260 
1261  HW_WR_FIELD32(baseAddr + UART_EFR, UART_EFR_ENHANCED_EN,
1262  UART_EFR_ENHANCED_EN_ENHANCED_EN_U_VALUE_1);
1263 
1264  /* Restoring the value of LCR. */
1265  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1266  }
1267 
1268  /* Preserving the current value of LCR. */
1269  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1270 
1271  /* Switching to Register Operational Mode of operation. */
1272  HW_WR_REG32(baseAddr + UART_LCR, HW_RD_REG32(baseAddr + UART_LCR)
1273  & 0x7FU);
1274 
1275  HW_WR_REG32(baseAddr + UART_IER, HW_RD_REG32(baseAddr + UART_IER) &
1276  ~(intrFlag & 0xFFU));
1277 
1278  /* Restoring the value of LCR. */
1279  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1280 
1281  /* Switch to mode B only when the upper 4 bits of IER needs to be changed */
1282  if((intrFlag & 0xF0U) > 0U)
1283  {
1284  /* Preserving the current value of LCR. */
1285  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1286  /* Switching to Register Configuration Mode B. */
1287  HW_WR_REG32(baseAddr + UART_LCR, UART_REG_CONFIG_MODE_B & 0xFFU);
1288 
1289  /* Restoring the value of EFR[4] to its original value. */
1290  HW_WR_FIELD32(baseAddr + UART_EFR, UART_EFR_ENHANCED_EN, enhanFnBitVal);
1291 
1292  /* Restoring the value of LCR. */
1293  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1294  }
1295 }
1296 
1297 static inline void UART_intr2Enable(uint32_t baseAddr, uint32_t intrFlag)
1298 {
1299  /* Programming the bits IER2[1:0]. */
1300  HW_WR_REG32(baseAddr + UART_IER2, HW_RD_REG32(baseAddr + UART_IER2) |
1301  (intrFlag & 0x03U));
1302 }
1303 
1304 static inline void UART_intr2Disable(uint32_t baseAddr, uint32_t intrFlag)
1305 {
1306  HW_WR_REG32(baseAddr + UART_IER2, HW_RD_REG32(baseAddr + UART_IER2) &
1307  ~(intrFlag & 0x3U));
1308 }
1309 
1310 static inline uint32_t UART_getIntrIdentityStatus(uint32_t baseAddr)
1311 {
1312  uint32_t lcrRegValue = 0U;
1313  uint32_t retVal = 0U;
1314 
1315  /* Preserving the current value of LCR. */
1316  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1317 
1318  /* Switching to Register Operational Mode of operation. */
1319  HW_WR_REG32(baseAddr + UART_LCR, HW_RD_REG32(baseAddr + UART_LCR)
1320  & 0x7FU);
1321 
1322  retVal = HW_RD_REG32(baseAddr + UART_IIR) & UART_IIR_IT_TYPE_MASK;
1323 
1324  /* Restoring the value of LCR. */
1325  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1326 
1327  return retVal;
1328 }
1329 
1330 static inline uint32_t UART_getIntr2Status(uint32_t baseAddr)
1331 {
1332  uint32_t retVal = 0U;
1333 
1334  retVal = HW_RD_REG32(baseAddr + UART_ISR2) &
1335  (UART_IER2_EN_RXFIFO_EMPTY_MASK | UART_IER2_EN_TXFIFO_EMPTY_MASK);
1336 
1337  return retVal;
1338 }
1339 
1340 static inline uint32_t UART_checkCharsAvailInFifo(uint32_t baseAddr)
1341 {
1342  uint32_t lcrRegValue = 0;
1343  uint32_t retVal = FALSE;
1344 
1345  /* Preserving the current value of LCR. */
1346  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1347 
1348  /* Switching to Register Operational Mode of operation. */
1349  HW_WR_REG32(baseAddr + UART_LCR, HW_RD_REG32(baseAddr + UART_LCR)
1350  & 0x7FU);
1351 
1352  /* Checking if the RHR(or RX FIFO) has atleast one byte to be read. */
1353  if ((uint32_t) UART_LSR_RX_FIFO_E_RX_FIFO_E_VALUE_0 !=
1354  (HW_RD_REG32(baseAddr + UART_LSR) &
1355  UART_LSR_RX_FIFO_E_MASK))
1356  {
1357  retVal = (uint32_t) TRUE;
1358  }
1359 
1360  /* Restoring the value of LCR. */
1361  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1362 
1363  return retVal;
1364 }
1365 
1366 static inline uint32_t UART_readLineStatus(uint32_t baseAddr)
1367 {
1368  uint32_t lcrRegValue = 0U;
1369  uint32_t retVal = 0U;
1370 
1371  /* Preserving the current value of LCR. */
1372  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1373 
1374  /* Switching to Register Operational Mode of operation. */
1375  HW_WR_REG32(baseAddr + UART_LCR, HW_RD_REG32(baseAddr + UART_LCR)
1376  & 0x7FU);
1377 
1378  retVal = HW_RD_REG32(baseAddr + UART_LSR);
1379 
1380  /* Restoring the value of LCR. */
1381  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1382 
1383  return retVal;
1384 }
1385 
1386 static inline uint8_t UART_getCharFifo(uint32_t baseAddr, uint8_t *readBuf)
1387 {
1388  uint8_t readByte = 0;
1389  uint32_t waitCount = UART_ERROR_COUNT;
1390  uint32_t errorVal;
1391  uint32_t lcrRegValue = 0;
1392 
1393  /* Preserving the current value of LCR. */
1394  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1395 
1396  /* Switching to Register Operational Mode of operation. */
1397  HW_WR_REG32(baseAddr + UART_LCR, HW_RD_REG32(baseAddr + UART_LCR)
1398  & 0x7FU);
1399 
1400  /* Read Rx Error Status */
1401  errorVal = HW_RD_REG32(baseAddr + UART_LSR) &
1402  (UART_LSR_RX_FIFO_STS_MASK |
1403  UART_LSR_RX_BI_MASK |
1404  UART_LSR_RX_FE_MASK |
1405  UART_LSR_RX_PE_MASK |
1406  UART_LSR_RX_OE_MASK);
1407 
1408  /* Restoring the value of LCR. */
1409  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1410 
1411  /* Read and throw Erroneous bytes from RxFIFO */
1412  while ((UART_LSR_RX_FIFO_STS_MASK |
1413  UART_LSR_RX_BI_MASK |
1414  UART_LSR_RX_FE_MASK |
1415  UART_LSR_RX_PE_MASK |
1416  UART_LSR_RX_OE_MASK) == errorVal)
1417  {
1418  readByte = HW_RD_REG32(baseAddr + UART_RHR);
1419  waitCount--;
1420  if (0U == waitCount)
1421  {
1422  break;
1423  }
1424 
1425  /* Preserving the current value of LCR. */
1426  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1427 
1428  /* Switching to Register Operational Mode of operation. */
1429  HW_WR_REG32(baseAddr + UART_LCR, HW_RD_REG32(baseAddr + UART_LCR)
1430  & 0x7FU);
1431 
1432  /* Read Rx Error Status */
1433  errorVal = HW_RD_REG32(baseAddr + UART_LSR) &
1434  (UART_LSR_RX_FIFO_STS_MASK |
1435  UART_LSR_RX_BI_MASK |
1436  UART_LSR_RX_FE_MASK |
1437  UART_LSR_RX_PE_MASK |
1438  UART_LSR_RX_OE_MASK);
1439 
1440  /* Restoring the value of LCR. */
1441  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1442  }
1443 
1444  /* Read non-erroneous byte from RxFIFO */
1445  readByte = HW_RD_REG32(baseAddr + UART_RHR);
1446 
1447  return readByte;
1448 }
1449 
1450 #ifdef __cplusplus
1451 }
1452 #endif
1453 
1454 #endif /* #ifndef UART_V0_H_ */
1455 
UART_enableLoopbackMode
void UART_enableLoopbackMode(uint32_t baseAddr)
Function to enable loopback mode. This function is for internal use. Not recommended for customers to...
UART_deinit
void UART_deinit(void)
This function de-initializes the UART module.
UART_Object::readTransferSem
void * readTransferSem
Definition: uart/v0/uart.h:581
UART_ERROR_COUNT
#define UART_ERROR_COUNT
Count Value to check error in the recieved byte
Definition: uart/v0/uart.h:82
UART_TRANSFER_MODE_BLOCKING
#define UART_TRANSFER_MODE_BLOCKING
UART read/write APIs blocks execution. This mode can only be used when called within a Task context.
Definition: uart/v0/uart.h:138
UART_Object::lockObj
SemaphoreP_Object lockObj
Definition: uart/v0/uart.h:579
UART_Transaction_init
static void UART_Transaction_init(UART_Transaction *trans)
Function to initialize the UART_Transaction struct to its defaults.
Definition: uart/v0/uart.h:875
UART_Object::readTransferSemObj
SemaphoreP_Object readTransferSemObj
Definition: uart/v0/uart.h:584
UART_REG_CONFIG_MODE_B
#define UART_REG_CONFIG_MODE_B
Definition: uart/v0/uart.h:396
UART_STOPBITS_1
#define UART_STOPBITS_1
Definition: uart/v0/uart.h:195
UART_TRANSFER_STATUS_SUCCESS
#define UART_TRANSFER_STATUS_SUCCESS
Transaction success.
Definition: uart/v0/uart.h:96
UART_Object::handle
UART_Handle handle
Definition: uart/v0/uart.h:539
UART_intr2Enable
static void UART_intr2Enable(uint32_t baseAddr, uint32_t intrFlag)
This API enables the specified interrupts in the UART mode of operation for IER2.
Definition: uart/v0/uart.h:1297
UART_Object::hwiHandle
void * hwiHandle
Definition: uart/v0/uart.h:591
UART_Object::writeBuf
const void * writeBuf
Definition: uart/v0/uart.h:546
SystemP.h
UART_Transaction::timeout
uint32_t timeout
Definition: uart/v0/uart.h:431
UART_Handle
void * UART_Handle
A handle that is returned from a UART_open() call.
Definition: uart/v0/uart.h:85
UART_Object::writeTrans
UART_Transaction * writeTrans
Definition: uart/v0/uart.h:570
UART_getHandle
UART_Handle UART_getHandle(uint32_t index)
Function to return a open'ed UART handle given a UART instance index.
UART_writeCancel
int32_t UART_writeCancel(UART_Handle handle, UART_Transaction *trans)
Function to perform UART canceling of current write transaction.
UART_Config
UART global configuration array.
Definition: uart/v0/uart.h:606
UART_Params::writeMode
uint32_t writeMode
Definition: uart/v0/uart.h:473
UART_getIntr2Status
static uint32_t UART_getIntr2Status(uint32_t baseAddr)
This API determines the UART Interrupt Status 2.
Definition: uart/v0/uart.h:1330
UART_Object::writeSizeRemaining
uint32_t writeSizeRemaining
Definition: uart/v0/uart.h:550
UART_CallbackFxn
void(* UART_CallbackFxn)(UART_Handle handle, UART_Transaction *transaction)
The definition of a callback function used by the UART driver when used in UART_TRANSFER_MODE_CALLBAC...
Definition: uart/v0/uart.h:446
UART_Params::dataLength
uint32_t dataLength
Definition: uart/v0/uart.h:463
SystemP_WAIT_FOREVER
#define SystemP_WAIT_FOREVER
Value to use when needing a timeout of infinity or wait forver until resource is available.
Definition: SystemP.h:83
UART_Params::intrPriority
uint8_t intrPriority
Definition: uart/v0/uart.h:491
UART_write
int32_t UART_write(UART_Handle handle, UART_Transaction *trans)
Function to perform UART write operation.
UART_Params::readMode
uint32_t readMode
Definition: uart/v0/uart.h:469
UART_RXTRIGLVL_8
#define UART_RXTRIGLVL_8
Definition: uart/v0/uart.h:265
SemaphoreP.h
UART_intrDisable
static void UART_intrDisable(uint32_t baseAddr, uint32_t intrFlag)
This API disables the specified interrupts in the UART mode of operation.
Definition: uart/v0/uart.h:1245
UART_disableLoopbackMode
void UART_disableLoopbackMode(uint32_t baseAddr)
Function to disable loopback mode. This function is for internal use. Not recommended for customers t...
UART_PARITY_NONE
#define UART_PARITY_NONE
Definition: uart/v0/uart.h:207
UART_Params::rxTrigLvl
uint32_t rxTrigLvl
Definition: uart/v0/uart.h:505
UART_getChar
static uint32_t UART_getChar(uint32_t baseAddr, uint8_t *pChar)
This API reads a byte from the Receiver Buffer Register (RBR). It checks once if any character is rea...
Definition: uart/v0/uart.h:1142
UART_close
void UART_close(UART_Handle handle)
Function to close a UART peripheral specified by the UART handle.
gUartConfig
UART_Config gUartConfig[]
Externally defined driver configuration array.
UART_getIntrIdentityStatus
static uint32_t UART_getIntrIdentityStatus(uint32_t baseAddr)
This API determines the UART Interrupt Status.
Definition: uart/v0/uart.h:1310
UART_Transaction::args
void * args
Definition: uart/v0/uart.h:435
UART_Params::uartDmaIndex
int32_t uartDmaIndex
Definition: uart/v0/uart.h:495
UART_Object::uartDmaHandle
void * uartDmaHandle
Definition: uart/v0/uart.h:595
UART_READ_RETURN_MODE_FULL
#define UART_READ_RETURN_MODE_FULL
Unblock/callback when buffer is full.
Definition: uart/v0/uart.h:166
UART_Object::isOpen
uint32_t isOpen
Definition: uart/v0/uart.h:575
UART_flushTxFifo
void UART_flushTxFifo(UART_Handle handle)
Function to flush a TX FIFO of peripheral specified by the UART handle.
UART_Params::transferMode
uint32_t transferMode
Definition: uart/v0/uart.h:487
UART_Params::skipIntrReg
uint32_t skipIntrReg
Definition: uart/v0/uart.h:493
UART_Config::attrs
UART_Attrs * attrs
Definition: uart/v0/uart.h:607
UART_Object::writeTransferSemObj
SemaphoreP_Object writeTransferSemObj
Definition: uart/v0/uart.h:589
UART_Object::lock
void * lock
Definition: uart/v0/uart.h:577
UART_Object::readCount
uint32_t readCount
Definition: uart/v0/uart.h:557
UART_Params::parityType
uint32_t parityType
Definition: uart/v0/uart.h:467
UART_Object::rxTimeoutCnt
uint32_t rxTimeoutCnt
Definition: uart/v0/uart.h:561
UART_putChar
static void UART_putChar(uint32_t baseAddr, uint8_t byteTx)
This API writes a byte to the Transmitter FIFO without checking for the emptiness of the Transmitter ...
Definition: uart/v0/uart.h:1136
UART_Object::writeCount
uint32_t writeCount
Definition: uart/v0/uart.h:548
UART_Params::hwFlowControl
uint32_t hwFlowControl
Definition: uart/v0/uart.h:479
UART_Object::readSizeRemaining
uint32_t readSizeRemaining
Definition: uart/v0/uart.h:559
UART_Params::readReturnMode
uint32_t readReturnMode
Definition: uart/v0/uart.h:471
HwiP.h
UART_init
void UART_init(void)
This function initializes the UART module.
UART_Params
UART Parameters.
Definition: uart/v0/uart.h:460
UART_readCancel
int32_t UART_readCancel(UART_Handle handle, UART_Transaction *trans)
Function to perform UART canceling of current read transaction.
UART_Params::baudRate
uint32_t baudRate
Definition: uart/v0/uart.h:461
UART_Params::readCallbackFxn
UART_CallbackFxn readCallbackFxn
Definition: uart/v0/uart.h:475
UART_Object::readErrorCnt
uint32_t readErrorCnt
Definition: uart/v0/uart.h:563
UART_Object::writeTransferSem
void * writeTransferSem
Definition: uart/v0/uart.h:586
UART_Transaction::status
uint32_t status
Definition: uart/v0/uart.h:433
UART_Config::object
UART_Object * object
Definition: uart/v0/uart.h:609
UART_Transaction
Data structure used with UART_read() and UART_write()
Definition: uart/v0/uart.h:423
UART_getBaseAddr
uint32_t UART_getBaseAddr(UART_Handle handle)
Function to get base address of UART instance of a particular handle.
UART_LEN_8
#define UART_LEN_8
Definition: uart/v0/uart.h:184
UART_checkCharsAvailInFifo
static uint32_t UART_checkCharsAvailInFifo(uint32_t baseAddr)
This API checks if the RX FIFO (or RHR in non-FIFO mode) has atleast one byte of data to be read.
Definition: uart/v0/uart.h:1340
UART_Params::intrNum
uint32_t intrNum
Definition: uart/v0/uart.h:489
UART_Attrs::inputClkFreq
uint32_t inputClkFreq
Definition: uart/v0/uart.h:523
UART_open
UART_Handle UART_open(uint32_t index, const UART_Params *prms)
This function opens a given UART peripheral.
UART_CONFIG_MODE_INTERRUPT
#define UART_CONFIG_MODE_INTERRUPT
Definition: uart/v0/uart.h:410
UART_Params::writeCallbackFxn
UART_CallbackFxn writeCallbackFxn
Definition: uart/v0/uart.h:477
HwiP_Object
Opaque Hwi object used with the Hwi APIs.
Definition: HwiP.h:91
UART_Object
UART driver object.
Definition: uart/v0/uart.h:535
UART_Params::hwFlowControlThr
uint32_t hwFlowControlThr
Definition: uart/v0/uart.h:481
UART_Object::readTrans
UART_Transaction * readTrans
Definition: uart/v0/uart.h:568
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uint32_t stopBits
Definition: uart/v0/uart.h:465
UART_intr2Disable
static void UART_intr2Disable(uint32_t baseAddr, uint32_t intrFlag)
This API disables the specified interrupts in the UART mode of operation for IER2.
Definition: uart/v0/uart.h:1304
UART_Object::readBuf
void * readBuf
Definition: uart/v0/uart.h:555
UART_Params::rxEvtNum
uint32_t rxEvtNum
Definition: uart/v0/uart.h:509
UART_Params_init
static void UART_Params_init(UART_Params *prms)
Function to initialize the UART_Params struct to its defaults.
Definition: uart/v0/uart.h:849
gUartConfigNum
uint32_t gUartConfigNum
Externally defined driver configuration array size.
SemaphoreP_Object
Opaque semaphore object used with the semaphore APIs.
Definition: SemaphoreP.h:59
UART_read
int32_t UART_read(UART_Handle handle, UART_Transaction *trans)
Function to perform UART read operation.
UART_TXTRIGLVL_32
#define UART_TXTRIGLVL_32
Definition: uart/v0/uart.h:282
UART_OPER_MODE_16X
#define UART_OPER_MODE_16X
Definition: uart/v0/uart.h:294
UART_Attrs
UART instance attributes - used during init time.
Definition: uart/v0/uart.h:517
UART_RXTRIGLVL_16
#define UART_RXTRIGLVL_16
Definition: uart/v0/uart.h:266
UART_readLineStatus
static uint32_t UART_readLineStatus(uint32_t baseAddr)
This API reads the line status register value.
Definition: uart/v0/uart.h:1366
UART_Params::txEvtNum
uint32_t txEvtNum
Definition: uart/v0/uart.h:511
UART_getCharFifo
static uint8_t UART_getCharFifo(uint32_t baseAddr, uint8_t *readBuf)
This API reads the data present at the top of the RX FIFO, that is, the data in the Receive Holding R...
Definition: uart/v0/uart.h:1386
UART_Attrs::baseAddr
uint32_t baseAddr
Definition: uart/v0/uart.h:521
UART_Transaction::buf
void * buf
Definition: uart/v0/uart.h:424
UART_intrEnable
static void UART_intrEnable(uint32_t baseAddr, uint32_t intrFlag)
This API enables the specified interrupts in the UART mode of operation.
Definition: uart/v0/uart.h:1170
UART_Object::hwiObj
HwiP_Object hwiObj
Definition: uart/v0/uart.h:593
UART_Object::prms
UART_Params prms
Definition: uart/v0/uart.h:541
UART_Transaction::count
uint32_t count
Definition: uart/v0/uart.h:427
UART_Params::txTrigLvl
uint32_t txTrigLvl
Definition: uart/v0/uart.h:507
UART_Params::operMode
uint32_t operMode
Definition: uart/v0/uart.h:503