| Module | Supported CPUs | SysConfig Support | OS support | Key features tested | Key features not tested / NOT supported |
| Cache | R5F | YES | FreeRTOS, NORTOS | Cache write back, invalidate, enable/disable | - |
| Clock | R5F | YES | FreeRTOS, NORTOS | Tick timer at user specified resolution, timeouts and delays | - |
| CpuId | R5F | NA | FreeRTOS, NORTOS | Verify Core ID and Cluster ID that application is currently running on | - |
| CycleCounter | R5F | NA | FreeRTOS, NORTOS | Measure CPU cycles using CPU specific internal counters | - |
| Debug | R5F | YES | FreeRTOS, NORTOS | Logging and assert to any combo of: UART, CCS, shared memory | - |
| Heap | R5F | NA | FreeRTOS, NORTOS | Create arbitrary heaps in user defined memory segments | - |
| Hwi | R5F | YES | FreeRTOS, NORTOS | Interrupt register, enable/disable/restore, Interrupt prioritization | - |
| MPU | R5F | YES | FreeRTOS, NORTOS | Setup MPU and control access to address space | - |
| Semaphore | R5F | NA | FreeRTOS, NORTOS | Binary, Counting Semaphore, recursive mutexs with timeout | - |
| Task | R5F | NA | FreeRTOS | Create, delete tasks | - |
| Timer | R5F | YES | FreeRTOS, NORTOS | Configure arbitrary timers | - |
| Peripheral | Supported CPUs | SysConfig Support | DMA Supported | Key features tested | Key features not tested / NOT supported |
| ADC | R5F | YES | Yes. Example: adc_soc_continuous_dma | Single software triggered conversion, Multiple ADC trigger using PWM, Result read using DMA, EPWM trip through PPB limit, burst mode oversampling | - |
| Bootloader | R5F | YES | Yes. DMA enabled for SBL QSPI | Boot modes: QSPI, UART. All R5F's | - |
| CMPSS | R5F | YES | NA | Asynchronous PWM trip | - |
| CPSW | R5F | YES | No | MAC loopback, PHY loopback, LWIP: Getting IP, Ping, Iperf, Layer 2 MAC, Layer 2 PTP Timestamping and CPSW Switch support | - |
| DAC | R5F | YES | Yes. Example: dac_sine_dma | Constant voltage, Square wave generation, Sine wave generation with and without DMA, Ramp wave generation, Random Voltage generation | - |
| ECAP | R5F | YES | No | ECAP APWM mode, PWM capture | - |
| EDMA | R5F | YES | NA | DMA transfer using interrupt and polling mode, QDMA Transfer, Channel Chaining, PaRAM Linking | - |
| EPWM | R5F | YES | Yes. Example: epwm_dma | PWM outputs A and B in up-down count mode, Trip zone, Update PWM using EDMA, Valley switching, High resolution time period adjustment | XCMP feature not tested |
| EQEP | R5F | YES | NA | Speed and Position measurement. | Frequency Measurement not tested |
| FSI | R5F | YES | No | RX, TX, polling, interrupt mode, single lane loopback. | - |
| GPIO | R5F | YES | NA | Output, Input and Interrupt functionality | - |
| I2C | R5F | YES | No | Master mode, basic read/write | - |
| IPC Notify | R5F | YES | NA | Mailbox functionality, IPC between RTOS/NORTOS CPUs | M4F core |
| IPC Rpmsg | R5F | YES | NA | RPMessage protocol based IPC | M4F core |
| MCAN | R5F | YES | No | RX, TX, interrupt and polling mode | Bus Off |
| MCSPI | R5F | YES | Yes. Example: mcspi_loopback_dma | Master/Slave mode, basic read/write, polling, interrupt and DMA mode | - |
| MDIO | R5F | YES | NA | Register read/write, link status and link interrupt enable API | - |
| MPU Firewall | R5F | YES | NA | Only compiled (Works only on HS-SE device) | - |
| PINMUX | R5F | YES | NA | Tested with multiple peripheral pinmuxes | - |
| PRUICSS | R5F | YES | NA | Tested with Ethercat FW HAL | - |
| QSPI | R5F | YES | Yes. Example: qspi_flash_dma_transfer | Read direct, Write indirect, Read/Write commands, DMA for read | - |
| SDFM | R5F | YES | No | Filter data read from CPU, Filter data read with PWM sync | - |
| SOC | R5F | YES | NA | Lock/unlock MMRs, clock enable, set Hz, Xbar configuration | - |
| SPINLOCK | R5F | NA | NA | Lock, unlock HW spinlocks | - |
| UART | R5F | YES | No | Basic read/write at baud rate 115200, polling, interrupt mode | HW flow control not tested, DMA mode not supported |
| WATCHDOG | R5F | YES | NA | Reset mode | Interrupt mode |
| ID | Head Line | Module | Applicable Releases | Applicable Devices | Resolution/Comments |
| MCUSDK-2254 | SBL QSPI bootmode is not working with DMA enabled | SBL | 08_02_01 | AM263x | EDMA Parameters were configured incorrectly. Enabled DMA by default in SBL SYSCFG. |
| MCUSDK-3398 | Address translation for R5FSS1 is missing | SBL | 08_02_00 | AM263x | Fixed |
| MCUSDK-3408 | sbl_uart_uniflash extra bytes written to the flash when flashing images | SBL | 08_02_00 | AM263x | Added a parameter actual file size in the uniflash header. This parameter will be used to determine how many bytes to flash |
| MCUSDK-3618 | AM263x: ePWM_setPhaseShift() API function doesn't correctly configure TBPHS | EPWM | 08_02_00 | AM263x | EPWM_setPhaseShift() uses 16-bit read/write, but TBPHS is a 32-bit register. Hence EPWM_setPhaseShift() doesn't take effect. Problem is resolved in 32-bit read/write is used instead of 16-bit read/write. |
| MCUSDK-3773 | Enet LWIP example fails with SBL on AM263X-LP | SBL, LWIP | 08_02_01 | AM263x | Increased the memory region for updated Descriptor memory |
| MCUSDK-3774 | Multi Core application with SBL QSPI DMA enabled is failing on AM263X-LP | EDMA, IPC_Notify, SBL | 08_02_01 | AM263x | For R5SS0-1 core, 0x8000 is the address where reset vectors needs to be copied. But in SBL QSPI with DMA enabled, actual physical address need to be passed while copying reset vectors via EDMA. During SBL execution R5SS0-0 core runs in Lockstep mode so Virtual to Physical Address calculation need to use LockStep TCM Size i.e. 64KB but only 32KB(R5SS0-0) is used.Updated this API. |
| MCUSDK-3804 | SDFM: API doc/comments: Valid value macros have unexpected CSL_ prefix | SDFM | 08_02_00 | AM263x | Fixed. Removed unwanted CSL_ prefix used in the documentation/comments for SDFM macros |
| MCUSDK-3823 | Wrong boot mode documentation for LP | Docs | 08_02_01 | AM263x | Boot mode switch setting not consistent in LP and CC. Fixed BOOT MODE documentation in Getting Started -> EVM Setup page. |
| MCUSDK-3864 | DAC: Incorrect reference voltage selection macros | DAC | 08_02_01 | AM263x | Fixed. enum DAC_ReferenceVoltage is now corrected with "DAC_REF_VREF and DAC_REF_VDDA" from "DAC_REF_VDAC and DAC_REF_ADC_VREFHI" |
| MCUSDK-3930 | DAC Sysconfig: Incorrect argument passed to DAC_setPWMSyncSignal results in ASSERT | DAC | 08_02_01 | AM263x | Fixed. Sysconfig scripts fixed to pass correct argument (1-32 for EPWM0-EPWM31) as per the DAC_setPWMSyncSignal requirement |
| ID | Head Line | Module | Reported in release | Workaround |
| MCUSDK-1016 | Semaphore does not function as expected when "post" call is present in multiple ISRs at different priorities | DPL, FreeRTOS | 08_00_03 | Disable interrupt nesting |
| MCUSDK-2252 | GPIO Pin Direction | GPIO. GPIO Pin Direction not getting automatically configured. | 08_00_02 | Use GPIO_setDirMode to set pin direction for GPIO pin. |
| MCUSDK-2464 | ADC sysconfig code generation issue | ADC | 08_00_03 | - |
| MCUSDK-2557 | eqep_frequency_measurement example is failing | SBL | 08_02_00 | - |
| MCUSDK-2703 | Interrupt XBAR instance for FSI is static | FSI | 08_00_03 | - |
| MCUSDK-3336 | FSI is not functional with clock divider value more than 8 | FSI | 08_02_00 | - |
| MCUSDK-3436 | QSPI flashing fails with uniflash | Flash | 08_02_00 | - |
| MCUSDK-3869 | AM263x - LwIP ICMP tests fails | Enet, LWIP | 08_02_00 | - |
| MCUSDK-3886 | MDIO - Phy link issue for MAC PORT 1 on am263x-lp | Enet, LWIP | 08_02_01 | - |
| SITARAAPPS-2040 | Dual Core configuration issue with CSP 1.1.3 (Sitara MCU Device Support) on AM263x | CSP Gel Scripts | 08_02_01 | Edit gel file as mentioned in Prerequisites while running multi core applications. |
1.8.20