soc.h

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/*
 *  Copyright (C) 2021 Texas Instruments Incorporated
 *
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 *  modification, are permitted provided that the following conditions
 *  are met:
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 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
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 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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 */
 
#ifndef SOC_AM263X_H_
#define SOC_AM263X_H_
 
#ifdef __cplusplus
extern "C"
{
#endif
 
#include <kernel/dpl/SystemP.h>
#include <drivers/hw_include/cslr_soc.h>
#include "soc_xbar.h"
#include "soc_rcm.h"
 
#define SOC_DOMAIN_ID_MAIN     (0U)
 
/*Control MMRs partition*/
#define MSS_CTRL_PARTITION0                                (1)
#define TOP_CTRL_PARTITION0                                (2)
#define CONTROLSS_CTRL_PARTITION0                          (3)
 
/*Clock and reset MMRs partition*/
#define MSS_RCM_PARTITION0                                 (4)
#define TOP_RCM_PARTITION0                                 (5)
 
/*Pinmux MMR*/
//#define IOMUX_PARTITION0                                   (6)
 
 
/* define the unlock and lock values for MSS_CTRL, TOP_CTRL, MSS_RCM, TOP_RCM*/
#define KICK_LOCK_VAL                           (0x00000000U)
#define KICK0_UNLOCK_VAL                        (0x01234567U)
#define KICK1_UNLOCK_VAL                        (0x0FEDCBA8U)
 
int32_t SOC_moduleClockEnable(uint32_t moduleId, uint32_t enable);
 
int32_t SOC_moduleSetClockFrequency(uint32_t moduleId, uint32_t clkId, uint64_t clkRate);
 
const char *SOC_getCoreName(uint16_t coreId);
 
uint64_t SOC_getSelfCpuClk(void);
 
void SOC_controlModuleLockMMR(uint32_t domainId, uint32_t partition);
 
void SOC_controlModuleUnlockMMR(uint32_t domainId, uint32_t partition);
 
void SOC_setEpwmTbClk(uint32_t epwmInstance, uint32_t enable);
 
void SOC_enableAdcReference(uint32_t adcInstance);
 
void SOC_setEpwmGroup(uint32_t epwmInstance, uint32_t group);
 
void SOC_gateEpwmClock(uint32_t epwmInstance);
 
void SOC_gateFsitxClock(uint32_t fsitxInstance);
 
void SOC_gateFsirxClock(uint32_t fsirxInstance);
 
void SOC_gateCmpssaClock(uint32_t cmpssaInstance);
 
void SOC_gateCmpssbClock(uint32_t cmpssbInstance);
 
void SOC_gateEcapClock(uint32_t ecapInstance);
 
void SOC_gateEqepClock(uint32_t eqepInstance);
 
void SOC_gateSdfmClock(uint32_t sdfmInstance);
 
void SOC_gateDacClock();
 
void SOC_gateAdcClock(uint32_t adcInstance);
 
void SOC_gateOttoClock(uint32_t ottoInstance);
 
void SOC_gateSdfmPllClock(uint32_t sdfmInstance);
 
void SOC_gateFsiPllClock(uint32_t fsiInstance);
 
void SOC_generateEpwmReset(uint32_t ePWMInstance);
 
void SOC_generateFsiTxReset(uint32_t fsitxInstance);
 
void SOC_generateFsiRxReset(uint32_t fsirxInstance);
 
void SOC_generateCmpssaReset(uint32_t cmpssaInstance);
 
void SOC_generateCmpssbReset(uint32_t cmpssbInstance);
 
void SOC_generateEcapReset(uint32_t ecapInstance);
 
void SOC_generateEqepReset(uint32_t eqepInstance);
 
void SOC_generateSdfmReset(uint32_t sdfmInstance);
 
void SOC_generateDacReset();
 
void SOC_generateAdcReset(uint32_t adcInstance);
 
void SOC_generateOttoReset(uint32_t ottoInstance);
 
uint64_t SOC_virtToPhy(void *virtAddr);
 
void *SOC_phyToVirt(uint64_t phyAddr);
 
#ifdef __cplusplus
}
#endif
 
#endif