AM263x MCU+ SDK  08.02.00
gpio/v0/gpio.h
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31  */
32 
55 #ifndef GPIO_V0_H_
56 #define GPIO_V0_H_
57 
58 /* ========================================================================== */
59 /* Include Files */
60 /* ========================================================================== */
61 
62 #include <drivers/hw_include/cslr.h>
63 #include <drivers/hw_include/cslr_gpio.h>
64 
65 #ifdef __cplusplus
66 extern "C" {
67 #endif
68 
69 /* ========================================================================== */
70 /* Macros & Typedefs */
71 /* ========================================================================== */
72 
79 #define GPIO_PIN_LOW (0U)
80 
81 #define GPIO_PIN_HIGH (1U)
82 
89 #define GPIO_DIRECTION_OUTPUT (0U)
90 #define GPIO_DIRECTION_INPUT (1U)
91 
99 #define GPIO_TRIG_TYPE_NONE (0U)
100 
101 #define GPIO_TRIG_TYPE_RISE_EDGE (1U)
102 
103 #define GPIO_TRIG_TYPE_FALL_EDGE (2U)
104 
105 #define GPIO_TRIG_TYPE_BOTH_EDGE (3U)
106 
109 #define GPIO_MAX_BANKS (9U)
110 
111 #define GPIO_MAX_PIN_PER_BANK (16U)
112 
113 #define GPIO_MAX_PIN_PER_INSTANCE (GPIO_MAX_BANKS * GPIO_MAX_PIN_PER_BANK)
114 
116 #define GPIO_BANKS_PER_REG (2U)
117 
118 #define GPIO_PINS_PER_REG (GPIO_BANKS_PER_REG * GPIO_MAX_PIN_PER_BANK)
119 
121 #define GPIO_PINS_PER_REG_SHIFT (5U)
122 
123 #define GPIO_PINS_PER_BANK_SHIFT (4U)
124 
126 #define GPIO_GET_BANK_INDEX(pinNum) (((uint32_t) pinNum) >> GPIO_PINS_PER_BANK_SHIFT)
127 
128 #define GPIO_GET_REG_INDEX(pinNum) (((uint32_t) pinNum) >> GPIO_PINS_PER_REG_SHIFT)
129 
130 #define GPIO_GET_BIT_POS(pinNum) (pinNum - ((GPIO_GET_REG_INDEX(pinNum)) << GPIO_PINS_PER_REG_SHIFT))
131 
132 #define GPIO_GET_BIT_MASK(pinNum) (((uint32_t) 1U) << GPIO_GET_BIT_POS(pinNum))
133 
134 #define GPIO_GET_BANK_BIT_POS(pinNum) (pinNum - ((GPIO_GET_BANK_INDEX(pinNum)) << GPIO_PINS_PER_BANK_SHIFT))
135 
136 #define GPIO_GET_BANK_BIT_MASK(pinNum) (((uint32_t) 1U) << GPIO_GET_BANK_BIT_POS(pinNum))
137 
138 /* ========================================================================== */
139 /* Structures and Enums */
140 /* ========================================================================== */
141 
142 /* None */
143 
144 /* ========================================================================== */
145 /* Global Variables Declarations */
146 /* ========================================================================== */
147 
148 /* None */
149 
150 /* ========================================================================== */
151 /* Function Declarations */
152 /* ========================================================================== */
153 
166 void GPIO_setDirMode(uint32_t baseAddr, uint32_t pinNum, uint32_t pinDir);
167 
176 static inline void GPIO_pinWriteHigh(uint32_t baseAddr, uint32_t pinNum);
177 
186 static inline void GPIO_pinWriteLow(uint32_t baseAddr, uint32_t pinNum);
187 
199 uint32_t GPIO_pinRead(uint32_t baseAddr, uint32_t pinNum);
200 
212 uint32_t GPIO_pinOutValueRead(uint32_t baseAddr, uint32_t pinNum);
213 
233 void GPIO_setTrigType(uint32_t baseAddr, uint32_t pinNum, uint32_t trigType);
234 
244 void GPIO_bankIntrEnable(uint32_t baseAddr, uint32_t bankNum);
245 
254 void GPIO_bankIntrDisable(uint32_t baseAddr, uint32_t bankNum);
255 
270 static inline uint32_t GPIO_getIntrStatus(uint32_t baseAddr, uint32_t pinNum);
271 
281 static inline void GPIO_clearIntrStatus(uint32_t baseAddr, uint32_t pinNum);
282 
292 static inline uint32_t GPIO_getBankIntrStatus(uint32_t baseAddr, uint32_t bankNum);
293 
301 static inline void GPIO_clearBankIntrStatus(uint32_t baseAddr,
302  uint32_t bankNum,
303  uint32_t intrStatus);
304 
305 /* ========================================================================== */
306 /* Static Function Definitions */
307 /* ========================================================================== */
308 
309 static inline void GPIO_pinWriteHigh(uint32_t baseAddr, uint32_t pinNum)
310 {
311  uint32_t regIndex, regVal;
312  volatile CSL_GpioRegs* hGpio = (volatile CSL_GpioRegs*)((uintptr_t) baseAddr);
313 
314  regIndex = GPIO_GET_REG_INDEX(pinNum);
315  regVal = GPIO_GET_BIT_MASK(pinNum);
316  CSL_REG32_WR(&hGpio->BANK_REGISTERS[regIndex].SET_DATA, regVal);
317 
318  return;
319 }
320 
321 static inline void GPIO_pinWriteLow(uint32_t baseAddr, uint32_t pinNum)
322 {
323  uint32_t regIndex, regVal;
324  volatile CSL_GpioRegs* hGpio = (volatile CSL_GpioRegs*)((uintptr_t) baseAddr);
325 
326  regIndex = GPIO_GET_REG_INDEX(pinNum);
327  regVal = GPIO_GET_BIT_MASK(pinNum);
328  CSL_REG32_WR(&hGpio->BANK_REGISTERS[regIndex].CLR_DATA, regVal);
329 
330  return;
331 }
332 
333 static inline uint32_t GPIO_getIntrStatus(uint32_t baseAddr, uint32_t pinNum)
334 {
335  uint32_t intrStatus;
336  uint32_t regIndex, bitPos;
337  volatile CSL_GpioRegs* hGpio = (volatile CSL_GpioRegs*)((uintptr_t) baseAddr);
338 
339  regIndex = GPIO_GET_REG_INDEX(pinNum);
340  bitPos = GPIO_GET_BIT_POS(pinNum);
341  intrStatus = CSL_FEXTR(hGpio->BANK_REGISTERS[regIndex].INTSTAT, bitPos, bitPos);
342 
343  return (intrStatus);
344 }
345 
346 static inline void GPIO_clearIntrStatus(uint32_t baseAddr, uint32_t pinNum)
347 {
348  uint32_t regIndex, regVal;
349  volatile CSL_GpioRegs* hGpio = (volatile CSL_GpioRegs*)((uintptr_t) baseAddr);
350 
351  /* Clear the interrupt status of specified gpio pin */
352  regIndex = GPIO_GET_REG_INDEX(pinNum);
353  regVal = GPIO_GET_BIT_MASK(pinNum);
354  CSL_REG32_WR(&hGpio->BANK_REGISTERS[regIndex].INTSTAT, regVal);
355 
356  return;
357 }
358 
359 static inline uint32_t GPIO_getBankIntrStatus(uint32_t baseAddr, uint32_t bankNum)
360 {
361  uint32_t intrStatus, regIdx = bankNum >> 1U;
362  volatile CSL_GpioRegs* hGpio = (volatile CSL_GpioRegs*)((uintptr_t) baseAddr);
363 
364  intrStatus = CSL_REG32_RD(&hGpio->BANK_REGISTERS[regIdx].INTSTAT);
365  if(bankNum & 0x01U)
366  {
367  intrStatus >>= GPIO_MAX_PIN_PER_BANK; /* Odd number bank - upper 16-bits are used */
368  }
369  intrStatus &= 0xFFFFU;
370 
371  return (intrStatus);
372 }
373 
374 static inline void GPIO_clearBankIntrStatus(uint32_t baseAddr,
375  uint32_t bankNum,
376  uint32_t intrStatus)
377 {
378  uint32_t regIdx = bankNum >> 1U;
379  volatile CSL_GpioRegs* hGpio = (volatile CSL_GpioRegs*)((uintptr_t) baseAddr);
380 
381  /* Clear the interrupt status of gpio bank */
382  intrStatus &= 0xFFFFU;
383  if(bankNum & 0x01U)
384  {
385  intrStatus <<= GPIO_MAX_PIN_PER_BANK; /* Odd number bank - upper 16-bits are used */
386  }
387  CSL_REG32_WR(&hGpio->BANK_REGISTERS[regIdx].INTSTAT, intrStatus);
388 
389  return;
390 }
391 
392 #ifdef __cplusplus
393 }
394 #endif
395 
396 #endif /* #ifndef GPIO_V0_H_ */
397 
GPIO_GET_BIT_MASK
#define GPIO_GET_BIT_MASK(pinNum)
Returns the bit mask within a register based on pin number.
Definition: gpio/v0/gpio.h:132
GPIO_getIntrStatus
static uint32_t GPIO_getIntrStatus(uint32_t baseAddr, uint32_t pinNum)
This API determines the enabled interrupt status of a specified pin.
Definition: gpio/v0/gpio.h:333
GPIO_pinOutValueRead
uint32_t GPIO_pinOutValueRead(uint32_t baseAddr, uint32_t pinNum)
This API determines the output logic level(value) on a specified GPIO pin.
GPIO_MAX_PIN_PER_BANK
#define GPIO_MAX_PIN_PER_BANK
Maximum number of pins per bank.
Definition: gpio/v0/gpio.h:111
GPIO_clearBankIntrStatus
static void GPIO_clearBankIntrStatus(uint32_t baseAddr, uint32_t bankNum, uint32_t intrStatus)
This API clears the interrupt status of the specified bank.
Definition: gpio/v0/gpio.h:374
GPIO_setDirMode
void GPIO_setDirMode(uint32_t baseAddr, uint32_t pinNum, uint32_t pinDir)
This API configures the direction of a specified GPIO pin as being either input or output.
GPIO_clearIntrStatus
static void GPIO_clearIntrStatus(uint32_t baseAddr, uint32_t pinNum)
This API clears the enabled interrupt status of a specified GPIO pin.
Definition: gpio/v0/gpio.h:346
GPIO_pinWriteLow
static void GPIO_pinWriteLow(uint32_t baseAddr, uint32_t pinNum)
This API drives an output GPIO pin to a logic LOW state.
Definition: gpio/v0/gpio.h:321
GPIO_pinWriteHigh
static void GPIO_pinWriteHigh(uint32_t baseAddr, uint32_t pinNum)
This API drives an output GPIO pin to a logic HIGH state.
Definition: gpio/v0/gpio.h:309
GPIO_bankIntrDisable
void GPIO_bankIntrDisable(uint32_t baseAddr, uint32_t bankNum)
This API disables the bank interrupt.
GPIO_GET_BIT_POS
#define GPIO_GET_BIT_POS(pinNum)
Returns the bit position within a register based on pin number.
Definition: gpio/v0/gpio.h:130
GPIO_setTrigType
void GPIO_setTrigType(uint32_t baseAddr, uint32_t pinNum, uint32_t trigType)
This API configures the trigger type for a specified input GPIO pin.
GPIO_GET_REG_INDEX
#define GPIO_GET_REG_INDEX(pinNum)
Returns the register index based on pin number.
Definition: gpio/v0/gpio.h:128
GPIO_getBankIntrStatus
static uint32_t GPIO_getBankIntrStatus(uint32_t baseAddr, uint32_t bankNum)
This API returns the interrupt status of the specified bank.
Definition: gpio/v0/gpio.h:359
GPIO_pinRead
uint32_t GPIO_pinRead(uint32_t baseAddr, uint32_t pinNum)
This API reads the logic level(value) on a specified GPIO pin.
GPIO_bankIntrEnable
void GPIO_bankIntrEnable(uint32_t baseAddr, uint32_t bankNum)
This API enables the bank interrupt. This has to be called after setting all the GPIO pin triggers of...