63 #include <drivers/hw_include/hw_types.h>
64 #include <drivers/hw_include/cslr_soc.h>
66 #include <drivers/hw_include/cslr_epwm.h>
79 #define EPWM_SYNC_OUT_SOURCE_M ((uint16_t)CSL_EPWM_EPWMSYNCOUTEN_SWEN_MASK |\
80 (uint16_t)CSL_EPWM_EPWMSYNCOUTEN_ZEROEN_MASK |\
81 (uint16_t)CSL_EPWM_EPWMSYNCOUTEN_CMPBEN_MASK |\
82 (uint16_t)CSL_EPWM_EPWMSYNCOUTEN_CMPCEN_MASK |\
83 (uint16_t)CSL_EPWM_EPWMSYNCOUTEN_CMPDEN_MASK |\
84 (uint16_t)CSL_EPWM_EPWMSYNCOUTEN_DCAEVT1EN_MASK |\
85 (uint16_t)CSL_EPWM_EPWMSYNCOUTEN_DCBEVT1EN_MASK)
94 #define EPWM_SYNC_OUT_PULSE_ON_SOFTWARE CSL_EPWM_EPWMSYNCOUTEN_SWEN_MASK
95 #define EPWM_SYNC_OUT_PULSE_ON_CNTR_ZERO CSL_EPWM_EPWMSYNCOUTEN_ZEROEN_MASK
97 #define EPWM_SYNC_OUT_PULSE_ON_CNTR_COMPARE_B CSL_EPWM_EPWMSYNCOUTEN_CMPBEN_MASK
99 #define EPWM_SYNC_OUT_PULSE_ON_CNTR_COMPARE_C CSL_EPWM_EPWMSYNCOUTEN_CMPCEN_MASK
101 #define EPWM_SYNC_OUT_PULSE_ON_CNTR_COMPARE_D CSL_EPWM_EPWMSYNCOUTEN_CMPDEN_MASK
103 #define EPWM_SYNC_OUT_PULSE_ON_DCA_EVT1_SYNC CSL_EPWM_EPWMSYNCOUTEN_DCAEVT1EN_MASK
105 #define EPWM_SYNC_OUT_PULSE_ON_DCB_EVT1_SYNC CSL_EPWM_EPWMSYNCOUTEN_DCBEVT1EN_MASK
107 #define EPWM_SYNC_OUT_PULSE_ON_ALL EPWM_SYNC_OUT_SOURCE_M
376 #define EPWM_TIME_BASE_STATUS_COUNT_DOWN (0U)
377 #define EPWM_TIME_BASE_STATUS_COUNT_UP (1U)
779 #define EPWM_DB_INPUT_EPWMA (0U)
780 #define EPWM_DB_INPUT_EPWMB (1U)
782 #define EPWM_DB_INPUT_DB_RED (2U)
863 #define EPWM_TZ_SIGNAL_CBC1 (0x1U)
864 #define EPWM_TZ_SIGNAL_CBC2 (0x2U)
866 #define EPWM_TZ_SIGNAL_CBC3 (0x4U)
868 #define EPWM_TZ_SIGNAL_CBC4 (0x8U)
870 #define EPWM_TZ_SIGNAL_CBC5 (0x10U)
872 #define EPWM_TZ_SIGNAL_CBC6 (0x20U)
874 #define EPWM_TZ_SIGNAL_DCAEVT2 (0x40U)
876 #define EPWM_TZ_SIGNAL_DCBEVT2 (0x80U)
878 #define EPWM_TZ_SIGNAL_OSHT1 (0x100U)
880 #define EPWM_TZ_SIGNAL_OSHT2 (0x200U)
882 #define EPWM_TZ_SIGNAL_OSHT3 (0x400U)
884 #define EPWM_TZ_SIGNAL_OSHT4 (0x800U)
886 #define EPWM_TZ_SIGNAL_OSHT5 (0x1000U)
888 #define EPWM_TZ_SIGNAL_OSHT6 (0x2000U)
890 #define EPWM_TZ_SIGNAL_DCAEVT1 (0x4000U)
892 #define EPWM_TZ_SIGNAL_DCBEVT1 (0x8000U)
894 #define EPWM_TZ_SIGNAL_CAPEVT_OST (0x10000U)
896 #define EPWM_TZ_SIGNAL_CAPEVT_CBC (0x1000000U)
1019 #define EPWM_TZ_INTERRUPT_CBC (0x2U)
1020 #define EPWM_TZ_INTERRUPT_OST (0x4U)
1022 #define EPWM_TZ_INTERRUPT_DCAEVT1 (0x8U)
1024 #define EPWM_TZ_INTERRUPT_DCAEVT2 (0x10U)
1026 #define EPWM_TZ_INTERRUPT_DCBEVT1 (0x20U)
1028 #define EPWM_TZ_INTERRUPT_DCBEVT2 (0x40U)
1030 #define EPWM_TZ_INTERRUPT_CAPEVT (0x80U)
1039 #define EPWM_TZ_FLAG_CBC (0x2U)
1040 #define EPWM_TZ_FLAG_OST (0x4U)
1042 #define EPWM_TZ_FLAG_DCAEVT1 (0x8U)
1044 #define EPWM_TZ_FLAG_DCAEVT2 (0x10U)
1046 #define EPWM_TZ_FLAG_DCBEVT1 (0x20U)
1048 #define EPWM_TZ_FLAG_DCBEVT2 (0x40U)
1050 #define EPWM_TZ_FLAG_CAPEVT (0x80U)
1060 #define EPWM_TZ_INTERRUPT (0x1U)
1070 #define EPWM_TZ_CBC_FLAG_1 (0x1U)
1071 #define EPWM_TZ_CBC_FLAG_2 (0x2U)
1073 #define EPWM_TZ_CBC_FLAG_3 (0x4U)
1075 #define EPWM_TZ_CBC_FLAG_4 (0x8U)
1077 #define EPWM_TZ_CBC_FLAG_5 (0x10U)
1079 #define EPWM_TZ_CBC_FLAG_6 (0x20U)
1081 #define EPWM_TZ_CBC_FLAG_DCAEVT2 (0x40U)
1083 #define EPWM_TZ_CBC_FLAG_DCBEVT2 (0x80U)
1085 #define EPWM_TZ_CBC_FLAG_CAPEVT (0x100U)
1096 #define EPWM_TZ_OST_FLAG_OST1 (0x1U)
1097 #define EPWM_TZ_OST_FLAG_OST2 (0x2U)
1099 #define EPWM_TZ_OST_FLAG_OST3 (0x4U)
1101 #define EPWM_TZ_OST_FLAG_OST4 (0x8U)
1103 #define EPWM_TZ_OST_FLAG_OST5 (0x10U)
1105 #define EPWM_TZ_OST_FLAG_OST6 (0x20U)
1107 #define EPWM_TZ_OST_FLAG_DCAEVT1 (0x40U)
1109 #define EPWM_TZ_OST_FLAG_DCBEVT1 (0x80U)
1111 #define EPWM_TZ_OST_FLAG_CAPEVT (0x100U)
1137 #define EPWM_TZ_FORCE_EVENT_CBC (0x2U)
1138 #define EPWM_TZ_FORCE_EVENT_OST (0x4U)
1140 #define EPWM_TZ_FORCE_EVENT_DCAEVT1 (0x8U)
1142 #define EPWM_TZ_FORCE_EVENT_DCAEVT2 (0x10U)
1144 #define EPWM_TZ_FORCE_EVENT_DCBEVT1 (0x20U)
1146 #define EPWM_TZ_FORCE_EVENT_DCBEVT2 (0x40U)
1148 #define EPWM_TZ_FORCE_EVENT_CAPEVT (0x80U)
1158 #define EPWM_TZ_SELECT_TRIPOUT_OST (0x1)
1159 #define EPWM_TZ_SELECT_TRIPOUT_CBC (0x2)
1161 #define EPWM_TZ_SELECT_TRIPOUT_TZ1 (0x4)
1163 #define EPWM_TZ_SELECT_TRIPOUT_TZ2 (0x8)
1165 #define EPWM_TZ_SELECT_TRIPOUT_TZ3 (0x10)
1167 #define EPWM_TZ_SELECT_TRIPOUT_TZ4 (0x20)
1169 #define EPWM_TZ_SELECT_TRIPOUT_TZ5 (0x40)
1171 #define EPWM_TZ_SELECT_TRIPOUT_TZ6 (0x80)
1173 #define EPWM_TZ_SELECT_TRIPOUT_DCAEVT1 (0x100)
1175 #define EPWM_TZ_SELECT_TRIPOUT_DCAEVT2 (0x200)
1177 #define EPWM_TZ_SELECT_TRIPOUT_DCBEVT1 (0x400)
1179 #define EPWM_TZ_SELECT_TRIPOUT_DCBEVT2 (0x800)
1181 #define EPWM_TZ_SELECT_TRIPOUT_CAPEVT (0x1000)
1191 #define EPWM_INT_TBCTR_ZERO (1U)
1192 #define EPWM_INT_TBCTR_PERIOD (2U)
1194 #define EPWM_INT_TBCTR_ETINTMIX (3U)
1196 #define EPWM_INT_TBCTR_U_CMPA (4U)
1198 #define EPWM_INT_TBCTR_U_CMPC (8U)
1200 #define EPWM_INT_TBCTR_D_CMPA (5U)
1202 #define EPWM_INT_TBCTR_D_CMPC (10U)
1204 #define EPWM_INT_TBCTR_U_CMPB (6U)
1206 #define EPWM_INT_TBCTR_U_CMPD (12U)
1208 #define EPWM_INT_TBCTR_D_CMPB (7U)
1210 #define EPWM_INT_TBCTR_D_CMPD (14U)
1220 #define EPWM_INT_MIX_TBCTR_ZERO (0x1)
1221 #define EPWM_INT_MIX_TBCTR_PERIOD (0x2)
1223 #define EPWM_INT_MIX_TBCTR_U_CMPA (0x4)
1225 #define EPWM_INT_MIX_TBCTR_D_CMPA (0x8)
1227 #define EPWM_INT_MIX_TBCTR_U_CMPB (0x10)
1229 #define EPWM_INT_MIX_TBCTR_D_CMPB (0x20)
1231 #define EPWM_INT_MIX_TBCTR_U_CMPC (0x40)
1233 #define EPWM_INT_MIX_TBCTR_D_CMPC (0x80)
1235 #define EPWM_INT_MIX_TBCTR_U_CMPD (0x100)
1237 #define EPWM_INT_MIX_TBCTR_D_CMPD (0x200)
1239 #define EPWM_INT_MIX_DCAEVT1 (0x400)
1346 #define EPWM_DC_COMBINATIONAL_TRIPIN1 (0x1U)
1347 #define EPWM_DC_COMBINATIONAL_TRIPIN2 (0x2U)
1349 #define EPWM_DC_COMBINATIONAL_TRIPIN3 (0x4U)
1351 #define EPWM_DC_COMBINATIONAL_TRIPIN4 (0x8U)
1353 #define EPWM_DC_COMBINATIONAL_TRIPIN5 (0x10U)
1355 #define EPWM_DC_COMBINATIONAL_TRIPIN6 (0x20U)
1357 #define EPWM_DC_COMBINATIONAL_TRIPIN7 (0x40U)
1359 #define EPWM_DC_COMBINATIONAL_TRIPIN8 (0x80U)
1361 #define EPWM_DC_COMBINATIONAL_TRIPIN9 (0x100U)
1363 #define EPWM_DC_COMBINATIONAL_TRIPIN10 (0x200U)
1365 #define EPWM_DC_COMBINATIONAL_TRIPIN11 (0x400U)
1367 #define EPWM_DC_COMBINATIONAL_TRIPIN12 (0x800U)
1369 #define EPWM_DC_COMBINATIONAL_TRIPIN14 (0x2000U)
1371 #define EPWM_DC_COMBINATIONAL_TRIPIN15 (0x4000U)
1399 #define EPWM_DC_TBCTR_ZERO (0x1)
1400 #define EPWM_DC_TBCTR_PERIOD (0x2)
1402 #define EPWM_DC_TBCTR_U_CMPA (0x4)
1404 #define EPWM_DC_TBCTR_D_CMPA (0x8)
1406 #define EPWM_DC_TBCTR_U_CMPB (0x10)
1408 #define EPWM_DC_TBCTR_D_CMPB (0x20)
1410 #define EPWM_DC_TBCTR_U_CMPC (0x40)
1412 #define EPWM_DC_TBCTR_D_CMPC (0x80)
1414 #define EPWM_DC_TBCTR_U_CMPD (0x100)
1416 #define EPWM_DC_TBCTR_D_CMPD (0x200)
1563 #define EPWM_GL_REGISTER_TBPRD_TBPRDHR (0x1U)
1564 #define EPWM_GL_REGISTER_CMPA_CMPAHR (0x2U)
1566 #define EPWM_GL_REGISTER_CMPB_CMPBHR (0x4U)
1568 #define EPWM_GL_REGISTER_CMPC (0x8U)
1570 #define EPWM_GL_REGISTER_CMPD (0x10U)
1572 #define EPWM_GL_REGISTER_DBRED_DBREDHR (0x20U)
1574 #define EPWM_GL_REGISTER_DBFED_DBFEDHR (0x40U)
1576 #define EPWM_GL_REGISTER_DBCTL (0x80U)
1578 #define EPWM_GL_REGISTER_AQCTLA_AQCTLA2 (0x100U)
1580 #define EPWM_GL_REGISTER_AQCTLB_AQCTLB2 (0x200U)
1582 #define EPWM_GL_REGISTER_AQCSFRC (0x400U)
1716 #define EPWM_MINDB_BLOCK_A (0x0)
1717 #define EPWM_MINDB_BLOCK_B (0x1)
1726 #define EPWM_MINDB_NO_INVERT (0x0)
1727 #define EPWM_MINDB_INVERT (0x1)
1736 #define EPWM_MINDB_INVERT_LOGICAL_AND (0x0)
1737 #define EPWM_MINDB_LOGICAL_OR (0x1)
1746 #define EPWM_MINDB_PWMB (0x0)
1747 #define EPWM_MINDB_PWM_OUTXBAR_OUT1 (0x1)
1749 #define EPWM_MINDB_PWM_OUTXBAR_OUT2 (0x2)
1751 #define EPWM_MINDB_PWM_OUTXBAR_OUT3 (0x3)
1753 #define EPWM_MINDB_PWM_OUTXBAR_OUT4 (0x4)
1755 #define EPWM_MINDB_PWM_OUTXBAR_OUT5 (0x5)
1757 #define EPWM_MINDB_PWM_OUTXBAR_OUT6 (0x6)
1759 #define EPWM_MINDB_PWM_OUTXBAR_OUT7 (0x7)
1761 #define EPWM_MINDB_PWM_OUTXBAR_OUT8 (0x8)
1763 #define EPWM_MINDB_PWM_OUTXBAR_OUT9 (0x9)
1765 #define EPWM_MINDB_PWM_OUTXBAR_OUT10 (0xA)
1767 #define EPWM_MINDB_PWM_OUTXBAR_OUT11 (0xB)
1769 #define EPWM_MINDB_PWM_OUTXBAR_OUT12 (0xC)
1771 #define EPWM_MINDB_PWM_OUTXBAR_OUT13 (0xD)
1773 #define EPWM_MINDB_PWM_OUTXBAR_OUT14 (0xE)
1775 #define EPWM_MINDB_PWM_OUTXBAR_OUT15 (0xF)
1784 #define EPWM_MINDB_BLOCKING_SIGNAL_SAME (0x0)
1785 #define EPWM_MINDB_BLOCKING_SIGNAL_DIFF (0x1)
1794 #define EPWM_MINDB_ICSS_XBAR_OUT0 (0x0)
1795 #define EPWM_MINDB_ICSS_XBAR_OUT1 (0x1)
1797 #define EPWM_MINDB_ICSS_XBAR_OUT2 (0x2)
1799 #define EPWM_MINDB_ICSS_XBAR_OUT3 (0x3)
1801 #define EPWM_MINDB_ICSS_XBAR_OUT4 (0x4)
1803 #define EPWM_MINDB_ICSS_XBAR_OUT5 (0x5)
1805 #define EPWM_MINDB_ICSS_XBAR_OUT6 (0x6)
1807 #define EPWM_MINDB_ICSS_XBAR_OUT7 (0x7)
1809 #define EPWM_MINDB_ICSS_XBAR_OUT8 (0x8)
1811 #define EPWM_MINDB_ICSS_XBAR_OUT9 (0x9)
1813 #define EPWM_MINDB_ICSS_XBAR_OUT10 (0xA)
1815 #define EPWM_MINDB_ICSS_XBAR_OUT11 (0xB)
1817 #define EPWM_MINDB_ICSS_XBAR_OUT12 (0xC)
1819 #define EPWM_MINDB_ICSS_XBAR_OUT13 (0xD)
1821 #define EPWM_MINDB_ICSS_XBAR_OUT14 (0xE)
1823 #define EPWM_MINDB_ICSS_XBAR_OUT15 (0xF)
1961 #define EPWM_DCxCTL_STEP (CSL_EPWM_DCBCTL - CSL_EPWM_DCACTL)
1962 #define EPWM_DCxxTRIPSEL (CSL_EPWM_DCALTRIPSEL - CSL_EPWM_DCAHTRIPSEL)
1963 #define EPWM_XREGSHDWxSTS_STEP (CSL_EPWM_XREGSHDW2STS-CSL_EPWM_XREGSHDW1STS)
1964 #define EPWM_XCMPx_ACTIVE_STEP (CSL_EPWM_XCMP2_ACTIVE-CSL_EPWM_XCMP1_ACTIVE)
1965 #define EPWM_XCMPx_STEP (CSL_EPWM_XCMP1_SHDW2-CSL_EPWM_XCMP1_SHDW1)
1966 #define EPWM_XCMPx_SHDWx_STEP (CSL_EPWM_XCMP2_SHDW1-CSL_EPWM_XCMP1_SHDW1)
1967 #define EPWM_LOCK_KEY (0xA5A50000U)
2008 HW_WR_REG16(base + CSL_EPWM_TBCTR, count);
2035 HW_WR_REG16(base + CSL_EPWM_TBCTL,
2036 (HW_RD_REG16(base + CSL_EPWM_TBCTL) |
2037 CSL_EPWM_TBCTL_PHSDIR_MASK));
2044 HW_WR_REG16(base + CSL_EPWM_TBCTL,
2045 (HW_RD_REG16(base + CSL_EPWM_TBCTL) &
2046 ~CSL_EPWM_TBCTL_PHSDIR_MASK));
2080 HW_WR_REG16(base + CSL_EPWM_TBCTL,
2081 ((HW_RD_REG16(base + CSL_EPWM_TBCTL) &
2082 ~(CSL_EPWM_TBCTL_CLKDIV_MASK | CSL_EPWM_TBCTL_HSPCLKDIV_MASK)) |
2083 (((uint16_t)prescaler << CSL_EPWM_TBCTL_CLKDIV_SHIFT) |
2084 ((uint16_t)highSpeedPrescaler << CSL_EPWM_TBCTL_HSPCLKDIV_SHIFT))));
2106 HW_WR_REG16(base + CSL_EPWM_TBCTL,
2107 HW_RD_REG16(base + CSL_EPWM_TBCTL) | CSL_EPWM_TBCTL_SWFSYNC_MASK);
2146 HW_WR_REG16(base + CSL_EPWM_EPWMSYNCINSEL,
2147 ((HW_RD_REG16(base + CSL_EPWM_EPWMSYNCINSEL) &
2148 (~CSL_EPWM_EPWMSYNCINSEL_SEL_MASK)) |
2149 ((uint16_t)source & CSL_EPWM_EPWMSYNCINSEL_SEL_MASK)));
2198 HW_WR_REG16(base + CSL_EPWM_EPWMSYNCOUTEN,
2199 (HW_RD_REG16(base + CSL_EPWM_EPWMSYNCOUTEN) |
2243 HW_WR_REG16(base + CSL_EPWM_EPWMSYNCOUTEN,
2244 (HW_RD_REG16(base + CSL_EPWM_EPWMSYNCOUTEN) &
2245 ~((uint16_t)source)));
2272 HW_WR_REG16(base + CSL_EPWM_TBCTL3,
2273 ((HW_RD_REG16(base + CSL_EPWM_TBCTL3) &
2274 ~(CSL_EPWM_TBCTL3_OSSFRCEN_MASK)) |
2275 (uint16_t)trigger));
2302 HW_WR_REG16(base + CSL_EPWM_TBCTL,
2303 (HW_RD_REG16(base + CSL_EPWM_TBCTL) & ~CSL_EPWM_TBCTL_PRDLD_MASK));
2310 HW_WR_REG16(base + CSL_EPWM_TBCTL,
2311 (HW_RD_REG16(base + CSL_EPWM_TBCTL) | CSL_EPWM_TBCTL_PRDLD_MASK));
2333 HW_WR_REG16(base + CSL_EPWM_TBCTL,
2334 (HW_RD_REG16(base + CSL_EPWM_TBCTL) | CSL_EPWM_TBCTL_PHSEN_MASK));
2354 HW_WR_REG16(base + CSL_EPWM_TBCTL,
2355 (HW_RD_REG16(base + CSL_EPWM_TBCTL) & ~CSL_EPWM_TBCTL_PHSEN_MASK));
2381 HW_WR_REG16(base + CSL_EPWM_TBCTL,
2382 ((HW_RD_REG16(base + CSL_EPWM_TBCTL) &
2383 ~(CSL_EPWM_TBCTL_CTRMODE_MASK)) | ((uint16_t)counterMode)));
2413 HW_WR_REG16(base + CSL_EPWM_TBCTL2,
2414 ((HW_RD_REG16(base + CSL_EPWM_TBCTL2) &
2415 ~(CSL_EPWM_TBCTL2_PRDLDSYNC_MASK)) |
2416 ((uint16_t)shadowLoadMode << CSL_EPWM_TBCTL2_PRDLDSYNC_SHIFT)));
2435 HW_WR_REG16(base + CSL_EPWM_TBCTL2,
2436 (HW_RD_REG16(base + CSL_EPWM_TBCTL2) |
2437 CSL_EPWM_TBCTL2_OSHTSYNCMODE_MASK));
2457 HW_WR_REG16(base + CSL_EPWM_TBCTL2,
2458 (HW_RD_REG16(base + CSL_EPWM_TBCTL2) &
2459 ~CSL_EPWM_TBCTL2_OSHTSYNCMODE_MASK));
2479 HW_WR_REG16(base + CSL_EPWM_TBCTL2,
2480 (HW_RD_REG16(base + CSL_EPWM_TBCTL2) | CSL_EPWM_TBCTL2_OSHTSYNC_MASK));
2494 static inline uint16_t
2500 return(HW_RD_REG16(base + CSL_EPWM_TBCTR));
2521 return(((HW_RD_REG16(base + CSL_EPWM_TBSTS) &
2522 CSL_EPWM_TBSTS_CTRMAX_MASK) ==
2523 CSL_EPWM_TBSTS_CTRMAX_MASK) ?
true :
false);
2544 HW_WR_REG16(base + CSL_EPWM_TBSTS,
2545 (HW_RD_REG16(base + CSL_EPWM_TBSTS) | CSL_EPWM_TBSTS_CTRMAX_MASK));
2566 return(((HW_RD_REG16(base + CSL_EPWM_TBSTS) & CSL_EPWM_TBSTS_SYNCI_MASK) ==
2567 CSL_EPWM_TBSTS_SYNCI_MASK) ?
true :
false);
2587 HW_WR_REG16(base + CSL_EPWM_TBSTS,
2588 (HW_RD_REG16(base + CSL_EPWM_TBSTS) | CSL_EPWM_TBSTS_SYNCI_MASK));
2604 static inline uint16_t
2610 return(HW_RD_REG16(base + CSL_EPWM_TBSTS) & CSL_EPWM_TBSTS_CTRDIR_MASK);
2634 HW_WR_REG16(base + CSL_EPWM_TBPHS,
2635 ((HW_RD_REG16(base + CSL_EPWM_TBPHS) &
2636 ~((uint32_t)CSL_EPWM_TBPHS_TBPHS_MASK)) |
2637 ((uint32_t)phaseCount << CSL_EPWM_TBPHS_TBPHS_SHIFT)));
2663 HW_WR_REG16(base + CSL_EPWM_TBPRD, periodCount);
2677 static inline uint16_t
2683 return(HW_RD_REG16(base + CSL_EPWM_TBPRD));
2753 uint32_t registerOffset;
2757 registerOffset = base + CSL_EPWM_EPWMXLINK2;
2758 linkComp = linkComp - 1;
2762 registerOffset = base + CSL_EPWM_EPWMXLINK;
2768 HW_WR_REG32(registerOffset,
2769 ((HW_RD_REG32(registerOffset) &
2770 ~((uint32_t)CSL_EPWM_EPWMXLINK_TBPRDLINK_MASK << linkComp)) |
2771 ((uint32_t)epwmLink << linkComp)));
2809 uint16_t syncModeOffset;
2810 uint16_t loadModeOffset;
2811 uint16_t shadowModeOffset;
2812 uint32_t registerOffset;
2817 syncModeOffset = CSL_EPWM_CMPCTL_LOADASYNC_SHIFT;
2818 loadModeOffset = CSL_EPWM_CMPCTL_LOADAMODE_SHIFT;
2819 shadowModeOffset = CSL_EPWM_CMPCTL_SHDWAMODE_SHIFT;
2823 syncModeOffset = CSL_EPWM_CMPCTL_LOADBSYNC_SHIFT;
2824 loadModeOffset = CSL_EPWM_CMPCTL_LOADBMODE_SHIFT;
2825 shadowModeOffset = CSL_EPWM_CMPCTL_SHDWBMODE_SHIFT;
2835 registerOffset = base + CSL_EPWM_CMPCTL;
2839 registerOffset = base + CSL_EPWM_CMPCTL2;
2846 HW_WR_REG16(registerOffset,
2847 ((HW_RD_REG16(registerOffset) &
2848 ~((CSL_EPWM_CMPCTL_LOADASYNC_MAX << syncModeOffset) |
2849 (CSL_EPWM_CMPCTL_LOADAMODE_MAX << loadModeOffset) |
2850 (CSL_EPWM_CMPCTL_SHDWAMODE_MAX << shadowModeOffset))) |
2851 ((((uint16_t)loadMode >> 2U) << syncModeOffset) |
2852 (((uint16_t)loadMode & CSL_EPWM_CMPCTL_LOADASYNC_MAX) <<
2878 uint16_t shadowModeOffset;
2879 uint32_t registerOffset;
2884 shadowModeOffset = CSL_EPWM_CMPCTL_SHDWAMODE_SHIFT;
2888 shadowModeOffset = CSL_EPWM_CMPCTL_SHDWBMODE_SHIFT;
2898 registerOffset = base + CSL_EPWM_CMPCTL;
2902 registerOffset = base + CSL_EPWM_CMPCTL2;
2908 HW_WR_REG16(registerOffset,
2909 (HW_RD_REG16(registerOffset) |
2910 (CSL_EPWM_CMPCTL_SHDWAMODE_MAX << shadowModeOffset)));
2936 uint32_t registerOffset;
2941 registerOffset = base + CSL_EPWM_CMPA + (uint16_t)compModule;
2952 HW_WR_REG16(registerOffset + 0x2U, compCount);
2959 HW_WR_REG16(registerOffset, compCount);
2980 static inline uint16_t
2983 uint32_t registerOffset;
2989 registerOffset = base + CSL_EPWM_CMPA + (uint16_t)compModule;
3000 compCount = (uint16_t)((HW_RD_REG32(registerOffset) &
3001 (uint32_t)CSL_EPWM_CMPA_CMPA_MASK) >>
3002 CSL_EPWM_CMPA_CMPA_SHIFT);
3009 compCount = HW_RD_REG16(registerOffset);
3043 return((((HW_RD_REG32(base + CSL_EPWM_CMPCTL) >>
3044 ((((uint16_t)compModule >> 1U) & 0x2U) +
3045 CSL_EPWM_CMPCTL_SHDWAFULL_SHIFT)) &
3046 0x1U) == 0x1U) ?
true:
false);
3087 uint16_t syncModeOffset;
3088 uint16_t shadowModeOffset;
3090 syncModeOffset = CSL_EPWM_AQCTL_LDAQASYNC_SHIFT + (uint16_t)aqModule;
3091 shadowModeOffset = CSL_EPWM_AQCTL_SHDWAQAMODE_SHIFT + (uint16_t)aqModule;
3097 HW_WR_REG16(base + CSL_EPWM_AQCTL,
3098 ((HW_RD_REG16(base + CSL_EPWM_AQCTL) &
3099 (~((CSL_EPWM_AQCTL_LDAQAMODE_MASK << (uint16_t)aqModule) |
3100 (CSL_EPWM_AQCTL_LDAQASYNC_MAX << (uint16_t)syncModeOffset))) |
3101 (CSL_EPWM_AQCTL_SHDWAQAMODE_MAX << shadowModeOffset)) |
3102 ((((uint16_t)loadMode >> 2U) << syncModeOffset) |
3103 (((uint16_t)loadMode & CSL_EPWM_AQCTL_LDAQAMODE_MASK) <<
3104 (uint16_t)aqModule))));
3127 uint16_t shadowModeOffset;
3129 shadowModeOffset = CSL_EPWM_AQCTL_SHDWAQAMODE_SHIFT + (uint16_t)aqModule;
3135 HW_WR_REG16(base + CSL_EPWM_AQCTL,
3136 (HW_RD_REG16(base + CSL_EPWM_AQCTL) &
3137 ~(CSL_EPWM_AQCTL_SHDWAQAMODE_MAX << shadowModeOffset)));
3169 HW_WR_REG16(base + CSL_EPWM_AQTSRCSEL,
3170 ((HW_RD_REG16(base + CSL_EPWM_AQTSRCSEL) &
3171 (~CSL_EPWM_AQTSRCSEL_T1SEL_MASK)) |
3172 ((uint16_t)trigger)));
3204 HW_WR_REG16(base + CSL_EPWM_AQTSRCSEL,
3205 ((HW_RD_REG16(base + CSL_EPWM_AQTSRCSEL) &
3206 (~CSL_EPWM_AQTSRCSEL_T2SEL_MASK)) |
3207 ((uint16_t)trigger << CSL_EPWM_AQTSRCSEL_T2SEL_SHIFT)));
3258 uint32_t registerOffset;
3259 uint32_t registerTOffset;
3264 registerOffset = CSL_EPWM_AQCTLA + (uint16_t)epwmOutput;
3265 registerTOffset = CSL_EPWM_AQCTLA2 + (uint16_t)epwmOutput;
3270 if(((uint16_t)
event & 0x1U) == 1U)
3275 HW_WR_REG16(base + registerTOffset,
3276 ((HW_RD_REG16(base + registerTOffset) &
3277 ~(CSL_EPWM_AQCTLA_ZRO_MAX << ((uint16_t)event - 1U))) |
3278 ((uint16_t)output << ((uint16_t)event - 1U))));
3285 HW_WR_REG16(base + registerOffset,
3286 ((HW_RD_REG16(base + registerOffset) &
3287 ~(CSL_EPWM_AQCTLA_ZRO_MAX << (uint16_t)event)) |
3288 ((uint16_t)output << (uint16_t)event)));
3381 uint32_t registerOffset;
3386 registerOffset = CSL_EPWM_AQCTLA + (uint16_t)epwmOutput;
3391 HW_WR_REG16(base + registerOffset, action);
3460 uint32_t registerTOffset;
3465 registerTOffset = CSL_EPWM_AQCTLA2 + (uint16_t)epwmOutput;
3470 HW_WR_REG16(base + registerTOffset, action);
3503 HW_WR_REG16(base + CSL_EPWM_AQSFRC,
3504 ((HW_RD_REG16(base + CSL_EPWM_AQSFRC) &
3505 ~CSL_EPWM_AQSFRC_RLDCSF_MASK) |
3506 ((uint16_t)mode << CSL_EPWM_AQSFRC_RLDCSF_SHIFT)));
3541 HW_WR_REG16(base + CSL_EPWM_AQCSFRC,
3542 ((HW_RD_REG16(base + CSL_EPWM_AQCSFRC) &
3543 ~CSL_EPWM_AQCSFRC_CSFA_MASK) |
3544 ((uint16_t)output)));
3548 HW_WR_REG16(base + CSL_EPWM_AQCSFRC,
3549 ((HW_RD_REG16(base + CSL_EPWM_AQCSFRC) &
3550 ~CSL_EPWM_AQCSFRC_CSFB_MASK) |
3551 ((uint16_t)output << CSL_EPWM_AQCSFRC_CSFB_SHIFT)));
3589 HW_WR_REG16(base + CSL_EPWM_AQSFRC,
3590 ((HW_RD_REG16(base + CSL_EPWM_AQSFRC) &
3591 ~CSL_EPWM_AQSFRC_ACTSFA_MASK) |
3592 ((uint16_t)output)));
3596 HW_WR_REG16(base + CSL_EPWM_AQSFRC,
3597 ((HW_RD_REG16(base + CSL_EPWM_AQSFRC) &
3598 ~CSL_EPWM_AQSFRC_ACTSFB_MASK) |
3599 ((uint16_t)output << CSL_EPWM_AQSFRC_ACTSFB_SHIFT)));
3628 HW_WR_REG16(base + CSL_EPWM_AQSFRC,
3629 (HW_RD_REG16(base + CSL_EPWM_AQSFRC) |
3630 CSL_EPWM_AQSFRC_OTSFA_MASK));
3634 HW_WR_REG16(base + CSL_EPWM_AQSFRC,
3635 (HW_RD_REG16(base + CSL_EPWM_AQSFRC) |
3636 CSL_EPWM_AQSFRC_OTSFB_MASK));
3667 bool enableSwapMode)
3671 mask = (uint16_t)1U << ((uint16_t)output + CSL_EPWM_DBCTL_OUTSWAP_SHIFT);
3678 HW_WR_REG16(base + CSL_EPWM_DBCTL,
3679 (HW_RD_REG16(base + CSL_EPWM_DBCTL) | mask));
3686 HW_WR_REG16(base + CSL_EPWM_DBCTL,
3687 (HW_RD_REG16(base + CSL_EPWM_DBCTL) & ~mask));
3715 bool enableDelayMode)
3719 mask = 1U << ((uint16_t)(delayMode + CSL_EPWM_DBCTL_OUT_MODE_SHIFT));
3726 HW_WR_REG16(base + CSL_EPWM_DBCTL,
3727 (HW_RD_REG16(base + CSL_EPWM_DBCTL) | mask));
3734 HW_WR_REG16(base + CSL_EPWM_DBCTL,
3735 (HW_RD_REG16(base + CSL_EPWM_DBCTL) & ~mask));
3767 shift = (((uint16_t)delayMode ^ 0x1U) + CSL_EPWM_DBCTL_POLSEL_SHIFT);
3772 HW_WR_REG16(base + CSL_EPWM_DBCTL,
3773 ((HW_RD_REG16(base + CSL_EPWM_DBCTL) & ~ (1U << shift)) |
3774 ((uint16_t)polarity << shift)));
3806 HW_WR_REG16(base + CSL_EPWM_DBCTL,
3807 ((HW_RD_REG16(base + CSL_EPWM_DBCTL) &
3808 ~(1U << (CSL_EPWM_DBCTL_IN_MODE_SHIFT))) |
3809 (input << CSL_EPWM_DBCTL_IN_MODE_SHIFT)));
3847 HW_WR_REG16(base + CSL_EPWM_DBCTL,
3848 (HW_RD_REG16(base + CSL_EPWM_DBCTL) |
3849 CSL_EPWM_DBCTL_DEDB_MODE_MASK));
3856 HW_WR_REG16(base + CSL_EPWM_DBCTL,
3857 (HW_RD_REG16(base + CSL_EPWM_DBCTL) &
3858 ~CSL_EPWM_DBCTL_DEDB_MODE_MASK));
3863 HW_WR_REG16(base + CSL_EPWM_DBCTL,
3864 ((HW_RD_REG16(base + CSL_EPWM_DBCTL) &
3865 ~(1U << (CSL_EPWM_DBCTL_IN_MODE_SHIFT + 1U))) |
3866 (input << (CSL_EPWM_DBCTL_IN_MODE_SHIFT + 1U))));
3896 HW_WR_REG16(base + CSL_EPWM_DBCTL2,
3897 ((HW_RD_REG16(base + CSL_EPWM_DBCTL2) &
3898 ~CSL_EPWM_DBCTL2_LOADDBCTLMODE_MASK) |
3899 (CSL_EPWM_DBCTL2_LOADDBCTLMODE_MASK | (uint16_t)loadMode)));
3920 HW_WR_REG16(base + CSL_EPWM_DBCTL2,
3921 (HW_RD_REG16(base + CSL_EPWM_DBCTL2) &
3922 ~CSL_EPWM_DBCTL2_SHDWDBCTLMODE_MASK));
3950 HW_WR_REG16(base + CSL_EPWM_DBCTL,
3951 ((HW_RD_REG16(base + CSL_EPWM_DBCTL) &
3952 ~CSL_EPWM_DBCTL_LOADREDMODE_MASK) |
3953 ((uint16_t)CSL_EPWM_DBCTL_SHDWDBREDMODE_MASK |
3954 ((uint16_t)loadMode << CSL_EPWM_DBCTL_LOADREDMODE_SHIFT))));
3975 HW_WR_REG16(base + CSL_EPWM_DBCTL,
3976 (HW_RD_REG16(base + CSL_EPWM_DBCTL) &
3977 ~CSL_EPWM_DBCTL_SHDWDBREDMODE_MASK));
4005 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4006 ((HW_RD_REG16(base + CSL_EPWM_DBCTL) &
4007 ~CSL_EPWM_DBCTL_LOADFEDMODE_MASK) |
4008 (CSL_EPWM_DBCTL_SHDWDBFEDMODE_MASK |
4009 ((uint16_t)loadMode << CSL_EPWM_DBCTL_LOADFEDMODE_SHIFT))));
4030 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4031 (HW_RD_REG16(base + CSL_EPWM_DBCTL) &
4032 ~CSL_EPWM_DBCTL_SHDWDBFEDMODE_MASK));
4060 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4061 ((HW_RD_REG16(base + CSL_EPWM_DBCTL) &
4062 ~CSL_EPWM_DBCTL_HALFCYCLE_MASK) |
4063 ((uint16_t)clockMode << CSL_EPWM_DBCTL_HALFCYCLE_SHIFT)));
4090 HW_WR_REG16(base + CSL_EPWM_DBRED, redCount);
4117 HW_WR_REG16(base + CSL_EPWM_DBFED, fedCount);
4140 HW_WR_REG16(base + CSL_EPWM_PCCTL,
4141 (HW_RD_REG16(base + CSL_EPWM_PCCTL) | CSL_EPWM_PCCTL_CHPEN_MASK));
4161 HW_WR_REG16(base + CSL_EPWM_PCCTL,
4162 (HW_RD_REG16(base + CSL_EPWM_PCCTL) & ~CSL_EPWM_PCCTL_CHPEN_MASK));
4191 HW_WR_REG16(base + CSL_EPWM_PCCTL,
4192 ((HW_RD_REG16(base + CSL_EPWM_PCCTL) & ~CSL_EPWM_PCCTL_CHPDUTY_MASK) |
4193 (dutyCycleCount << CSL_EPWM_PCCTL_CHPDUTY_SHIFT)));
4222 HW_WR_REG16(base + CSL_EPWM_PCCTL,
4223 ((HW_RD_REG16(base + CSL_EPWM_PCCTL) &
4224 ~(uint16_t)CSL_EPWM_PCCTL_CHPFREQ_MASK) |
4225 (freqDiv << CSL_EPWM_PCCTL_CHPFREQ_SHIFT)));
4249 DebugP_assert(firstPulseWidth <= CSL_EPWM_PCCTL_OSHTWTH_MAX);
4254 HW_WR_REG16(base + CSL_EPWM_PCCTL,
4255 ((HW_RD_REG16(base + CSL_EPWM_PCCTL) &
4256 ~(uint16_t)CSL_EPWM_PCCTL_OSHTWTH_MASK) |
4257 (firstPulseWidth << CSL_EPWM_PCCTL_OSHTWTH_SHIFT)));
4302 HW_WR_REG32(base + CSL_EPWM_TZSEL,
4303 (HW_RD_REG32(base + CSL_EPWM_TZSEL) | tzSignal));
4345 HW_WR_REG32(base + CSL_EPWM_TZSEL,
4346 (HW_RD_REG32(base + CSL_EPWM_TZSEL) & ~tzSignal));
4389 HW_WR_REG16(base + CSL_EPWM_TZDCSEL,
4390 ((HW_RD_REG16(base + CSL_EPWM_TZDCSEL) &
4391 ~(CSL_EPWM_TZDCSEL_DCAEVT1_MASK << (uint16_t)dcType)) |
4392 ((uint16_t)dcEvent << (uint16_t)dcType)));
4414 HW_WR_REG16(base + CSL_EPWM_TZCTL2,
4415 (HW_RD_REG16(base + CSL_EPWM_TZCTL2) | CSL_EPWM_TZCTL2_ETZE_MASK));
4435 HW_WR_REG16(base + CSL_EPWM_TZCTL2,
4436 (HW_RD_REG16(base + CSL_EPWM_TZCTL2) & ~CSL_EPWM_TZCTL2_ETZE_MASK));
4478 HW_WR_REG16(base + CSL_EPWM_TZCTL,
4479 ((HW_RD_REG16(base + CSL_EPWM_TZCTL) &
4480 ~(CSL_EPWM_TZCTL_TZA_MASK << (uint16_t)tzEvent)) |
4481 ((uint16_t)tzAction << (uint16_t)tzEvent)));
4529 HW_WR_REG16(base + CSL_EPWM_TZCTL2,
4530 ((HW_RD_REG16(base + CSL_EPWM_TZCTL2) &
4531 ~(CSL_EPWM_TZCTL2_TZAU_MASK << (uint16_t)tzAdvEvent)) |
4532 ((uint16_t)tzAdvAction << (uint16_t)tzAdvEvent)));
4534 HW_WR_REG16(base + CSL_EPWM_TZCTL2,
4535 (HW_RD_REG16(base + CSL_EPWM_TZCTL2) | CSL_EPWM_TZCTL2_ETZE_MASK));
4581 HW_WR_REG16(base + CSL_EPWM_TZCTLDCA,
4582 ((HW_RD_REG16(base + CSL_EPWM_TZCTLDCA) &
4583 ~(CSL_EPWM_TZCTLDCA_DCAEVT1U_MASK << (uint16_t)tzAdvDCEvent)) |
4584 ((uint16_t)tzAdvDCAction << (uint16_t)tzAdvDCEvent)));
4586 HW_WR_REG16(base + CSL_EPWM_TZCTL2,
4587 (HW_RD_REG16(base + CSL_EPWM_TZCTL2) | CSL_EPWM_TZCTL2_ETZE_MASK));
4632 HW_WR_REG16(base + CSL_EPWM_TZCTLDCB,
4633 ((HW_RD_REG16(base + CSL_EPWM_TZCTLDCB) &
4634 ~(CSL_EPWM_TZCTLDCB_DCBEVT1U_MASK << (uint16_t)tzAdvDCEvent)) |
4635 ((uint16_t)tzAdvDCAction << (uint16_t)tzAdvDCEvent)));
4637 HW_WR_REG16(base + CSL_EPWM_TZCTL2,
4638 (HW_RD_REG16(base + CSL_EPWM_TZCTL2) | CSL_EPWM_TZCTL2_ETZE_MASK));
4669 DebugP_assert((tzInterrupt >= 0U) && (tzInterrupt < 0x80U));
4674 HW_WR_REG16(base + CSL_EPWM_TZEINT,
4675 (HW_RD_REG16(base + CSL_EPWM_TZEINT) | tzInterrupt));
4711 HW_WR_REG16(base + CSL_EPWM_TZEINT,
4712 (HW_RD_REG16(base + CSL_EPWM_TZEINT) & ~tzInterrupt));
4735 static inline uint16_t
4741 return(HW_RD_REG16(base + CSL_EPWM_TZFLG) & 0xFFU);
4767 static inline uint16_t
4773 return(HW_RD_REG16(base + CSL_EPWM_TZCBCFLG) & 0x1FFU);
4797 static inline uint16_t
4803 return(HW_RD_REG16(base + CSL_EPWM_TZOSTFLG) & 0x1FFU);
4833 HW_WR_REG16(base + CSL_EPWM_TZCLR,
4834 ((HW_RD_REG16(base + CSL_EPWM_TZCLR) &
4835 ~CSL_EPWM_TZCLR_CBCPULSE_MASK) |
4836 ((uint16_t)clearEvent << CSL_EPWM_TZCLR_CBCPULSE_SHIFT)));
4873 HW_WR_REG16(base + CSL_EPWM_TZCLR,
4874 (HW_RD_REG16(base + CSL_EPWM_TZCLR) | tzFlags));
4911 HW_WR_REG16(base + CSL_EPWM_TZCBCCLR,
4912 (HW_RD_REG16(base + CSL_EPWM_TZCBCCLR) | tzCBCFlags));
4948 HW_WR_REG16(base + CSL_EPWM_TZOSTCLR,
4949 (HW_RD_REG16(base + CSL_EPWM_TZOSTCLR) | tzOSTFlags));
4982 HW_WR_REG16(base + CSL_EPWM_TZFRC,
4983 (HW_RD_REG16(base + CSL_EPWM_TZFRC) | tzForceEvent));
5009 HW_WR_REG16(base + CSL_EPWM_TZTRIPOUTSEL,
5010 (HW_RD_REG16(base + CSL_EPWM_TZTRIPOUTSEL) | tzOutput));
5036 HW_WR_REG16(base + CSL_EPWM_TZTRIPOUTSEL,
5037 (HW_RD_REG16(base + CSL_EPWM_TZTRIPOUTSEL) & ~tzOutput));
5060 HW_WR_REG16(base + CSL_EPWM_ETSEL,
5061 (HW_RD_REG16(base + CSL_EPWM_ETSEL) | CSL_EPWM_ETSEL_INTEN_MASK));
5081 HW_WR_REG16(base + CSL_EPWM_ETSEL,
5082 (HW_RD_REG16(base + CSL_EPWM_ETSEL) & ~CSL_EPWM_ETSEL_INTEN_MASK));
5113 uint16_t mixedSource)
5120 DebugP_assert(((interruptSource > 0U) && (interruptSource < 9U)) ||
5121 (interruptSource == 10U) || (interruptSource == 12U) ||
5122 (interruptSource == 14U));
5132 intSource = interruptSource >> 1U;
5137 HW_WR_REG16(base + CSL_EPWM_ETSEL,
5138 (HW_RD_REG16(base + CSL_EPWM_ETSEL) |
5139 CSL_EPWM_ETSEL_INTSELCMP_MASK));
5146 intSource = interruptSource;
5151 HW_WR_REG16(base + CSL_EPWM_ETSEL,
5152 (HW_RD_REG16(base + CSL_EPWM_ETSEL) &
5153 ~CSL_EPWM_ETSEL_INTSELCMP_MASK));
5157 intSource = interruptSource;
5162 HW_WR_REG16(base + CSL_EPWM_ETINTMIXEN, mixedSource);
5166 intSource = interruptSource;
5172 HW_WR_REG16(base + CSL_EPWM_ETSEL,
5173 ((HW_RD_REG16(base + CSL_EPWM_ETSEL) &
5174 ~CSL_EPWM_ETSEL_INTSEL_MASK) | intSource));
5202 HW_WR_REG16(base + CSL_EPWM_ETPS,
5203 (HW_RD_REG16(base + CSL_EPWM_ETPS) | CSL_EPWM_ETPS_INTPSSEL_MASK));
5205 HW_WR_REG16(base + CSL_EPWM_ETINTPS,
5206 ((HW_RD_REG16(base + CSL_EPWM_ETINTPS) &
5207 ~CSL_EPWM_ETINTPS_INTPRD2_MASK) | eventCount));
5229 return(((HW_RD_REG16(base + CSL_EPWM_ETFLG) & 0x1U) ==
5230 0x1U) ?
true :
false);
5250 HW_WR_REG16(base + CSL_EPWM_ETCLR,
5251 (HW_RD_REG16(base + CSL_EPWM_ETCLR) | CSL_EPWM_ETCLR_INT_MASK));
5274 HW_WR_REG16(base + CSL_EPWM_ETCNTINITCTL,
5275 (HW_RD_REG16(base + CSL_EPWM_ETCNTINITCTL) |
5276 CSL_EPWM_ETCNTINITCTL_INTINITEN_MASK));
5297 HW_WR_REG16(base + CSL_EPWM_ETCNTINITCTL,
5298 (HW_RD_REG16(base + CSL_EPWM_ETCNTINITCTL) &
5299 ~CSL_EPWM_ETCNTINITCTL_INTINITEN_MASK));
5323 HW_WR_REG16(base + CSL_EPWM_ETCNTINITCTL,
5324 (HW_RD_REG16(base + CSL_EPWM_ETCNTINITCTL) |
5325 CSL_EPWM_ETCNTINITCTL_INTINITFRC_MASK));
5348 DebugP_assert(eventCount <= CSL_EPWM_ETCNTINIT_INTINIT_MAX);
5353 HW_WR_REG16(base + CSL_EPWM_ETCNTINIT,
5354 ((HW_RD_REG16(base + CSL_EPWM_ETCNTINIT) &
5355 ~CSL_EPWM_ETCNTINIT_INTINIT_MASK) |
5356 (uint16_t)(eventCount & CSL_EPWM_ETCNTINIT_INTINIT_MASK)));
5370 static inline uint16_t
5376 return(((HW_RD_REG16(base + CSL_EPWM_ETINTPS) &
5377 CSL_EPWM_ETINTPS_INTCNT2_MASK) >>
5378 CSL_EPWM_ETINTPS_INTCNT2_SHIFT));
5398 HW_WR_REG16(base + CSL_EPWM_ETFRC,
5399 (HW_RD_REG16(base + CSL_EPWM_ETFRC) | CSL_EPWM_ETFRC_INT_MASK));
5428 HW_WR_REG16(base + CSL_EPWM_ETSEL,
5429 (HW_RD_REG16(base + CSL_EPWM_ETSEL) | CSL_EPWM_ETSEL_SOCAEN_MASK));
5433 HW_WR_REG16(base + CSL_EPWM_ETSEL,
5434 (HW_RD_REG16(base + CSL_EPWM_ETSEL) | CSL_EPWM_ETSEL_SOCBEN_MASK));
5461 HW_WR_REG16(base + CSL_EPWM_ETSEL,
5462 (HW_RD_REG16(base + CSL_EPWM_ETSEL) & ~CSL_EPWM_ETSEL_SOCAEN_MASK));
5466 HW_WR_REG16(base + CSL_EPWM_ETSEL,
5467 (HW_RD_REG16(base + CSL_EPWM_ETSEL) & ~CSL_EPWM_ETSEL_SOCBEN_MASK));
5507 uint16_t mixedSource)
5516 source = (uint16_t)socSource >> 1U;
5520 source = (uint16_t)socSource;
5528 HW_WR_REG16(base + CSL_EPWM_ETSEL,
5529 ((HW_RD_REG16(base + CSL_EPWM_ETSEL) &
5530 ~CSL_EPWM_ETSEL_SOCASEL_MASK) |
5531 (source << CSL_EPWM_ETSEL_SOCASEL_SHIFT)));
5544 HW_WR_REG16(base + CSL_EPWM_ETSEL,
5545 (HW_RD_REG16(base + CSL_EPWM_ETSEL) &
5546 ~CSL_EPWM_ETSEL_SOCASELCMP_MASK));
5556 HW_WR_REG16(base + CSL_EPWM_ETSEL,
5557 (HW_RD_REG16(base + CSL_EPWM_ETSEL) |
5558 CSL_EPWM_ETSEL_SOCASELCMP_MASK));
5565 HW_WR_REG16(base + CSL_EPWM_ETSOCAMIXEN, mixedSource);
5579 HW_WR_REG16(base + CSL_EPWM_ETSEL,
5580 ((HW_RD_REG16(base + CSL_EPWM_ETSEL) &
5581 ~CSL_EPWM_ETSEL_SOCBSEL_MASK) |
5582 (source << CSL_EPWM_ETSEL_SOCBSEL_SHIFT)));
5595 HW_WR_REG16(base + CSL_EPWM_ETSEL,
5596 (HW_RD_REG16(base + CSL_EPWM_ETSEL) &
5597 ~CSL_EPWM_ETSEL_SOCBSELCMP_MASK));
5607 HW_WR_REG16(base + CSL_EPWM_ETSEL,
5608 (HW_RD_REG16(base + CSL_EPWM_ETSEL) |
5609 CSL_EPWM_ETSEL_SOCBSELCMP_MASK));
5616 HW_WR_REG16(base + CSL_EPWM_ETSOCBMIXEN, mixedSource);
5653 uint16_t preScaleCount)
5658 DebugP_assert(preScaleCount <= CSL_EPWM_ETSOCPS_SOCAPRD2_MAX);
5663 HW_WR_REG16(base + CSL_EPWM_ETPS,
5664 (HW_RD_REG16(base + CSL_EPWM_ETPS) |
5665 CSL_EPWM_ETPS_SOCPSSEL_MASK));
5672 HW_WR_REG16(base + CSL_EPWM_ETSOCPS,
5673 ((HW_RD_REG16(base + CSL_EPWM_ETSOCPS) &
5674 ~CSL_EPWM_ETSOCPS_SOCAPRD2_MASK) |
5682 HW_WR_REG16(base + CSL_EPWM_ETSOCPS,
5683 ((HW_RD_REG16(base + CSL_EPWM_ETSOCPS) &
5684 ~CSL_EPWM_ETSOCPS_SOCBPRD2_MASK) |
5685 (preScaleCount << CSL_EPWM_ETSOCPS_SOCBPRD2_SHIFT)));
5712 return((((HW_RD_REG16(base + CSL_EPWM_ETFLG) >>
5713 ((uint16_t)adcSOCType + CSL_EPWM_ETFLG_SOCA_SHIFT)) &
5714 0x1U) == 0x1U) ?
true :
false);
5739 HW_WR_REG16(base + CSL_EPWM_ETCLR,
5740 (HW_RD_REG16(base + CSL_EPWM_ETCLR) |
5741 1U << ((uint16_t)adcSOCType + CSL_EPWM_ETCLR_SOCA_SHIFT)));
5770 HW_WR_REG16(base + CSL_EPWM_ETCNTINITCTL,
5771 (HW_RD_REG16(base + CSL_EPWM_ETCNTINITCTL) | 1U <<
5772 ((uint16_t)adcSOCType + CSL_EPWM_ETCNTINITCTL_SOCAINITEN_SHIFT)));
5800 HW_WR_REG16(base + CSL_EPWM_ETCNTINITCTL,
5801 (HW_RD_REG16(base + CSL_EPWM_ETCNTINITCTL) &
5802 ~(1U << ((uint16_t)adcSOCType +
5803 CSL_EPWM_ETCNTINITCTL_SOCAINITEN_SHIFT))));
5829 HW_WR_REG16(base + CSL_EPWM_ETCNTINITCTL,
5830 (HW_RD_REG16(base + CSL_EPWM_ETCNTINITCTL) |
5831 1U << ((uint16_t)adcSOCType +
5832 CSL_EPWM_ETCNTINITCTL_SOCAINITFRC_SHIFT)));
5855 uint16_t eventCount)
5860 DebugP_assert(eventCount <= CSL_EPWM_ETCNTINIT_SOCAINIT_MAX);
5867 HW_WR_REG16(base + CSL_EPWM_ETCNTINIT,
5868 ((HW_RD_REG16(base + CSL_EPWM_ETCNTINIT) &
5869 ~CSL_EPWM_ETCNTINIT_SOCAINIT_MASK) |
5870 (uint16_t)(eventCount << CSL_EPWM_ETCNTINIT_SOCAINIT_SHIFT)));
5874 HW_WR_REG16(base + CSL_EPWM_ETCNTINIT,
5875 ((HW_RD_REG16(base + CSL_EPWM_ETCNTINIT) &
5876 ~CSL_EPWM_ETCNTINIT_SOCBINIT_MASK) |
5877 (eventCount << CSL_EPWM_ETCNTINIT_SOCBINIT_SHIFT)));
5896 static inline uint16_t
5900 uint16_t eventCount;
5907 eventCount = (HW_RD_REG16(base + CSL_EPWM_ETSOCPS) >>
5908 CSL_EPWM_ETSOCPS_SOCACNT2_SHIFT) &
5909 CSL_EPWM_ETSOCPS_SOCACNT2_MAX;
5913 eventCount = (HW_RD_REG16(base + CSL_EPWM_ETSOCPS) >>
5914 CSL_EPWM_ETSOCPS_SOCBCNT2_SHIFT) &
5915 CSL_EPWM_ETSOCPS_SOCBCNT2_MAX;
5942 HW_WR_REG16(base + CSL_EPWM_ETFRC,
5943 (HW_RD_REG16(base + CSL_EPWM_ETFRC) |
5944 1U << ((uint16_t)adcSOCType + CSL_EPWM_ETFRC_SOCA_SHIFT)));
5983 HW_WR_REG16(base + CSL_EPWM_DCTRIPSEL,
5984 ((HW_RD_REG16(base + CSL_EPWM_DCTRIPSEL) &
5985 ~(CSL_EPWM_DCTRIPSEL_DCAHCOMPSEL_MASK <<
5986 ((uint16_t)dcType << 2U))) |
5987 ((uint16_t)tripSource << ((uint16_t)dcType << 2U))));
6010 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6011 (HW_RD_REG16(base + CSL_EPWM_DCFCTL) | CSL_EPWM_DCFCTL_BLANKE_MASK));
6031 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6032 (HW_RD_REG16(base + CSL_EPWM_DCFCTL) & ~CSL_EPWM_DCFCTL_BLANKE_MASK));
6053 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6054 (HW_RD_REG16(base + CSL_EPWM_DCFCTL) | CSL_EPWM_DCFCTL_BLANKINV_MASK));
6074 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6075 (HW_RD_REG16(base + CSL_EPWM_DCFCTL) &
6076 ~CSL_EPWM_DCFCTL_BLANKINV_MASK));
6101 uint16_t mixedSource)
6108 HW_WR_REG16(base + CSL_EPWM_BLANKPULSEMIXSEL, mixedSource);
6114 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6115 ((HW_RD_REG16(base + CSL_EPWM_DCFCTL) &
6116 ~CSL_EPWM_DCFCTL_PULSESEL_MASK) |
6117 ((uint16_t)((uint32_t)blankingPulse <<
6118 CSL_EPWM_DCFCTL_PULSESEL_SHIFT))));
6146 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6147 ((HW_RD_REG16(base + CSL_EPWM_DCFCTL) & ~CSL_EPWM_DCFCTL_SRCSEL_MASK) |
6148 ((uint16_t)filterInput)));
6172 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6173 (HW_RD_REG16(base + CSL_EPWM_DCFCTL) |
6174 CSL_EPWM_DCFCTL_EDGEFILTSEL_MASK));
6194 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6195 (HW_RD_REG16(base + CSL_EPWM_DCFCTL) &
6196 ~CSL_EPWM_DCFCTL_EDGEFILTSEL_MASK));
6222 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6223 (HW_RD_REG16(base + CSL_EPWM_DCFCTL) &
6224 ~CSL_EPWM_DCFCTL_EDGEMODE_MASK) |
6225 (edgeMode << CSL_EPWM_DCFCTL_EDGEMODE_SHIFT));
6256 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6257 (HW_RD_REG16(base + CSL_EPWM_DCFCTL) &
6258 ~CSL_EPWM_DCFCTL_EDGECOUNT_MASK) |
6259 (edgeCount << CSL_EPWM_DCFCTL_EDGECOUNT_SHIFT));
6274 static inline uint16_t
6280 return((HW_RD_REG16(base + CSL_EPWM_DCFCTL) &
6281 CSL_EPWM_DCFCTL_EDGECOUNT_MASK) >>
6282 CSL_EPWM_DCFCTL_EDGECOUNT_SHIFT);
6297 static inline uint16_t
6303 return((HW_RD_REG16(base + CSL_EPWM_DCFCTL) &
6304 CSL_EPWM_DCFCTL_EDGESTATUS_MASK) >>
6305 CSL_EPWM_DCFCTL_EDGESTATUS_SHIFT);
6328 HW_WR_REG16(base + CSL_EPWM_DCFOFFSET, windowOffsetCount);
6350 HW_WR_REG16(base + CSL_EPWM_DCFWINDOW, windowLengthCount);
6364 static inline uint16_t
6370 return(HW_RD_REG16(base + CSL_EPWM_DCFOFFSETCNT));
6384 static inline uint16_t
6390 return(HW_RD_REG16(base + CSL_EPWM_DCFWINDOWCNT));
6428 uint32_t registerOffset;
6437 HW_WR_REG16(base + registerOffset,
6438 ((HW_RD_REG16(base + registerOffset) &
6439 ~CSL_EPWM_DCACTL_EVT1SRCSEL_MASK) |
6440 (uint16_t)dcEventSource));
6444 HW_WR_REG16(base + registerOffset,
6445 ((HW_RD_REG16(base + registerOffset) &
6446 ~CSL_EPWM_DCACTL_EVT2SRCSEL_MASK) |
6447 ((uint16_t)dcEventSource << CSL_EPWM_DCACTL_EVT2SRCSEL_SHIFT)));
6483 uint32_t registerOffset;
6492 HW_WR_REG16(base + registerOffset,
6493 ((HW_RD_REG16(base + registerOffset) &
6494 ~CSL_EPWM_DCACTL_EVT1FRCSYNCSEL_MASK) |
6495 ((uint16_t)syncMode << CSL_EPWM_DCACTL_EVT1FRCSYNCSEL_SHIFT)));
6499 HW_WR_REG16(base + registerOffset,
6500 ((HW_RD_REG16(base + registerOffset) &
6501 ~CSL_EPWM_DCACTL_EVT2FRCSYNCSEL_MASK) |
6502 ((uint16_t)syncMode << CSL_EPWM_DCACTL_EVT2FRCSYNCSEL_SHIFT)));
6526 uint32_t registerOffset;
6533 HW_WR_REG16(base + registerOffset,
6534 (HW_RD_REG16(base + registerOffset) | CSL_EPWM_DCACTL_EVT1SOCE_MASK));
6557 uint32_t registerOffset;
6564 HW_WR_REG16(base + registerOffset,
6565 (HW_RD_REG16(base + registerOffset) & ~CSL_EPWM_DCACTL_EVT1SOCE_MASK));
6588 uint32_t registerOffset;
6595 HW_WR_REG16(base + registerOffset,
6596 (HW_RD_REG16(base + registerOffset) | CSL_EPWM_DCACTL_EVT1SYNCE_MASK));
6619 uint32_t registerOffset;
6626 HW_WR_REG16(base + registerOffset,
6627 (HW_RD_REG16(base + registerOffset) &
6628 ~CSL_EPWM_DCACTL_EVT1SYNCE_MASK));
6661 uint32_t registerOffset;
6670 HW_WR_REG16(base + registerOffset,
6671 ((HW_RD_REG16(base + registerOffset) &
6672 ~CSL_EPWM_DCACTL_EVT1LATSEL_MASK) |
6673 ((uint16_t)latchMode << CSL_EPWM_DCACTL_EVT1LATSEL_SHIFT)));
6677 HW_WR_REG16(base + registerOffset,
6678 ((HW_RD_REG16(base + registerOffset) &
6679 ~CSL_EPWM_DCACTL_EVT2LATSEL_MASK) |
6680 ((uint16_t)latchMode << CSL_EPWM_DCACTL_EVT2LATSEL_SHIFT)));
6719 uint32_t registerOffset;
6728 HW_WR_REG16(base + registerOffset,
6729 ((HW_RD_REG16(base + registerOffset) &
6730 ~CSL_EPWM_DCACTL_EVT1LATCLRSEL_MASK) |
6731 ((uint16_t)clearEvent << CSL_EPWM_DCACTL_EVT1LATCLRSEL_SHIFT)));
6735 HW_WR_REG16(base + registerOffset,
6736 ((HW_RD_REG16(base + registerOffset) &
6737 ~CSL_EPWM_DCACTL_EVT2LATCLRSEL_MASK) |
6738 ((uint16_t)clearEvent << CSL_EPWM_DCACTL_EVT2LATCLRSEL_SHIFT)));
6770 uint32_t registerOffset;
6780 status = HW_RD_REG16(base + registerOffset) &
6781 CSL_EPWM_DCACTL_EVT1LAT_MASK;
6785 status = HW_RD_REG16(base + registerOffset) &
6786 CSL_EPWM_DCACTL_EVT2LAT_MASK;
6789 return(status != 0U);
6812 HW_WR_REG16(base + CSL_EPWM_DCCAPCTL,
6813 (HW_RD_REG16(base + CSL_EPWM_DCCAPCTL) | CSL_EPWM_DCCAPCTL_CAPE_MASK));
6833 HW_WR_REG16(base + CSL_EPWM_DCCAPCTL,
6834 (HW_RD_REG16(base + CSL_EPWM_DCCAPCTL) &
6835 ~CSL_EPWM_DCCAPCTL_CAPE_MASK));
6856 if(enableShadowMode)
6861 HW_WR_REG16(base + CSL_EPWM_DCCAPCTL,
6862 (HW_RD_REG16(base + CSL_EPWM_DCCAPCTL) &
6863 ~CSL_EPWM_DCCAPCTL_SHDWMODE_MASK));
6870 HW_WR_REG16(base + CSL_EPWM_DCCAPCTL,
6871 (HW_RD_REG16(base + CSL_EPWM_DCCAPCTL) |
6872 CSL_EPWM_DCCAPCTL_SHDWMODE_MASK));
6896 return((HW_RD_REG16(base + CSL_EPWM_DCCAPCTL) &
6897 CSL_EPWM_DCCAPCTL_CAPSTS_MASK) == CSL_EPWM_DCCAPCTL_CAPSTS_MASK);
6913 static inline uint16_t
6919 return(HW_RD_REG16(base + CSL_EPWM_DCCAP));
6948 uint32_t registerOffset;
6954 registerOffset = CSL_EPWM_DCAHTRIPSEL +
6960 HW_WR_REG16(base + registerOffset,
6961 (HW_RD_REG16(base + registerOffset) | tripInput));
6966 HW_WR_REG16(base + CSL_EPWM_DCTRIPSEL,
6967 (HW_RD_REG16(base + CSL_EPWM_DCTRIPSEL) |
6968 (CSL_EPWM_DCTRIPSEL_DCAHCOMPSEL_MASK << ((uint16_t)dcType << 2U))));
6997 uint32_t registerOffset;
7003 registerOffset = CSL_EPWM_DCAHTRIPSEL +
7009 HW_WR_REG16(base + registerOffset,
7010 (HW_RD_REG16(base + registerOffset) & ~tripInput));
7033 HW_WR_REG16(base + CSL_EPWM_VCAPCTL,
7034 (HW_RD_REG16(base + CSL_EPWM_VCAPCTL) | CSL_EPWM_VCAPCTL_VCAPE_MASK));
7054 HW_WR_REG16(base + CSL_EPWM_VCAPCTL,
7055 (HW_RD_REG16(base + CSL_EPWM_VCAPCTL) & ~CSL_EPWM_VCAPCTL_VCAPE_MASK));
7079 HW_WR_REG16(base + CSL_EPWM_VCAPCTL,
7080 (HW_RD_REG16(base + CSL_EPWM_VCAPCTL) |
7081 CSL_EPWM_VCAPCTL_VCAPSTART_MASK));
7105 HW_WR_REG16(base + CSL_EPWM_VCAPCTL,
7106 ((HW_RD_REG16(base + CSL_EPWM_VCAPCTL) &
7107 ~CSL_EPWM_VCAPCTL_TRIGSEL_MASK) |
7108 ((uint16_t)trigger << CSL_EPWM_VCAPCTL_TRIGSEL_SHIFT)));
7143 HW_WR_REG16(base + CSL_EPWM_VCNTCFG,
7144 ((HW_RD_REG16(base + CSL_EPWM_VCNTCFG) &
7145 ~(CSL_EPWM_VCNTCFG_STARTEDGE_MASK | CSL_EPWM_VCNTCFG_STOPEDGE_MASK)) |
7146 (startCount | (stopCount << CSL_EPWM_VCNTCFG_STOPEDGE_SHIFT))));
7166 HW_WR_REG16(base + CSL_EPWM_VCAPCTL,
7167 (HW_RD_REG16(base + CSL_EPWM_VCAPCTL) |
7168 CSL_EPWM_VCAPCTL_EDGEFILTDLYSEL_MASK));
7188 HW_WR_REG16(base + CSL_EPWM_VCAPCTL,
7189 (HW_RD_REG16(base + CSL_EPWM_VCAPCTL) &
7190 ~CSL_EPWM_VCAPCTL_EDGEFILTDLYSEL_MASK));
7211 HW_WR_REG16(base + CSL_EPWM_SWVDELVAL, delayOffsetValue);
7232 HW_WR_REG16(base + CSL_EPWM_VCAPCTL,
7233 ((HW_RD_REG16(base + CSL_EPWM_VCAPCTL) &
7234 ~CSL_EPWM_VCAPCTL_VDELAYDIV_MASK) |
7235 ((uint16_t)delayMode << CSL_EPWM_VCAPCTL_VDELAYDIV_SHIFT)));
7262 return(((HW_RD_REG16(base + CSL_EPWM_VCNTCFG) &
7263 CSL_EPWM_VCNTCFG_STARTEDGESTS_MASK) ==
7264 CSL_EPWM_VCNTCFG_STARTEDGESTS_MASK) ?
true :
false);
7271 return(((HW_RD_REG16(base + CSL_EPWM_VCNTCFG) &
7272 CSL_EPWM_VCNTCFG_STOPEDGESTS_MASK) ==
7273 CSL_EPWM_VCNTCFG_STOPEDGESTS_MASK) ?
true :
false);
7291 static inline uint16_t
7297 return(HW_RD_REG16(base + CSL_EPWM_VCNTVAL));
7311 static inline uint16_t
7317 return(HW_RD_REG16(base + CSL_EPWM_HWVDELVAL));
7339 HW_WR_REG16(base + CSL_EPWM_GLDCTL,
7340 (HW_RD_REG16(base + CSL_EPWM_GLDCTL) | CSL_EPWM_GLDCTL_GLD_MASK));
7361 HW_WR_REG16(base + CSL_EPWM_GLDCTL,
7362 (HW_RD_REG16(base + CSL_EPWM_GLDCTL) & ~CSL_EPWM_GLDCTL_GLD_MASK));
7400 HW_WR_REG16(base + CSL_EPWM_GLDCTL,
7401 ((HW_RD_REG16(base + CSL_EPWM_GLDCTL) &
7402 ~CSL_EPWM_GLDCTL_GLDMODE_MASK) |
7403 ((uint16_t)loadTrigger << CSL_EPWM_GLDCTL_GLDMODE_SHIFT)));
7433 HW_WR_REG16(base + CSL_EPWM_GLDCTL,
7434 ((HW_RD_REG16(base + CSL_EPWM_GLDCTL) & ~CSL_EPWM_GLDCTL_GLDPRD_MASK) |
7435 (prescalePulseCount << CSL_EPWM_GLDCTL_GLDPRD_SHIFT)));
7451 static inline uint16_t
7457 return((HW_RD_REG16(base + CSL_EPWM_GLDCTL) >>
7458 CSL_EPWM_GLDCTL_GLDCNT_SHIFT) & CSL_EPWM_GLDCTL_GLDCNT_MAX);
7480 HW_WR_REG16(base + CSL_EPWM_GLDCTL,
7481 (HW_RD_REG16(base + CSL_EPWM_GLDCTL) &
7482 ~CSL_EPWM_GLDCTL_OSHTMODE_MASK));
7504 HW_WR_REG16(base + CSL_EPWM_GLDCTL,
7505 (HW_RD_REG16(base + CSL_EPWM_GLDCTL) | CSL_EPWM_GLDCTL_OSHTMODE_MASK));
7527 HW_WR_REG16(base + CSL_EPWM_GLDCTL2,
7528 (HW_RD_REG16(base + CSL_EPWM_GLDCTL2) | CSL_EPWM_GLDCTL2_OSHTLD_MASK));
7549 HW_WR_REG16(base + CSL_EPWM_GLDCTL2,
7550 (HW_RD_REG16(base + CSL_EPWM_GLDCTL2) | CSL_EPWM_GLDCTL2_GFRCLD_MASK));
7584 DebugP_assert((loadRegister > 0x0000U) && (loadRegister < 0x0800U));
7589 HW_WR_REG16(base + CSL_EPWM_GLDCFG,
7590 (HW_RD_REG16(base + CSL_EPWM_GLDCFG) | loadRegister));
7625 DebugP_assert((loadRegister > 0x0000U) && (loadRegister < 0x0800U));
7631 HW_WR_REG16(base + CSL_EPWM_GLDCFG,
7632 (HW_RD_REG16(base + CSL_EPWM_GLDCFG) & ~loadRegister));
7654 HW_WR_REG32(base + CSL_EPWM_EPWMLOCK,
7678 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
7679 (HW_RD_REG32(base + CSL_EPWM_MINDBCFG) |
7680 CSL_EPWM_MINDBCFG_ENABLEA_MASK));
7684 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
7685 (HW_RD_REG32(base + CSL_EPWM_MINDBCFG) |
7686 CSL_EPWM_MINDBCFG_ENABLEB_MASK));
7707 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
7708 (HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
7709 ~CSL_EPWM_MINDBCFG_ENABLEA_MASK));
7713 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
7714 (HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
7715 ~CSL_EPWM_MINDBCFG_ENABLEB_MASK));
7739 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
7740 ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
7741 ~CSL_EPWM_MINDBCFG_INVERTA_MASK) |
7742 (invert<<CSL_EPWM_MINDBCFG_INVERTA_SHIFT)));
7746 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
7747 ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
7748 ~CSL_EPWM_MINDBCFG_INVERTB_MASK) |
7749 (invert<<CSL_EPWM_MINDBCFG_INVERTB_SHIFT)));
7770 uint32_t referenceSignal)
7774 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
7775 ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
7776 ~CSL_EPWM_MINDBCFG_POLSELA_MASK) |
7777 (referenceSignal<<CSL_EPWM_MINDBCFG_POLSELA_SHIFT)));
7781 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
7782 ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
7783 ~CSL_EPWM_MINDBCFG_POLSELB_MASK) |
7784 (referenceSignal<<CSL_EPWM_MINDBCFG_POLSELB_SHIFT)));
7804 uint32_t blockingSignal)
7808 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
7809 ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
7810 ~CSL_EPWM_MINDBCFG_SELBLOCKA_MASK) |
7811 (blockingSignal<<CSL_EPWM_MINDBCFG_SELBLOCKA_SHIFT)));
7815 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
7816 ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
7817 ~CSL_EPWM_MINDBCFG_SELBLOCKB_MASK) |
7818 (blockingSignal<<CSL_EPWM_MINDBCFG_SELBLOCKB_SHIFT)));
7837 uint32_t referenceSignal)
7841 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
7842 ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
7843 ~CSL_EPWM_MINDBCFG_SELA_MASK) |
7844 (referenceSignal<<CSL_EPWM_MINDBCFG_SELA_SHIFT)));
7848 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
7849 ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
7850 ~CSL_EPWM_MINDBCFG_SELB_MASK) |
7851 (referenceSignal<<CSL_EPWM_MINDBCFG_SELB_SHIFT)));
7867 static inline uint32_t
7874 retval = (HW_RD_REG32(base + CSL_EPWM_MINDBDLY) &
7875 CSL_EPWM_MINDBDLY_DELAYA_MASK);
7879 retval = (HW_RD_REG32(base + CSL_EPWM_MINDBDLY) &
7880 CSL_EPWM_MINDBDLY_DELAYB_MASK);
7905 HW_WR_REG32(base + CSL_EPWM_MINDBDLY,
7906 ((HW_RD_REG32(base + CSL_EPWM_MINDBDLY) &
7907 ~CSL_EPWM_MINDBDLY_DELAYA_MASK) |
7908 (delay<<CSL_EPWM_MINDBDLY_DELAYA_SHIFT)));
7912 HW_WR_REG32(base + CSL_EPWM_MINDBDLY,
7913 ((HW_RD_REG32(base + CSL_EPWM_MINDBDLY) &
7914 ~CSL_EPWM_MINDBDLY_DELAYB_MASK) |
7915 (delay<<CSL_EPWM_MINDBDLY_DELAYB_SHIFT)));
7939 HW_WR_REG32(base + CSL_EPWM_LUTCTLA,
7940 (HW_RD_REG32(base + CSL_EPWM_LUTCTLA) |
7941 CSL_EPWM_LUTCTLA_BYPASS_MASK));
7945 HW_WR_REG32(base + CSL_EPWM_LUTCTLB,
7946 (HW_RD_REG32(base + CSL_EPWM_LUTCTLB) |
7947 CSL_EPWM_LUTCTLB_BYPASS_MASK));
7968 HW_WR_REG32(base + CSL_EPWM_LUTCTLA,
7969 (HW_RD_REG32(base + CSL_EPWM_LUTCTLA) &
7970 ~CSL_EPWM_LUTCTLA_BYPASS_MASK));
7974 HW_WR_REG32(base + CSL_EPWM_LUTCTLB,
7975 (HW_RD_REG32(base + CSL_EPWM_LUTCTLB) &
7976 ~CSL_EPWM_LUTCTLB_BYPASS_MASK));
7998 HW_WR_REG32(base + CSL_EPWM_LUTCTLA,
7999 ((HW_RD_REG32(base + CSL_EPWM_LUTCTLA) &
8000 ~CSL_EPWM_LUTCTLA_SELXBAR_MASK) |
8001 (xbarInput<<CSL_EPWM_LUTCTLA_SELXBAR_SHIFT)));
8005 HW_WR_REG32(base + CSL_EPWM_LUTCTLB,
8006 ((HW_RD_REG32(base + CSL_EPWM_LUTCTLB) &
8007 ~CSL_EPWM_LUTCTLB_SELXBAR_MASK) |
8008 (xbarInput<<CSL_EPWM_LUTCTLB_SELXBAR_SHIFT)));
8030 HW_WR_REG32(base + CSL_EPWM_LUTCTLA,
8031 ((HW_RD_REG32(base + CSL_EPWM_LUTCTLA) &
8032 ~(CSL_EPWM_LUTCTLA_LUTDEC0_MAX <<
8033 (CSL_EPWM_LUTCTLA_LUTDEC0_SHIFT+decx))) |
8034 (force<<(CSL_EPWM_LUTCTLA_LUTDEC0_SHIFT+decx))));
8068 HW_WR_REG32(base + CSL_EPWM_TBPHS, phaseCount);
8098 HW_WR_REG16(base + CSL_EPWM_TBPHS,
8099 ((HW_RD_REG16(base + CSL_EPWM_TBPHS) &
8100 ~((uint32_t)CSL_EPWM_TBPHS_TBPHSHR_MASK)) |
8101 ((uint32_t)hrPhaseCount << CSL_EPWM_TBPHS_TBPHSHR_SHIFT)));
8128 DebugP_assert(hrPeriodCount <= CSL_EPWM_TBPRDHR_TBPRDHR_MAX);
8133 HW_WR_REG16(base + CSL_EPWM_TBPRDHR, hrPeriodCount << 8);
8147 static inline uint16_t
8153 return(HW_RD_REG16(base + CSL_EPWM_TBPRDHR));
8189 HW_WR_REG16(base + CSL_EPWM_HRCNFG,
8190 ((HW_RD_REG16(base + CSL_EPWM_HRCNFG) &
8191 ~(CSL_EPWM_HRCNFG_EDGMODE_MAX << (uint16_t)channel)) |
8192 ((uint16_t)mepEdgeMode << (uint16_t)channel)));
8226 HW_WR_REG16(base + CSL_EPWM_HRCNFG,
8227 ((HW_RD_REG16(base + CSL_EPWM_HRCNFG) &
8228 ~(CSL_EPWM_HRCNFG_CTLMODE_MAX << ((uint16_t)channel + 2U))) |
8229 ((uint16_t)mepCtrlMode << ((uint16_t)channel + 2U))));
8264 HW_WR_REG16(base + CSL_EPWM_HRCNFG,
8265 ((HW_RD_REG16(base + CSL_EPWM_HRCNFG) &
8266 ~(CSL_EPWM_HRCNFG_HRLOAD_MAX << ((uint16_t)channel + 3U))) |
8267 ((uint16_t)loadEvent << ((uint16_t)channel + 3U))));
8290 if(enableOutputSwap)
8292 HW_WR_REG16(base + CSL_EPWM_HRCNFG,
8293 HW_RD_REG16(base + CSL_EPWM_HRCNFG) | CSL_EPWM_HRCNFG_SWAPAB_MASK);
8297 HW_WR_REG16(base + CSL_EPWM_HRCNFG,
8298 HW_RD_REG16(base + CSL_EPWM_HRCNFG) & ~CSL_EPWM_HRCNFG_SWAPAB_MASK);
8323 HW_WR_REG16(base + CSL_EPWM_HRCNFG,
8324 ((HW_RD_REG16(base + CSL_EPWM_HRCNFG) & ~(CSL_EPWM_HRCNFG_SELOUTB_MASK)) |
8325 ((uint16_t)outputOnB << CSL_EPWM_HRCNFG_SELOUTB_SHIFT)));
8346 HW_WR_REG16(base + CSL_EPWM_HRCNFG,
8347 HW_RD_REG16(base + CSL_EPWM_HRCNFG) | CSL_EPWM_HRCNFG_AUTOCONV_MASK);
8368 HW_WR_REG16(base + CSL_EPWM_HRCNFG,
8369 HW_RD_REG16(base + CSL_EPWM_HRCNFG) & ~CSL_EPWM_HRCNFG_AUTOCONV_MASK);
8389 HW_WR_REG16(base + CSL_EPWM_HRPCTL,
8390 HW_RD_REG16(base + CSL_EPWM_HRPCTL) | CSL_EPWM_HRPCTL_HRPE_MASK);
8410 HW_WR_REG16(base + CSL_EPWM_HRPCTL,
8411 HW_RD_REG16(base + CSL_EPWM_HRPCTL) & ~CSL_EPWM_HRPCTL_HRPE_MASK);
8432 HW_WR_REG16(base + CSL_EPWM_HRPCTL,
8433 HW_RD_REG16(base + CSL_EPWM_HRPCTL) | CSL_EPWM_HRPCTL_TBPHSHRLOADE_MASK);
8453 HW_WR_REG16(base + CSL_EPWM_HRPCTL,
8454 HW_RD_REG16(base + CSL_EPWM_HRPCTL) & ~CSL_EPWM_HRPCTL_TBPHSHRLOADE_MASK);
8493 HW_WR_REG16(base + CSL_EPWM_HRPCTL,
8494 ((HW_RD_REG16(base + CSL_EPWM_HRPCTL) &
8495 ~(CSL_EPWM_HRPCTL_PWMSYNCSELX_MASK | CSL_EPWM_HRPCTL_PWMSYNCSEL_MASK)) |
8496 ((uint16_t)syncPulseSource << 1U)));
8500 HW_WR_REG16(base + CSL_EPWM_HRPCTL,
8501 ((HW_RD_REG16(base + CSL_EPWM_HRPCTL) & ~CSL_EPWM_HRPCTL_PWMSYNCSELX_MASK) |
8502 ((uint16_t)syncPulseSource << CSL_EPWM_HRPCTL_PWMSYNCSELX_SHIFT)));
8529 HW_WR_REG16(base + CSL_EPWM_TRREM, trremVal & CSL_EPWM_TRREM_TRREM_MASK);
8571 HW_WR_REG32(base + CSL_EPWM_CMPA, compCount << 8);
8578 HW_WR_REG32(base + CSL_EPWM_CMPB, compCount << 8);
8599 static inline uint32_t
8613 compCount = HW_RD_REG32(base + CSL_EPWM_CMPA);
8620 compCount = HW_RD_REG32(base + CSL_EPWM_CMPA);
8648 uint16_t hrCompCount)
8663 HW_WR_REG32(base + CSL_EPWM_CMPA,
8664 HW_RD_REG32(base + CSL_EPWM_CMPA) | (hrCompCount & CSL_EPWM_CMPA_CMPAHR_MASK));
8671 HW_WR_REG32(base + CSL_EPWM_CMPB,
8672 HW_RD_REG32(base + CSL_EPWM_CMPB) | (hrCompCount & CSL_EPWM_CMPB_CMPBHR_MASK));
8692 static inline uint16_t
8696 uint16_t hrCompCount;
8706 hrCompCount = (HW_RD_REG16(base + CSL_EPWM_CMPA) & CSL_EPWM_CMPA_CMPAHR_MASK);
8713 hrCompCount = (HW_RD_REG16(base + CSL_EPWM_CMPB) & CSL_EPWM_CMPB_CMPBHR_MASK);
8716 return(hrCompCount);
8746 HW_WR_REG16(base + CSL_EPWM_DBREDHR,
8747 HW_RD_REG16(base + CSL_EPWM_DBREDHR) |
8748 (hrRedCount << CSL_EPWM_DBREDHR_DBREDHR_SHIFT));
8777 HW_WR_REG16(base + CSL_EPWM_DBFEDHR,
8778 HW_RD_REG16(base + CSL_EPWM_DBFEDHR) &
8779 ~CSL_EPWM_DBFEDHR_DBFEDHR_MASK |
8780 (hrFedCount << CSL_EPWM_DBFEDHR_DBFEDHR_SHIFT));
8808 HW_WR_REG16(base + CSL_OTTOCAL_HRMSTEP,
8809 ((HW_RD_REG16(base + CSL_OTTOCAL_HRMSTEP) & ~CSL_OTTOCAL_HRMSTEP_HRMSTEP_MASK) |
8810 mepCount << CSL_OTTOCAL_HRMSTEP_HRMSTEP_SHIFT));
8841 HW_WR_REG16(base + CSL_EPWM_HRCNFG2,
8842 ((HW_RD_REG16(base + CSL_EPWM_HRCNFG2) & ~CSL_EPWM_HRCNFG2_EDGMODEDB_MASK) |
8843 ((uint16_t)mepDBEdge << CSL_EPWM_HRCNFG2_EDGMODEDB_SHIFT)));
8871 HW_WR_REG16(base + CSL_EPWM_HRCNFG2,
8872 ((HW_RD_REG16(base + CSL_EPWM_HRCNFG2) & ~CSL_EPWM_HRCNFG2_CTLMODEDBRED_MASK) |
8873 ((uint16_t)loadEvent << CSL_EPWM_HRCNFG2_CTLMODEDBRED_SHIFT)));
8900 HW_WR_REG16(base + CSL_EPWM_HRCNFG2,
8901 ((HW_RD_REG16(base + CSL_EPWM_HRCNFG2) & ~CSL_EPWM_HRCNFG2_CTLMODEDBFED_MASK) |
8902 ((uint16_t)loadEvent << CSL_EPWM_HRCNFG2_CTLMODEDBFED_SHIFT)));
8956 #endif // EPWM_V1_H_