AM263Px MCU+ SDK  10.01.00
soc_xbar.h
Go to the documentation of this file.
1 /********************************************************************
2  * Copyright (C) 2020 Texas Instruments Incorporated.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  *
8  * Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  *
11  * Redistributions in binary form must reproduce the above copyright
12  * notice, this list of conditions and the following disclaimer in the
13  * documentation and/or other materials provided with the
14  * distribution.
15  *
16  * Neither the name of Texas Instruments Incorporated nor the names of
17  * its contributors may be used to endorse or promote products derived
18  * from this software without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  *
32  * Name : soc_xbar.h
33 */
34 
35 #ifndef SOC_XBAR_AM263PX_H_
36 #define SOC_XBAR_AM263PX_H_
37 
38 //*****************************************************************************
39 //
40 // If building with a C++ compiler, make all of the definitions in this header
41 // have a C binding.
42 //
43 //*****************************************************************************
44 #ifdef __cplusplus
45 extern "C"
46 {
47 #endif
48 
58 #include <stdbool.h>
59 #include <stdint.h>
60 #include <drivers/hw_include/hw_types.h>
61 #include <drivers/hw_include/cslr_soc.h>
62 #include <kernel/dpl/DebugP.h>
63 
64 #define CSL_CONTROLSS_INPUTXBAR_STEP (CSL_CONTROLSS_INPUTXBAR_INPUTXBAR1_GSEL - CSL_CONTROLSS_INPUTXBAR_INPUTXBAR0_GSEL)
65 #define CSL_CONTROLSS_PWMXBAR_STEP (CSL_CONTROLSS_PWMXBAR_PWMXBAR1_G0 - CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G0)
66 #define CSL_CONTROLSS_MDLXBAR_STEP (CSL_CONTROLSS_MDLXBAR_MDLXBAR1_G0 - CSL_CONTROLSS_MDLXBAR_MDLXBAR0_G0)
67 #define CSL_CONTROLSS_ICLXBAR_STEP (CSL_CONTROLSS_ICLXBAR_ICLXBAR1_G0 - CSL_CONTROLSS_ICLXBAR_ICLXBAR0_G0)
68 #define CSL_CONTROLSS_INTXBAR_STEP (CSL_CONTROLSS_INTXBAR_INTXBAR1_G0 - CSL_CONTROLSS_INTXBAR_INTXBAR0_G0)
69 #define CSL_CONTROLSS_DMAXBAR_STEP (CSL_CONTROLSS_DMAXBAR_DMAXBAR1_GSEL - CSL_CONTROLSS_DMAXBAR_DMAXBAR0_GSEL)
70 #define CSL_CONTROLSS_OUTPUTXBAR_STEP (CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR1_G0 - CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G0)
71 #define CSL_CONTROLSS_PWMSYNCOUTXBAR_STEP (CSL_CONTROLSS_PWMSYNCOUTXBAR_PWMSYNCOUTXBAR1_G0 - CSL_CONTROLSS_PWMSYNCOUTXBAR_PWMSYNCOUTXBAR0_G0)
72 
83 static inline void
84 SOC_xbarSelectInputXBarInputSource(uint32_t base, uint8_t out, uint8_t group_select, uint8_t group0_muxctl, uint8_t group1_muxctl)
85 {
86  HW_WR_REG32(base + CSL_CONTROLSS_INPUTXBAR_INPUTXBAR0_GSEL + (out * CSL_CONTROLSS_INPUTXBAR_STEP), group_select & CSL_CONTROLSS_INPUTXBAR_INPUTXBAR0_GSEL_GSEL_MASK);
87  HW_WR_REG32(base + CSL_CONTROLSS_INPUTXBAR_INPUTXBAR0_G0 + (out * CSL_CONTROLSS_INPUTXBAR_STEP), group0_muxctl & CSL_CONTROLSS_INPUTXBAR_INPUTXBAR0_G0_SEL_MASK);
88  HW_WR_REG32(base + CSL_CONTROLSS_INPUTXBAR_INPUTXBAR0_G1 + (out * CSL_CONTROLSS_INPUTXBAR_STEP), group1_muxctl & CSL_CONTROLSS_INPUTXBAR_INPUTXBAR0_G1_SEL_MASK);
89 
90 }
91 
103 static inline void
104 SOC_xbarSelectInputXBarInputSource_ext(uint32_t base, uint8_t out, uint8_t group_select, uint8_t group0_muxctl, uint8_t group1_muxctl, uint8_t group2_muxctl)
105 {
106  HW_WR_REG32(base + CSL_CONTROLSS_INPUTXBAR_INPUTXBAR0_GSEL + (out * CSL_CONTROLSS_INPUTXBAR_STEP), group_select & CSL_CONTROLSS_INPUTXBAR_INPUTXBAR0_GSEL_GSEL_MASK);
107  HW_WR_REG32(base + CSL_CONTROLSS_INPUTXBAR_INPUTXBAR0_G0 + (out * CSL_CONTROLSS_INPUTXBAR_STEP), group0_muxctl & CSL_CONTROLSS_INPUTXBAR_INPUTXBAR0_G0_SEL_MASK);
108  HW_WR_REG32(base + CSL_CONTROLSS_INPUTXBAR_INPUTXBAR0_G1 + (out * CSL_CONTROLSS_INPUTXBAR_STEP), group1_muxctl & CSL_CONTROLSS_INPUTXBAR_INPUTXBAR0_G1_SEL_MASK);
109  HW_WR_REG32(base + CSL_CONTROLSS_INPUTXBAR_INPUTXBAR0_G2 + (out * CSL_CONTROLSS_INPUTXBAR_STEP), group1_muxctl & CSL_CONTROLSS_INPUTXBAR_INPUTXBAR0_G2_SEL_MASK);
110 
111 }
112 
120 static inline uint32_t
121 SOC_xbarGetPWMXBarOutputSignalStatus(uint32_t base)
122 {
123  return(HW_RD_REG32(base + CSL_CONTROLSS_PWMXBAR_PWMXBAR_STATUS) & CSL_CONTROLSS_PWMXBAR_PWMXBAR_STATUS_STS_MASK);
124 }
125 
133 static inline void
134 SOC_xbarInvertPWMXBarOutputSignalBeforeLatch(uint32_t base, uint32_t invert_mask)
135 {
136  HW_WR_REG32(base + CSL_CONTROLSS_PWMXBAR_PWMXBAR_FLAGINVERT, invert_mask & CSL_CONTROLSS_PWMXBAR_PWMXBAR_FLAGINVERT_INVERT_MASK);
137 }
138 
146 static inline uint32_t
147 SOC_xbarGetPWMXBarOutputSignalLatchedFlag(uint32_t base)
148 {
149  return(HW_RD_REG32(base + CSL_CONTROLSS_PWMXBAR_PWMXBAR_FLAG));
150 }
151 
159 static inline void
160 SOC_xbarClearPWMXBarOutputSignalLatchedFlag(uint32_t base, uint32_t clr)
161 {
162  HW_WR_REG32(base + CSL_CONTROLSS_PWMXBAR_PWMXBAR_FLAG_CLR, clr);
163 }
164 
181 static inline void
182 SOC_xbarSelectPWMXBarInputSource(uint32_t base, uint8_t out, uint32_t group0_mask, uint32_t group1_mask, uint32_t group2_mask, uint32_t group3_mask, uint32_t group4_mask, uint32_t group5_mask, uint32_t group6_mask, uint32_t group7_mask, uint32_t group8_mask)
183 {
184  HW_WR_REG32(base + out*CSL_CONTROLSS_PWMXBAR_STEP + CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G0, group0_mask & CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G0_SEL_MASK);
185  HW_WR_REG32(base + out*CSL_CONTROLSS_PWMXBAR_STEP + CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G1, group1_mask & CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G1_SEL_MASK);
186  HW_WR_REG32(base + out*CSL_CONTROLSS_PWMXBAR_STEP + CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G2, group2_mask & CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G2_SEL_MASK);
187  HW_WR_REG32(base + out*CSL_CONTROLSS_PWMXBAR_STEP + CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G3, group3_mask & CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G3_SEL_MASK);
188  HW_WR_REG32(base + out*CSL_CONTROLSS_PWMXBAR_STEP + CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G4, group4_mask & CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G4_SEL_MASK);
189  HW_WR_REG32(base + out*CSL_CONTROLSS_PWMXBAR_STEP + CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G5, group5_mask & CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G5_SEL_MASK);
190  HW_WR_REG32(base + out*CSL_CONTROLSS_PWMXBAR_STEP + CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G6, group6_mask & CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G6_SEL_MASK);
191  HW_WR_REG32(base + out*CSL_CONTROLSS_PWMXBAR_STEP + CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G7, group7_mask & CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G7_SEL_MASK);
192  HW_WR_REG32(base + out*CSL_CONTROLSS_PWMXBAR_STEP + CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G8, group8_mask & CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G8_SEL_MASK);
193 }
194 
195 
213 static inline void
214 SOC_xbarSelectPWMXBarInputSource_ext(uint32_t base, uint8_t out, uint32_t group0_mask, uint32_t group1_mask, uint32_t group2_mask, uint32_t group3_mask, uint32_t group4_mask, uint32_t group5_mask, uint32_t group6_mask, uint32_t group7_mask, uint32_t group8_mask, uint32_t group9_mask)
215 {
216  HW_WR_REG32(base + out*CSL_CONTROLSS_PWMXBAR_STEP + CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G0, group0_mask & CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G0_SEL_MASK);
217  HW_WR_REG32(base + out*CSL_CONTROLSS_PWMXBAR_STEP + CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G1, group1_mask & CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G1_SEL_MASK);
218  HW_WR_REG32(base + out*CSL_CONTROLSS_PWMXBAR_STEP + CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G2, group2_mask & CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G2_SEL_MASK);
219  HW_WR_REG32(base + out*CSL_CONTROLSS_PWMXBAR_STEP + CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G3, group3_mask & CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G3_SEL_MASK);
220  HW_WR_REG32(base + out*CSL_CONTROLSS_PWMXBAR_STEP + CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G4, group4_mask & CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G4_SEL_MASK);
221  HW_WR_REG32(base + out*CSL_CONTROLSS_PWMXBAR_STEP + CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G5, group5_mask & CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G5_SEL_MASK);
222  HW_WR_REG32(base + out*CSL_CONTROLSS_PWMXBAR_STEP + CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G6, group6_mask & CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G6_SEL_MASK);
223  HW_WR_REG32(base + out*CSL_CONTROLSS_PWMXBAR_STEP + CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G7, group7_mask & CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G7_SEL_MASK);
224  HW_WR_REG32(base + out*CSL_CONTROLSS_PWMXBAR_STEP + CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G8, group8_mask & CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G8_SEL_MASK);
225  HW_WR_REG32(base + out*CSL_CONTROLSS_PWMXBAR_STEP + CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G9, group9_mask & CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G9_SEL_MASK);
226 }
227 
238 static inline void
239 SOC_xbarSelectMinimumDeadBandLogicXBarInputSource(uint32_t base, uint8_t out, uint32_t group0_mask, uint32_t group1_mask, uint32_t group2_mask)
240 {
241  //TBD: 32 bit field required?
242  HW_WR_REG32(base + out*CSL_CONTROLSS_MDLXBAR_STEP + CSL_CONTROLSS_MDLXBAR_MDLXBAR0_G0, group0_mask & CSL_CONTROLSS_MDLXBAR_MDLXBAR0_G0_SEL_MASK);
243  HW_WR_REG32(base + out*CSL_CONTROLSS_MDLXBAR_STEP + CSL_CONTROLSS_MDLXBAR_MDLXBAR0_G1, group1_mask & CSL_CONTROLSS_MDLXBAR_MDLXBAR0_G1_SEL_MASK);
244  HW_WR_REG32(base + out*CSL_CONTROLSS_MDLXBAR_STEP + CSL_CONTROLSS_MDLXBAR_MDLXBAR0_G2, group2_mask & CSL_CONTROLSS_MDLXBAR_MDLXBAR0_G2_SEL_MASK);
245 }
246 
257 static inline void
258 SOC_xbarSelectIllegalComboLogicXBarInputSource(uint32_t base, uint8_t out, uint32_t group0_mask, uint32_t group1_mask, uint32_t group2_mask)
259 {
260  //TBD: 32 bit field required?
261  HW_WR_REG32(base + out*CSL_CONTROLSS_ICLXBAR_STEP + CSL_CONTROLSS_ICLXBAR_ICLXBAR0_G0, group0_mask & CSL_CONTROLSS_ICLXBAR_ICLXBAR0_G0_SEL_MASK);
262  HW_WR_REG32(base + out*CSL_CONTROLSS_ICLXBAR_STEP + CSL_CONTROLSS_ICLXBAR_ICLXBAR0_G1, group1_mask & CSL_CONTROLSS_ICLXBAR_ICLXBAR0_G1_SEL_MASK);
263  HW_WR_REG32(base + out*CSL_CONTROLSS_ICLXBAR_STEP + CSL_CONTROLSS_ICLXBAR_ICLXBAR0_G2, group2_mask & CSL_CONTROLSS_ICLXBAR_ICLXBAR0_G2_SEL_MASK);
264 }
265 
280 static inline void
281 SOC_xbarSelectInterruptXBarInputSource(uint32_t base, uint8_t out, uint32_t group0_mask, uint32_t group1_mask, uint32_t group2_mask, uint32_t group3_mask, uint32_t group4_mask, uint32_t group5_mask, uint32_t group6_mask)
282 {
283  //TBD: 32 bit field required?
284  HW_WR_REG32(base + out*CSL_CONTROLSS_INTXBAR_STEP + CSL_CONTROLSS_INTXBAR_INTXBAR0_G0, group0_mask & CSL_CONTROLSS_INTXBAR_INTXBAR0_G0_SEL_MASK);
285  HW_WR_REG32(base + out*CSL_CONTROLSS_INTXBAR_STEP + CSL_CONTROLSS_INTXBAR_INTXBAR0_G1, group1_mask & CSL_CONTROLSS_INTXBAR_INTXBAR0_G1_SEL_MASK);
286  HW_WR_REG32(base + out*CSL_CONTROLSS_INTXBAR_STEP + CSL_CONTROLSS_INTXBAR_INTXBAR0_G2, group2_mask & CSL_CONTROLSS_INTXBAR_INTXBAR0_G2_SEL_MASK);
287  HW_WR_REG32(base + out*CSL_CONTROLSS_INTXBAR_STEP + CSL_CONTROLSS_INTXBAR_INTXBAR0_G3, group3_mask & CSL_CONTROLSS_INTXBAR_INTXBAR0_G3_SEL_MASK);
288  HW_WR_REG32(base + out*CSL_CONTROLSS_INTXBAR_STEP + CSL_CONTROLSS_INTXBAR_INTXBAR0_G4, group4_mask & CSL_CONTROLSS_INTXBAR_INTXBAR0_G4_SEL_MASK);
289  HW_WR_REG32(base + out*CSL_CONTROLSS_INTXBAR_STEP + CSL_CONTROLSS_INTXBAR_INTXBAR0_G5, group5_mask & CSL_CONTROLSS_INTXBAR_INTXBAR0_G5_SEL_MASK);
290  HW_WR_REG32(base + out*CSL_CONTROLSS_INTXBAR_STEP + CSL_CONTROLSS_INTXBAR_INTXBAR0_G6, group6_mask & CSL_CONTROLSS_INTXBAR_INTXBAR0_G6_SEL_MASK);
291 }
292 
293 
311 static inline void
312 SOC_xbarSelectInterruptXBarInputSource_ext(uint32_t base, uint8_t out, uint32_t group0_mask, uint32_t group1_mask, uint32_t group2_mask, uint32_t group3_mask, uint32_t group4_mask, uint32_t group5_mask, uint32_t group6_mask, uint32_t group7_mask, uint32_t group8_mask, uint32_t group9_mask)
313 {
314  //TBD: 32 bit field required?
315  HW_WR_REG32(base + out*CSL_CONTROLSS_INTXBAR_STEP + CSL_CONTROLSS_INTXBAR_INTXBAR0_G0, group0_mask & CSL_CONTROLSS_INTXBAR_INTXBAR0_G0_SEL_MASK);
316  HW_WR_REG32(base + out*CSL_CONTROLSS_INTXBAR_STEP + CSL_CONTROLSS_INTXBAR_INTXBAR0_G1, group1_mask & CSL_CONTROLSS_INTXBAR_INTXBAR0_G1_SEL_MASK);
317  HW_WR_REG32(base + out*CSL_CONTROLSS_INTXBAR_STEP + CSL_CONTROLSS_INTXBAR_INTXBAR0_G2, group2_mask & CSL_CONTROLSS_INTXBAR_INTXBAR0_G2_SEL_MASK);
318  HW_WR_REG32(base + out*CSL_CONTROLSS_INTXBAR_STEP + CSL_CONTROLSS_INTXBAR_INTXBAR0_G3, group3_mask & CSL_CONTROLSS_INTXBAR_INTXBAR0_G3_SEL_MASK);
319  HW_WR_REG32(base + out*CSL_CONTROLSS_INTXBAR_STEP + CSL_CONTROLSS_INTXBAR_INTXBAR0_G4, group4_mask & CSL_CONTROLSS_INTXBAR_INTXBAR0_G4_SEL_MASK);
320  HW_WR_REG32(base + out*CSL_CONTROLSS_INTXBAR_STEP + CSL_CONTROLSS_INTXBAR_INTXBAR0_G5, group5_mask & CSL_CONTROLSS_INTXBAR_INTXBAR0_G5_SEL_MASK);
321  HW_WR_REG32(base + out*CSL_CONTROLSS_INTXBAR_STEP + CSL_CONTROLSS_INTXBAR_INTXBAR0_G6, group6_mask & CSL_CONTROLSS_INTXBAR_INTXBAR0_G6_SEL_MASK);
322  HW_WR_REG32(base + out*CSL_CONTROLSS_INTXBAR_STEP + CSL_CONTROLSS_INTXBAR_INTXBAR0_G7, group7_mask & CSL_CONTROLSS_INTXBAR_INTXBAR0_G7_SEL_MASK);
323  HW_WR_REG32(base + out*CSL_CONTROLSS_INTXBAR_STEP + CSL_CONTROLSS_INTXBAR_INTXBAR0_G8, group8_mask & CSL_CONTROLSS_INTXBAR_INTXBAR0_G8_SEL_MASK);
324  HW_WR_REG32(base + out*CSL_CONTROLSS_INTXBAR_STEP + CSL_CONTROLSS_INTXBAR_INTXBAR0_G9, group9_mask & CSL_CONTROLSS_INTXBAR_INTXBAR0_G9_SEL_MASK);
325 }
326 
341 static inline void
342 SOC_xbarSelectDMAXBarInputSource(uint32_t base, uint8_t out, uint8_t group_select, uint8_t group0_muxctl, uint8_t group1_muxctl, uint8_t group2_muxctl, uint8_t group3_muxctl, uint8_t group4_muxctl, uint8_t group5_muxctl)
343 {
344  HW_WR_REG32(base + out*CSL_CONTROLSS_DMAXBAR_STEP + CSL_CONTROLSS_DMAXBAR_DMAXBAR0_GSEL , group_select & CSL_CONTROLSS_DMAXBAR_DMAXBAR0_GSEL_GSEL_MASK);
345  HW_WR_REG32(base + out*CSL_CONTROLSS_DMAXBAR_STEP + CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G0 , group0_muxctl & CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G0_SEL_MASK);
346  HW_WR_REG32(base + out*CSL_CONTROLSS_DMAXBAR_STEP + CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G1 , group1_muxctl & CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G1_SEL_MASK);
347  HW_WR_REG32(base + out*CSL_CONTROLSS_DMAXBAR_STEP + CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G2 , group2_muxctl & CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G2_SEL_MASK);
348  HW_WR_REG32(base + out*CSL_CONTROLSS_DMAXBAR_STEP + CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G3 , group3_muxctl & CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G3_SEL_MASK);
349  HW_WR_REG32(base + out*CSL_CONTROLSS_DMAXBAR_STEP + CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G4 , group4_muxctl & CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G4_SEL_MASK);
350  HW_WR_REG32(base + out*CSL_CONTROLSS_DMAXBAR_STEP + CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G5 , group5_muxctl & CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G5_SEL_MASK);
351 
352 }
353 
354 
370 static inline void
371 SOC_xbarSelectDMAXBarInputSource_ext(uint32_t base, uint8_t out, uint8_t group_select, uint8_t group0_muxctl, uint8_t group1_muxctl, uint8_t group2_muxctl, uint8_t group3_muxctl, uint8_t group4_muxctl, uint8_t group5_muxctl, uint8_t group6_muxctl)
372 {
373  HW_WR_REG32(base + out*CSL_CONTROLSS_DMAXBAR_STEP + CSL_CONTROLSS_DMAXBAR_DMAXBAR0_GSEL , group_select & CSL_CONTROLSS_DMAXBAR_DMAXBAR0_GSEL_GSEL_MASK);
374  HW_WR_REG32(base + out*CSL_CONTROLSS_DMAXBAR_STEP + CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G0 , group0_muxctl & CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G0_SEL_MASK);
375  HW_WR_REG32(base + out*CSL_CONTROLSS_DMAXBAR_STEP + CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G1 , group1_muxctl & CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G1_SEL_MASK);
376  HW_WR_REG32(base + out*CSL_CONTROLSS_DMAXBAR_STEP + CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G2 , group2_muxctl & CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G2_SEL_MASK);
377  HW_WR_REG32(base + out*CSL_CONTROLSS_DMAXBAR_STEP + CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G3 , group3_muxctl & CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G3_SEL_MASK);
378  HW_WR_REG32(base + out*CSL_CONTROLSS_DMAXBAR_STEP + CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G4 , group4_muxctl & CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G4_SEL_MASK);
379  HW_WR_REG32(base + out*CSL_CONTROLSS_DMAXBAR_STEP + CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G5 , group5_muxctl & CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G5_SEL_MASK);
380  HW_WR_REG32(base + out*CSL_CONTROLSS_DMAXBAR_STEP + CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G6 , group6_muxctl & CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G6_SEL_MASK);
381 
382 }
383 
391 static inline uint32_t
392 SOC_xbarGetOutputXBarOutputSignalStatus(uint32_t base)
393 {
394  return(HW_RD_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_STATUS)& CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_STATUS_STS_MASK);
395 }
396 
404 static inline void
405 SOC_xbarInvertOutputXBarOutputSignalBeforeLatch(uint32_t base, uint32_t invert)
406 {
407  HW_WR_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_FLAGINVERT, invert & CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_FLAGINVERT_INVERT_MASK);
408 }
409 
417 static inline uint32_t
418 SOC_xbarGetOutputXBarOutputSignalLatchedFlag(uint32_t base)
419 {
420  return(HW_RD_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_FLAG));
421 }
422 
430 static inline void
431 SOC_xbarClearOutputXBarOutputSignalLatchedFlag(uint32_t base, uint32_t clr)
432 {
433  HW_WR_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_FLAG_CLR, clr);
434 }
435 
443 static inline void
444 SOC_xbarForceOutputXBarOutputSignalLatchedFlag(uint32_t base, uint32_t force)
445 {
446  HW_WR_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_FLAGFORCE, force & CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_FLAGFORCE_FRC_MASK);
447 }
448 
456 static inline void
457 SOC_xbarSelectLatchOutputXBarOutputSignal(uint32_t base, uint32_t latchselect)
458 {
459  HW_WR_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_OUTLATCH, latchselect & CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_OUTLATCH_LATCHSEL_MASK);
460 }
461 
469 static inline void
470 SOC_xbarSelectStretchedPulseOutputXBarOutputSignal(uint32_t base, uint32_t stretchselect)
471 {
472  HW_WR_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_OUTSTRETCH, stretchselect & CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_OUTSTRETCH_STRETCHSEL_MASK);
473 }
474 
482 static inline void
483 SOC_xbarSelectStretchedPulseLengthOutputXBarOutputSignal(uint32_t base, uint32_t lengthselect)
484 {
485  HW_WR_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_OUTLENGTH, lengthselect & CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_OUTLENGTH_LENGTHSEL_MASK);
486 }
487 
495 static inline void
496 SOC_xbarInvertOutputXBarOutputSignal(uint32_t base, uint32_t invertout)
497 {
498  HW_WR_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_OUTINVERT, invertout & CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_OUTINVERT_OUTINVERT_MASK);
499 }
500 
519 static inline void
520 SOC_xbarSelectOutputXBarInputSource(uint32_t base, uint8_t out, uint32_t group0_mask, uint32_t group1_mask, uint32_t group2_mask, uint32_t group3_mask, uint32_t group4_mask, uint32_t group5_mask, uint32_t group6_mask, uint32_t group7_mask, uint32_t group8_mask, uint32_t group9_mask, uint32_t group10_mask)
521 {
522  HW_WR_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G0 + out * CSL_CONTROLSS_OUTPUTXBAR_STEP, group0_mask & CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G0_SEL_MASK);
523  HW_WR_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G1 + out * CSL_CONTROLSS_OUTPUTXBAR_STEP, group1_mask & CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G1_SEL_MASK);
524  HW_WR_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G2 + out * CSL_CONTROLSS_OUTPUTXBAR_STEP, group2_mask & CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G2_SEL_MASK);
525  HW_WR_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G3 + out * CSL_CONTROLSS_OUTPUTXBAR_STEP, group3_mask & CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G3_SEL_MASK);
526  HW_WR_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G4 + out * CSL_CONTROLSS_OUTPUTXBAR_STEP, group4_mask & CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G4_SEL_MASK);
527  HW_WR_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G5 + out * CSL_CONTROLSS_OUTPUTXBAR_STEP, group5_mask & CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G5_SEL_MASK);
528  HW_WR_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G6 + out * CSL_CONTROLSS_OUTPUTXBAR_STEP, group6_mask & CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G6_SEL_MASK);
529  HW_WR_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G7 + out * CSL_CONTROLSS_OUTPUTXBAR_STEP, group7_mask & CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G7_SEL_MASK);
530  HW_WR_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G8 + out * CSL_CONTROLSS_OUTPUTXBAR_STEP, group8_mask & CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G8_SEL_MASK);
531  HW_WR_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G9 + out * CSL_CONTROLSS_OUTPUTXBAR_STEP, group9_mask & CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G9_SEL_MASK);
532  HW_WR_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G10 + out * CSL_CONTROLSS_OUTPUTXBAR_STEP, group10_mask & CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G10_SEL_MASK);
533 }
534 
535 
544 static inline void
545 SOC_xbarSelectPWMSyncOutXBarInput(uint32_t base, uint8_t out, uint32_t input)
546 {
547  //TBD: 32 bit field for selecting 32 inputs
548  HW_WR_REG32(base + CSL_CONTROLSS_PWMSYNCOUTXBAR_PWMSYNCOUTXBAR0_G0 + out * CSL_CONTROLSS_PWMSYNCOUTXBAR_STEP, input & CSL_CONTROLSS_PWMSYNCOUTXBAR_PWMSYNCOUTXBAR0_G0_SEL_MASK);
549 }
550 
551 
561 static inline void
562 SOC_xbarSelectPWMSyncOutXBarInput_ext(uint32_t base, uint8_t out, uint32_t group0_mask, uint32_t group1_mask)
563 {
564  //TBD: 32 bit field for selecting 32 inputs
565  HW_WR_REG32(base + CSL_CONTROLSS_PWMSYNCOUTXBAR_PWMSYNCOUTXBAR0_G0 + out * CSL_CONTROLSS_PWMSYNCOUTXBAR_STEP, group0_mask & CSL_CONTROLSS_PWMSYNCOUTXBAR_PWMSYNCOUTXBAR0_G0_SEL_MASK);
566  HW_WR_REG32(base + CSL_CONTROLSS_PWMSYNCOUTXBAR_PWMSYNCOUTXBAR0_G1 + out * CSL_CONTROLSS_PWMSYNCOUTXBAR_STEP, group1_mask & CSL_CONTROLSS_PWMSYNCOUTXBAR_PWMSYNCOUTXBAR0_G1_SEL_MASK);
567 }
568 
569 
578 static inline void
579 SOC_xbarSelectEdmaTrigXbarInputSource(uint32_t base, uint8_t out, uint8_t mux_control)
580 {
581  HW_WR_REG32(base + CSL_EDMA_TRIG_XBAR_MUXCNTL(out), (CSL_EDMA_TRIG_XBAR_MUXCNTL_INT_ENABLE_MASK) | (mux_control & CSL_EDMA_TRIG_XBAR_MUXCNTL_ENABLE_MASK));
582 }
583 
592 static inline void
593 SOC_xbarSelectGpioIntrXbarInputSource(uint32_t base, uint8_t out, uint8_t mux_control)
594 {
595  HW_WR_REG32(base + CSL_GPIO_INTR_XBAR_MUXCNTL(out), (CSL_GPIO_INTR_XBAR_MUXCNTL_INT_ENABLE_MASK) | (mux_control & CSL_GPIO_INTR_XBAR_MUXCNTL_ENABLE_MASK));
596 }
597 
606 static inline void
607 SOC_xbarSelectIcssmIntrXbarInputSource(uint32_t base, uint8_t out, uint8_t mux_control)
608 {
609  HW_WR_REG32(base + CSL_ICSSM_INTR_XBAR_MUXCNTL(out), (CSL_ICSSM_INTR_XBAR_MUXCNTL_INT_ENABLE_MASK) | (mux_control & CSL_ICSSM_INTR_XBAR_MUXCNTL_ENABLE_MASK));
610 }
611 
620 static inline void
621 SOC_xbarSelectTimesyncXbar0InputSource(uint32_t base, uint8_t out, uint8_t mux_control)
622 {
623  HW_WR_REG32(base + CSL_SOC_TIMESYNC_XBAR0_MUXCNTL(out), (CSL_SOC_TIMESYNC_XBAR0_MUXCNTL_INT_ENABLE_MASK) | (mux_control & CSL_SOC_TIMESYNC_XBAR0_MUXCNTL_ENABLE_MASK));
624 }
625 
634 static inline void
635 SOC_xbarSelectTimesyncXbar1InputSource(uint32_t base, uint8_t out, uint8_t mux_control)
636 {
637  HW_WR_REG32(base + CSL_SOC_TIMESYNC_XBAR1_MUXCNTL(out), (CSL_SOC_TIMESYNC_XBAR1_MUXCNTL_INT_ENABLE_MASK) | (mux_control & CSL_SOC_TIMESYNC_XBAR1_MUXCNTL_ENABLE_MASK));
638 }
639 
642 #ifdef __cplusplus
643 }
644 #endif
645 
646 #endif // SOC_XBAR_AM263PX_H_
SOC_xbarSelectPWMSyncOutXBarInput_ext
static void SOC_xbarSelectPWMSyncOutXBarInput_ext(uint32_t base, uint8_t out, uint32_t group0_mask, uint32_t group1_mask)
Trip & Sync xbar: API to select input sources of PWM Syncout XBar.
Definition: soc_xbar.h:562
CSL_CONTROLSS_PWMSYNCOUTXBAR_STEP
#define CSL_CONTROLSS_PWMSYNCOUTXBAR_STEP
Definition: soc_xbar.h:71
SOC_xbarSelectEdmaTrigXbarInputSource
static void SOC_xbarSelectEdmaTrigXbarInputSource(uint32_t base, uint8_t out, uint8_t mux_control)
SoC level xbars: API to select input source of EDMA Trigger XBar.
Definition: soc_xbar.h:579
SOC_xbarInvertOutputXBarOutputSignalBeforeLatch
static void SOC_xbarInvertOutputXBarOutputSignalBeforeLatch(uint32_t base, uint32_t invert)
Trip & Sync xbar: API to configure inversion of output signal status flag (latched) of Output XBars.
Definition: soc_xbar.h:405
SOC_xbarSelectInterruptXBarInputSource
static void SOC_xbarSelectInterruptXBarInputSource(uint32_t base, uint8_t out, uint32_t group0_mask, uint32_t group1_mask, uint32_t group2_mask, uint32_t group3_mask, uint32_t group4_mask, uint32_t group5_mask, uint32_t group6_mask)
Trip & Sync xbar: API to select input sources of Interrupt XBar.
Definition: soc_xbar.h:281
SOC_xbarSelectMinimumDeadBandLogicXBarInputSource
static void SOC_xbarSelectMinimumDeadBandLogicXBarInputSource(uint32_t base, uint8_t out, uint32_t group0_mask, uint32_t group1_mask, uint32_t group2_mask)
Trip & Sync xbar: API to select input sources of MDL XBar.
Definition: soc_xbar.h:239
SOC_xbarSelectInterruptXBarInputSource_ext
static void SOC_xbarSelectInterruptXBarInputSource_ext(uint32_t base, uint8_t out, uint32_t group0_mask, uint32_t group1_mask, uint32_t group2_mask, uint32_t group3_mask, uint32_t group4_mask, uint32_t group5_mask, uint32_t group6_mask, uint32_t group7_mask, uint32_t group8_mask, uint32_t group9_mask)
Trip & Sync xbar: API to select input sources of Interrupt XBar.
Definition: soc_xbar.h:312
SOC_xbarSelectPWMSyncOutXBarInput
static void SOC_xbarSelectPWMSyncOutXBarInput(uint32_t base, uint8_t out, uint32_t input)
Trip & Sync xbar: API to select input sources of PWM Syncout XBar.
Definition: soc_xbar.h:545
CSL_CONTROLSS_INTXBAR_STEP
#define CSL_CONTROLSS_INTXBAR_STEP
Definition: soc_xbar.h:68
SOC_xbarGetOutputXBarOutputSignalLatchedFlag
static uint32_t SOC_xbarGetOutputXBarOutputSignalLatchedFlag(uint32_t base)
Trip & Sync xbar: API to read latched output signal status of all Output XBars.
Definition: soc_xbar.h:418
SOC_xbarSelectInputXBarInputSource_ext
static void SOC_xbarSelectInputXBarInputSource_ext(uint32_t base, uint8_t out, uint8_t group_select, uint8_t group0_muxctl, uint8_t group1_muxctl, uint8_t group2_muxctl)
Trip & Sync xbar: API to select input source of Input XBar.
Definition: soc_xbar.h:104
CSL_CONTROLSS_OUTPUTXBAR_STEP
#define CSL_CONTROLSS_OUTPUTXBAR_STEP
Definition: soc_xbar.h:70
SOC_xbarSelectStretchedPulseLengthOutputXBarOutputSignal
static void SOC_xbarSelectStretchedPulseLengthOutputXBarOutputSignal(uint32_t base, uint32_t lengthselect)
Trip & Sync xbar: API to configure pulse streching length of output of Output XBars.
Definition: soc_xbar.h:483
SOC_xbarSelectGpioIntrXbarInputSource
static void SOC_xbarSelectGpioIntrXbarInputSource(uint32_t base, uint8_t out, uint8_t mux_control)
SoC level xbars: API to select input source of GPIO Interrupt XBar.
Definition: soc_xbar.h:593
SOC_xbarSelectIllegalComboLogicXBarInputSource
static void SOC_xbarSelectIllegalComboLogicXBarInputSource(uint32_t base, uint8_t out, uint32_t group0_mask, uint32_t group1_mask, uint32_t group2_mask)
Trip & Sync xbar: API to select input sources of ICL XBar.
Definition: soc_xbar.h:258
SOC_xbarSelectLatchOutputXBarOutputSignal
static void SOC_xbarSelectLatchOutputXBarOutputSignal(uint32_t base, uint32_t latchselect)
Trip & Sync xbar: API to select output of Output XBars.
Definition: soc_xbar.h:457
CSL_CONTROLSS_PWMXBAR_STEP
#define CSL_CONTROLSS_PWMXBAR_STEP
Definition: soc_xbar.h:65
CSL_CONTROLSS_MDLXBAR_STEP
#define CSL_CONTROLSS_MDLXBAR_STEP
Definition: soc_xbar.h:66
SOC_xbarInvertOutputXBarOutputSignal
static void SOC_xbarInvertOutputXBarOutputSignal(uint32_t base, uint32_t invertout)
Trip & Sync xbar: API to configure inversion of output signal of Output XBars.
Definition: soc_xbar.h:496
CSL_CONTROLSS_DMAXBAR_STEP
#define CSL_CONTROLSS_DMAXBAR_STEP
Definition: soc_xbar.h:69
SOC_xbarClearOutputXBarOutputSignalLatchedFlag
static void SOC_xbarClearOutputXBarOutputSignalLatchedFlag(uint32_t base, uint32_t clr)
Trip & Sync xbar: API to clear output signal status flag (latched) of Output XBars.
Definition: soc_xbar.h:431
SOC_xbarSelectTimesyncXbar0InputSource
static void SOC_xbarSelectTimesyncXbar0InputSource(uint32_t base, uint8_t out, uint8_t mux_control)
SoC level xbars: API to select input source of TimeSync XBar0.
Definition: soc_xbar.h:621
SOC_xbarSelectTimesyncXbar1InputSource
static void SOC_xbarSelectTimesyncXbar1InputSource(uint32_t base, uint8_t out, uint8_t mux_control)
SoC level xbars: API to select input source of TimeSync XBar1.
Definition: soc_xbar.h:635
SOC_xbarSelectPWMXBarInputSource
static void SOC_xbarSelectPWMXBarInputSource(uint32_t base, uint8_t out, uint32_t group0_mask, uint32_t group1_mask, uint32_t group2_mask, uint32_t group3_mask, uint32_t group4_mask, uint32_t group5_mask, uint32_t group6_mask, uint32_t group7_mask, uint32_t group8_mask)
Trip & Sync xbar: API to select input sources of PWM XBar.
Definition: soc_xbar.h:182
SOC_xbarSelectInputXBarInputSource
static void SOC_xbarSelectInputXBarInputSource(uint32_t base, uint8_t out, uint8_t group_select, uint8_t group0_muxctl, uint8_t group1_muxctl)
Trip & Sync xbar: API to select input source of Input XBar.
Definition: soc_xbar.h:84
SOC_xbarSelectOutputXBarInputSource
static void SOC_xbarSelectOutputXBarInputSource(uint32_t base, uint8_t out, uint32_t group0_mask, uint32_t group1_mask, uint32_t group2_mask, uint32_t group3_mask, uint32_t group4_mask, uint32_t group5_mask, uint32_t group6_mask, uint32_t group7_mask, uint32_t group8_mask, uint32_t group9_mask, uint32_t group10_mask)
Trip & Sync xbar: API to select input sources of Output XBar.
Definition: soc_xbar.h:520
SOC_xbarInvertPWMXBarOutputSignalBeforeLatch
static void SOC_xbarInvertPWMXBarOutputSignalBeforeLatch(uint32_t base, uint32_t invert_mask)
Trip & Sync xbar: API to configure inversion of output signal status flag (latched) of PWM XBars.
Definition: soc_xbar.h:134
DebugP.h
SOC_xbarSelectDMAXBarInputSource
static void SOC_xbarSelectDMAXBarInputSource(uint32_t base, uint8_t out, uint8_t group_select, uint8_t group0_muxctl, uint8_t group1_muxctl, uint8_t group2_muxctl, uint8_t group3_muxctl, uint8_t group4_muxctl, uint8_t group5_muxctl)
Trip & Sync xbar: API to select input source of DMA XBar.
Definition: soc_xbar.h:342
CSL_CONTROLSS_ICLXBAR_STEP
#define CSL_CONTROLSS_ICLXBAR_STEP
Definition: soc_xbar.h:67
SOC_xbarSelectPWMXBarInputSource_ext
static void SOC_xbarSelectPWMXBarInputSource_ext(uint32_t base, uint8_t out, uint32_t group0_mask, uint32_t group1_mask, uint32_t group2_mask, uint32_t group3_mask, uint32_t group4_mask, uint32_t group5_mask, uint32_t group6_mask, uint32_t group7_mask, uint32_t group8_mask, uint32_t group9_mask)
Trip & Sync xbar: API to select input sources of PWM XBar.
Definition: soc_xbar.h:214
SOC_xbarGetOutputXBarOutputSignalStatus
static uint32_t SOC_xbarGetOutputXBarOutputSignalStatus(uint32_t base)
Trip & Sync xbar: API to read raw output signal status of all Output XBars.
Definition: soc_xbar.h:392
SOC_xbarForceOutputXBarOutputSignalLatchedFlag
static void SOC_xbarForceOutputXBarOutputSignalLatchedFlag(uint32_t base, uint32_t force)
Trip & Sync xbar: API to force output signal status flag (latched) of Output XBars.
Definition: soc_xbar.h:444
SOC_xbarSelectStretchedPulseOutputXBarOutputSignal
static void SOC_xbarSelectStretchedPulseOutputXBarOutputSignal(uint32_t base, uint32_t stretchselect)
Trip & Sync xbar: API to enable pulse stretching of output of Output XBars.
Definition: soc_xbar.h:470
SOC_xbarSelectDMAXBarInputSource_ext
static void SOC_xbarSelectDMAXBarInputSource_ext(uint32_t base, uint8_t out, uint8_t group_select, uint8_t group0_muxctl, uint8_t group1_muxctl, uint8_t group2_muxctl, uint8_t group3_muxctl, uint8_t group4_muxctl, uint8_t group5_muxctl, uint8_t group6_muxctl)
Trip & Sync xbar: API to select input source of DMA XBar.
Definition: soc_xbar.h:371
SOC_xbarGetPWMXBarOutputSignalStatus
static uint32_t SOC_xbarGetPWMXBarOutputSignalStatus(uint32_t base)
Trip & Sync xbar: API to read raw output signal status of all PWM XBars.
Definition: soc_xbar.h:121
SOC_xbarClearPWMXBarOutputSignalLatchedFlag
static void SOC_xbarClearPWMXBarOutputSignalLatchedFlag(uint32_t base, uint32_t clr)
Trip & Sync xbar: API to clear output signal status flag (latched) of PWM XBars.
Definition: soc_xbar.h:160
CSL_CONTROLSS_INPUTXBAR_STEP
#define CSL_CONTROLSS_INPUTXBAR_STEP
Definition: soc_xbar.h:64
SOC_xbarSelectIcssmIntrXbarInputSource
static void SOC_xbarSelectIcssmIntrXbarInputSource(uint32_t base, uint8_t out, uint8_t mux_control)
SoC level xbars: API to select input source of ICSSM Interrupt XBar.
Definition: soc_xbar.h:607
SOC_xbarGetPWMXBarOutputSignalLatchedFlag
static uint32_t SOC_xbarGetPWMXBarOutputSignalLatchedFlag(uint32_t base)
Trip & Sync xbar: API to read latched output signal status of all PWM XBars.
Definition: soc_xbar.h:147