 |
AM263Px MCU+ SDK
11.00.00
|
|
Go to the documentation of this file.
58 #include <drivers/hw_include/csl_types.h>
59 #include <drivers/hw_include/cslr_mcspi.h>
60 #include <drivers/hw_include/cslr.h>
61 #include <drivers/mcspi/v0/lld/dma/mcspi_dma.h>
82 #define MCSPI_STATUS_SUCCESS ((int32_t)0)
87 #define MCSPI_STATUS_FAILURE ((int32_t)-1)
92 #define MCSPI_TIMEOUT ((int32_t)-2)
97 #define MCSPI_INVALID_PARAM ((int32_t)-3)
102 #define MCSPI_STATUS_BUSY ((int32_t)-4)
107 #define MCSPI_INVALID_STATE ((int32_t)-5)
117 #define MCSPI_NO_WAIT ((uint32_t)0)
122 #define MCSPI_WAIT_FOREVER ((uint32_t)-1)
131 #define MCSPI_STATE_RESET ((uint32_t)0U)
136 #define MCSPI_STATE_READY ((uint32_t)1U)
141 #define MCSPI_STATE_BUSY ((uint32_t)2U)
146 #define MCSPI_STATE_ERROR ((uint32_t)3U)
158 #define MCSPI_CHANNEL_0 (0U)
159 #define MCSPI_CHANNEL_1 (1U)
160 #define MCSPI_CHANNEL_2 (2U)
161 #define MCSPI_CHANNEL_3 (3U)
172 #define MCSPI_OPER_MODE_POLLED (0U)
173 #define MCSPI_OPER_MODE_INTERRUPT (1U)
174 #define MCSPI_OPER_MODE_DMA (2U)
178 #define MCSPI_MAX_NUM_CHANNELS (4U)
188 #define MCSPI_TRANSFER_COMPLETED ((int32_t)0U)
189 #define MCSPI_TRANSFER_STARTED ((int32_t)1U)
190 #define MCSPI_TRANSFER_CANCELLED ((int32_t)2U)
191 #define MCSPI_TRANSFER_FAILED ((int32_t)3U)
192 #define MCSPI_TRANSFER_CSN_DEASSERT ((int32_t)4U)
193 #define MCSPI_TRANSFER_TIMEOUT ((int32_t)5U)
212 #define MCSPI_MS_MODE_CONTROLLER (CSL_MCSPI_MODULCTRL_MS_MASTER)
214 #define MCSPI_MS_MODE_PERIPHERAL (CSL_MCSPI_MODULCTRL_MS_SLAVE)
231 #define MCSPI_FF_POL0_PHA0 (0U)
232 #define MCSPI_FF_POL0_PHA1 (1U)
233 #define MCSPI_FF_POL1_PHA0 (2U)
234 #define MCSPI_FF_POL1_PHA1 (3U)
246 #define MCSPI_CS_POL_HIGH (CSL_MCSPI_CH0CONF_EPOL_ACTIVEHIGH)
248 #define MCSPI_CS_POL_LOW (CSL_MCSPI_CH0CONF_EPOL_ACTIVELOW)
257 #define MCSPI_TR_MODE_TX_RX (CSL_MCSPI_CH0CONF_TRM_TRANSRECEI)
258 #define MCSPI_TR_MODE_RX_ONLY (CSL_MCSPI_CH0CONF_TRM_RECEIVONLY)
259 #define MCSPI_TR_MODE_TX_ONLY (CSL_MCSPI_CH0CONF_TRM_TRANSONLY)
269 #define MCSPI_IS_D0 (CSL_MCSPI_CH0CONF_IS_LINE0)
271 #define MCSPI_IS_D1 (CSL_MCSPI_CH0CONF_IS_LINE1)
281 #define MCSPI_DPE_ENABLE (CSL_MCSPI_CH0CONF_DPE0_ENABLED)
283 #define MCSPI_DPE_DISABLE (CSL_MCSPI_CH0CONF_DPE0_DISABLED)
292 #define MCSPI_SLV_CS_SELECT_0 (CSL_MCSPI_CH0CONF_SPIENSLV_SPIEN0)
293 #define MCSPI_SLV_CS_SELECT_1 (CSL_MCSPI_CH0CONF_SPIENSLV_SPIEN1)
294 #define MCSPI_SLV_CS_SELECT_2 (CSL_MCSPI_CH0CONF_SPIENSLV_SPIEN2)
295 #define MCSPI_SLV_CS_SELECT_3 (CSL_MCSPI_CH0CONF_SPIENSLV_SPIEN3)
305 #define MCSPI_SB_POL_HIGH (CSL_MCSPI_CH0CONF_SBPOL_HIGHLEVEL)
307 #define MCSPI_SB_POL_LOW (CSL_MCSPI_CH0CONF_SBPOL_LOWLEVEL)
319 #define MCSPI_TCS0_0_CLK (CSL_MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY)
321 #define MCSPI_TCS0_1_CLK (CSL_MCSPI_CH0CONF_TCS0_ONECYCLEDLY)
323 #define MCSPI_TCS0_2_CLK (CSL_MCSPI_CH0CONF_TCS0_TWOCYCLEDLY)
325 #define MCSPI_TCS0_3_CLK (CSL_MCSPI_CH0CONF_TCS0_THREECYCLEDLY)
338 #define MCSPI_CH_MODE_SINGLE (CSL_MCSPI_MODULCTRL_SINGLE_SINGLE)
340 #define MCSPI_CH_MODE_MULTI (CSL_MCSPI_MODULCTRL_SINGLE_MULTI)
353 #define MCSPI_PINMODE_3PIN (CSL_MCSPI_MODULCTRL_PIN34_3PINMODE)
354 #define MCSPI_PINMODE_4PIN (CSL_MCSPI_MODULCTRL_PIN34_4PINMODE)
366 #define MCSPI_INITDLY_0 (CSL_MCSPI_MODULCTRL_INITDLY_NODELAY)
368 #define MCSPI_INITDLY_4 (CSL_MCSPI_MODULCTRL_INITDLY_4CLKDLY)
370 #define MCSPI_INITDLY_8 (CSL_MCSPI_MODULCTRL_INITDLY_8CLKDLY)
372 #define MCSPI_INITDLY_16 (CSL_MCSPI_MODULCTRL_INITDLY_16CLKDLY)
374 #define MCSPI_INITDLY_32 (CSL_MCSPI_MODULCTRL_INITDLY_32CLKDLY)
378 #define MCSPI_ERROR_TX_UNDERFLOW (0x00000001U)
379 #define MCSPI_ERROR_RX_OVERFLOW (0x00000002U)
382 #define MCSPI_MAX_CLK_DIVIDER_SUPPORTED (4096U)
389 #define MCSPI_FIFO_LENGTH (64U)
393 #define MCSPI_RX_FIFO_ENABLE ((uint32_t) CSL_MCSPI_CH0CONF_FFER_FFENABLED \
395 CSL_MCSPI_CH0CONF_FFER_SHIFT)
400 #define MCSPI_RX_FIFO_DISABLE ((uint32_t) CSL_MCSPI_CH0CONF_FFER_FFDISABLED \
401 << CSL_MCSPI_CH0CONF_FFER_SHIFT)
406 #define MCSPI_TX_FIFO_ENABLE ((uint32_t) CSL_MCSPI_CH0CONF_FFEW_FFENABLED \
407 << CSL_MCSPI_CH0CONF_FFEW_SHIFT)
412 #define MCSPI_TX_FIFO_DISABLE ((uint32_t) CSL_MCSPI_CH0CONF_FFEW_FFDISABLED \
413 << CSL_MCSPI_CH0CONF_FFEW_SHIFT)
418 #define MCSPI_REG_OFFSET (0x14U)
420 #define MCSPI_CHCONF(x) ((uint32_t) CSL_MCSPI_CH0CONF + \
421 (uint32_t) ((uint32_t) MCSPI_REG_OFFSET * \
424 #define MCSPI_CHSTAT(x) ((uint32_t) CSL_MCSPI_CH0STAT + \
425 (uint32_t) ((uint32_t) MCSPI_REG_OFFSET * \
428 #define MCSPI_CHCTRL(x) ((uint32_t) CSL_MCSPI_CH0CTRL + \
429 (uint32_t) ((uint32_t) MCSPI_REG_OFFSET * \
432 #define MCSPI_CHTX(x) ((uint32_t) CSL_MCSPI_TX0 + \
433 (uint32_t) ((uint32_t) MCSPI_REG_OFFSET * \
436 #define MCSPI_CHRX(x) ((uint32_t) CSL_MCSPI_RX0 + \
437 (uint32_t) ((uint32_t) MCSPI_REG_OFFSET * \
440 #define MCSPI_CLKD_MASK (0x0FU)
443 #define MCSPI_IRQSTATUS_CLEAR_ALL (CSL_MCSPI_IRQSTATUS_EOW_MASK | \
444 CSL_MCSPI_IRQSTATUS_WKS_MASK | \
445 CSL_MCSPI_IRQSTATUS_RX3_FULL_MASK | \
446 CSL_MCSPI_IRQSTATUS_TX3_UNDERFLOW_MASK | \
447 CSL_MCSPI_IRQSTATUS_TX3_EMPTY_MASK | \
448 CSL_MCSPI_IRQSTATUS_RX2_FULL_MASK | \
449 CSL_MCSPI_IRQSTATUS_TX2_UNDERFLOW_MASK | \
450 CSL_MCSPI_IRQSTATUS_TX2_EMPTY_MASK | \
451 CSL_MCSPI_IRQSTATUS_RX1_FULL_MASK | \
452 CSL_MCSPI_IRQSTATUS_TX1_UNDERFLOW_MASK | \
453 CSL_MCSPI_IRQSTATUS_TX1_EMPTY_MASK | \
454 CSL_MCSPI_IRQSTATUS_RX0_OVERFLOW_MASK | \
455 CSL_MCSPI_IRQSTATUS_RX0_FULL_MASK | \
456 CSL_MCSPI_IRQSTATUS_TX0_UNDERFLOW_MASK | \
457 CSL_MCSPI_IRQSTATUS_TX0_EMPTY_MASK)
531 typedef struct MCSPI_ExtendedParams_s
775 uint32_t dataSize, uint32_t csDisable);
778 uint32_t baseAddr, uint32_t intFlags)
781 CSL_REG32_WR(baseAddr + CSL_MCSPI_SYST, chObj->
systRegVal);
783 CSL_REG32_WR(baseAddr + CSL_MCSPI_IRQSTATUS, intFlags);
1098 uint32_t numWordsRxTx);
1189 static inline uint32_t
MCSPI_readChConf(uint32_t baseAddr, uint32_t chNum);
1243 uint32_t enableFlag);
1265 uint32_t enableFlag);
1302 uint32_t dataWidth);
1384 if(chConfig != NULL)
1410 trans->
txBuf = NULL;
1411 trans->
rxBuf = NULL;
1419 uint8_t bufWidthShift = 0U;
1425 else if(dataSize <= 16U)
1434 return bufWidthShift;
1470 CSL_REG32_WR(baseAddr +
MCSPI_CHTX(chNum), txData);
1475 uint32_t enableFlag)
1481 enableFlag >> CSL_MCSPI_CH0CONF_FFEW_SHIFT);
1486 uint32_t enableFlag)
1492 enableFlag >> CSL_MCSPI_CH0CONF_FFER_SHIFT);
1498 return (CSL_REG32_RD(baseAddr +
MCSPI_CHRX(chNum)));
1507 CSL_FINS(regVal, MCSPI_CH0CONF_WL, (dataWidth - 1U));
int32_t MCSPI_lld_readWriteDmaCancel(MCSPILLD_Handle hMcspi)
This API cancels current McSPI transfer in DMA mode.
uint32_t pinMode
Definition: mcspi_lld.h:709
static uint8_t MCSPI_getBufWidthShift(uint32_t dataSize)
This API will return the buffer width in bytes based on dataSize.
Definition: mcspi_lld.h:1417
int32_t MCSPI_lld_dmaDeInit(MCSPILLD_Handle hMcspi, const MCSPI_ChConfig *chCfg, uint32_t chCnt)
API to close an MCSPI DMA channel.
EDMA Instance Configuration. Pointer to this object is returned as handle by driver open.
Definition: edma/v0/edma.h:675
void * args
Definition: hsmclient_msg.h:4
uint32_t(* MCSPI_clockGet)(void)
Definition: mcspi_lld.h:73
uint8_t * curTxBufPtr
Definition: mcspi_lld.h:657
MCSPI driver initialization object.
Definition: mcspi_lld.h:698
MCSPI channel object.
Definition: mcspi_lld.h:639
uint32_t count
Definition: mcspi_lld.h:493
uint32_t txFifoTrigLvl
Definition: mcspi_lld.h:603
#define MCSPI_CHTX(x)
Base address of McSPI_CHTX(x)
Definition: mcspi_lld.h:432
#define MCSPI_FF_POL0_PHA0
Definition: mcspi_lld.h:231
uint32_t rxFifoTrigLvl
Definition: mcspi_lld.h:605
uint32_t intrNum
Definition: mcspi_lld.h:701
int32_t MCSPI_lld_readWriteCancel(MCSPILLD_Handle hMcspi)
This API cancels current McSPI transfer.
#define MCSPI_DPE_DISABLE
No transmission on Data Line.
Definition: mcspi_lld.h:283
uint32_t status
Definition: mcspi_lld.h:518
Data structure used with MCSPI_transfer()
Definition: mcspi_lld.h:472
uint32_t effTxFifoDepth
Definition: mcspi_lld.h:679
#define MCSPI_TCS0_0_CLK
0.5 clock cycles delay
Definition: mcspi_lld.h:319
static void MCSPI_writeTxDataReg(uint32_t baseAddr, uint32_t txData, uint32_t chNum)
This API will put the data on to the McSPI Channel transmit register.
Definition: mcspi_lld.h:1465
uint32_t transferDataSize
Definition: mcspi_lld.h:758
uint32_t MCSPI_lld_getBaseAddr(MCSPILLD_Handle handle)
Function to get base address of MCSPI instance of a particular handle.
uint32_t intrMask
Definition: mcspi_lld.h:683
MCSPI_clockGet clockP_get
Definition: mcspi_lld.h:723
#define MCSPI_WAIT_FOREVER
Value to use when needing a timeout of infinity or wait forver until resource is available.
Definition: mcspi_lld.h:122
uint32_t chConfRegVal
Definition: mcspi_lld.h:687
static void MCSPI_enableTxFIFO(uint32_t baseAddr, uint32_t chNum, uint32_t enableFlag)
This API will enable/disable the Tx FIFOs of McSPI peripheral.
Definition: mcspi_lld.h:1473
int32_t MCSPI_lld_transferCancel(MCSPILLD_Handle hMcspi)
This API cancels current McSPI transfer.
uint32_t errorFlag
Definition: mcspi_lld.h:748
#define MCSPI_SLV_CS_SELECT_0
Definition: mcspi_lld.h:292
uint8_t intrPriority
Definition: mcspi_lld.h:705
void(* MCSPI_errorCallbackFxn)(void *args, uint32_t transferStatus)
The definition of a error callback function used by the SPI driver when used in MCSPI_TRANSFER_MODE_C...
Definition: mcspi_lld.h:629
uint32_t dmaChConfigNum
Definition: mcspi_lld.h:645
#define MCSPI_CHCONF(x)
Base address of McSPI_CHCONF(x)
Definition: mcspi_lld.h:420
void MCSPI_lld_controllerIsr(void *args)
This is the McSPI Controller ISR and can be used as IRQ handler in Controller mode.
int32_t MCSPI_lld_readWriteIntr(MCSPILLD_Handle hMcspi, void *txBuf, void *rxBuf, uint32_t count, uint32_t timeout, const MCSPI_ExtendedParams *extendedParams)
This API reads writes data from the McSPI instance in Interrupt mode.
uint32_t bitRate
Definition: mcspi_lld.h:574
int32_t MCSPI_lld_dmaTransfer(MCSPILLD_Handle hMcspi, MCSPI_ChObject *chObj, const MCSPI_Transaction *transaction)
API to do a DMA transfer using a specific DMA driver - UDMA, EDMA etc.
void * args
Definition: mcspi_lld.h:553
MCSPI_transferCallbackFxn transferCallbackFxn
Definition: mcspi_lld.h:725
int32_t MCSPI_lld_read(MCSPILLD_Handle hMcspi, void *rxBuf, uint32_t count, uint32_t timeout, const MCSPI_ExtendedParams *extendedParams)
This API reads data from the McSPI instance in Polling mode.
static void MCSPI_lld_Transaction_init(MCSPI_Transaction *trans)
Function to initialize the MCSPI_Transaction struct to its defaults.
Definition: mcspi_lld.h:1402
MCSPI driver object.
Definition: mcspi_lld.h:735
#define MCSPI_SB_POL_LOW
Start-bit polarity is held to 0 during MCSPI transfer.
Definition: mcspi_lld.h:307
uint32_t timeout
Definition: mcspi_lld.h:516
static uint32_t MCSPI_readRxDataReg(uint32_t baseAddr, uint32_t chNum)
This API will return the data present in the MCSPI_RX register.
Definition: mcspi_lld.h:1495
#define MCSPI_DPE_ENABLE
Data line selected for transmission.
Definition: mcspi_lld.h:281
uint32_t csDisable
Definition: mcspi_lld.h:476
#define MCSPI_IS_D1
Data line 1 (SPIDAT[1]) selected for reception.
Definition: mcspi_lld.h:271
uint32_t chCtrlRegVal
Definition: mcspi_lld.h:689
struct MCSPILLD_InitObject * MCSPILLD_InitHandle
void MCSPI_lld_peripheralIsr(void *args)
This is the McSPI Peripheral ISR and can be used as IRQ handler in Peripheral mode.
#define MCSPI_CHRX(x)
Base address of McSPI_CHRX(x)
Definition: mcspi_lld.h:436
int32_t MCSPI_lld_writeDma(MCSPILLD_Handle hMcspi, void *txBuf, uint32_t count, uint32_t timeout, const MCSPI_ExtendedParams *extendedParams)
This API writes data to the McSPI instance in DMA mode.
uint32_t trMode
Definition: mcspi_lld.h:578
void(* MCSPI_transferCallbackFxn)(void *args, uint32_t transferStatus)
The definition of a transfer completion callback function used by the SPI driver when used in MCSPI_T...
Definition: mcspi_lld.h:620
MCSPILLD_InitHandle hMcspiInit
Definition: mcspi_lld.h:746
#define MCSPI_TR_MODE_TX_RX
Definition: mcspi_lld.h:257
#define MCSPI_CHSTAT(x)
Base address of McSPI_CHSTAT(x)
Definition: mcspi_lld.h:424
#define MCSPI_CHANNEL_0
Definition: mcspi_lld.h:158
uint32_t transferChannel
Definition: mcspi_lld.h:754
static void MCSPI_lld_ChConfig_init(MCSPI_ChConfig *chConfig)
Function to initialize the MCSPI_ChConfig struct to its defaults.
Definition: mcspi_lld.h:1382
uint32_t isOpen
Definition: mcspi_lld.h:651
static uint32_t MCSPI_readChCtrlReg(uint32_t baseAddr, uint32_t chNum)
This API returns Channel control register value.
Definition: mcspi_lld.h:1443
uint32_t state
Definition: mcspi_lld.h:742
int32_t MCSPI_lld_initDma(MCSPILLD_Handle hMcspi)
This API Initializes the McSPI instance in DMA Mode.
int32_t MCSPI_lld_deInitDma(MCSPILLD_Handle hMcspi)
This API De-Initializes the McSPI instance in DMA mode.
int32_t MCSPI_lld_dmaChInit(MCSPILLD_Handle hMcspi, uint32_t chCnt)
API to init a DMA Channel opened.
int32_t MCSPI_lld_transfer(MCSPILLD_Handle hMcspi, MCSPI_Transaction *transaction)
This API transfers data from the McSPI instance in Polling mode.
void MCSPI_initiateLastChunkTransfer(MCSPILLD_Handle hMcspi, MCSPI_ChObject *chObj, const MCSPI_Transaction *transaction)
This API will initiate the last chuncks when FIFO is enabled. The byte thats are non-multiple of FIFO...
uint32_t curRxWords
Definition: mcspi_lld.h:665
int32_t MCSPI_lld_transferDmaCancel(MCSPILLD_Handle hMcspi)
This API cancels current McSPI transfer in DMA mode.
int32_t MCSPI_lld_init(MCSPILLD_Handle hMcspi)
This API Initializes the McSPI instance.
void MCSPI_clearAllIrqStatus(uint32_t baseAddr)
int32_t MCSPI_lld_transferDma(MCSPILLD_Handle hMcspi, MCSPI_Transaction *transaction)
This API reads data from the McSPI instance in DMA mode.
static void MCSPI_enableRxFIFO(uint32_t baseAddr, uint32_t chNum, uint32_t enableFlag)
This API will enable/disable the Rx FIFOs of McSPI peripheral.
Definition: mcspi_lld.h:1484
static void MCSPI_intrStatusClear(const MCSPI_ChObject *chObj, uint32_t baseAddr, uint32_t intFlags)
Definition: mcspi_lld.h:777
uint32_t csPolarity
Definition: mcspi_lld.h:576
uint32_t startBitPolarity
Definition: mcspi_lld.h:592
uint32_t turboEnable
Definition: mcspi_lld.h:595
uint32_t channel
Definition: mcspi_lld.h:533
void * transferMutex
Definition: mcspi_lld.h:744
uint32_t multiWordAccess
Definition: mcspi_lld.h:713
int32_t MCSPI_lld_dmaInit(MCSPI_DmaHandle mcspiDmaHandle)
API to open an MCSPI DMA channel.
void MCSPI_reset(uint32_t baseAddr)
void MCSPI_lld_dmaStop(MCSPILLD_Handle hMcspi, MCSPI_ChObject *chObj, uint32_t chNum)
API to Stop DMA using a specific DMA driver - UDMA, EDMA etc.
int32_t MCSPI_lld_writeIntr(MCSPILLD_Handle hMcspi, void *txBuf, uint32_t count, uint32_t timeout, const MCSPI_ExtendedParams *extendedParams)
This API writes data to the McSPI instance in Interrupt mode.
uint32_t csDisable
Definition: mcspi_lld.h:653
void * args
Definition: mcspi_lld.h:514
uint32_t dataWidthBitMask
Definition: mcspi_lld.h:677
Data structure used with MCSPI_lld_read(), MCSPI_lld_readIntr(), MCSPI_lld_readDma(),...
Definition: mcspi_lld.h:532
uint32_t dataSize
Definition: mcspi_lld.h:542
uint32_t startBitEnable
Definition: mcspi_lld.h:589
void * txBuf
Definition: mcspi_lld.h:496
#define MCSPI_CHCTRL(x)
Base address of McSPI_CHCTRL(x)
Definition: mcspi_lld.h:428
uint32_t chMode
Definition: mcspi_lld.h:707
int32_t MCSPI_lld_reConfigFifo(MCSPILLD_Handle handle, uint32_t chNum, uint32_t numWordsRxTx)
Function to re-configure Effective FIFO Words.
void * rxBuf
Definition: mcspi_lld.h:507
uint32_t systRegVal
Definition: mcspi_lld.h:691
uint32_t effRxFifoDepth
Definition: mcspi_lld.h:681
#define MCSPI_MAX_NUM_CHANNELS
Max number of channels/Chip Select (CS) supported.
Definition: mcspi_lld.h:178
uint32_t dataSize
Definition: mcspi_lld.h:482
int32_t MCSPI_lld_write(MCSPILLD_Handle hMcspi, void *txBuf, uint32_t count, uint32_t timeout, const MCSPI_ExtendedParams *extendedParams)
This API writes data to the McSPI instance in Polling mode.
uint32_t curTxWords
Definition: mcspi_lld.h:661
MCSPI_DmaHandle mcspiDmaHandle
Definition: mcspi_lld.h:721
uint32_t slvCsSelect
Definition: mcspi_lld.h:586
int32_t MCSPI_lld_deInit(MCSPILLD_Handle hMcspi)
This API De-Initializes the McSPI instance.
static uint32_t MCSPI_readChStatusReg(uint32_t baseAddr, uint32_t chNum)
This API will return the status of the McSPI channel currently in use.
Definition: mcspi_lld.h:1437
void MCSPI_stop(MCSPILLD_Handle hMcspi, MCSPI_ChObject *chObj, uint32_t chNum)
uint8_t bufWidthShift
Definition: mcspi_lld.h:671
MCSPI_Transaction transaction
Definition: mcspi_lld.h:760
struct MCSPILLD_Object * MCSPILLD_Handle
int32_t MCSPI_lld_readWriteDma(MCSPILLD_Handle hMcspi, void *txBuf, void *rxBuf, uint32_t count, uint32_t timeout, const MCSPI_ExtendedParams *extendedParams)
This API reads writes data from the McSPI instance in DMA mode.
uint32_t csDisable
Definition: mcspi_lld.h:536
uint8_t * curRxBufPtr
Definition: mcspi_lld.h:659
int32_t MCSPI_lld_readIntr(MCSPILLD_Handle hMcspi, void *rxBuf, uint32_t count, uint32_t timeout, const MCSPI_ExtendedParams *extendedParams)
This API reads data from the McSPI instance in Interrupt mode.
#define MCSPI_CS_POL_LOW
SPIEN (CS) is held low during the ACTIVE state.
Definition: mcspi_lld.h:248
void * args
Definition: mcspi_lld.h:762
int32_t MCSPI_lld_readWrite(MCSPILLD_Handle hMcspi, void *txBuf, void *rxBuf, uint32_t count, uint32_t timeout, const MCSPI_ExtendedParams *extendedParams)
This API reads writes data from the McSPI instance in polling mode.
uint32_t defaultTxData
Definition: mcspi_lld.h:600
uint32_t dpe1
Definition: mcspi_lld.h:584
uint32_t msMode
Definition: mcspi_lld.h:715
uint32_t csEnable
Definition: mcspi_lld.h:655
uint32_t operMode
Definition: mcspi_lld.h:703
static void MCSPI_writeChCtrlReg(uint32_t baseAddr, uint32_t chNum, uint32_t regVal)
This API sets Channel control register value.
Definition: mcspi_lld.h:1448
MCSPI_ChConfig * chCfg
Definition: mcspi_lld.h:643
struct MCSPI_DmaChConfig_s * MCSPI_DmaChConfig
Definition: mcspi_dma_edma.h:78
static uint32_t MCSPI_readChConf(uint32_t baseAddr, uint32_t chNum)
This API returns Channel Config register value.
Definition: mcspi_lld.h:1454
MCSPI_DmaChConfig dmaChCfg
Definition: mcspi_lld.h:685
uint32_t channel
Definition: mcspi_lld.h:473
int32_t MCSPI_lld_readDma(MCSPILLD_Handle hMcspi, void *rxBuf, uint32_t count, uint32_t timeout, const MCSPI_ExtendedParams *extendedParams)
This API reads data from the McSPI instance in DMA mode.
int32_t MCSPI_lld_transferIntr(MCSPILLD_Handle hMcspi, MCSPI_Transaction *transaction)
This API reads data from the McSPI instance in Interrupt mode.
uint32_t inputSelect
Definition: mcspi_lld.h:580
uint32_t baseAddr
Definition: mcspi_lld.h:736
uint32_t dpe0
Definition: mcspi_lld.h:582
void MCSPI_setChDataSize(uint32_t baseAddr, MCSPI_ChObject *chObj, uint32_t dataSize, uint32_t csDisable)
int32_t MCSPI_lld_getState(MCSPILLD_Handle hMcspi)
This API returns the driver state.
MCSPI configuration parameters for the channel.
Definition: mcspi_lld.h:569
static void MCSPI_writeChConfReg(uint32_t baseAddr, uint32_t chNum, uint32_t regVal)
This API sets Channel Config register value.
Definition: mcspi_lld.h:1459
MCSPI_errorCallbackFxn errorCallbackFxn
Definition: mcspi_lld.h:727
uint32_t transferCsDisable
Definition: mcspi_lld.h:756
uint32_t initDelay
Definition: mcspi_lld.h:711
static void MCSPI_setDataWidth(uint32_t baseAddr, uint32_t chNum, uint32_t dataWidth)
This API will set the data width in the channel config register.
Definition: mcspi_lld.h:1501
uint32_t inputClkFreq
Definition: mcspi_lld.h:699
uint32_t frameFormat
Definition: mcspi_lld.h:572
uint32_t csIdleTime
Definition: mcspi_lld.h:597
uint32_t chNum
Definition: mcspi_lld.h:570