Release Notes 11.00.00

Table of Contents

• New in this Release
• Modules Not tested/supported in this release
  • Device and Validation Information
  • Dependent Tools and Compiler Information
  • Key Features
    • Experimental Features
    • OS Kernel
    • Driver Porting Layer (DPL)
    • Secondary Bootloader (SBL)
    • SOC Device Drivers
    • Trigonometric Operations
    • Board Device Drivers
    • Networking
    • Safety Diagnostic Library
    • PRU IO
  • Fixed Issues
  • Known Issues
  • Errata
  • Limitations
  • Upgrade and Compatibility Information
    • How to run FOTA examples on AM263PX-SIP board
    • Compiling examples in MacOS machines
    • RPRC Image format is Deprecated and Corresponding SBL's are also removed from SDK
    • Flash Reset moved to SysCfg
    • Module clock configuration through Clock Tree
    • Migrating back from CCS Theia to CCS Eclipse
      • Importing and Building in Eclipse
      • CCS SBL Loading
    • Migrating examples to 11.00.00 from older versions
      • Makefile Changes
    • SDL PBIST Self test
    • Compiler Options
    • SOC Device Drivers
    • Ethernet and Networking

Attention

1. Also refer to individual module pages for more details on each feature, unsupported features, important usage guidelines.

2. RPRC image format has been deprecated from this release. Multi Core ELF image format should be used. (Understanding Multicore ELF image format).

3. The default Stack size is 16KB and Heap size 32 KB for SDK examples. This can be adjusted as per application requirement through Memory Configurator in SysCfg or by updating Linker script in case of standalone applications.

4. SDK has been updated to support CCS Theia Out of Box from this release. Refer to Compatibility section below for changes w.r.t Eclipse.

5. The default SysCfg linked to CCS is an older version and needs to updated to the SDK supported version mentioned below. Please follow steps mentioned in Check Packages as seen by CCS.

6. Uniflash 9.2.0 does not support out of the box flashing of AM263Px-CC Rev B and AM263Px-LP Rev A binaries. As a workaround, use Uniflash's custom flasher feature mentioned here Custom Flash Support. Out of box flashing support for these boards will be available in the next Uniflash release.

7. For customer migrating from any release before SDK 10.00.00 to 10.00.00 or any release after, "DPL CFG" module has to be added in SysCfg in order to enable interrupts during DPL initialization. This module was added in SysCfg for 10.00.00 release to allow configuring Init time Enable/Disable of interrupts for RTOS applications (Default set to enabled).

Note

The examples will show usage of SW modules and APIs on a specific CPU instance and OS combination.
Unless explicitly noted otherwise, the SW modules would work in both FreeRTOS and no-RTOS environment.
Unless explicitly noted otherwise, the SW modules would work on any of the R5F's present on the SOC.

New in this Release

Feature	Module
Clock Tree support for PLL and Peripheral clock configuration	Sysconfig
CCS Theia Support	CCS
Multi Core FreeRTOS IPC Example	IPC
OSPI Phy Graph Plotter Example	OSPI
Board Level Sysconfig Support	Sysconfig
McSPI External Loopback Example	McSPI
SBL over Ethernet	Bootloader
LwIP stack upgrade to STABLE-2_2_1_RELEASE	Networking
Ethernet example demonstrating low-latency Raw-UDP traffic prioritization for industrial applications	Networking

Modules Not tested/supported in this release

Device and Validation Information

SOC	Supported CPUs	EVM	Host PC
AM263Px	R5F	AM263Px ControlCard Rev B (referred to as am263px-cc in code).	Windows 10 64b or Ubuntu 18.04 64b or MacOS
AM263Px	R5F	AM263Px LaunchPad Rev A (referred to as am263px-lp in code).	Windows 10 64b or Ubuntu 18.04 64b or MacOS

Dependent Tools and Compiler Information

Tools	Supported CPUs	Version
Code Composer Studio	R5F	20.3.0
SysConfig	R5F	1.25.0 build, build 4268
TI ARM CLANG	R5F	4.0.3.LTS
FreeRTOS Kernel	R5F	11.1.0
LwIP	R5F	STABLE-2_2_1_RELEASE
Mbed-TLS	R5F	2.13.1
Uniflash	R5F	9.2.0

Key Features

Experimental Features

Attention

Features listed below are early versions and should be considered as "experimental".

Users can evaluate the feature, however the feature is not fully tested at TI side.

TI would not support these feature on public e2e.

Experimental features will be enabled with limited examples and SW modules.

Feature	Module
GUI for UART Uniflash Tool	Bootloader
Ether-ring Driver Implementation	Networking
Ether-ring Demo with Real Time Traffic Generator and Background LwIP traffic	Networking
Smart Layout	OptiFlash
Etherring demo showcasing the integration of vehicle CAN bus data through a CAN-Ethernet gateway	Networking
Ethernet MDIO with Clause 45 support	Networking

OS Kernel

OS	Supported CPUs	SysConfig Support	Key features tested	Key features not tested / NOT supported
FreeRTOS Kernel	R5F	NA	Task, Task notification, interrupts, semaphores, mutexs, timers	Task load measurement using FreeRTOS run time statistics APIs. Limited support for ROV features.
FreeRTOS POSIX	R5F	NA	pthread, mqueue, semaphore, clock	-
NO RTOS	R5F	NA	See Driver Porting Layer (DPL) below	-

Driver Porting Layer (DPL)

Module	Supported CPUs	SysConfig Support	OS support	Key features tested	Key features not tested / NOT supported
Cache	R5F	YES	FreeRTOS, NORTOS	Cache write back, invalidate, enable/disable	-
Clock	R5F	YES	FreeRTOS, NORTOS	Tick timer at user specified resolution, timeouts and delays	-
CpuId	R5F	NA	FreeRTOS, NORTOS	Verify Core ID and Cluster ID that application is currently running on	-
CycleCounter	R5F	NA	FreeRTOS, NORTOS	Measure CPU cycles using CPU specific internal counters	-
Debug	R5F	YES	FreeRTOS, NORTOS	Logging and assert to any combo of: UART, CCS, shared memory	-
Heap	R5F	NA	FreeRTOS, NORTOS	Create arbitrary heaps in user defined memory segments	-
Hwi	R5F	YES	FreeRTOS, NORTOS	Interrupt register, enable/disable/restore, Interrupt prioritization	-
MPU	R5F	YES	FreeRTOS, NORTOS	Setup MPU and control access to address space	-
Semaphore	R5F	NA	FreeRTOS, NORTOS	Binary, Counting Semaphore, recursive mutexs with timeout	-
Task	R5F	NA	FreeRTOS	Create, delete tasks	-
Timer	R5F	YES	FreeRTOS, NORTOS	Configure arbitrary timers	-

Secondary Bootloader (SBL)

Module	Supported CPUs	SysConfig Support	OS support	Key features tested	Key features not tested / NOT supported
Bootloader	R5FSS0-0	YES	NORTOS	Boot modes: OSPI, UART. All R5F's. MCELF, multi-core image format	-

SOC Device Drivers

Peripheral	Supported CPUs	SysConfig Support	DMA Supported	Key features tested	Key features not tested / NOT supported
ADC, ADC_R	R5F	YES	Yes. Examples: adc_soc_continuous_dma, adc_alternate_dma_trigger	Single software triggered conversion, Multiple ADC trigger using PWM, Result read using DMA (normal and alternate triggers), EPWM trip through PPB limit, PPB features, Burst mode, Single and Differential mode, Interrupt with Offset from Aquisition Window, EPWM/ECAP/RTI triggered conversions, Trigger Repeater for Undersampling and Oversampling, Global Force on Multiple ADCs, Internal DAC Loopback to Calibration Channels, Safety Checker and Aggregator, Open Short Detection feature	External channel selection
Bootloader	R5F	YES	Yes. DMA enabled for SBL OSPI	Boot modes: OSPI, UART. All R5F's	-
CMPSS	R5F	YES	NA	Asynchronous PWM trip, digital filter, Calibration, Diode Emulation example	CMPSS Dac LoopBack feature
CPSW	R5F	YES	No	MAC loopback, PHY loopback, LWIP: Getting IP, Ping, Iperf, Layer 2 MAC, Layer 2 PTP Timestamping and Ethernet CPSW Switch support, TSN stack	RMII, MII mode
DAC	R5F	YES	Yes. Example: dac_sine_dma	Constant voltage, Square wave generation, Sine wave generation with and without DMA, Ramp wave generation, Random Voltage generation	-
ECAP	R5F	YES	yes. Example : ecap_edma	ECAP APWM mode, PWM capture, DMA trigger in both APWM and Capture Modes, ecap signal monitoring example	-
EDMA	R5F	YES	NA	DMA transfer using interrupt and polling mode, QDMA Transfer, Channel Chaining, PaRAM Linking, Error Handling	-
EPWM	R5F	YES	Yes. Example: epwm_dma, epwm_xcmp_dma	Multiple EPWM Sync from Top Module, PWM outputs A and B in up-down count mode, Trip zone, Update PWM using EDMA, Valley switching, High resolution time period adjustment, chopper module features, type5 features	-
EQEP	R5F	YES	NA	Speed and Position measurement. Frequency Measurement, Speed and Direction Measurement, cw-ccw modes	-
FSI	R5F	YES	Yes. Example: fsi_loopback_dma	RX, TX, polling, interrupt mode, Dma, single lane loopback.	- FSI Spi Mode
GPIO	R5F	YES	NA	Output, Input and Interrupt functionality	-
I2C	R5F	YES	No	Controller mode, basic read/write	-
IPC Notify	R5F	YES	NA	Mailbox functionality, IPC between RTOS/NORTOS CPUs	M4F core
IPC Rpmsg	R5F	YES	NA	RPMessage protocol based IPC	M4F core
LIN	R5F	YES	YES	RX, TX, polling, interrupt, DMA mode.	-
MCAN	R5F	YES	No	RX, TX, interrupt and polling mode, Corrupt Message Transmission Prevention, Error Passive state, Bus Off State, Bus Monitoring Mode	-
MCSPI	R5F	YES	Yes. Example: mcspi_loopback_dma	Controller/Peripheral mode, basic read/write, polling, interrupt and DMA mode	-
MDIO	R5F	YES	NA	Register read/write, link status and link interrupt enable API	-
MMCSD	R5F	YES	NA	MMCSD 4bit, Raw read/write, file IO, eMMC	-
PINMUX	R5F	YES	NA	Tested with multiple peripheral pinmuxes	-
PMU	R5F	NO	NA	Tested various PMU events	Counter overflow detection is not enabled
OptiFlash	R5F	Yes	NA	FLC, RL2, RAT functionality, XIP with RL2 enabled, OTFA, FOTA, Optishare, Smart Layout	-
OSPI	R5F	YES	Yes. Example: ospi_flash_dma	Read direct, Write indirect, Read/Write commands, DMA for read	-
RTI	R5F	YES	No	Counter read, timebase selection, comparator setup for Interrupt, DMA requests	Capture feature, fast enabling/disabling of events not tested
RESOLVER	R5F	YES	No	Angle and Speed Calcution. input Band Pass Filter, Manual Phase Gain Correction and Manual Ideal Sample Selection Mode calculation, Non-Rotational Safety Diagnostic features, Dual motor/Single motor redundant sensing	Tuning, Rotational Safety Diagnostic features
SDFM	R5F	YES	yes. Example : sdfm_filter_sync_dmaread	Filter data read from CPU, Filter data read with PWM sync, triggered DMA read from the Filter FIFO, ECAP Clock LoopBack	-
SOC	R5F	YES	NA	Lock/unlock MMRs, clock enable, set Hz, Xbar configuration, SW Warm Reset, Address Translation	-
SPINLOCK	R5F	NA	NA	Lock, unlock HW spinlock	-
UART	R5F	YES	Yes. Example: uart_echo_dma	Basic read/write at baud rate 115200, polling, interrupt mode	HW flow control not tested, DMA mode not supported
WATCHDOG	R5F	YES	NA	Reset mode, Interrupt mode	-

Trigonometric Operations

Peripheral	Supported CPUs	SysConfig Support	DMA Supported	Key features tested	Key features not tested / NOT supported
TMU	R5F	NO	NA	TMU Operations, Pipelining, Contex Save	Square Root, Division Operations. more than 1 Interrupt Nesting for the contex save is not Supported.

Board Device Drivers

Peripheral	Supported CPUs	SysConfig Support	Key features tested	Key features not tested
EEPROM	R5F	YES	Only compiled	-
FLASH	R5F	YES	OSPI Flash	-
LED	R5F	YES	GPIO	-
ETHPHY	R5F	YES	Tested with ethercat_slave_beckhoff_ssc_demo example	-
PMIC	R5F	YES	LDO Voltage control	-
IOEXPANDER	R5F	YES	IO configurability	-

Networking

Module	Supported CPUs	SysConfig Support	OS Support	Key features tested	Key features not tested
Time-Sensitive Networking(gPTP-IEEE 802.1AS)	R5F	NO	FreeRTOS	gPTP IEEE 802.1 AS-2020 compliant gPTP stack, End Nodes and Bridge mode support, YANG data model configuration, IEEE 1722 compliant AVTP Stack	Multi-Clock Domain
LwIP	R5F	YES	FreeRTOS	TCP/UDP IP networking stack with and without checksum offload enabled, TCP/UDP IP networking stack with server and client functionality, basic Socket APIs, netconn APIs and raw APIs, DHCP, ping, TCP iperf, scatter-gather, DSCP priority mapping	Other LwIP features
Ethernet driver (ENET)	R5F	YES	FreeRTOS	Ethernet as port using CPSW, MAC loopback and PHY loopback, Layer 2 MAC, Packet Timestamping, CPSW Switch, CPSW EST, interrupt pacing, Policer and Classifier, MDIO Manual Mode, Credit Based Shaper (IEEE 802.1Qav), Strapped PHY (Early Ethernet)	N/A
ICSS-EMAC	R5F	YES	FreeRTOS	Switch and MAC features, Storm Prevention (MAC), Host Statistics, Multicast Filtering	Promiscuous Mode
Ether-ring Implementation	R5F	NO	FreeRTOS	Duplicate Rejection, Ring termination and Packet Duplication, Latency measurement for different real-time traffic profiles, Performance KPIs	N/A

Safety Diagnostic Library

Module	Supported CPUs	SysConfig Support	OS support	Key features tested	Key features not tested / NOT supported
MCRC	R5F	NA	NORTOS	Full CPU, Auto CPU Mode and Semi CPU Auto Mode	-
DCC	R5F	NA	NORTOS	Single Shot and Continuous modes	-
PBIST	R5F	NA	NORTOS	Memories supported by MSS PBIST controller.	-
ESM	R5F	NA	NORTOS	Tested in combination with RTI, DCC	-
RTI	R5F	NA	NORTOS	WINDOWSIZE_100_PERCENT, WINDOWSIZE_50_PERCENT ,Latency/Propagation timing error(early)(50% window),Latency/Propagation timing error(late)(50% window)	-
ECC	R5F	NA	NORTOS	ECC of MSS_L2, R5F TCM, MCAN, VIM, ICSSM, TPTC	FSS FOTA and OSPI
ECC Bus Safety	R5F	NA	NORTOS	AHB, AXI, TPTC	-
CCM	R5F	NA	NORTOS	CCM Self Test Mode,Error Forcing Mode and Self Test Error Forcing Mode. TMU and RL2 are also validated	-
R5F STC(LBIST), Static Register Read	R5F	NA	NORTOS	STC of R5F, R5F CPU Static Register Read	-
TMU ROM Checksum	R5F	NA	NORTOS	ROM checksum for TMU	-
Time out Gasket(STOG)	R5F	NA	NORTOS	Timeout gasket feature	-
Thermal Monitor(VTM)	R5F	NA	NORTOS	Over, under and thershold temperature interrupts	-
Integrated Example	R5F	NA	FreeRTOS	Integrated example with all the SDL modules integrated in to one example.	ECC for TPTC, ECC Bus Safety and STC.

Note: SDL is validated only on ControlCard.

PRU IO

Module	Supported CPUs	SysConfig Support	OS Support	Key features tested	Key features not tested
Empty	PRU	YES	Bare Metal	Empty project to get started with PRU firmware development	-

Fixed Issues

ID	Head Line	Module	Applicable Releases	Applicable Devices	Resolution/Comments
MCUSDK-14749	McSPI: Non Powers of 2 cannot be configured as fifo trigger levels in polling and interrupt mode	McSPI	10.02.00 onwards	AM263x, AM263Px	Fix in SysCfg Meta file.
MCUSDK-13966	All UART triggers levels not exposed in SysCfg	UART	10.00.00 onwards	AM263x, AM263Px	Update SysCfg to show all trigger levels from 1 to 64.
MCUSDK-14573	Incorrect handling of errata i2310 in UART isr	UART	10.00.00 onwards	AM263x, AM263Px	Reorder the ISR state machine for handling UART errata correctly.
MCUSDK-14704	Adding multiple instances of UART DMA LLD causes failure	UART	10.01.00 onwards	AM263x, AM263Px	SysCfg template update to pass the EDMA handle correctly
MCUSDK-14706	GPIO Qual selection API missing	GPIO	10.00.00 onwards	AM263x, AM263Px	Qual sel API added in pinmux driver
MCUSDK-14569	UART Errata i2310 is missing a step	UART	10.00.00 onwards	AM263x, AM263Px	Added IIR register read to clear the interrupt
MCUSDK-14620	SDK build fails in Mac Machines	Build	10.02.00 onwards	AM263x, AM263Px	Added GMAC library for MAC into SDK
MCUSDK-14659	Incorrect RTI clock source mux address for RTI 4 to 7	RTI	10.00.00 onwards	AM263Px	Updated to correct mux addresses in SysCfg
MCUSDK-13182	SysCfg unexpectedly changes OSPI Pin	OSPI	10.00.00 onwards	AM263Px	The OSPI pins are locked in SDK examples.
MCUSDK-14857, MCUSDK-14731	Core 1 unhalted in SBL before FSM Trigger, Memory load	SBL	10.00.00 onwards	AM263x, AM263Px	Skip unhalting core 1 of both clusters in dual core mode
MCUSDK-14712	OSPI Reset Pin being used before configuration	OSPI	10.00.00 onwards	AM263Px	Configure OSPI reset in OSPI open instead of Flash open
PROC_SDL-9179	Redefinition error in MCU_PBIST Sysconfig	SDL	10.02.00 onwards	AM263Px, AM261x	Resolved in Source code
PROC_SDL-9148	ECC D-Data fail during release	SDL	10.02.00 onwards	AM263x, AM263Px	Fixed in example.
PROC_SDL-9160	PBIST does not cover the VIM memories	SDL	10.02.00 onwards	AM263x, AM263Px, AM261x	Fixed in Source and Used polling method instead of ISR to cover VIM memory
PROC_SDL-9154	VTM Example stuck in UC2	SDL	10.02.00 onwards	AM263Px, AM261x	Fixed in example
MCUSDK-14695	SDFM_configComparator has incorrect input in examples	SDFM	10.00.00 onwards	AM263x, AM263Px	Updated example to pass correct value
MCUSDK-13153	Self nesting of interrupts is not working	DPL	09.01.00 onwards	AM263x, AM263Px	Added macros for handling self re-entrant IRQ
MCUSDK-11935	DPL Low Latency Interrupt Application: controlfnc section missing in linker command	DPL	09.00.00 onwards	AM263x, AM263Px	Added missing .controlfnc section in linker command file of DPL Low Latency Interrupt example
MCUSDK-14696	ADC Sysconfig does not seem to generate codes for repeaters	ADC	10.00.00 onwards	AM263Px	Fixed syscfg template file to generate trigger repeater code for burst mode
MCUSDK-14645	Implementation of the ADC_selectSOCExtChannel	ADC	10.01.00 onwards	AM263Px	Fixed ADC_selectSOCExtChannel API implementation
MCUSDK-14746	TMU: Docs: QUAD feature listed under not supported section	TMU	10.02.00 onwards	AM263Px	Updated documentation
MCUSDK-14661	Errata i2485 config missing in empty projects	TMU	10.02.00 onwards	AM263Px	Updated example syscfg to have the part of TCMA blocked for R5SS1_CORE1
MCUSDK-14917	"Selected mode" in pinmux.csv.xdt file not being updated correctly in SysCfg	Pinmux	10.01.00 onwards	AM263x, AM263Px, AM261x	Fixed in Pinmux CSV template

Known Issues

ID	Head Line	Module	Reported in release	Workaround
MCUSDK-13865	HRPWM Deadband sfo example has 1ns jitter	EPWM	10.00.00 onwards	-
MCUSDK-13201	HRPWM waveform not generating (in updwon count) when prescaler is non-zero and HRPE is enabled	EPWM	10.00.01 onwards	None
MCUSDK-13834	EQEP: EQEP frequency measurement example is not working as expected	EQEP	10.00.01 onwards	None
MCUSDK-14059	CMPSS DE example has Glitch in PWM output	CMPSS	10.00.01 onwards	None
MCUSDK-13011	Multicore Empty project not working properly	FreeRTOS	09.01.00 onwards	-
PINDSW-7715	Dual EMAC instance not working with both ports together for icss_emac_lwip example	ICSS-EMAC	09.02.00 onwards	None
PINDSW-7746	Low iperf values in TCP and UDP	ICSS-EMAC	09.02.00 onwards	None
PINDSW-8118	Enabling DHCP mode in icss_emac_lwip example causes assert	ICSS-EMAC	09.02.00 onwards	None
MCUSDK-12756	MbedTLS - Timing side channel attack in RSA private operation exposing plaintext.	Mbed-TLS	08.06.00 onwards	None
MCUSDK-14898	SDL apps fails on other than RFSS0-0 with SBL	SBL, SDL	11.00.00 onwards	This because SBL brings the RFSS1-0 out of reset before the SBL UART prints gets flushed. This will be fixed in next release. As a workaround the application in R5FSS1-0 can delay the start of application till SBL UART prints gets completed.
PROC_SDL-8392	In ECC bus safety example, ECC error is not properly cleared at the source.	SDL	09.00.00 onwards	None
PROC_SDL-8787	ECC TPTC and STC examples are not supported in SDL integrated example.	SDL	10.01.00 onwards	Use standalone examples and for STC use sbl_null with syscfg enabled
PROC_SDL-8857	SDL integrated example does not support ECC Bus Safety.	SDL	10.01.00 onwards	Use standalone example.
PROC_SDL-9163	ECC Aggregators FSS FOTA and OSPI	SDL	10.02.00 onwards	None
MCUSDK-13652	Readelf throws warning while parsing RS note	SBL, QSPI	10.00.00 onwards	-
MCUSDK-14509	AM263x/Am263px/AM261x: 10% Packet drop with UDP iperf in 100M bandwidth in 1Gbps FullDuplex linkspeed	Networking	10.00.00 onwards	-
MCUSDK-14883	AM263x, AM263Px: SBL: RPRC descoping broke SBL over Ethernet example	Networking	11.00.00 onwards	-
MCUSDK-14582	Flash: Incorrect flash name after Loading Flash JSON	OSPI	10.00.00 onwards	-
MCUSDK-14647	All CANFD standard ID conigurations are not exposed in SysCfg	CAN	10.02.00 onwards	Configure Config type, ID's,etc in application
MCUSDK-14714	Bufnum of 6 and 12 will cause the vring indexes to get corrupted	IPC	10.00.00 onwards	Use other VRING buffer numbers.
MCUSDK-14879	Potential system hang issue due to priority mask based critical sections.	FreeRTOS	10.00.00 onwards	Not to use Priority mask based critical sections (Disabled by default in SDK).
MCUSDK-14893	Sub projects under system projects cannot be changed in CCS Theia	CCS	11.00.00 onwards	-
MCUSDK-14819	Ram is getting erased/overwritten once warm reset is done in application	SBL	11.00.00 onwards	-
MCUSDK-14851	Few parameters are incorrect in JEDEC table from ospi diag example	OSPI	11.00.00 onwards	Refer flash datasheet and update
MCUSDK-14895	UART LLD Rx error checking logic checks if all errors exist at once	UART	10.00.00 onwards	-
MCUSDK-13011	Data Abort in application when all cores are running freertos using Gel files(CCS)	FreeRTOS	10.00.00 onwards	Flash and use SBL NULL instead of gel files
MCUSDK-14941	McSPI: Non Multiple's of FIFO cannot be transferred in DMA mode	McSPI	10.00.00 onwards	Use FIFO Trigger level of 1.
MCUSDK-14936	Uniflash unable to connect to target in OSPI boot mode	Uniflash	10.01.00 onwards	-
MCUSDK-14914	Unable to add UART communication port to target configuration in Theia	Real Time Debug	10.02.00 onwards	Use the CCXML file from CCS eclipse after updating to correct COM port.

Errata

ID	Head Line	Module	SDK Status
i2189	OSPI: Controller PHY Tuning Algorithm	OSPI	Implemented
i2311	USART: Spurious DMA Interrupts	UART	Implemented
i2324	No synchronizer present between GCM and GCD status signals	Common	Implemented
i2345	CPSW: Ethernet Packet corruption occurs if CPDMA fetches a packet which spans across memory banks	CPSW	Implemented
i2351	OSPI: Controller does not support Continuous Read mode with NAND Flash	OSPI	Implemented
i2354	SDFM: Two Back-to-Back Writes to SDCPARMx Register Bit Fields CEVT1SEL, CEVT2SEL, and HZEN Within Three SD-Modulator Clock Cycles can Corrupt SDFM State Machine, Resulting in Spurious Comparator Events	SDFM	Open
i2356	ADC: Interrupts may Stop if INTxCONT (Continue-to-Interrupt Mode) is not Set	ADC	Implemented
i2375	SDFM: SDFM module event flags (SDIFLG.FLTx_FLG_CEVTx) do not get set again if the comparator event is still active and digital filter path (using SDCOMPxCTL.CEVTxDIGFILTSEL) is being selected	SDFM	Open
i2383	OSPI: 2-byte address is not supported in PHY DDR mode	OSPI	Implemented
i2401	CPSW: Host Timestamps Cause CPSW Port to Lock up	CPSW	Open
i2404	Race condition in mailbox registers resulting in events miss	IPC, Mailbox	Implemented
i2405	CONTROLSS: Race condition OUTPUT_XBAR and PWM_XBAR resulting in event miss	Crossbar	Open
i2485	AM263PX: TMU: TCM Memory Corruption on R5SS0_CORE1 and R5SS1_CORE1 when writing to TMU Registers	TMU	Implemented a workaround Errata : TCM Memory Corruption on R5SS0_CORE1 and R5SS1_CORE1 when writing to TMU Registers Workaround: Do not use initial bytes (0x40-0x3A0) of ATCM from CPU1 allocation. Initial bytes (0x40-0x3A0 => 868 bytes) of CORE1 TCM are blocked using linker command settings of multi-core application/examples. Refer TMU 4 Cores Support

Limitations

ID	Head Line	Module	Reported in release	Workaround
MCUSDK-13630	Cache should not be enabled at last 32B L2 Bank boundary	Cache	10.01.00	Create MPU configurations for last 32B of each L2 Bank with Non Cached attribute

Upgrade and Compatibility Information

How to run FOTA examples on AM263PX-SIP board

One difference between AM263PX-SIP and AM263PX is the in package flash. In SIP board, flash is of Non-RWW in nature whereas, it is of RWW in other case. Example FLSOPSKD Benchmark is made to work out of box for AM263PX board but need some manual changes to make it work on AM263PX-SIP board. Here, to make this example with AM263PX-SIP board, please remove the RUN_XIP_IN_PARALLEL macro.

Compiling examples in MacOS machines

Currently the gmac library packaged within SDK is compiled using gcc darwin23.6.0 on Apple MAC. To build SDK examples on a different toolchain, recompile the gmac library by using these steps:

$ cd {SDK_PATH}/tools/boot/multicore-elf/c_modules/gmac
$ make all

• A new library will be created inside mac/dist.
• Rename this file to "gmac.arm64-apple-darwin.darwin.dylib".

RPRC Image format is Deprecated and Corresponding SBL's are also removed from SDK

RPRC image format is no longer supported and MCELF will be the only file format. Older SBL's and Cfg files which mapped to RPRC format are removed and replaced with MCELF variants. Below is the list of updated SBL's and Cfg files:

Deprecated SBL + CFG File	Supported SBL + CFG File
SBL QSPI (default_sbl_qspi.cfg)	SBL QSPI MULTICORE ELF (mcelf_sbl_qspi.cfg)
SBL UART	SBL UART MULTICORE ELF
SBL SD (default_sbl_sd.cfg)	SBL SD MULTICORE ELF (mcelf_sbl_sd.cfg)
SBL CAN (default_sbl_can.cfg)	SBL CAN MULTICORE ELF (mcelf_sbl_can.cfg)
SBL CAN UNIFLASH (default_sbl_can_uniflash.cfg, default_sbl_can_uniflash_app.cfg)	SBL CAN UNIFLASH MULTICORE ELF (mcelf_sbl_can_uniflash.cfg, mcelf_sbl_can_uniflash_app.cfg)

Please refer to the updated SDK example makefiles for Infra changes.

Flash Reset moved to SysCfg

Earlier, flash reset was done in board.c file within application which is now moved to SysCfg. If Flash reset logic needs to be added, please enable "Enable Flash Reset API" configurable in Flash module. This is by enabled out of box for all SDK Flash examples. For custom flash, define the flash reset API in application and add the API name to "Flash Reset Function" configurable.

Module clock configuration through Clock Tree

Previously our SDK had a mix of hardcoded clock configurations and limited configuration flexibility through sysconfig for the modules. With Clocktree, we now have a clear view of the entire clock tree with configurable components like PLL, DPLL, muxes, dividers added with validity checks. Earlier, the Input clock source and frequency for any module was configured through the module view in SysCfg. From now, this has to be done through clocktree.

Please refer to Clocktree for more details.

Migrating back from CCS Theia to CCS Eclipse

SDK was supporting CCS Eclipse until this release and now been migrated to support CCS Theia Out of Box. Below sections describe how to update the applications for Eclipse if needed.

Importing and Building in Eclipse

CCS Projectspec files are same for both Theia and Eclipse. Hence, no update is needed to import and build an SDK application on Eclipse.

CCS SBL Loading

JS Script for SBL loading on eclipse is updated to "load_sbl_eclipse.js". Please refer to CCS Tools for more details.

Migrating examples to 11.00.00 from older versions

Note

Images are shown for AM64x. It is application for AM263PX as well.

Makefile Changes

Library Name change on makefile and CCS projects

From 11.00.00 SDK all the libraries are built separately for OS. There are separate libraries available for NoRTOS and FreeROTS. So the makefiles needs to be updated accordingly. Please refer the sample changes on the makefile below. These changes are not applicbale for the librarries which were already built separately for NoRTOS/FreeRTOS like kernel libraries.

For NoRTOS/baremetal,

Library name change for NoRTOS example

For FreeRTOS,

Library name change for FreeRTOS example

similar change can be done on the CCS project as well

OS define on makefile and CCS projects

Additional macro OS_NORTOS or OS_FREERTOS should be defined on the makefile or CC project based on the OS of the project.

For NoRTOS/baremetal,

OS Macro addition for NoRTOS example

For FreeRTOS,

OS Macro addition for FreeRTOS example

SDL PBIST Self test

VIM Memory groups are added to PBIST self test from this release. Because of this change, Self test (SDL_PBIST_selfTest) API has to be called in polling mode only and interrupt mode is not supported.

Compiler Options

Module	Affected API	Change	Additional Remarks
-	-	-	-

SOC Device Drivers

Module	Affected API	Change	Additional Remarks
-	-	-	-

Ethernet and Networking

Module	Affected API	Change	Additional Remarks
-	-	-	-