AM263Px MCU+ SDK  10.02.00
Release Notes 10.02.00

Attention
1. Also refer to individual module pages for more details on each feature, unsupported features, important usage guidelines.
2. Multi Core ELF image format support has been added (Understanding Multicore ELF image format). RPRC format will be deprecated from SDK 11.0.
3. The default Stack size is 16KB and Heap size 32 KB for SDK examples. This can be adjusted as per application requirement through Memory Configurator in SysCfg or by updating Linker script in case of standalone applications.
4. SDK will be migrated to support CCS Theia from next release (SDK 11.0) and the support for CCS Eclipse will be deprecated.
5. There is a known issue that OSPI pins in SysCfg GUI are getting reset automatically during any module change. The workaround is that OSPI Pins should be locked after proper configuration according to the board Pinout.
6. The default SysCfg linked to CCS is an older version and needs to updated to the SDK supported version mentioned below. Please follow steps mentioned in Check Packages as seen by CCS.
Note
The examples will show usage of SW modules and APIs on a specific CPU instance and OS combination.
Unless explicitly noted otherwise, the SW modules would work in both FreeRTOS and no-RTOS environment.
Unless explicitly noted otherwise, the SW modules would work on any of the R5F's present on the SOC.

New in this Release

Feature Module
OTFA Security Support OptiFlash
FreeRTOS MPU Support for R5F and Examples Kernel
EDMA Error Handling Support EDMA
LIN LLD Support LIN

Modules Not tested/supported in this release

  • -

Device and Validation Information

SOC Supported CPUs EVM Host PC
AM263Px R5F AM263Px ControlCard Rev A (referred to as am263px-cc in code).
Windows 10 64b or Ubuntu 18.04 64b
AM263Px R5F AM263Px LaunchPad Rev E2 (referred to as am263px-lp in code).
Windows 10 64b or Ubuntu 18.04 64b

Dependent Tools and Compiler Information

Tools Supported CPUs Version
Code Composer Studio R5F 12.8.1
SysConfig R5F 1.23.0 build, build 4000
TI ARM CLANG R5F 4.0.1.LTS
FreeRTOS Kernel R5F 11.1.0
LwIP R5F STABLE-2_2_0_RELEASE
Mbed-TLS R5F 2.13.1

Key Features

Experimental Features

Attention
Features listed below are early versions and should be considered as "experimental".
Users can evaluate the feature, however the feature is not fully tested at TI side.
TI would not support these feature on public e2e.
Experimental features will be enabled with limited examples and SW modules.
Feature Module
GUI for UART Uniflash Tool Bootloader
Ether-ring Driver Implementation Networking
Ether-ring Demo with Real Time Traffic Generator and Background LwIP traffic Networking

OS Kernel

OS Supported CPUs SysConfig Support Key features tested Key features not tested / NOT supported
FreeRTOS Kernel R5F NA Task, Task notification, interrupts, semaphores, mutexs, timers Task load measurement using FreeRTOS run time statistics APIs. Limited support for ROV features.
FreeRTOS POSIX R5F NA pthread, mqueue, semaphore, clock -
NO RTOS R5F NA See Driver Porting Layer (DPL) below -

Driver Porting Layer (DPL)

Module Supported CPUs SysConfig Support OS support Key features tested Key features not tested / NOT supported
Cache R5F YES FreeRTOS, NORTOS Cache write back, invalidate, enable/disable -
Clock R5F YES FreeRTOS, NORTOS Tick timer at user specified resolution, timeouts and delays -
CpuId R5F NA FreeRTOS, NORTOS Verify Core ID and Cluster ID that application is currently running on -
CycleCounter R5F NA FreeRTOS, NORTOS Measure CPU cycles using CPU specific internal counters -
Debug R5F YES FreeRTOS, NORTOS Logging and assert to any combo of: UART, CCS, shared memory -
Heap R5F NA FreeRTOS, NORTOS Create arbitrary heaps in user defined memory segments -
Hwi R5F YES FreeRTOS, NORTOS Interrupt register, enable/disable/restore, Interrupt prioritization -
MPU R5F YES FreeRTOS, NORTOS Setup MPU and control access to address space -
Semaphore R5F NA FreeRTOS, NORTOS Binary, Counting Semaphore, recursive mutexs with timeout -
Task R5F NA FreeRTOS Create, delete tasks -
Timer R5F YES FreeRTOS, NORTOS Configure arbitrary timers -

Secondary Bootloader (SBL)

Module Supported CPUs SysConfig Support OS support Key features tested Key features not tested / NOT supported
Bootloader R5FSS0-0 YES NORTOS Boot modes: OSPI, UART. All R5F's. RPRC, MCELF, multi-core image format Force Dual Core Mode

SOC Device Drivers

Peripheral Supported CPUs SysConfig Support DMA Supported Key features tested Key features not tested / NOT supported
ADC, ADC_R R5F YES Yes. Examples: adc_soc_continuous_dma, adc_alternate_dma_trigger Single software triggered conversion, Multiple ADC trigger using PWM, Result read using DMA (normal and alternate triggers), EPWM trip through PPB limit, PPB features, Burst mode, Single and Differential mode, Interrupt with Offset from Aquisition Window, EPWM/ECAP/RTI triggered conversions, Trigger Repeater for Undersampling and Oversampling, Global Force on Multiple ADCs, Internal DAC Loopback to Calibration Channels, Safety Checker and Aggregator, Open Short Detection feature External channel selection
Bootloader R5F YES Yes. DMA enabled for SBL OSPI Boot modes: OSPI, UART. All R5F's -
CMPSS R5F YES NA Asynchronous PWM trip, digital filter, Calibration, Diode Emulation example CMPSS Dac LoopBack feature
CPSW R5F YES No MAC loopback, PHY loopback, LWIP: Getting IP, Ping, Iperf, Layer 2 MAC, Layer 2 PTP Timestamping and Ethernet CPSW Switch support, TSN stack RMII, MII mode
DAC R5F YES Yes. Example: dac_sine_dma Constant voltage, Square wave generation, Sine wave generation with and without DMA, Ramp wave generation, Random Voltage generation -
ECAP R5F YES yes. Example : ecap_edma ECAP APWM mode, PWM capture, DMA trigger in both APWM and Capture Modes, ecap signal monitoring example -
EDMA R5F YES NA DMA transfer using interrupt and polling mode, QDMA Transfer, Channel Chaining, PaRAM Linking, Error Handling -
EPWM R5F YES Yes. Example: epwm_dma, epwm_xcmp_dma Multiple EPWM Sync from Top Module, PWM outputs A and B in up-down count mode, Trip zone, Update PWM using EDMA, Valley switching, High resolution time period adjustment, chopper module features, type5 features -
EQEP R5F YES NA Speed and Position measurement. Frequency Measurement, Speed and Direction Measurement, cw-ccw modes -
FSI R5F YES Yes. Example: fsi_loopback_dma RX, TX, polling, interrupt mode, Dma, single lane loopback. - FSI Spi Mode
GPIO R5F YES NA Output, Input and Interrupt functionality -
I2C R5F YES No Controller mode, basic read/write -
IPC Notify R5F YES NA Mailbox functionality, IPC between RTOS/NORTOS CPUs M4F core
IPC Rpmsg R5F YES NA RPMessage protocol based IPC M4F core
LIN R5F YES YES RX, TX, polling, interrupt, DMA mode. -
MCAN R5F YES No RX, TX, interrupt and polling mode, Corrupt Message Transmission Prevention, Error Passive state, Bus Off State, Bus Monitoring Mode -
MCSPI R5F YES Yes. Example: mcspi_loopback_dma Controller/Peripheral mode, basic read/write, polling, interrupt and DMA mode -
MDIO R5F YES NA Register read/write, link status and link interrupt enable API -
MMCSD R5F YES NA MMCSD 4bit, Raw read/write file IO, eMMC
PINMUX R5F YES NA Tested with multiple peripheral pinmuxes -
PMU R5F NO NA Tested various PMU events Counter overflow detection is not enabled
OptiFlash R5F Yes NA FLC, RL2, RAT functionality, XIP with RL2 enabled, OTFA, FOTA, Optishare, Smart Layout -
OSPI R5F YES Yes. Example: ospi_flash_dma Read direct, Write indirect, Read/Write commands, DMA for read -
RTI R5F YES No Counter read, timebase selection, comparator setup for Interrupt, DMA requests Capture feature, fast enabling/disabling of events not tested
RESOLVER R5F YES No Angle and Speed Calcution. input Band Pass Filter, Manual Phase Gain Correction and Manual Ideal Sample Selection Mode calculation, Non-Rotational Safety Diagnostic features, Dual motor/Single motor redundant sensing Tuning, Rotational Safety Diagnostic features
SDFM R5F YES yes. Example : sdfm_filter_sync_dmaread Filter data read from CPU, Filter data read with PWM sync, triggered DMA read from the Filter FIFO, ECAP Clock LoopBack -
SOC R5F YES NA Lock/unlock MMRs, clock enable, set Hz, Xbar configuration, SW Warm Reset, Address Translation -
SPINLOCK R5F NA NA Lock, unlock HW spinlock -
UART R5F YES Yes. Example: uart_echo_dma Basic read/write at baud rate 115200, polling, interrupt mode HW flow control not tested, DMA mode not supported
WATCHDOG R5F YES NA Reset mode, Interrupt mode -

Trigonometric Operations

Peripheral Supported CPUs SysConfig Support DMA Supported Key features tested Key features not tested / NOT supported
TMU R5F NO NA TMU Operations, Pipelining, Contex Save Square Root, Division Operations. more than 1 Interrupt Nesting for the contex save is not Supported.

Board Device Drivers

Peripheral Supported CPUs SysConfig Support Key features tested Key features not tested
EEPROM R5F YES Only compiled -
FLASH R5F YES OSPI Flash -
LED R5F YES GPIO -
ETHPHY R5F YES Tested with ethercat_slave_beckhoff_ssc_demo example -
PMIC R5F YES LDO Voltage control -
IOEXPANDER R5F YES IO configurability -

Networking

Module Supported CPUs SysConfig Support OS Support Key features tested Key features not tested
Time-Sensitive Networking(gPTP-IEEE 802.1AS) R5F NO FreeRTOS gPTP IEEE 802.1 AS-2020 compliant gPTP stack, End Nodes and Bridge mode support, YANG data model configuration, IEEE 1722 compliant AVTP Stack Multi-Clock Domain
LwIP R5F YES FreeRTOS TCP/UDP IP networking stack with and without checksum offload enabled, TCP/UDP IP networking stack with server and client functionality, basic Socket APIs, netconn APIs and raw APIs, DHCP, ping, TCP iperf, scatter-gather, DSCP priority mapping Other LwIP features
Ethernet driver (ENET) R5F YES FreeRTOS Ethernet as port using CPSW, MAC loopback and PHY loopback, Layer 2 MAC, Packet Timestamping, CPSW Switch, CPSW EST, interrupt pacing, Policer and Classifier, MDIO Manual Mode, Credit Based Shaper (IEEE 802.1Qav), Strapped PHY (Early Ethernet) RMII, MII mode
ICSS-EMAC R5F YES FreeRTOS Switch and MAC features, Storm Prevention (MAC), Host Statistics, Multicast Filtering Promiscuous Mode
Ether-ring Implementation R5F NO FreeRTOS Duplicate Rejection, Ring termination and Packet Duplication, Latency measurement for different real-time traffic profiles, Performance KPIs N/A

Safety Diagnostic Library

Module Supported CPUs SysConfig Support OS support Key features tested Key features not tested / NOT supported
MCRC R5F NA NORTOS Full CPU, Auto CPU Mode and Semi CPU Auto Mode -
DCC R5F NA NORTOS Single Shot and Continuous modes -
PBIST R5F NA NORTOS Memories supported by MSS PBIST controller. -
ESM R5F NA NORTOS Tested in combination with RTI, DCC -
RTI R5F NA NORTOS WINDOWSIZE_100_PERCENT, WINDOWSIZE_50_PERCENT ,Latency/Propagation timing error(early)(50% window),Latency/Propagation timing error(late)(50% window) -
ECC R5F NA NORTOS ECC of MSS_L2, R5F TCM, MCAN, VIM, ICSSM, TPTC FSS FOTA and OSPI
ECC Bus Safety R5F NA NORTOS AHB, AXI, TPTC -
CCM R5F NA NORTOS CCM Self Test Mode,Error Forcing Mode and Self Test Error Forcing Mode. TMU and RL2 are also validated -
R5F STC(LBIST), Static Register Read R5F NA NORTOS STC of R5F, R5F CPU Static Register Read -
TMU ROM Checksum R5F NA NORTOS ROM checksum for TMU -
Time out Gasket(STOG) R5F NA NORTOS Timeout gasket feature -
Thermal Monitor(VTM) R5F NA NORTOS Over, under and thershold temperature interrupts -
Integrated Example R5F NA FreeRTOS Integrated example with all the SDL modules integrated in to one example. ECC for TPTC, ECC Bus Safety and STC.

Note: SDL is validated only on ControlCard.

PRU IO

Module Supported CPUs SysConfig Support OS Support Key features tested Key features not tested
Empty PRU YES Bare Metal Empty project to get started with PRU firmware development -

Fixed Issues

ID Head Line Module Applicable Releases Applicable Devices Resolution/Comments
PROC_SDL-8519 In ECC for R5F data cache only, double bit test is not supported. SDL 10.01.00 onwards AM263x, AM263Px Fixed the example.
PROC_SDL-8864 D-tag and D-data ECC examples fail in release profile. SDL 10.01.00 onwards AM263x, AM263Px Fixed the example.
PROC_SDL-8866 BTCM ECC example fails in release profile.. SDL 10.01.00 onwards AM263Px Fixed the example.
PROC_SDL-8859 STC example does not support R5FSS0. SDL 10.01.00 onwards AM263Px Moved the example in SBL NULL Bootloader example.
MCUSDK-13341 ECAP: Emulation mode does not work. ECAP 9.02.00 onwards AM263x, AM263Px, AM261x Added halt control API for ECAP in soc.c file and emulation mode in syscfg to be emulation free.
MCUSDK-14051 EQEP: CW CCW example doesn't use polling or interrupt EQEP 10.01.00 onwards AM263x, AM263Px, AM261x Modified example to use unit timer interrupt.
MCUSDK-12354 ADC: Syscfg code generation failed for soc-reference ADC 9.01.00 onwards AM263x, AM263Px, AM261x Update reference monitor number and buffer number
MCUSDK-14332 SDFM soc ctrl syscfg: code generates outside callable functions SDFM 10.00.01 onwards AM263x, AM263Px, AM261x Updated code generation of soc ctrl sdfm module in syscfg.
MCUSDK-12265 SDFM single channel filter sync CPU read example failure for AM263P-LP. ADC 9.00.01 onwards AM263Px New ccs version has updated gel files that configure PLLs in dev boot mode.
MCUSDK-12238 OUTPUTXBAR input sources from CMPSS needs to be renamed ADC 9.00.01 onwards AM263Px OUTPUTXBAR input sources from CMPSS are renamed as CMPSSA/Bx_CTRIPOUTH/L.
MCUSDK-13563 Add IO Expander support in Syscfg SYSCFG 10.00.01 onwards AM263x, AM263Px Added IO Expander support for AM263x and AM263Px in Syscfg.
MCUSDK-13874 Syscfg load json function for flash configuration imports does not work OSPI 10.00.00 onwards AM263x, AM263Px Fix in SysCfg Meta file.
MCUSDK-13109 RTI Interrupt req is Pulse type and not Level type RTI 10.00.00 onwards AM263x, AM263Px, AM261x Updated interrupt type to Pulse
MCUSDK-14371 Incorrect RTI4 Clock Source register RTI 10.00.00 onwards AM263Px Updated RTI4 Clock Source Mux register address
MCUSDK-14133 Missing XBAR instances for RTI, MCAN, and McSPI XBAR 10.00.00 onwards AM263Px Added these instances in SysCfg
MCUSDK-13523 McSPI FIFO not enabled in DMA mode McSPI 10.00.00 onwards AM263Px Added FIFO support in McSPI driver for Read and Write
MCUSDK-14026 RTI5 to RTI 7 Interrupts not getting triggered RTI 10.00.00 onwards AM263Px Incorrect Interrupt numbers in SysCfg meta file
MCUSDK-14516 UART ISR Blocking for long time UART 10.00.00 onwards AM263x, AM263Px, AM261x Removed unwanted timeout loop in UART ISR
MCUSDK-13473 UART uniflash script fails with large images ( > 1MB) SBL 10.00.00 onwards AM263x, AM263Px, AM261x Reference before assignment error in python script
MCUSDK-14150 Flash Reset failure for Rev A board SBL 10.00.00 onwards AM263Px Added support for new Reset logic in Rev A
MCUSDK-13013 OSPI missing ECC_FAIL signal OSPI 09.02.00 onwards AM263Px Added ECC FAIL signal in SysCfg
MCUSDK-13495 Applications with XIP sections more than 1MB fails to boot Flash, SBL 09.02.00 onwards AM263Px SBL Update to accept more than 1MB of data.

Known Issues

ID Head Line Module Reported in release Workaround
MCUSDK-13865 HRPWM Deadband sfo example has 1ns jitter EPWM 10.00.00 onwards -
MCUSDK-13201 HRPWM waveform not generating (in updwon count) when prescaler is non-zero and HRPE is enabled EPWM 10.00.01 onwards None
MCUSDK-13834 EQEP: EQEP frequency measurement example is not working as expected EQEP 10.00.01 onwards None
MCUSDK-14059 CMPSS DE example has Glitch in PWM output CMPSS 10.00.01 onwards None
MCUSDK-13011 Multicore Empty project not working properly FreeRTOS 09.01.00 onwards -
PINDSW-7715 Dual EMAC instance not working with both ports together for icss_emac_lwip example ICSS-EMAC 09.02.00 onwards None
PINDSW-7746 Low iperf values in TCP and UDP ICSS-EMAC 09.02.00 onwards None
PINDSW-8118 Enabling DHCP mode in icss_emac_lwip example causes assert ICSS-EMAC 09.02.00 onwards None
MCUSDK-12756 MbedTLS - Timing side channel attack in RSA private operation exposing plaintext. Mbed-TLS 08.06.00 onwards None
PROC_SDL-8392 In ECC bus safety example, ECC error is not properly cleared at the source. SDL 09.00.00 onwards None
PROC_SDL-8787 ECC TPTC and STC examples are not supported in SDL integrated example. SDL 10.01.00 onwards Use standalone examples.
PROC_SDL-8857 SDL integrated example does not support ECC Bus Safety. SDL 10.01.00 onwards Use standalone example.
PROC_SDL-9148 ECC D-Data fail during release SDL 10.02.00 onwards None
PROC_SDL-9149 ECC D-Tag stuck in System_Init during release R5FSS1-0 SDL 10.02.00 onwards None
PROC_SDL-9150 PBIST Example and Test apps are getting mixed data with bootloader data in R5FSS1-0 SDL 10.02.00 onwards Functionality works and log gets mixed. Disable DPL_Log.
PROC_SDL-9151 CCM Example and Test apps are getting mixed data with bootloader data in R5FSS1-0 SDL 10.02.00 onwards Functionality works and log gets mixed. Disable DPL_Log.
PROC_SDL-9152 R5F Utils Example and Test apps are getting mixed data with bootloader data SDL 10.02.00 onwards Functionality works and log gets mixed. Disable DPL_Log.
PROC_SDL-9153 TOG Example stuck in System_Init during release SDL 10.02.00 onwards None
PROC_SDL-9154 VTM Example stuck in UC2 SDL 10.02.00 onwards None
PROC_SDL-9163 ECC Aggregators FSS FOTA and OSPI SDL 10.02.00 onwards None
PROC_SDL-9179 Redefinition error in MCU_PBIST Sysconfig SDL 10.02.00 onwards Use sdl examples instead of sbl_null to enable MCU_PBIST SYSCFG and test.
MCUSDK-13652 Readelf throws warning while parsing RS note SBL, QSPI 10.00.00 onwards -
MCUSDK-13182 SysCfg unexpectedly changes OSPI Pin OSPI 10.00.00 onwards Lock the OSPI Pins in SysCfg.
MCUSDK-14110 Error building examples in CCS in mac Infra Example build fails in CCS only in MAC Machines Building projects in CCS in MAC machines
MCUSDK-13513 AM263Px: UDP and TCP IPERF TX is unstable with 100Mbps link speed Networking 10.00.00 onwards -
MCUSDK-14473 AM263Px: Multiple chip selects cannot be configured in SysCfg OSPI 10.00.00 onwards -
MCUSDK-14509 AM263x/Am263px/AM261x: 10% Packet drop with UDP iperf in 100M bandwidth in 1Gbps FullDuplex linkspeed Networking 10.00.00 onwards -
MCUSDK-14582 Flash: Incorrect flash name after Loading Flash JSON OSPI 10.00.00 onwards -
MCUSDK-14102 Applications > 1MB not flashing using TI Uniflash tool Uniflash tool 10.00.00 onwards Issues with flashing applications > 1MB in serial session
MCUSDK-14547 XIP Flashing not supported in SBL JTAG Uniflash example SBL 10.00.00 onwards -

Errata

ID Head Line Module SDK Status
i2189 OSPI: Controller PHY Tuning Algorithm OSPI Implemented
i2311 USART: Spurious DMA Interrupts UART Implemented
i2324 No synchronizer present between GCM and GCD status signals Common Implemented
i2345 CPSW: Ethernet Packet corruption occurs if CPDMA fetches a packet which spans across memory banks CPSW Implemented
i2351 OSPI: Controller does not support Continuous Read mode with NAND Flash OSPI Implemented
i2354 SDFM: Two Back-to-Back Writes to SDCPARMx Register Bit Fields CEVT1SEL, CEVT2SEL, and HZEN Within Three SD-Modulator Clock Cycles can Corrupt SDFM State Machine, Resulting in Spurious Comparator Events SDFM Open
i2356 ADC: Interrupts may Stop if INTxCONT (Continue-to-Interrupt Mode) is not Set ADC Implemented
i2375 SDFM: SDFM module event flags (SDIFLG.FLTx_FLG_CEVTx) do not get set again if the comparator event is still active and digital filter path (using SDCOMPxCTL.CEVTxDIGFILTSEL) is being selected SDFM Open
i2383 OSPI: 2-byte address is not supported in PHY DDR mode OSPI Implemented
i2401 CPSW: Host Timestamps Cause CPSW Port to Lock up CPSW Open
i2404 Race condition in mailbox registers resulting in events miss IPC, Mailbox Implemented
i2405 CONTROLSS: Race condition OUTPUT_XBAR and PWM_XBAR resulting in event miss Crossbar Open
i2485 AM263PX: TMU: TCM Memory Corruption on R5SS0_CORE1 and R5SS1_CORE1 when writing to TMU Registers TMU Implemented a workaround Errata : TCM Memory Corruption on R5SS0_CORE1 and R5SS1_CORE1 when writing to TMU Registers
Workaround: Do not use initial bytes (0x40-0x3A0) of ATCM from CPU1 allocation. Initial bytes (0x40-0x3A0 => 868 bytes) of CORE1 TCM are blocked using linker command settings of multi-core application/examples.
Refer TMU 4 Cores Support

Limitations

ID Head Line Module Reported in release Workaround
MCUSDK-13630 Cache should not be enabled at last 32B L2 Bank boundary Cache 10.01.00 Create MPU configurations for last 32B of each L2 Bank with Non Cached attribute

Upgrade and Compatibility Information

How to run FOTA examples on AM263PX-SIP board

One difference between AM263PX-SIP and AM263PX is the in package flash. In SIP board, flash is of Non-RWW in nature whereas, it is of RWW in other case. Example FLSOPSKD Benchmark is made to work out of box for AM263PX board but need some manual changes to make it work on AM263PX-SIP board. Here, to make this example with AM263PX-SIP board, please removed the RUN_XIP_IN_PARALLEL macro.

Changes in FLSOPSKD and FOTAAgent driver

These 2 drivers has been revamped from grounds up and there is an API compatibility break from previous release. On how to use the latest drivers please refer to FLSOPSKD and FOTA Agent.

Compiler Options

Module Affected API Change Additional Remarks
- - - -

SOC Device Drivers

Module Affected API Change Additional Remarks
- - - -

Ethernet and Networking

Module Affected API Change Additional Remarks
- - - -