AM263Px MCU+ SDK
09.01.00
sdl_ecc_bus_safety_soc.h
Go to the documentation of this file.
1
/*
2
* Copyright (c) 2022-23 Texas Instruments Incorporated
3
*
4
* Redistribution and use in source and binary forms, with or without
5
* modification, are permitted provided that the following conditions
6
* are met:
7
*
8
* Redistributions of source code must retain the above copyright
9
* notice, this list of conditions and the following disclaimer.
10
*
11
* Redistributions in binary form must reproduce the above copyright
12
* notice, this list of conditions and the following disclaimer in the
13
* documentation and/or other materials provided with the
14
* distribution.
15
*
16
* Neither the name of Texas Instruments Incorporated nor the names of
17
* its contributors may be used to endorse or promote products derived
18
* from this software without specific prior written permission.
19
*
20
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31
*
32
*/
33
39
#ifndef SDL_MSS_CR5_SOC_H_
40
#define SDL_MSS_CR5_SOC_H_
41
42
/* ========================================================================== */
43
/* Include Files */
44
/* ========================================================================== */
45
46
#include <sdl/include/am263px/sdlr_soc_baseaddress.h>
47
#include <sdl/include/am263px/sdlr_mss_ctrl.h>
48
49
#ifdef _cplusplus
50
extern
"C"
{
51
#endif
52
53
/* ========================================================================== */
54
/* Macros & Typedefs */
55
/* ========================================================================== */
56
#define SDL_ECC_BUS_SAFETY_MSS_BUS_CFG (uint32_t)SDL_MSS_CTRL_U_BASE
57
#define DWORD (0x20U)
58
#define SDL_MSS_CTRL_R5SS0_CORE0_AHB_BASE (0x000000A0U)
59
#define SDL_MSS_CTRL_R5SS1_CORE0_AHB_BASE (0x000000A4U)
60
#define SDL_MSS_CTRL_R5SS0_CORE1_AHB_BASE (0x000000B0U)
61
#define SDL_MSS_CTRL_R5SS1_CORE1_AHB_BASE (0x000000B4U)
62
#define SDL_MSS_CTRL_R5SS0_CORE0_AHB_END (SDL_MSS_CTRL_R5SS0_CORE0_AHB_BASE + SDL_MSS_CTRL_R5SS0_CORE0_AHB_SIZE)
63
#define SDL_MSS_CTRL_R5SS1_CORE0_AHB_END (SDL_MSS_CTRL_R5SS1_CORE0_AHB_BASE + SDL_MSS_CTRL_R5SS1_CORE0_AHB_SIZE)
64
#define SDL_MSS_CTRL_R5SS0_CORE1_AHB_END (SDL_MSS_CTRL_R5SS0_CORE1_AHB_BASE + SDL_MSS_CTRL_R5SS0_CORE1_AHB_SIZE)
65
#define SDL_MSS_CTRL_R5SS1_CORE1_AHB_END (SDL_MSS_CTRL_R5SS1_CORE1_AHB_BASE + SDL_MSS_CTRL_R5SS1_CORE1_AHB_SIZE)
66
67
#define SDL_R5SS0_CORE0_TCMA_U_SIZE (0x000000020)
68
#define SDL_R5SS0_CORE0_TCMB_U_SIZE (0x000000020)
69
#define SDL_MSS_CR5A_TCM_U_BASE (SDL_R5SS0_CORE0_TCMA_U_BASE )
70
#define SDL_MSS_CR5B_TCM_U_BASE (SDL_R5SS0_CORE0_TCMB_U_BASE )
71
#define SDL_MSS_CR5A_TCM_U_END (SDL_R5SS0_CORE0_TCMA_U_BASE + SDL_R5SS0_CORE0_TCMA_U_SIZE)
72
#define SDL_MSS_CR5B_TCM_U_END (SDL_R5SS0_CORE0_TCMB_U_BASE + SDL_R5SS0_CORE0_TCMB_U_SIZE)
73
#define SDL_MBOX_SRAM_U_BASE_END (SDL_MBOX_SRAM_U_BASE+100U)
74
#define SDL_MMC0_U_BASE_END (SDL_MMC0_U_BASE+0X1FFCU-DWORD)
75
#define SDL_CORE_VBUSP_START (0x50800000U)
76
#define SDL_CORE_VBUSP_START_END (SDL_CORE_VBUSP_START+0X1FFCU)
77
#define SDL_PERI_VBUSP_START (0x50200000)
78
#define SDL_PERI_VBUSP_START_END (SDL_PERI_VBUSP_START+0X7FFFFCU)
79
#define SDL_MPU_L2OCRAM_BANK0 (0x40020000U)
80
#define SDL_MPU_L2OCRAM_BANK0_END (0x40020FFFU-DWORD)
81
#define SDL_MPU_L2OCRAM_BANK1 (0x40040000U)
82
#define SDL_MPU_L2OCRAM_BANK1_END (0x40040FFFU-DWORD)
83
#define SDL_MPU_L2OCRAM_BANK2 (0x40060000U)
84
#define SDL_MPU_L2OCRAM_BANK2_END (0x40060FFFU-DWORD)
85
#define SDL_MPU_L2OCRAM_BANK3 (0x40080000U)
86
#define SDL_MPU_L2OCRAM_BANK3_END (0x40080FFFU-DWORD)
87
#define SDL_MSS_QSPI_U_BASE (SDL_QSPI0_U_BASE)
88
#define SDL_MSS_QSPI_U_SIZE (0x000001D8U)
89
#define SDL_MSS_QSPI_U_END (SDL_MSS_QSPI_U_BASE + SDL_MSS_QSPI_U_SIZE)
90
#define SDL_MSS_MCRC_U_BASE (SDL_MCRC0_U_BASE)
91
#define SDL_MSS_MCRC_U_SIZE (0x000001E4U)
92
#define SDL_MSS_MCRC_U_END (SDL_MSS_MCRC_U_BASE + SDL_MSS_MCRC_U_SIZE)
93
#define SDL_MSS_STM_STIM_U_BASE (SDL_STM_STIM_U_BASE)
94
#define SDL_MSS_STM_STIM_U_SIZE (0x00FFFFFFU)
95
#define SDL_MSS_STM_STIM_U_END (SDL_MSS_STM_STIM_U_BASE + SDL_MSS_STM_STIM_U_SIZE)
96
97
/* Macro defines Ecc Bus Safety Nodes in the MSS Subsystem */
98
#define SDL_ECC_BUS_SAFETY_MSS_MBOX 0U
99
#define SDL_ECC_BUS_SAFETY_MSS_TPTC_A0_RD 1U
100
#define SDL_ECC_BUS_SAFETY_MSS_TPTC_A1_RD 2U
101
#define SDL_ECC_BUS_SAFETY_MSS_CR5A_AXI_RD 3U
102
#define SDL_ECC_BUS_SAFETY_MSS_CR5B_AXI_RD 4U
103
#define SDL_ECC_BUS_SAFETY_MSS_CR5C_AXI_RD 5U
104
#define SDL_ECC_BUS_SAFETY_MSS_CR5D_AXI_RD 6U
105
#define SDL_ECC_BUS_SAFETY_MSS_CR5A_AXI_S 7U
106
#define SDL_ECC_BUS_SAFETY_MSS_CR5B_AXI_S 8U
107
#define SDL_ECC_BUS_SAFETY_MSS_CR5C_AXI_S 9U
108
#define SDL_ECC_BUS_SAFETY_MSS_CR5D_AXI_S 10U
109
#define SDL_ECC_BUS_SAFETY_MSS_TPTC_A0_WR 11U
110
#define SDL_ECC_BUS_SAFETY_MSS_TPTC_A1_WR 12U
111
#define SDL_ECC_BUS_SAFETY_MSS_TPTC_B0_WR 13U
112
#define SDL_ECC_BUS_SAFETY_MSS_CR5A_AHB 14U
113
#define SDL_ECC_BUS_SAFETY_MSS_CR5B_AHB 15U
114
#define SDL_ECC_BUS_SAFETY_MSS_CR5C_AHB 16U
115
#define SDL_ECC_BUS_SAFETY_MSS_CR5D_AHB 17U
116
#define SDL_ECC_BUS_SAFETY_MSS_CR5A_AXI_WR 18U
117
#define SDL_ECC_BUS_SAFETY_MSS_CR5B_AXI_WR 19U
118
#define SDL_ECC_BUS_SAFETY_MSS_CR5C_AXI_WR 20U
119
#define SDL_ECC_BUS_SAFETY_MSS_CR5D_AXI_WR 21U
120
#define SDL_ECC_BUS_SAFETY_MSS_MAIN_VBUSP 22U
121
#define SDL_ECC_BUS_SAFETY_MSS_PERI_VBUSP 23U
122
#define SDL_ECC_BUS_SAFETY_MSS_QSPI 24U
123
#define SDL_ECC_BUS_SAFETY_MSS_CPSW 25U
124
#define SDL_ECC_BUS_SAFETY_MSS_MCRC 26U
125
#define SDL_ECC_BUS_SAFETY_MSS_L2_A 27U
126
#define SDL_ECC_BUS_SAFETY_MSS_L2_B 28U
127
#define SDL_ECC_BUS_SAFETY_MSS_L2_C 29U
128
#define SDL_ECC_BUS_SAFETY_MSS_L2_D 30U
129
#define SDL_ECC_BUS_SAFETY_MSS_SCRP 31U
130
#define SDL_ECC_BUS_SAFETY_MSS_DAP 32U
131
#define SDL_ECC_BUS_SAFETY_MSS_MMC 33U
132
#define SDL_ECC_BUS_SAFETY_MSS_SCRP0 35U
133
#define SDL_ECC_BUS_SAFETY_MSS_SCRP1 36U
134
#define SDL_ECC_BUS_SAFETY_ICSSM_PDSP0 37U
135
#define SDL_ECC_BUS_SAFETY_ICSSM_PDSP1 38U
136
#define SDL_ECC_BUS_SAFETY_ICSSM_S 39U
137
#define SDL_ECC_BUS_SAFETY_DAP 40U
138
#define SDL_ECC_BUS_SAFETY_MSS_STM_STIM 41U
139
140
#ifdef _cplusplus
141
}
142
143
#endif
/*extern "C" */
144
145
#endif
146
source
sdl
ecc_bus_safety
v0
soc
am263px
sdl_ecc_bus_safety_soc.h
generated by
1.8.20