AM261x MCU+ SDK  10.00.01
soc_xbar.h
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32  * Name : soc_xbar.h
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34 
35 #ifndef SOC_XBAR_AM261X_H_
36 #define SOC_XBAR_AM261X_H_
37 
38 //*****************************************************************************
39 //
40 // If building with a C++ compiler, make all of the definitions in this header
41 // have a C binding.
42 //
43 //*****************************************************************************
44 #ifdef __cplusplus
45 extern "C"
46 {
47 #endif
48 
58 #include <stdbool.h>
59 #include <stdint.h>
60 #include <drivers/hw_include/hw_types.h>
61 #include <drivers/hw_include/cslr_soc.h>
62 #include <kernel/dpl/DebugP.h>
63 
64 #define CSL_CONTROLSS_INPUTXBAR_STEP (CSL_CONTROLSS_INPUTXBAR_INPUTXBAR1_GSEL - CSL_CONTROLSS_INPUTXBAR_INPUTXBAR0_GSEL)
65 #define CSL_CONTROLSS_PWMXBAR_STEP (CSL_CONTROLSS_PWMXBAR_PWMXBAR1_G0 - CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G0)
66 #define CSL_CONTROLSS_MDLXBAR_STEP (CSL_CONTROLSS_MDLXBAR_MDLXBAR1_G0 - CSL_CONTROLSS_MDLXBAR_MDLXBAR0_G0)
67 #define CSL_CONTROLSS_ICLXBAR_STEP (CSL_CONTROLSS_ICLXBAR_ICLXBAR1_G0 - CSL_CONTROLSS_ICLXBAR_ICLXBAR0_G0)
68 #define CSL_CONTROLSS_INTXBAR_STEP (CSL_CONTROLSS_INTXBAR_INTXBAR1_G0 - CSL_CONTROLSS_INTXBAR_INTXBAR0_G0)
69 #define CSL_CONTROLSS_DMAXBAR_STEP (CSL_CONTROLSS_DMAXBAR_DMAXBAR1_GSEL - CSL_CONTROLSS_DMAXBAR_DMAXBAR0_GSEL)
70 #define CSL_CONTROLSS_OUTPUTXBAR_STEP (CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR1_G0 - CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G0)
71 #define CSL_CONTROLSS_PWMSYNCOUTXBAR_STEP (CSL_CONTROLSS_PWMSYNCOUTXBAR_PWMSYNCOUTXBAR1_G0 - CSL_CONTROLSS_PWMSYNCOUTXBAR_PWMSYNCOUTXBAR0_G0)
72 
83 static inline void
84 SOC_xbarSelectInputXBarInputSource(uint32_t base, uint8_t out, uint8_t group_select, uint8_t group0_muxctl, uint8_t group1_muxctl)
85 {
86  HW_WR_REG32(base + CSL_CONTROLSS_INPUTXBAR_INPUTXBAR0_GSEL + (out * CSL_CONTROLSS_INPUTXBAR_STEP), group_select & CSL_CONTROLSS_INPUTXBAR_INPUTXBAR0_GSEL_GSEL_MASK);
87  HW_WR_REG32(base + CSL_CONTROLSS_INPUTXBAR_INPUTXBAR0_G0 + (out * CSL_CONTROLSS_INPUTXBAR_STEP), group0_muxctl & CSL_CONTROLSS_INPUTXBAR_INPUTXBAR0_G0_SEL_MASK);
88  HW_WR_REG32(base + CSL_CONTROLSS_INPUTXBAR_INPUTXBAR0_G1 + (out * CSL_CONTROLSS_INPUTXBAR_STEP), group1_muxctl & CSL_CONTROLSS_INPUTXBAR_INPUTXBAR0_G1_SEL_MASK);
89 
90 }
91 
103 static inline void
104 SOC_xbarSelectInputXBarInputSource_ext(uint32_t base, uint8_t out, uint8_t group_select, uint8_t group0_muxctl, uint8_t group1_muxctl, uint8_t group2_muxctl)
105 {
106  HW_WR_REG32(base + CSL_CONTROLSS_INPUTXBAR_INPUTXBAR0_GSEL + (out * CSL_CONTROLSS_INPUTXBAR_STEP), group_select & CSL_CONTROLSS_INPUTXBAR_INPUTXBAR0_GSEL_GSEL_MASK);
107  HW_WR_REG32(base + CSL_CONTROLSS_INPUTXBAR_INPUTXBAR0_G0 + (out * CSL_CONTROLSS_INPUTXBAR_STEP), group0_muxctl & CSL_CONTROLSS_INPUTXBAR_INPUTXBAR0_G0_SEL_MASK);
108  HW_WR_REG32(base + CSL_CONTROLSS_INPUTXBAR_INPUTXBAR0_G1 + (out * CSL_CONTROLSS_INPUTXBAR_STEP), group1_muxctl & CSL_CONTROLSS_INPUTXBAR_INPUTXBAR0_G1_SEL_MASK);
109  HW_WR_REG32(base + CSL_CONTROLSS_INPUTXBAR_INPUTXBAR0_G2 + (out * CSL_CONTROLSS_INPUTXBAR_STEP), group1_muxctl & CSL_CONTROLSS_INPUTXBAR_INPUTXBAR0_G2_SEL_MASK);
110 
111 }
112 
120 static inline uint32_t
121 SOC_xbarGetPWMXBarOutputSignalStatus(uint32_t base)
122 {
123  return(HW_RD_REG32(base + CSL_CONTROLSS_PWMXBAR_PWMXBAR_STATUS) & CSL_CONTROLSS_PWMXBAR_PWMXBAR_STATUS_STS_MASK);
124 }
125 
133 static inline void
134 SOC_xbarInvertPWMXBarOutputSignalBeforeLatch(uint32_t base, uint32_t invert_mask)
135 {
136  HW_WR_REG32(base + CSL_CONTROLSS_PWMXBAR_PWMXBAR_FLAGINVERT, invert_mask & CSL_CONTROLSS_PWMXBAR_PWMXBAR_FLAGINVERT_INVERT_MASK);
137 }
138 
146 static inline uint32_t
147 SOC_xbarGetPWMXBarOutputSignalLatchedFlag(uint32_t base)
148 {
149  return(HW_RD_REG32(base + CSL_CONTROLSS_PWMXBAR_PWMXBAR_FLAG));
150 }
151 
159 static inline void
160 SOC_xbarClearPWMXBarOutputSignalLatchedFlag(uint32_t base, uint32_t clr)
161 {
162  HW_WR_REG32(base + CSL_CONTROLSS_PWMXBAR_PWMXBAR_FLAG_CLR, clr);
163 }
164 
181 static inline void
182 SOC_xbarSelectPWMXBarInputSource(uint32_t base, uint8_t out, uint32_t group0_mask, uint32_t group1_mask, uint32_t group2_mask, uint32_t group3_mask, uint32_t group4_mask, uint32_t group5_mask, uint32_t group6_mask, uint32_t group7_mask, uint32_t group8_mask)
183 {
184  HW_WR_REG32(base + out*CSL_CONTROLSS_PWMXBAR_STEP + CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G0, group0_mask & CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G0_SEL_MASK);
185  HW_WR_REG32(base + out*CSL_CONTROLSS_PWMXBAR_STEP + CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G1, group1_mask & CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G1_SEL_MASK);
186  HW_WR_REG32(base + out*CSL_CONTROLSS_PWMXBAR_STEP + CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G2, group2_mask & CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G2_SEL_MASK);
187  HW_WR_REG32(base + out*CSL_CONTROLSS_PWMXBAR_STEP + CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G3, group3_mask & CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G3_SEL_MASK);
188  HW_WR_REG32(base + out*CSL_CONTROLSS_PWMXBAR_STEP + CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G4, group4_mask & CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G4_SEL_MASK);
189  HW_WR_REG32(base + out*CSL_CONTROLSS_PWMXBAR_STEP + CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G5, group5_mask & CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G5_SEL_MASK);
190  HW_WR_REG32(base + out*CSL_CONTROLSS_PWMXBAR_STEP + CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G6, group6_mask & CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G6_SEL_MASK);
191  HW_WR_REG32(base + out*CSL_CONTROLSS_PWMXBAR_STEP + CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G7, group7_mask & CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G7_SEL_MASK);
192  HW_WR_REG32(base + out*CSL_CONTROLSS_PWMXBAR_STEP + CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G8, group8_mask & CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G8_SEL_MASK);
193 }
194 
195 
213 static inline void
214 SOC_xbarSelectPWMXBarInputSource_ext(uint32_t base, uint8_t out, uint32_t group0_mask, uint32_t group1_mask, uint32_t group2_mask, uint32_t group3_mask, uint32_t group4_mask, uint32_t group5_mask, uint32_t group6_mask, uint32_t group7_mask, uint32_t group8_mask, uint32_t group9_mask)
215 {
216  HW_WR_REG32(base + out*CSL_CONTROLSS_PWMXBAR_STEP + CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G0, group0_mask & CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G0_SEL_MASK);
217  HW_WR_REG32(base + out*CSL_CONTROLSS_PWMXBAR_STEP + CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G1, group1_mask & CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G1_SEL_MASK);
218  HW_WR_REG32(base + out*CSL_CONTROLSS_PWMXBAR_STEP + CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G2, group2_mask & CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G2_SEL_MASK);
219  HW_WR_REG32(base + out*CSL_CONTROLSS_PWMXBAR_STEP + CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G3, group3_mask & CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G3_SEL_MASK);
220  HW_WR_REG32(base + out*CSL_CONTROLSS_PWMXBAR_STEP + CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G4, group4_mask & CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G4_SEL_MASK);
221  HW_WR_REG32(base + out*CSL_CONTROLSS_PWMXBAR_STEP + CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G5, group5_mask & CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G5_SEL_MASK);
222  HW_WR_REG32(base + out*CSL_CONTROLSS_PWMXBAR_STEP + CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G6, group6_mask & CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G6_SEL_MASK);
223  HW_WR_REG32(base + out*CSL_CONTROLSS_PWMXBAR_STEP + CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G7, group7_mask & CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G7_SEL_MASK);
224  HW_WR_REG32(base + out*CSL_CONTROLSS_PWMXBAR_STEP + CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G8, group8_mask & CSL_CONTROLSS_PWMXBAR_PWMXBAR0_G8_SEL_MASK);
225 }
226 
237 static inline void
238 SOC_xbarSelectMinimumDeadBandLogicXBarInputSource(uint32_t base, uint8_t out, uint32_t group0_mask, uint32_t group1_mask, uint32_t group2_mask)
239 {
240  //TBD: 32 bit field required?
241  HW_WR_REG32(base + out*CSL_CONTROLSS_MDLXBAR_STEP + CSL_CONTROLSS_MDLXBAR_MDLXBAR0_G0, group0_mask & CSL_CONTROLSS_MDLXBAR_MDLXBAR0_G0_SEL_MASK);
242  HW_WR_REG32(base + out*CSL_CONTROLSS_MDLXBAR_STEP + CSL_CONTROLSS_MDLXBAR_MDLXBAR0_G1, group1_mask & CSL_CONTROLSS_MDLXBAR_MDLXBAR0_G1_SEL_MASK);
243  HW_WR_REG32(base + out*CSL_CONTROLSS_MDLXBAR_STEP + CSL_CONTROLSS_MDLXBAR_MDLXBAR0_G2, group2_mask & CSL_CONTROLSS_MDLXBAR_MDLXBAR0_G2_SEL_MASK);
244 }
245 
256 static inline void
257 SOC_xbarSelectIllegalComboLogicXBarInputSource(uint32_t base, uint8_t out, uint32_t group0_mask, uint32_t group1_mask, uint32_t group2_mask)
258 {
259  //TBD: 32 bit field required?
260  HW_WR_REG32(base + out*CSL_CONTROLSS_ICLXBAR_STEP + CSL_CONTROLSS_ICLXBAR_ICLXBAR0_G0, group0_mask & CSL_CONTROLSS_ICLXBAR_ICLXBAR0_G0_SEL_MASK);
261  HW_WR_REG32(base + out*CSL_CONTROLSS_ICLXBAR_STEP + CSL_CONTROLSS_ICLXBAR_ICLXBAR0_G1, group1_mask & CSL_CONTROLSS_ICLXBAR_ICLXBAR0_G1_SEL_MASK);
262  HW_WR_REG32(base + out*CSL_CONTROLSS_ICLXBAR_STEP + CSL_CONTROLSS_ICLXBAR_ICLXBAR0_G2, group2_mask & CSL_CONTROLSS_ICLXBAR_ICLXBAR0_G2_SEL_MASK);
263 }
264 
279 static inline void
280 SOC_xbarSelectInterruptXBarInputSource(uint32_t base, uint8_t out, uint32_t group0_mask, uint32_t group1_mask, uint32_t group2_mask, uint32_t group3_mask, uint32_t group4_mask, uint32_t group5_mask, uint32_t group6_mask)
281 {
282  //TBD: 32 bit field required?
283  HW_WR_REG32(base + out*CSL_CONTROLSS_INTXBAR_STEP + CSL_CONTROLSS_INTXBAR_INTXBAR0_G0, group0_mask & CSL_CONTROLSS_INTXBAR_INTXBAR0_G0_SEL_MASK);
284  HW_WR_REG32(base + out*CSL_CONTROLSS_INTXBAR_STEP + CSL_CONTROLSS_INTXBAR_INTXBAR0_G1, group1_mask & CSL_CONTROLSS_INTXBAR_INTXBAR0_G1_SEL_MASK);
285  HW_WR_REG32(base + out*CSL_CONTROLSS_INTXBAR_STEP + CSL_CONTROLSS_INTXBAR_INTXBAR0_G2, group2_mask & CSL_CONTROLSS_INTXBAR_INTXBAR0_G2_SEL_MASK);
286  HW_WR_REG32(base + out*CSL_CONTROLSS_INTXBAR_STEP + CSL_CONTROLSS_INTXBAR_INTXBAR0_G3, group3_mask & CSL_CONTROLSS_INTXBAR_INTXBAR0_G3_SEL_MASK);
287  HW_WR_REG32(base + out*CSL_CONTROLSS_INTXBAR_STEP + CSL_CONTROLSS_INTXBAR_INTXBAR0_G4, group4_mask & CSL_CONTROLSS_INTXBAR_INTXBAR0_G4_SEL_MASK);
288  HW_WR_REG32(base + out*CSL_CONTROLSS_INTXBAR_STEP + CSL_CONTROLSS_INTXBAR_INTXBAR0_G5, group5_mask & CSL_CONTROLSS_INTXBAR_INTXBAR0_G5_SEL_MASK);
289  HW_WR_REG32(base + out*CSL_CONTROLSS_INTXBAR_STEP + CSL_CONTROLSS_INTXBAR_INTXBAR0_G6, group6_mask & CSL_CONTROLSS_INTXBAR_INTXBAR0_G6_SEL_MASK);
290 }
291 
292 
310 static inline void
311 SOC_xbarSelectInterruptXBarInputSource_ext(uint32_t base, uint8_t out, uint32_t group0_mask, uint32_t group1_mask, uint32_t group2_mask, uint32_t group3_mask, uint32_t group4_mask, uint32_t group5_mask, uint32_t group6_mask, uint32_t group7_mask, uint32_t group8_mask, uint32_t group9_mask)
312 {
313  //TBD: 32 bit field required?
314  HW_WR_REG32(base + out*CSL_CONTROLSS_INTXBAR_STEP + CSL_CONTROLSS_INTXBAR_INTXBAR0_G0, group0_mask & CSL_CONTROLSS_INTXBAR_INTXBAR0_G0_SEL_MASK);
315  HW_WR_REG32(base + out*CSL_CONTROLSS_INTXBAR_STEP + CSL_CONTROLSS_INTXBAR_INTXBAR0_G1, group1_mask & CSL_CONTROLSS_INTXBAR_INTXBAR0_G1_SEL_MASK);
316  HW_WR_REG32(base + out*CSL_CONTROLSS_INTXBAR_STEP + CSL_CONTROLSS_INTXBAR_INTXBAR0_G2, group2_mask & CSL_CONTROLSS_INTXBAR_INTXBAR0_G2_SEL_MASK);
317  HW_WR_REG32(base + out*CSL_CONTROLSS_INTXBAR_STEP + CSL_CONTROLSS_INTXBAR_INTXBAR0_G3, group3_mask & CSL_CONTROLSS_INTXBAR_INTXBAR0_G3_SEL_MASK);
318  HW_WR_REG32(base + out*CSL_CONTROLSS_INTXBAR_STEP + CSL_CONTROLSS_INTXBAR_INTXBAR0_G4, group4_mask & CSL_CONTROLSS_INTXBAR_INTXBAR0_G4_SEL_MASK);
319  HW_WR_REG32(base + out*CSL_CONTROLSS_INTXBAR_STEP + CSL_CONTROLSS_INTXBAR_INTXBAR0_G5, group5_mask & CSL_CONTROLSS_INTXBAR_INTXBAR0_G5_SEL_MASK);
320  HW_WR_REG32(base + out*CSL_CONTROLSS_INTXBAR_STEP + CSL_CONTROLSS_INTXBAR_INTXBAR0_G6, group6_mask & CSL_CONTROLSS_INTXBAR_INTXBAR0_G6_SEL_MASK);
321  HW_WR_REG32(base + out*CSL_CONTROLSS_INTXBAR_STEP + CSL_CONTROLSS_INTXBAR_INTXBAR0_G7, group7_mask & CSL_CONTROLSS_INTXBAR_INTXBAR0_G7_SEL_MASK);
322 }
323 
338 static inline void
339 SOC_xbarSelectDMAXBarInputSource(uint32_t base, uint8_t out, uint8_t group_select, uint8_t group0_muxctl, uint8_t group1_muxctl, uint8_t group2_muxctl, uint8_t group3_muxctl, uint8_t group4_muxctl, uint8_t group5_muxctl)
340 {
341  HW_WR_REG32(base + out*CSL_CONTROLSS_DMAXBAR_STEP + CSL_CONTROLSS_DMAXBAR_DMAXBAR0_GSEL , group_select & CSL_CONTROLSS_DMAXBAR_DMAXBAR0_GSEL_GSEL_MASK);
342  HW_WR_REG32(base + out*CSL_CONTROLSS_DMAXBAR_STEP + CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G0 , group0_muxctl & CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G0_SEL_MASK);
343  HW_WR_REG32(base + out*CSL_CONTROLSS_DMAXBAR_STEP + CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G1 , group1_muxctl & CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G1_SEL_MASK);
344  HW_WR_REG32(base + out*CSL_CONTROLSS_DMAXBAR_STEP + CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G2 , group2_muxctl & CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G2_SEL_MASK);
345  HW_WR_REG32(base + out*CSL_CONTROLSS_DMAXBAR_STEP + CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G3 , group3_muxctl & CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G3_SEL_MASK);
346  HW_WR_REG32(base + out*CSL_CONTROLSS_DMAXBAR_STEP + CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G4 , group4_muxctl & CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G4_SEL_MASK);
347  HW_WR_REG32(base + out*CSL_CONTROLSS_DMAXBAR_STEP + CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G5 , group5_muxctl & CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G5_SEL_MASK);
348 
349 }
350 
351 
367 static inline void
368 SOC_xbarSelectDMAXBarInputSource_ext(uint32_t base, uint8_t out, uint8_t group_select, uint8_t group0_muxctl, uint8_t group1_muxctl, uint8_t group2_muxctl, uint8_t group3_muxctl, uint8_t group4_muxctl, uint8_t group5_muxctl, uint8_t group6_muxctl)
369 {
370  HW_WR_REG32(base + out*CSL_CONTROLSS_DMAXBAR_STEP + CSL_CONTROLSS_DMAXBAR_DMAXBAR0_GSEL , group_select & CSL_CONTROLSS_DMAXBAR_DMAXBAR0_GSEL_GSEL_MASK);
371  HW_WR_REG32(base + out*CSL_CONTROLSS_DMAXBAR_STEP + CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G0 , group0_muxctl & CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G0_SEL_MASK);
372  HW_WR_REG32(base + out*CSL_CONTROLSS_DMAXBAR_STEP + CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G1 , group1_muxctl & CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G1_SEL_MASK);
373  HW_WR_REG32(base + out*CSL_CONTROLSS_DMAXBAR_STEP + CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G2 , group2_muxctl & CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G2_SEL_MASK);
374  HW_WR_REG32(base + out*CSL_CONTROLSS_DMAXBAR_STEP + CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G3 , group3_muxctl & CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G3_SEL_MASK);
375  HW_WR_REG32(base + out*CSL_CONTROLSS_DMAXBAR_STEP + CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G4 , group4_muxctl & CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G4_SEL_MASK);
376  HW_WR_REG32(base + out*CSL_CONTROLSS_DMAXBAR_STEP + CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G5 , group5_muxctl & CSL_CONTROLSS_DMAXBAR_DMAXBAR0_G5_SEL_MASK);
377 
378 }
379 
387 static inline uint32_t
388 SOC_xbarGetOutputXBarOutputSignalStatus(uint32_t base)
389 {
390  return(HW_RD_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_STATUS)& CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_STATUS_STS_MASK);
391 }
392 
400 static inline void
401 SOC_xbarInvertOutputXBarOutputSignalBeforeLatch(uint32_t base, uint32_t invert)
402 {
403  HW_WR_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_FLAGINVERT, invert & CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_FLAGINVERT_INVERT_MASK);
404 }
405 
413 static inline uint32_t
414 SOC_xbarGetOutputXBarOutputSignalLatchedFlag(uint32_t base)
415 {
416  return(HW_RD_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_FLAG));
417 }
418 
426 static inline void
427 SOC_xbarClearOutputXBarOutputSignalLatchedFlag(uint32_t base, uint32_t clr)
428 {
429  HW_WR_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_FLAG_CLR, clr);
430 }
431 
439 static inline void
440 SOC_xbarForceOutputXBarOutputSignalLatchedFlag(uint32_t base, uint32_t force)
441 {
442  HW_WR_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_FLAGFORCE, force & CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_FLAGFORCE_FRC_MASK);
443 }
444 
452 static inline void
453 SOC_xbarSelectLatchOutputXBarOutputSignal(uint32_t base, uint32_t latchselect)
454 {
455  HW_WR_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_OUTLATCH, latchselect & CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_OUTLATCH_LATCHSEL_MASK);
456 }
457 
465 static inline void
466 SOC_xbarSelectStretchedPulseOutputXBarOutputSignal(uint32_t base, uint32_t stretchselect)
467 {
468  HW_WR_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_OUTSTRETCH, stretchselect & CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_OUTSTRETCH_STRETCHSEL_MASK);
469 }
470 
478 static inline void
479 SOC_xbarSelectStretchedPulseLengthOutputXBarOutputSignal(uint32_t base, uint32_t lengthselect)
480 {
481  HW_WR_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_OUTLENGTH, lengthselect & CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_OUTLENGTH_LENGTHSEL_MASK);
482 }
483 
491 static inline void
492 SOC_xbarInvertOutputXBarOutputSignal(uint32_t base, uint32_t invertout)
493 {
494  HW_WR_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_OUTINVERT, invertout & CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_OUTINVERT_OUTINVERT_MASK);
495 }
496 
515 static inline void
516 SOC_xbarSelectOutputXBarInputSource(uint32_t base, uint8_t out, uint32_t group0_mask, uint32_t group1_mask, uint32_t group2_mask, uint32_t group3_mask, uint32_t group4_mask, uint32_t group5_mask, uint32_t group6_mask, uint32_t group7_mask, uint32_t group8_mask, uint32_t group9_mask, uint32_t group10_mask)
517 {
518  HW_WR_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G0 + out * CSL_CONTROLSS_OUTPUTXBAR_STEP, group0_mask & CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G0_SEL_MASK);
519  HW_WR_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G1 + out * CSL_CONTROLSS_OUTPUTXBAR_STEP, group1_mask & CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G1_SEL_MASK);
520  HW_WR_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G2 + out * CSL_CONTROLSS_OUTPUTXBAR_STEP, group2_mask & CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G2_SEL_MASK);
521  HW_WR_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G3 + out * CSL_CONTROLSS_OUTPUTXBAR_STEP, group3_mask & CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G3_SEL_MASK);
522  HW_WR_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G4 + out * CSL_CONTROLSS_OUTPUTXBAR_STEP, group4_mask & CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G4_SEL_MASK);
523  HW_WR_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G5 + out * CSL_CONTROLSS_OUTPUTXBAR_STEP, group5_mask & CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G5_SEL_MASK);
524  HW_WR_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G6 + out * CSL_CONTROLSS_OUTPUTXBAR_STEP, group6_mask & CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G6_SEL_MASK);
525  HW_WR_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G7 + out * CSL_CONTROLSS_OUTPUTXBAR_STEP, group7_mask & CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G7_SEL_MASK);
526  HW_WR_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G8 + out * CSL_CONTROLSS_OUTPUTXBAR_STEP, group8_mask & CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G8_SEL_MASK);
527  HW_WR_REG32(base + CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G9 + out * CSL_CONTROLSS_OUTPUTXBAR_STEP, group9_mask & CSL_CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G9_SEL_MASK);
528 }
529 
530 
539 static inline void
540 SOC_xbarSelectPWMSyncOutXBarInput(uint32_t base, uint8_t out, uint32_t input)
541 {
542  //TBD: 32 bit field for selecting 32 inputs
543  HW_WR_REG32(base + CSL_CONTROLSS_PWMSYNCOUTXBAR_PWMSYNCOUTXBAR0_G0 + out * CSL_CONTROLSS_PWMSYNCOUTXBAR_STEP, input & CSL_CONTROLSS_PWMSYNCOUTXBAR_PWMSYNCOUTXBAR0_G0_SEL_MASK);
544 }
545 
546 
556 static inline void
557 SOC_xbarSelectPWMSyncOutXBarInput_ext(uint32_t base, uint8_t out, uint32_t group0_mask, uint32_t group1_mask)
558 {
559  //TBD: 32 bit field for selecting 32 inputs
560  HW_WR_REG32(base + CSL_CONTROLSS_PWMSYNCOUTXBAR_PWMSYNCOUTXBAR0_G0 + out * CSL_CONTROLSS_PWMSYNCOUTXBAR_STEP, group0_mask & CSL_CONTROLSS_PWMSYNCOUTXBAR_PWMSYNCOUTXBAR0_G0_SEL_MASK);
561  HW_WR_REG32(base + CSL_CONTROLSS_PWMSYNCOUTXBAR_PWMSYNCOUTXBAR0_G1 + out * CSL_CONTROLSS_PWMSYNCOUTXBAR_STEP, group1_mask & CSL_CONTROLSS_PWMSYNCOUTXBAR_PWMSYNCOUTXBAR0_G1_SEL_MASK);
562 }
563 
564 
573 static inline void
574 SOC_xbarSelectEdmaTrigXbarInputSource(uint32_t base, uint8_t out, uint8_t mux_control)
575 {
576  HW_WR_REG32(base + CSL_EDMA_TRIG_XBAR_MUXCNTL(out), (CSL_EDMA_TRIG_XBAR_MUXCNTL_INT_ENABLE_MASK) | (mux_control & CSL_EDMA_TRIG_XBAR_MUXCNTL_ENABLE_MASK));
577 }
578 
587 static inline void
588 SOC_xbarSelectGpioIntrXbarInputSource(uint32_t base, uint8_t out, uint8_t mux_control)
589 {
590  HW_WR_REG32(base + CSL_GPIO_INTR_XBAR_MUXCNTL(out), (CSL_GPIO_INTR_XBAR_MUXCNTL_INT_ENABLE_MASK) | (mux_control & CSL_GPIO_INTR_XBAR_MUXCNTL_ENABLE_MASK));
591 }
592 
601 static inline void
602 SOC_xbarSelectIcssmIntrXbarInputSource(uint32_t base, uint8_t out, uint8_t mux_control)
603 {
604  HW_WR_REG32(base + CSL_ICSSM_INTR_XBAR_MUXCNTL(out), (CSL_ICSSM_INTR_XBAR_MUXCNTL_INT_ENABLE_MASK) | (mux_control & CSL_ICSSM_INTR_XBAR_MUXCNTL_ENABLE_MASK));
605 }
606 
615 static inline void
616 SOC_xbarSelectTimesyncXbar0InputSource(uint32_t base, uint8_t out, uint8_t mux_control)
617 {
618  HW_WR_REG32(base + CSL_SOC_TIMESYNC_XBAR0_MUXCNTL(out), (CSL_SOC_TIMESYNC_XBAR0_MUXCNTL_INT_ENABLE_MASK) | (mux_control & CSL_SOC_TIMESYNC_XBAR0_MUXCNTL_ENABLE_MASK));
619 }
620 
629 static inline void
630 SOC_xbarSelectTimesyncXbar1InputSource(uint32_t base, uint8_t out, uint8_t mux_control)
631 {
632  HW_WR_REG32(base + CSL_SOC_TIMESYNC_XBAR1_MUXCNTL(out), (CSL_SOC_TIMESYNC_XBAR1_MUXCNTL_INT_ENABLE_MASK) | (mux_control & CSL_SOC_TIMESYNC_XBAR1_MUXCNTL_ENABLE_MASK));
633 }
634 
637 #ifdef __cplusplus
638 }
639 #endif
640 
641 #endif // SOC_XBAR_AM261X_H_
SOC_xbarSelectPWMSyncOutXBarInput_ext
static void SOC_xbarSelectPWMSyncOutXBarInput_ext(uint32_t base, uint8_t out, uint32_t group0_mask, uint32_t group1_mask)
Trip & Sync xbar: API to select input sources of PWM Syncout XBar.
Definition: soc_xbar.h:557
CSL_CONTROLSS_PWMSYNCOUTXBAR_STEP
#define CSL_CONTROLSS_PWMSYNCOUTXBAR_STEP
Definition: soc_xbar.h:71
SOC_xbarSelectEdmaTrigXbarInputSource
static void SOC_xbarSelectEdmaTrigXbarInputSource(uint32_t base, uint8_t out, uint8_t mux_control)
SoC level xbars: API to select input source of EDMA Trigger XBar.
Definition: soc_xbar.h:574
SOC_xbarInvertOutputXBarOutputSignalBeforeLatch
static void SOC_xbarInvertOutputXBarOutputSignalBeforeLatch(uint32_t base, uint32_t invert)
Trip & Sync xbar: API to configure inversion of output signal status flag (latched) of Output XBars.
Definition: soc_xbar.h:401
SOC_xbarSelectInterruptXBarInputSource
static void SOC_xbarSelectInterruptXBarInputSource(uint32_t base, uint8_t out, uint32_t group0_mask, uint32_t group1_mask, uint32_t group2_mask, uint32_t group3_mask, uint32_t group4_mask, uint32_t group5_mask, uint32_t group6_mask)
Trip & Sync xbar: API to select input sources of Interrupt XBar.
Definition: soc_xbar.h:280
SOC_xbarSelectMinimumDeadBandLogicXBarInputSource
static void SOC_xbarSelectMinimumDeadBandLogicXBarInputSource(uint32_t base, uint8_t out, uint32_t group0_mask, uint32_t group1_mask, uint32_t group2_mask)
Trip & Sync xbar: API to select input sources of MDL XBar.
Definition: soc_xbar.h:238
SOC_xbarSelectInterruptXBarInputSource_ext
static void SOC_xbarSelectInterruptXBarInputSource_ext(uint32_t base, uint8_t out, uint32_t group0_mask, uint32_t group1_mask, uint32_t group2_mask, uint32_t group3_mask, uint32_t group4_mask, uint32_t group5_mask, uint32_t group6_mask, uint32_t group7_mask, uint32_t group8_mask, uint32_t group9_mask)
Trip & Sync xbar: API to select input sources of Interrupt XBar.
Definition: soc_xbar.h:311
SOC_xbarSelectPWMSyncOutXBarInput
static void SOC_xbarSelectPWMSyncOutXBarInput(uint32_t base, uint8_t out, uint32_t input)
Trip & Sync xbar: API to select input sources of PWM Syncout XBar.
Definition: soc_xbar.h:540
CSL_CONTROLSS_INTXBAR_STEP
#define CSL_CONTROLSS_INTXBAR_STEP
Definition: soc_xbar.h:68
SOC_xbarGetOutputXBarOutputSignalLatchedFlag
static uint32_t SOC_xbarGetOutputXBarOutputSignalLatchedFlag(uint32_t base)
Trip & Sync xbar: API to read latched output signal status of all Output XBars.
Definition: soc_xbar.h:414
SOC_xbarSelectInputXBarInputSource_ext
static void SOC_xbarSelectInputXBarInputSource_ext(uint32_t base, uint8_t out, uint8_t group_select, uint8_t group0_muxctl, uint8_t group1_muxctl, uint8_t group2_muxctl)
Trip & Sync xbar: API to select input source of Input XBar.
Definition: soc_xbar.h:104
CSL_CONTROLSS_OUTPUTXBAR_STEP
#define CSL_CONTROLSS_OUTPUTXBAR_STEP
Definition: soc_xbar.h:70
SOC_xbarSelectStretchedPulseLengthOutputXBarOutputSignal
static void SOC_xbarSelectStretchedPulseLengthOutputXBarOutputSignal(uint32_t base, uint32_t lengthselect)
Trip & Sync xbar: API to configure pulse streching length of output of Output XBars.
Definition: soc_xbar.h:479
SOC_xbarSelectGpioIntrXbarInputSource
static void SOC_xbarSelectGpioIntrXbarInputSource(uint32_t base, uint8_t out, uint8_t mux_control)
SoC level xbars: API to select input source of GPIO Interrupt XBar.
Definition: soc_xbar.h:588
SOC_xbarSelectIllegalComboLogicXBarInputSource
static void SOC_xbarSelectIllegalComboLogicXBarInputSource(uint32_t base, uint8_t out, uint32_t group0_mask, uint32_t group1_mask, uint32_t group2_mask)
Trip & Sync xbar: API to select input sources of ICL XBar.
Definition: soc_xbar.h:257
SOC_xbarSelectLatchOutputXBarOutputSignal
static void SOC_xbarSelectLatchOutputXBarOutputSignal(uint32_t base, uint32_t latchselect)
Trip & Sync xbar: API to select output of Output XBars.
Definition: soc_xbar.h:453
CSL_CONTROLSS_PWMXBAR_STEP
#define CSL_CONTROLSS_PWMXBAR_STEP
Definition: soc_xbar.h:65
CSL_CONTROLSS_MDLXBAR_STEP
#define CSL_CONTROLSS_MDLXBAR_STEP
Definition: soc_xbar.h:66
SOC_xbarInvertOutputXBarOutputSignal
static void SOC_xbarInvertOutputXBarOutputSignal(uint32_t base, uint32_t invertout)
Trip & Sync xbar: API to configure inversion of output signal of Output XBars.
Definition: soc_xbar.h:492
CSL_CONTROLSS_DMAXBAR_STEP
#define CSL_CONTROLSS_DMAXBAR_STEP
Definition: soc_xbar.h:69
SOC_xbarClearOutputXBarOutputSignalLatchedFlag
static void SOC_xbarClearOutputXBarOutputSignalLatchedFlag(uint32_t base, uint32_t clr)
Trip & Sync xbar: API to clear output signal status flag (latched) of Output XBars.
Definition: soc_xbar.h:427
SOC_xbarSelectTimesyncXbar0InputSource
static void SOC_xbarSelectTimesyncXbar0InputSource(uint32_t base, uint8_t out, uint8_t mux_control)
SoC level xbars: API to select input source of TimeSync XBar0.
Definition: soc_xbar.h:616
SOC_xbarSelectTimesyncXbar1InputSource
static void SOC_xbarSelectTimesyncXbar1InputSource(uint32_t base, uint8_t out, uint8_t mux_control)
SoC level xbars: API to select input source of TimeSync XBar1.
Definition: soc_xbar.h:630
SOC_xbarSelectPWMXBarInputSource
static void SOC_xbarSelectPWMXBarInputSource(uint32_t base, uint8_t out, uint32_t group0_mask, uint32_t group1_mask, uint32_t group2_mask, uint32_t group3_mask, uint32_t group4_mask, uint32_t group5_mask, uint32_t group6_mask, uint32_t group7_mask, uint32_t group8_mask)
Trip & Sync xbar: API to select input sources of PWM XBar.
Definition: soc_xbar.h:182
SOC_xbarSelectInputXBarInputSource
static void SOC_xbarSelectInputXBarInputSource(uint32_t base, uint8_t out, uint8_t group_select, uint8_t group0_muxctl, uint8_t group1_muxctl)
Trip & Sync xbar: API to select input source of Input XBar.
Definition: soc_xbar.h:84
SOC_xbarSelectOutputXBarInputSource
static void SOC_xbarSelectOutputXBarInputSource(uint32_t base, uint8_t out, uint32_t group0_mask, uint32_t group1_mask, uint32_t group2_mask, uint32_t group3_mask, uint32_t group4_mask, uint32_t group5_mask, uint32_t group6_mask, uint32_t group7_mask, uint32_t group8_mask, uint32_t group9_mask, uint32_t group10_mask)
Trip & Sync xbar: API to select input sources of Output XBar.
Definition: soc_xbar.h:516
SOC_xbarInvertPWMXBarOutputSignalBeforeLatch
static void SOC_xbarInvertPWMXBarOutputSignalBeforeLatch(uint32_t base, uint32_t invert_mask)
Trip & Sync xbar: API to configure inversion of output signal status flag (latched) of PWM XBars.
Definition: soc_xbar.h:134
DebugP.h
SOC_xbarSelectDMAXBarInputSource
static void SOC_xbarSelectDMAXBarInputSource(uint32_t base, uint8_t out, uint8_t group_select, uint8_t group0_muxctl, uint8_t group1_muxctl, uint8_t group2_muxctl, uint8_t group3_muxctl, uint8_t group4_muxctl, uint8_t group5_muxctl)
Trip & Sync xbar: API to select input source of DMA XBar.
Definition: soc_xbar.h:339
CSL_CONTROLSS_ICLXBAR_STEP
#define CSL_CONTROLSS_ICLXBAR_STEP
Definition: soc_xbar.h:67
SOC_xbarSelectPWMXBarInputSource_ext
static void SOC_xbarSelectPWMXBarInputSource_ext(uint32_t base, uint8_t out, uint32_t group0_mask, uint32_t group1_mask, uint32_t group2_mask, uint32_t group3_mask, uint32_t group4_mask, uint32_t group5_mask, uint32_t group6_mask, uint32_t group7_mask, uint32_t group8_mask, uint32_t group9_mask)
Trip & Sync xbar: API to select input sources of PWM XBar.
Definition: soc_xbar.h:214
SOC_xbarGetOutputXBarOutputSignalStatus
static uint32_t SOC_xbarGetOutputXBarOutputSignalStatus(uint32_t base)
Trip & Sync xbar: API to read raw output signal status of all Output XBars.
Definition: soc_xbar.h:388
SOC_xbarForceOutputXBarOutputSignalLatchedFlag
static void SOC_xbarForceOutputXBarOutputSignalLatchedFlag(uint32_t base, uint32_t force)
Trip & Sync xbar: API to force output signal status flag (latched) of Output XBars.
Definition: soc_xbar.h:440
SOC_xbarSelectStretchedPulseOutputXBarOutputSignal
static void SOC_xbarSelectStretchedPulseOutputXBarOutputSignal(uint32_t base, uint32_t stretchselect)
Trip & Sync xbar: API to enable pulse stretching of output of Output XBars.
Definition: soc_xbar.h:466
SOC_xbarSelectDMAXBarInputSource_ext
static void SOC_xbarSelectDMAXBarInputSource_ext(uint32_t base, uint8_t out, uint8_t group_select, uint8_t group0_muxctl, uint8_t group1_muxctl, uint8_t group2_muxctl, uint8_t group3_muxctl, uint8_t group4_muxctl, uint8_t group5_muxctl, uint8_t group6_muxctl)
Trip & Sync xbar: API to select input source of DMA XBar.
Definition: soc_xbar.h:368
SOC_xbarGetPWMXBarOutputSignalStatus
static uint32_t SOC_xbarGetPWMXBarOutputSignalStatus(uint32_t base)
Trip & Sync xbar: API to read raw output signal status of all PWM XBars.
Definition: soc_xbar.h:121
SOC_xbarClearPWMXBarOutputSignalLatchedFlag
static void SOC_xbarClearPWMXBarOutputSignalLatchedFlag(uint32_t base, uint32_t clr)
Trip & Sync xbar: API to clear output signal status flag (latched) of PWM XBars.
Definition: soc_xbar.h:160
CSL_CONTROLSS_INPUTXBAR_STEP
#define CSL_CONTROLSS_INPUTXBAR_STEP
Definition: soc_xbar.h:64
SOC_xbarSelectIcssmIntrXbarInputSource
static void SOC_xbarSelectIcssmIntrXbarInputSource(uint32_t base, uint8_t out, uint8_t mux_control)
SoC level xbars: API to select input source of ICSSM Interrupt XBar.
Definition: soc_xbar.h:602
SOC_xbarGetPWMXBarOutputSignalLatchedFlag
static uint32_t SOC_xbarGetPWMXBarOutputSignalLatchedFlag(uint32_t base)
Trip & Sync xbar: API to read latched output signal status of all PWM XBars.
Definition: soc_xbar.h:147