soc_rcm.h

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/*
 *  Copyright (C) 2021 Texas Instruments Incorporated
 *
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 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
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 *    distribution.
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 *    from this software without specific prior written permission.
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 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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 */
 
#ifndef SOC_RCM_AM261X_H_
#define SOC_RCM_AM261X_H_
 
#include <stdint.h>
 
#ifdef __cplusplus
extern "C"
{
#endif
 
#include <kernel/dpl/SystemP.h>
 
#define SOC_RCM_FREQ_MHZ2HZ(x)          ((x) * 1000 * 1000)
#define SOC_RCM_FREQ_HZ2MHZ(x)          ((x) / (1000 * 1000))
 
#define SOC_RCM_R5_FREQ_400MHZ          (0x0U)
#define SOC_RCM_R5_FREQ_500MHZ          (0x1U)
 
typedef enum SOC_WarmResetCause_e
{
    SOC_WarmResetCause_POWER_ON_RESET = 0x41U,
    SOC_WarmResetCause_MSS_WDT0 = 0x42U,
    SOC_WarmResetCause_MSS_WDT1 = 0x44U,
    SOC_WarmResetCause_MSS_WDT2 = 0x48U,
    SOC_WarmResetCause_MSS_WDT3 = 0x50U,
    SOC_WarmResetCause_TOP_RCM_WARM_RESET_REQ = 0x60U,
    SOC_WarmResetCause_EXT_PAD_RESET = 0x40U,
    SOC_WarmResetCause_HSM_WDT = 0xC0U,
    SOC_WarmResetCause_DBG_RESET = 0x140U,
    SOC_WarmResetCause_TEMP_SENSOR0_RESET = 0x240U,
    SOC_WarmResetCause_TEMP_SENSOR1_RESET = 0x440U,
 
}SOC_WarmResetCause;
typedef enum SOC_WarmResetSource_e
{
    SOC_WarmResetSource_PAD_BYPASS = CSL_TOP_RCM_WARM_RESET_CONFIG_PAD_BYPASS_MASK,
    SOC_WarmResetSource_DEBUGSS = CSL_TOP_RCM_WARM_RESET_CONFIG_DEBUGSS_RST_EN_MASK,
    SOC_WarmResetSource_TSENSE0 = CSL_TOP_RCM_WARM_RESET_CONFIG_TSENSE0_RST_EN_MASK,
    SOC_WarmResetSource_TSENSE1 = CSL_TOP_RCM_WARM_RESET_CONFIG_TSENSE1_RST_EN_MASK,
    SOC_WarmResetSource_WDOG0 = CSL_TOP_RCM_WARM_RESET_CONFIG_WDOG0_RST_EN_MASK,
    SOC_WarmResetSource_WDOG1 = CSL_TOP_RCM_WARM_RESET_CONFIG_WDOG1_RST_EN_MASK,
 
}SOC_WarmResetSource;
typedef enum SOC_RcmWarm_ResetTime123_e
{
    SOC_WARM_RESET_PAD_TIME_500NS = 0U,
    SOC_WARM_RESET_PAD_TIME_1US,
    SOC_WARM_RESET_PAD_TIME_2US,
    SOC_WARM_RESET_PAD_TIME_4US,
    SOC_WARM_RESET_PAD_TIME_8US,
    SOC_WARM_RESET_PAD_TIME_16US,
    SOC_WARM_RESET_PAD_TIME_32US,
    SOC_WARM_RESET_PAD_TIME_64US,
    SOC_WARM_RESET_PAD_TIME_128US,
    SOC_WARM_RESET_PAD_TIME_256US,
    SOC_WARM_RESET_PAD_TIME_512US,
    SOC_WARM_RESET_PAD_TIME_1024US,
    SOC_WARM_RESET_PAD_TIME_2048US,
    SOC_WARM_RESET_PAD_TIME_4096US,
    SOC_WARM_RESET_PAD_TIME_8192US,
    SOC_WARM_RESET_PAD_TIME_16384US,
 
} SOC_RcmWarm_ResetTime123;
typedef enum SOC_RcmResetCause_e
{
    SOC_RcmResetCause_POWER_ON_RESET = 0x0U,
    SOC_RcmResetCause_WARM_RESET = 0x1U,
    SOC_RcmResetCause_STC_RESET = 0x2U,
    SOC_RcmResetCause_MMR_CPU0_VIM0_RESET = 0x3U,
    SOC_RcmResetCause_MMR_CPU1_VIM1_RESET = 0x4U,
    SOC_RcmResetCause_MMR_CPU0_RESET = 0x5U,
    SOC_RcmResetCause_MMR_CPU1_RESET = 0x6U,
    SOC_RcmResetCause_DBG_CPU0_RESET = 0x7U,
    SOC_RcmResetCause_DBG_CPU1_RESET = 0x8U,
    SOC_RcmResetCause_FSM_TRIGGER_RESET = 0x9U,
    SOC_RcmResetCause_POR_RST_CTRL0 = 0xAU,
    SOC_RcmResetCause_RST_CAUSE_UNKNOWN = 0xBU,
 
}SOC_RcmResetCause;
typedef enum SOC_Rcmr5fssNum_e
{
    r5fss0 = 0x0U,
    r5fss1 = 0x1U,
}SOC_Rcmr5fssNum;
typedef enum SOC_RcmPeripheralId_e
{
    SOC_RcmPeripheralId_MCAN0,
    SOC_RcmPeripheralId_MCAN1,
    SOC_RcmPeripheralId_OSPI0,
    SOC_RcmPeripheralId_OSPI1,
    SOC_RcmPeripheralId_RTI0,
    SOC_RcmPeripheralId_RTI1,
    SOC_RcmPeripheralId_RTI2,
    SOC_RcmPeripheralId_RTI3,
    SOC_RcmPeripheralId_WDT0,
    SOC_RcmPeripheralId_WDT1,
    SOC_RcmPeripheralId_MCSPI0,
    SOC_RcmPeripheralId_MCSPI1,
    SOC_RcmPeripheralId_MCSPI2,
    SOC_RcmPeripheralId_MCSPI3,
    SOC_RcmPeripheralId_MMC0,
    SOC_RcmPeripheralId_ICSSM0_CORE,
    SOC_RcmPeripheralId_ICSSM0_UART0,
    SOC_RcmPeripheralId_ICSSM1_CORE,
    SOC_RcmPeripheralId_ICSSM1_UART0,
    SOC_RcmPeripheralId_CPTS,
    SOC_RcmPeripheralId_GPMC,
    SOC_RcmPeripheralId_CONTROLSS_PLL,
    SOC_RcmPeripheralId_I2C,
    SOC_RcmPeripheralId_LIN0_UART0,
    SOC_RcmPeripheralId_LIN1_UART1,
    SOC_RcmPeripheralId_LIN2_UART2,
    SOC_RcmPeripheralId_LIN3_UART3,
}SOC_RcmPeripheralId;
typedef enum SOC_RcmPeripheralClockSource_e
{
    SOC_RcmPeripheralClockSource_XTALCLK,
    SOC_RcmPeripheralClockSource_SYS_CLK,
    SOC_RcmPeripheralClockSource_WUCPUCLK,
    SOC_RcmPeripheralClockSource_EXT_REFCLK,
    SOC_RcmPeripheralClockSource_RCCLK10M,
    SOC_RcmPeripheralClockSource_RCCLK32K,
    SOC_RcmPeripheralClockSource_CTPS_GENF0,
    SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT0,
    SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT1,
    SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT2,
    SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT3,
    SOC_RcmPeripheralClockSource_DPLL_ETH_HSDIV0_CLKOUT0,
    SOC_RcmPeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT0,
    SOC_RcmPeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT2,
} SOC_RcmPeripheralClockSource;
typedef enum SOC_RcmPllFoutFreqId_e
{
    RCM_PLL_FOUT_FREQID_CLK_500MHZ,
    RCM_PLL_FOUT_FREQID_CLK_900MHZ,
    RCM_PLL_FOUT_FREQID_CLK_960MHZ,
    RCM_PLL_FOUT_FREQID_CLK_2000MHZ,
} SOC_RcmPllFoutFreqId;
typedef enum SOC_RcmXtalFreqId_e
{
    RCM_XTAL_FREQID_CLK_25MHZ,
} SOC_RcmXtalFreqId;
 
typedef enum SOC_RcmPllId_e
{
    RCM_PLLID_CORE,
    RCM_PLLID_ETH,
    RCM_PLLID_PER,
    RCM_PLLID_XTALCLK,
    RCM_PLLID_WUCPUCLK,
    RCM_PLLID_RCCLK32K,
    RCM_PLLID_RCCLK10M,
    RCM_PLLID_EXTREFCLK,
} SOC_RcmPllId;
typedef enum SOC_RcmPllHSDIVOutId_e
{
    RCM_PLLHSDIV_OUT_0,
    RCM_PLLHSDIV_OUT_1,
    RCM_PLLHSDIV_OUT_2,
    RCM_PLLHSDIV_OUT_3,
    RCM_PLLHSDIV_OUT_NONE,
} SOC_RcmPllHSDIVOutId;
typedef struct SOC_RcmClkSrcInfo_s
{
    SOC_RcmPllId pllId;
    SOC_RcmPllHSDIVOutId hsDivOut;
} SOC_RcmClkSrcInfo;
 
typedef struct SOC_RcmXTALInfo_s
{
    uint32_t Finp;
    bool     div2flag;
} SOC_RcmXTALInfo;
 
typedef struct SOC_RcmADPLLJConfig_s
{
    uint32_t N; /* Input Clock divider/Pre-divider (N) */
    uint32_t M2; /* Post divider (M2) */
    uint32_t M;  /* Multiplier integer (M) */
    uint32_t FracM; /* Multiplier fractional (M) */
    uint32_t Fout; /* Output frequency of PLL */
    uint32_t Finp; /* Output frequency of PLL */
    uint32_t SD;   /* Sigma delta divider */
} SOC_RcmADPLLJConfig_t;
 
#define RCM_PLL_HSDIV_OUTPUT_ENABLE_0                                 (1U << 0U)
#define RCM_PLL_HSDIV_OUTPUT_ENABLE_1                                 (1U << 1U)
#define RCM_PLL_HSDIV_OUTPUT_ENABLE_2                                 (1U << 2U)
#define RCM_PLL_HSDIV_OUTPUT_ENABLE_3                                 (1U << 3U)
#define RCM_PLL_HSDIV_OUTPUT_ENABLE_ALL     (RCM_PLL_HSDIV_OUTPUT_ENABLE_0   | \
                                             RCM_PLL_HSDIV_OUTPUT_ENABLE_1   | \
                                             RCM_PLL_HSDIV_OUTPUT_ENABLE_2   | \
                                             RCM_PLL_HSDIV_OUTPUT_ENABLE_3)
 
#define RCM_PLL_HSDIV_OUTPUT_IDX0                                            (0)
#define RCM_PLL_HSDIV_OUTPUT_IDX1                                            (1)
#define RCM_PLL_HSDIV_OUTPUT_IDX2                                            (2)
#define RCM_PLL_HSDIV_OUTPUT_IDX3                                            (3)
#define RCM_PLL_HSDIV_OUTPUT_COUNT               (RCM_PLL_HSDIV_OUTPUT_IDX3 + 1)
 
typedef struct SOC_RcmPllHsDivOutConfig_s
{
    uint32_t hsdivOutEnMask;
    uint32_t hsDivOutFreqHz[RCM_PLL_HSDIV_OUTPUT_COUNT];
} SOC_RcmPllHsDivOutConfig;
 
extern void SOC_rcmCoreApllConfig(SOC_RcmPllFoutFreqId outFreqId, SOC_RcmPllHsDivOutConfig *hsDivCfg);
 
extern void SOC_rcmEthApllConfig(SOC_RcmPllFoutFreqId outFreqId, SOC_RcmPllHsDivOutConfig *hsDivCfg);
 
extern uint32_t SOC_rcmCoreApllRelockPreRequisite(void);
 
extern void SOC_rcmSetR5ClockSource(uint32_t r5ClkSrc);
 
 
extern void SOC_rcmCoreApllHSDivConfig(SOC_RcmPllFoutFreqId outFreqId, SOC_RcmPllHsDivOutConfig *hsDivCfg);
 
extern void SOC_rcmPerApllConfig(SOC_RcmPllFoutFreqId outFreqId, SOC_RcmPllHsDivOutConfig *hsDivCfg);
 
extern void SOC_rcmsetR5SysClock(uint32_t cr5FreqHz, uint32_t sysClkFreqHz,
                                 uint32_t cpuId);
 
extern void SOC_rcmsetTraceClock(uint32_t traceFreqHz);
 
extern void SOC_rcmsetClkoutClock(uint32_t clkout0FreqHz, uint32_t clkout1FreqHz);
 
extern int32_t SOC_rcmSetPeripheralClock(SOC_RcmPeripheralId periphId, SOC_RcmPeripheralClockSource clkSource, uint32_t freqHz);
 
extern SOC_RcmResetCause SOC_rcmGetResetCause(SOC_Rcmr5fssNum r5fssNum);
 
int32_t SOC_rcmEnablePeripheralClock(SOC_RcmPeripheralId periphId, uint32_t enable);
 
int32_t SOC_rcmSetR5Clock(uint32_t r5FreqHz, uint32_t sysClkFreqHz, uint32_t cpuId);
 
uint32_t SOC_rcmGetR5Clock(uint32_t cpuId);
 
void SOC_rcmR5ConfigLockStep(uint32_t cpuId);
 
void SOC_rcmR5ConfigDualCore(uint32_t cpuId);
 
extern void SOC_rcmSetR5ClockSource(uint32_t r5ClkSrc);
 
void SOC_rcmR5SS0TriggerReset(void);
 
void SOC_rcmCoreR5FUnhalt(uint32_t cpuId);
 
void SOC_rcmStartMemInitTCMA(uint32_t cpuId);
 
void SOC_rcmWaitMemInitTCMA(uint32_t cpuId);
 
void SOC_rcmStartMemInitTCMB(uint32_t cpuId);
 
void SOC_rcmWaitMemInitTCMB(uint32_t cpuId);
 
void SOC_rcmMemInitMailboxMemory(void);
void SOC_rcmMemInitL2Memory(void);
void SOC_rcmR5SS0PowerOnReset(void);
 
void SOC_rcmR5SS1TriggerReset(void);
 
void SOC_rcmR5SS1PowerOnReset(void);
 
uint32_t SOC_rcmIsR5FInLockStepMode(uint32_t r5fClusterGroupId);
 
void SOC_generateSwWarmReset(void);
 
void SOC_configureWarmResetSource(uint32_t source);
 
SOC_WarmResetCause SOC_getWarmResetCause(void);
 
void SOC_clearWarmResetCause(void);
 
void SOC_configureWarmResetOutputDelay(uint16_t opDelayValue);
 
void SOC_configureWarmResetInputRiseDelay(uint16_t inpRiseDelayValue);
 
void SOC_configureWarmResetInputFallDelay(uint16_t inpFallDelayValue);
 
#ifdef __cplusplus
}
#endif
 
#endif