icssg.h

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/*
 *  Copyright (c) Texas Instruments Incorporated 2020-2025
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef ICSSG_H_
#define ICSSG_H_
 
/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */
 
#include <stdint.h>
#include <include/mod/icssg_timesync.h>
#include <include/mod/icssg_stats.h>
#include <include/mod/mdio.h>
#include <include/phy/enetphy.h>
#include <include/core/enet_mod_phy.h>
#include <priv/core/enet_rm_priv.h>
#include <drivers/pruicss/g_v0/pruicss.h>
#include <include/core/enet_dma.h>
 
#ifdef __cplusplus
extern "C" {
#endif
 
/* ========================================================================== */
/*                                 Macros                                     */
/* ========================================================================== */
 
#define ICSSG_CFG_DEFAULT_AGING_PERIOD_MS   (0x6FC23AC00)
 
#define ICSSG_IEP_DFLT_CYCLE_TIME_NSECS     (1000000U)
 
#define ICSSG_PUBLIC_IOCTL(x)             (ENET_IOCTL_PER_BASE |  \
                                           ENET_IOCTL_PER_ICSSG | \
                                           ENET_IOCTL_MIN(x))
 
#define ICSSG_PORT_NUM                    (3U)
 
#define ICSSG_MAC_PORT_MAX                (ICSSG_PORT_NUM - 1U)
 
#define ICSSG_PER_DUALMAC_PORT_MAX        (1U)
 
#define ICSSG_PER_SWITCH_PORT_MAX         (ICSSG_MAC_PORT_MAX)
 
#ifdef SOC_AM65XX
#define ICSSG_INSTANCE_NUM                  (3U)
#else
#define ICSSG_INSTANCE_NUM                  (2U)
#endif
 
#define ICSSG_MAX_NUM_BUFFER_POOLS          (24U)
 
#define ICSSG_DUALMAC_TX_CH_NUM             (ENET_CFG_RM_TX_CH_MAX)
 
#define ICSSG_DUALMAC_RX_FLOW_NUM           (ENET_CFG_RM_RX_CH_MAX / 2)
 
#define ICSSG_SWITCH_TX_CH_NUM              (ENET_CFG_RM_TX_CH_MAX)
 
#define ICSSG_SWITCH_RX_FLOW_NUM            (ENET_CFG_RM_RX_CH_MAX)
 
#define ICSSG_DUALMAC_PORT_BUFFER_POOL_NUM  (0U)
 
#define ICSSG_DUALMAC_HOST_EGRESS_QUEUE_NUM (2U)
 
#define ICSSG_SWITCH_PORT_BUFFER_POOL_NUM   (8U)
 
#define ICSSG_SWITCH_PORT_BUFFER_POOL_NUM_MAX   (8U)
 
#define ICSSG_SWITCH_HOST_OWN_BUFFER_POOL_MAX_OFFSET   (16U)
 
#define ICSSG_SWITCH_HOST_EGRESS_QUEUE_NUM  (2U)
 
#define ICSSG_HOST_EGRESS_BUFFER_PADDING    (2048U)
 
#define ICSSG_SCRATCH_BUFFER_SIZE           (ENET_UTILS_ALIGN((2048U), ICSSG_CACHELINE_ALIGNMENT))
 
#define ICSSG_FDB_ENTRY_P0_MEMBERSHIP         (ENET_BIT(0U))
 
#define ICSSG_FDB_ENTRY_P1_MEMBERSHIP         (ENET_BIT(1U))
 
#define ICSSG_FDB_ENTRY_P2_MEMBERSHIP         (ENET_BIT(2U))
 
#define ICSSG_FDB_ENTRY_AGEABLE               (ENET_BIT(3U))
 
#define ICSSG_FDB_ENTRY_BLOCK                 (ENET_BIT(4U))
 
#define ICSSG_FDB_ENTRY_SECURE                (ENET_BIT(5U))
 
#define ICSSG_FDB_ENTRY_TOUCHED               (ENET_BIT(6U))
 
#define ICSSG_FDB_ENTRY_VALID                 (ENET_BIT(7U))
 
/* RX Rate Source Selection */
 
#define ICSSG_RATE_SRC_SEL_FT1_MATCH0         (0U)
#define ICSSG_RATE_SRC_SEL_FT1_MATCH1         (1U)
#define ICSSG_RATE_SRC_SEL_FT1_MATCH2         (2U)
#define ICSSG_RATE_SRC_SEL_FT1_MATCH3         (3U)
#define ICSSG_RATE_SRC_SEL_FT1_MATCH4         (4U)
#define ICSSG_RATE_SRC_SEL_FT1_MATCH5         (5U)
#define ICSSG_RATE_SRC_SEL_FT1_MATCH6         (6U)
#define ICSSG_RATE_SRC_SEL_FT1_MATCH7         (7U)
#define ICSSG_RATE_SRC_SEL_FT3_MATCH0         (8U)
#define ICSSG_RATE_SRC_SEL_FT3_MATCH1         (9U)
#define ICSSG_RATE_SRC_SEL_FT3_MATCH2         (10U)
#define ICSSG_RATE_SRC_SEL_FT3_MATCH3         (11U)
#define ICSSG_RATE_SRC_SEL_FT3_MATCH4         (12U)
#define ICSSG_RATE_SRC_SEL_FT3_MATCH5         (13U)
#define ICSSG_RATE_SRC_SEL_FT3_MATCH6         (14U)
#define ICSSG_RATE_SRC_SEL_FT3_MATCH7         (15U)
#define ICSSG_RATE_SRC_SEL_FT3_MATCH8         (16U)
#define ICSSG_RATE_SRC_SEL_FT3_MATCH9         (17U)
#define ICSSG_RATE_SRC_SEL_FT3_MATCH10        (18U)
#define ICSSG_RATE_SRC_SEL_FT3_MATCH11        (19U)
#define ICSSG_RATE_SRC_SEL_FT3_MATCH12        (20U)
#define ICSSG_RATE_SRC_SEL_FT3_MATCH13        (21U)
#define ICSSG_RATE_SRC_SEL_FT3_MATCH14        (22U)
#define ICSSG_RATE_SRC_SEL_FT3_MATCH15        (23U)
#define ICSSG_RATE_SRC_SEL_FT_RX_UC           (24U)
#define ICSSG_RATE_SRC_SEL_FT_RX_MC           (25U)
#define ICSSG_RATE_SRC_SEL_FT_RX_BC           (26U)
#define ICSSG_RATE_SRC_SEL_FT_RX_SAV          (27U)
#define ICSSG_RATE_SRC_SEL_FT_RX_FWD          (28U)
#define ICSSG_RATE_SRC_SEL_FT_RX_RCV          (29U)
#define ICSSG_RATE_SRC_SEL_FT_RX_VLAN         (30U)
#define ICSSG_RATE_SRC_SEL_FT_RX_DA_P         (31U)
#define ICSSG_RATE_SRC_SEL_FT_RX_DA_I         (32U)
#define ICSSG_RATE_SRC_SEL_RX_CLASS_RAW0      (33U)
#define ICSSG_RATE_SRC_SEL_RX_CLASS_RAW1      (34U)
#define ICSSG_RATE_SRC_SEL_RX_CLASS_RAW2      (35U)
#define ICSSG_RATE_SRC_SEL_RX_CLASS_RAW3      (36U)
#define ICSSG_RATE_SRC_SEL_RX_CLASS_RAW4      (37U)
#define ICSSG_RATE_SRC_SEL_RX_CLASS_RAW5      (38U)
#define ICSSG_RATE_SRC_SEL_RX_CLASS_RAW6      (39U)
#define ICSSG_RATE_SRC_SEL_RX_CLASS_RAW7      (40U)
#define ICSSG_RATE_SRC_SEL_RX_CLASS_RAW8      (41U)
#define ICSSG_RATE_SRC_SEL_RX_CLASS_RAW9      (42U)
#define ICSSG_RATE_SRC_SEL_RX_CLASS_RAW10     (43U)
#define ICSSG_RATE_SRC_SEL_RX_CLASS_RAW11     (44U)
#define ICSSG_RATE_SRC_SEL_RX_CLASS_RAW12     (45U)
#define ICSSG_RATE_SRC_SEL_RX_CLASS_RAW13     (46U)
#define ICSSG_RATE_SRC_SEL_RX_CLASS_RAW14     (47U)
#define ICSSG_RATE_SRC_SEL_RX_CLASS_RAW15     (48U)
 
/* RX class data mapping */
#define ICCSG_RX_CLASS_DATA_FT3_MATCH0        (0U)
#define ICCSG_RX_CLASS_DATA_FT3_MATCH1        (1U)
#define ICCSG_RX_CLASS_DATA_FT3_MATCH2        (2U)
#define ICCSG_RX_CLASS_DATA_FT3_MATCH3        (3U)
#define ICCSG_RX_CLASS_DATA_FT3_MATCH4        (4U)
#define ICCSG_RX_CLASS_DATA_FT3_MATCH5        (5U)
#define ICCSG_RX_CLASS_DATA_FT3_MATCH6        (6U)
#define ICCSG_RX_CLASS_DATA_FT3_MATCH7        (7U)
#define ICCSG_RX_CLASS_DATA_FT3_MATCH8        (8U)
#define ICCSG_RX_CLASS_DATA_FT3_MATCH9        (9U)
#define ICCSG_RX_CLASS_DATA_FT3_MATCH10       (10U)
#define ICCSG_RX_CLASS_DATA_FT3_MATCH11       (11U)
#define ICCSG_RX_CLASS_DATA_FT3_MATCH12       (12U)
#define ICCSG_RX_CLASS_DATA_FT3_MATCH13       (13U)
#define ICCSG_RX_CLASS_DATA_FT3_MATCH14       (14U)
#define ICCSG_RX_CLASS_DATA_FT3_MATCH15       (15U)
#define ICCSG_RX_CLASS_DATA_FT1_MATCH0        (16U)
#define ICCSG_RX_CLASS_DATA_FT1_MATCH1        (17U)
#define ICCSG_RX_CLASS_DATA_FT1_MATCH2        (18U)
#define ICCSG_RX_CLASS_DATA_FT1_MATCH3        (19U)
#define ICCSG_RX_CLASS_DATA_FT1_MATCH4        (20U)
#define ICCSG_RX_CLASS_DATA_FT1_MATCH5        (21U)
#define ICCSG_RX_CLASS_DATA_FT1_MATCH6        (22U)
#define ICCSG_RX_CLASS_DATA_FT1_MATCH7        (23U)
#define ICCSG_RX_CLASS_DATA_FT_RX_DA_I        (24U)
#define ICCSG_RX_CLASS_DATA_FT_RX_DA_P        (25U)
#define ICCSG_RX_CLASS_DATA_FT_RX_VLAN        (26U)
#define ICCSG_RX_CLASS_DATA_FT_RX_RCV         (27U)
#define ICCSG_RX_CLASS_DATA_FT_RX_FWD         (28U)
#define ICCSG_RX_CLASS_DATA_FT_RX_BC          (29U)
#define ICCSG_RX_CLASS_DATA_FT_RX_MC          (30U)
#define ICCSG_RX_CLASS_DATA_FT_RX_SAV         (31U)
 
#define ICSSG_TAS_MIN_CYCLE_TIME_NS           (1000000)
 
#define ICSSG_TAS_MIN_WINDOW_DURATION_NS      (10000)
 
/* ========================================================================== */
/*                         Structures and Enums                               */
/* ========================================================================== */
 
typedef enum Icssg_Instance_Num_e
{
    ICSSG_INSTANCE_NUM_0,
 
    ICSSG_INSTANCE_NUM_1,
 
    ICSSG_INSTANCE_NUM_2,
} Icssg_Instance_Num;
 
typedef struct Icssg_TxTsEvtCbInfo_s
{
    uint32_t txTsId;
 
    uint64_t ts;
} Icssg_TxTsEvtCbInfo;
 
typedef enum Icssg_Ioctl_e
{
    ICSSG_MACPORT_IOCTL_ENABLE_PROMISC_MODE = ICSSG_PUBLIC_IOCTL(0U),
 
    ICSSG_MACPORT_IOCTL_DISABLE_PROMISC_MODE = ICSSG_PUBLIC_IOCTL(1U),
 
    ICSSG_PER_IOCTL_VLAN_RESET_TABLE = ICSSG_PUBLIC_IOCTL(2U),
 
    ICSSG_PER_IOCTL_VLAN_SET_ENTRY = ICSSG_PUBLIC_IOCTL(3U),
 
    ICSSG_PER_IOCTL_VLAN_GET_ENTRY = ICSSG_PUBLIC_IOCTL(4U),
 
    ICSSG_PER_IOCTL_SET_PORT_STATE = ICSSG_PUBLIC_IOCTL(5U),
 
    ICSSG_FDB_IOCTL_ADD_ENTRY = ICSSG_PUBLIC_IOCTL(6U),
 
    ICSSG_FDB_IOCTL_REMOVE_ENTRY = ICSSG_PUBLIC_IOCTL(7U),
 
    ICSSG_FDB_IOCTL_REMOVE_ALL_ENTRIES = ICSSG_PUBLIC_IOCTL(8U),
 
    ICSSG_FDB_IOCTL_REMOVE_AGEABLE_ENTRIES = ICSSG_PUBLIC_IOCTL(9U),
 
    ICSSG_FDB_IOCTL_READ_SLOT_ENTRIES = ICSSG_PUBLIC_IOCTL(10U),
 
    ICSSG_FDB_IOCTL_GET_SLOT_ENTRIES = ICSSG_PUBLIC_IOCTL(11U),
 
    ICSSG_MACPORT_IOCTL_SET_MACADDR = ICSSG_PUBLIC_IOCTL(12U),
 
    ICSSG_HOSTPORT_IOCTL_SET_MACADDR = ICSSG_PUBLIC_IOCTL(13U),
 
    ICSSG_PER_IOCTL_TAS_TRIGGER = ICSSG_PUBLIC_IOCTL(14U),
 
    ICSSG_PER_IOCTL_TAS_ENABLE = ICSSG_PUBLIC_IOCTL(15U),
 
    ICSSG_PER_IOCTL_TAS_DISABLE = ICSSG_PUBLIC_IOCTL(16U),
 
    ICSSG_PER_IOCTL_TAS_RESET = ICSSG_PUBLIC_IOCTL(17U),
 
    ICSSG_PER_IOCTL_VLAN_SET_HOSTPORT_DFLT_VID = ICSSG_PUBLIC_IOCTL(18U),
 
    ICSSG_PER_IOCTL_VLAN_SET_MACPORT_DFLT_VID = ICSSG_PUBLIC_IOCTL(19U),
 
    ICSSG_FDB_IOCTL_SET_AGING_PERIOD = ICSSG_PUBLIC_IOCTL(20U),
 
    ICSSG_MACPORT_IOCTL_ENABLE_UCAST_FLOOD = ICSSG_PUBLIC_IOCTL(21U),
 
    ICSSG_MACPORT_IOCTL_DISABLE_UCAST_FLOOD = ICSSG_PUBLIC_IOCTL(22U),
 
    ICSSG_MACPORT_IOCTL_ENABLE_MCAST_FLOOD = ICSSG_PUBLIC_IOCTL(23U),
 
    ICSSG_MACPORT_IOCTL_DISABLE_MCAST_FLOOD = ICSSG_PUBLIC_IOCTL(24U),
 
    ICSSG_MACPORT_IOCTL_SET_ACCEPT_FRAME_CHECK = ICSSG_PUBLIC_IOCTL(25U),
 
    ICSSG_MACPORT_IOCTL_SET_INGRESS_RATE_LIM = ICSSG_PUBLIC_IOCTL(26U),
 
    ICSSG_MACPORT_IOCTL_SET_QUEUE_CUT_THROUGH_PREEMPT_SELECT = ICSSG_PUBLIC_IOCTL(27U),
 
    ICSSG_MACPORT_IOCTL_CONFIG_SPL_FRAME_PRIO = ICSSG_PUBLIC_IOCTL(28U),
 
    ICSSG_ENABLE_PROTOCOL_SPECIFIC_TAG_IOCTL = ICSSG_PUBLIC_IOCTL(29U),
 
    ICSSG_DISABLE_PROTOCOL_SPECIFIC_TAG_IOCTL = ICSSG_PUBLIC_IOCTL(30U),
 
    ICSSG_INTERNAL_IOCTL_REGISTER_HANDLER = ICSSG_PUBLIC_IOCTL(31U),
} Icssg_Ioctl;
 
typedef enum Icssg_QueuePreemptMode_e
{
    ICSSG_QUEUE_PREEMPT_MODE_EXPRESS,
 
    ICSSG_QUEUE_PREEMPT_MODE_PREEMPT,
} Icssg_QueuePreemptMode;
 
typedef enum Icssg_QueueForwardMode_e
{
    ICSSG_QUEUE_FORWARD_MODE_STOREANDFWD,
 
    ICSSG_QUEUE_FORWARD_MODE_CUTTHROUGH,
} Icssg_QueueForwardMode;
 
typedef struct IcssgMacPort_SetQueueCtPremptModeInArgs_s
{
    Enet_MacPort macPort;
 
    Icssg_QueuePreemptMode queuePreemptMode[ENET_PRI_NUM];
 
    Icssg_QueueForwardMode queueForwardMode[ENET_PRI_NUM];
} IcssgMacPort_SetQueueCtPremptModeInArgs;
 
typedef struct IcssgMacPort_ConfigSpecialFramePrioInArgs_s
{
    Enet_MacPort macPort;
 
    uint8_t specialFramePrio;
} IcssgMacPort_ConfigSpecialFramePrioInArgs;
 
typedef enum Icssg_PortState_e
{
    ICSSG_PORT_STATE_DISABLED,
 
    ICSSG_PORT_STATE_BLOCKING,
 
    ICSSG_PORT_STATE_FORWARD,
 
    ICSSG_PORT_STATE_FORWARD_WO_LEARNING,
 
    ICSSG_PORT_STATE_TAS_TRIGGER,
 
    ICSSG_PORT_STATE_TAS_ENABLE,
 
    ICSSG_PORT_STATE_TAS_RESET,
 
    ICSSG_PORT_STATE_TAS_DISABLE,
} Icssg_PortState;
 
typedef struct IcssgMacPort_SetPortStateInArgs_s
{
    Enet_MacPort macPort;
 
    Icssg_PortState portState;
} IcssgMacPort_SetPortStateInArgs;
 
typedef enum Icssg_AcceptFrameCheck_e
{
    ICSSG_ACCEPT_ONLY_VLAN_TAGGED,
 
    ICSSG_ACCEPT_ONLY_UNTAGGED_PRIO_TAGGED,
 
    ICSSG_ACCEPT_ALL,
} Icssg_AcceptFrameCheck;
 
typedef struct Icssg_SetAcceptFrameCheckInArgs_s
{
    Enet_MacPort macPort;
 
    Icssg_AcceptFrameCheck acceptFrameCheck;
} Icssg_SetAcceptFrameCheckInArgs;
 
typedef struct Icssg_MacAddr_s
{
    uint8_t macAddr[ENET_MAC_ADDR_LEN];
} Icssg_MacAddr;
 
typedef struct IcssgMacPort_SetMacAddressInArgs_s
{
    Enet_MacPort macPort;
 
    uint8_t macAddr[ENET_MAC_ADDR_LEN];
} IcssgMacPort_SetMacAddressInArgs;
 
 
typedef struct Icssg_VlanFidParams_s
{
    uint8_t fid;
 
    bool hostMember;
 
    bool p1Member;
 
    bool p2Member;
 
    bool hostTagged;
 
    bool p1Tagged;
 
    bool p2Tagged;
 
    bool streamVid;
 
    bool floodToHost;
} Icssg_VlanFidParams;
 
typedef struct Icssg_VlanFidEntry_s
{
    uint16_t vlanId;
 
    Icssg_VlanFidParams vlanFidParams;
} Icssg_VlanFidEntry;
 
typedef struct Icssg_FdbEntry_s
{
    uint8_t macAddr[ENET_MAC_ADDR_LEN];
 
    int16_t vlanId;
 
    uint8_t fdbEntry[2];
} Icssg_FdbEntry;
 
typedef struct Icssg_HwFdbEntry_s
{
    uint8_t macAddr[ENET_MAC_ADDR_LEN];
 
    uint8_t fid_c1;
 
    uint8_t fid_c2;
} Icssg_HwFdbEntry;
 
typedef struct Icssg_FdbEntry_ReadSlotInArgs_s
{
    uint16_t broadSideSlot;
} Icssg_FdbEntry_ReadSlotInArgs;
 
typedef struct Icssg_FdbEntry_GetSlotOutArgs_s
{
    Icssg_HwFdbEntry fdbSlotEntries[4];
} Icssg_FdbEntry_GetSlotOutArgs;
 
typedef struct Icssg_DfltVlanCfg_s
{
    Enet_MacPort macPort;
 
    uint16_t vlanId;
 
    uint8_t pcp;
} Icssg_DfltVlanCfg;
 
typedef struct Icssg_MacPortDfltVlanCfgInArgs_s
{
    Enet_MacPort macPort;
 
    EnetPort_VlanCfg vlanCfg;
} Icssg_MacPortDfltVlanCfgInArgs;
 
typedef struct Icssg_IngressRateLim_s
{
    Enet_MacPort macPort;
 
    uint32_t rateLimit; //In Mbps
    uint32_t rateSrcSel;//0..47
    uint8_t  rateIndex; //0..7, 0xFF : skip
    uint8_t  classIndex; //0..15 - FW dependent
    uint8_t  notMask; //Bit 0 : !AND Bit1 : !OR
    uint8_t  classSel; //0: OR 1 : AND 2: OR AND AND 3 : OR OR AND
    uint32_t classDataAndTerm;
    uint32_t classDataOrTerm;
    struct FT_S {
        uint8_t index; //FT1 (0..7) FT3 (0..15)0XFF : Skip
        uint8_t type; // 0 : FT1 or 1 : FT3
        uint16_t ft1Start;
        uint16_t ft1Len;
        uint16_t ft1Cfg;
        union FT_U {
            struct FT1_CONFIG_S {
                uint32_t destAddrLow;
                uint32_t destAddrHigh;
                uint32_t destAddrMaskLow;
                uint32_t destAddrMaskHigh;
            } ft1;
            struct FT3_CONFIG_S {
                uint32_t start;
                uint32_t startAuto;
                uint32_t startLen;
                uint32_t jmpOffset;
                uint32_t len;
                uint32_t config;
                uint32_t type;
                uint32_t typeMask;
                uint32_t patternLow;
                uint32_t patternHigh;
                uint32_t patternMaskLow;
                uint32_t patternMaskHigh;
            } ft3;
        } u;
    } filter[2];
} Icssg_IngressRateLim;
 
typedef struct Icssg_custom_Fw_s
{
    const uint32_t *pru;
 
    uint32_t pruSize;
 
    const uint32_t *rtu;
 
    uint32_t rtuSize;
 
    const uint32_t *txpru;
 
    uint32_t txpruSize;
} Icssg_custom_Fw;
 
typedef struct Icssg_FwPoolMem_s
{
    uint8_t *portBufferPoolMem;
 
    uint32_t portBufferPoolSize;
 
    uint32_t portBufferPoolNum;
 
    uint8_t *hostBufferPoolMem;
 
    uint32_t hostBufferPoolSize;
 
    uint32_t hostBufferPoolNum;
 
    uint8_t *hostEgressQueueMem;
 
    uint8_t *hostEgressPreQueueMem;
 
    uint32_t hostEgressQueueSize;
 
    uint32_t hostEgressPreQueueSize;
 
    uint32_t hostEgressQueueNum;
 
    uint8_t *scratchBufferMem;
 
    uint32_t scratchBufferSize;
} Icssg_FwPoolMem;
 
typedef struct Icssg_MdioLinkStateChangeInfo_s
{
    uint32_t phyAddr;
 
    bool aliveChanged;
 
    bool isAlive;
 
    bool linkChanged;
 
    bool isLinked;
} Icssg_MdioLinkStateChangeInfo;
 
typedef void (*Icssg_MdioLinkStateChangeCb)(Icssg_MdioLinkStateChangeInfo *info,
                                           void *appArg);
 
typedef void (*Icssg_portLinkStateChangeCb)(Enet_MacPort macPort, bool isLinkUp,
                                           void *appArg);
 
typedef struct Icssg_mdioLinkIntCfg_s
{
    Icssg_MdioLinkStateChangeCb mdioLinkStateChangeCb;
 
    void *mdioLinkStateChangeCbArg;
    const PRUICSS_IntcInitData  *prussIntcInitData;
    int32_t                      coreIntrNum;
    uint32_t                     pruEvtNum[ICSSG_MAC_PORT_MAX];
    uint32_t                     isPulseIntr;
    uint32_t                     intrPrio;
} Icssg_mdioLinkIntCfg;
 
 
typedef struct Icssg_portLinkIntCfg_s
{
    Icssg_portLinkStateChangeCb portLinkStateChangeCb;
 
    void *portLinkStateChangeCbArg;
} Icssg_portLinkIntCfg;
 
typedef struct Icssg_Cfg_s
{
    uint64_t agingPeriod;
 
    EnetPort_VlanCfg vlanCfg;
 
    const EnetDma_Cfg *dmaCfg;
 
    EnetRm_ResCfg resCfg;
 
    Mdio_Cfg mdioCfg;
 
    IcssgTimeSync_Cfg timeSyncCfg;
 
    EnetMacPort_Interface mii;
 
    uint32_t cycleTimeNs;
 
    Icssg_mdioLinkIntCfg mdioLinkIntCfg;
 
    Icssg_portLinkIntCfg portLinkIntCfg;
 
    bool disablePhyDriver;
 
    uint32_t qosLevels;
 
    uint32_t isPremQueEnable;
 
    IcssgTimeSync_ClkType clockTypeFw;
 
    Icssg_custom_Fw fw[ICSSG_MAC_PORT_MAX];
} Icssg_Cfg;
 
typedef struct IccsgMacPort_Cfg_s
{
    bool promiscEn;
 
    bool ucastFloodEn;
 
    bool mcastFloodEn;
 
    Icssg_AcceptFrameCheck acceptFrameCheck;
 
    EnetPort_VlanCfg vlanCfg;
 
    Icssg_QueuePreemptMode queuePreemptMode[ENET_PRI_NUM];
 
    Icssg_QueueForwardMode queueForwardMode[ENET_PRI_NUM];
 
    uint8_t specialFramePrio;
} IcssgMacPort_Cfg;
 
 
/* ========================================================================== */
/*                         Global Variables Declarations                      */
/* ========================================================================== */
 
const Icssg_FwPoolMem *EnetCb_GetFwPoolMem(Enet_Type enetType,
                                      uint32_t instId);
 
/* ========================================================================== */
/*                          Function Declarations                             */
/* ========================================================================== */
 
void IcssgMacPort_initCfg(IcssgMacPort_Cfg *macPortCfg);
 
uint32_t Icssg_getSliceNum(Enet_Type enetType,
                           uint32_t instId,
                           Enet_MacPort macPort);
 
/* ========================================================================== */
/*                        Deprecated Function Declarations                    */
/* ========================================================================== */
 
/* None */
 
/* ========================================================================== */
/*                       Static Function Definitions                          */
/* ========================================================================== */
 
/* None */
 
#ifdef __cplusplus
}
#endif
 
#endif /* ICSSG_H_ */