PRU IPC module provides APIs for communicating with the PRU core with low latency. The communication is done in the form of blocks of data transfer in one exchange. Options are available for configuring multiple buffers and multiple blocks per buffer. The PRU sends one block of data for all buffers at a time, and the next block after that.

The block diagram for the PRU IPC communication is given below.

Features Supported

Configurables: number of buffers, number of blocks, block size, data size
Interrupt option after a block of data is sent by PRU
Configurable shared memory location where the buffers will be placed - by specifying it in linker file
Optional interrupt to PRU after a block of data is sent by R5F
Custom interrupt mapping through ICSS INTC module

SysConfig Features

Note: It is strongly recommend to use SysConfig where it is available instead of using direct SW API calls. This will help simplify the SW application and also catch common mistakes early in the development cycle.

SysConfig is used for configuring all the PRU IPC options mentioned above, through PRU IPC module under PRU IO.

Based on the configuration selected, the SysConfig generated code does following:
- Create macros like CONFIG_PRU_IPC1 using the name passed in SysConfig. This is used as an input to PRU_IPC_open API.
- Generates sample code for linker in ti_drivers_config.c

Features NOT Supported

Currently only PRU cores are supported (not RTU PRU and TX PRU cores)

Usage Guidelines

Add PRU IPC using SysConfig

Add a PRU IPC instance using SysConfig, by selecting PRU IPC under PRU IO in the left pane in SysConfig
Configure the instance as per requirements

Update linker command file

A shared memory region between CPU and PRU-ICSS needs to be allocated which the PRU and R5F cores will use for exchanging data. The generated code in ti_drivers_config.c contains sample linker file code which needs to be placed in project's linker file.

Update MPU for the CPU

The shared memory section (described in the above section) which was put in the linker command file needs to be mapped as Cached+Sharable for the CPU.
This can be done via SysConfig, by adding additional MPU entries using the MPU module under TI DRIVER PORTING LAYER (DPL) in SysConfig. Following is an example:

These APIs are for the R5F side. Please also look into the PRU side macros available for usage in PRU firmware.

Example Usage

The PRU IPC is being used in PRU-ADC interfacing examples in which PRU transfers the samples to R5F (to TCM). There, Number of channels correspond to number of buffers and packet size correspond to sample size.

Initialize PRU IPC Instance

    /* ----------------------------------------------------------------- */
    /* Initialize IPC between r5f and PRU cores                          */
    /* ----------------------------------------------------------------- */
    PRU_IPC_Params pruIpcparams = {
                                .pruicssHandle = gPruIcss0Handle,
                                .transferCallbackFxn = &PRU_IPC_Isr,
    };
 
    gPruIpc0Handle = PRU_IPC_open(CONFIG_PRU_IPC0, &pruIpcparams);
    DebugP_assert(gPruIpc0Handle != NULL);

Transfer data

    /* Receive Data from PRU core */
    PRU_IPC_getData(gPruIpc0Handle, samples);
    /* Send Data to PRU core */
    PRU_IPC_sendData(gPruIpc0Handle, samples);

Usage on PRU Firmware Side:

m_pru_ipc_init      R0.b0           ; Initializes PRU IPC paramenters, use R0.b0 register only
ldi                 R1.b0, &R3      ; Starting memory address of registers to send
m_pru_ipc_send      R1.b0, R3, R0.b0, PRU_IPC_RX_INTR_ENABLE, PRU_IPC_RX_EVENT  ; Send data to shared memory

API

APIs for PRU IPC: R5F-PRU communication

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