AM243x MCU+ SDK  09.02.00
enetphy.h
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1 /*
2  * Copyright (c) Texas Instruments Incorporated 2020
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
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10  *
11  * Redistributions in binary form must reproduce the above copyright
12  * notice, this list of conditions and the following disclaimer in the
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14  * distribution.
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18  * from this software without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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23  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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26  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  */
32 
61 #ifndef ENETPHY_H_
62 #define ENETPHY_H_
63 
64 /* ========================================================================== */
65 /* Include Files */
66 /* ========================================================================== */
67 
68 #include <stdint.h>
69 #include <stdbool.h>
70 
71 #ifdef __cplusplus
72 extern "C" {
73 #endif
74 
75 /* ========================================================================== */
76 /* Macros */
77 /* ========================================================================== */
78 
80 #define ENETPHY_IS_ADDR_VALID(addr) ((addr) <= 31U)
81 
83 #define ENETPHY_BIT(n) (1U << (n))
84 
86 #define ENETPHY_IS_BIT_SET(val, n) (((val) & ENETPHY_BIT(n)) != 0U)
87 
89 #define ENETPHY_ARRAYSIZE(x) (sizeof(x) / sizeof(x[0]))
90 
100 /* Ethernet PHY driver error codes are same as CSL's to maintain consistency */
101 
103 #define ENETPHY_SOK (CSL_PASS)
104 
106 #define ENETPHY_EFAIL (CSL_EFAIL)
107 
109 #define ENETPHY_EBADARGS (CSL_EBADARGS)
110 
112 #define ENETPHY_EINVALIDPARAMS (CSL_EINVALID_PARAMS)
113 
115 #define ENETPHY_ETIMEOUT (CSL_ETIMEOUT)
116 
118 #define ENETPHY_EALLOC (CSL_EALLOC)
119 
121 #define ENETPHY_EPERM (CSL_EALLOC - 4)
122 
124 #define ENETPHY_ENOTSUPPORTED (CSL_EALLOC - 5)
125 
138 #define ENETPHY_LINK_CAP_HD10 ENETPHY_BIT(1)
139 
141 #define ENETPHY_LINK_CAP_FD10 ENETPHY_BIT(2)
142 
144 #define ENETPHY_LINK_CAP_HD100 ENETPHY_BIT(3)
145 
147 #define ENETPHY_LINK_CAP_FD100 ENETPHY_BIT(4)
148 
150 #define ENETPHY_LINK_CAP_HD1000 ENETPHY_BIT(5)
151 
153 #define ENETPHY_LINK_CAP_FD1000 ENETPHY_BIT(6)
154 
156 #define ENETPHY_LINK_CAP_10 (ENETPHY_LINK_CAP_HD10 | \
157  ENETPHY_LINK_CAP_FD10)
158 
160 #define ENETPHY_LINK_CAP_100 (ENETPHY_LINK_CAP_HD100 | \
161  ENETPHY_LINK_CAP_FD100)
162 
164 #define ENETPHY_LINK_CAP_1000 (ENETPHY_LINK_CAP_HD1000 | \
165  ENETPHY_LINK_CAP_FD1000)
166 
168 #define ENETPHY_LINK_CAP_ALL (ENETPHY_LINK_CAP_HD10 | \
169  ENETPHY_LINK_CAP_FD10 | \
170  ENETPHY_LINK_CAP_HD100 | \
171  ENETPHY_LINK_CAP_FD100 | \
172  ENETPHY_LINK_CAP_HD1000 | \
173  ENETPHY_LINK_CAP_FD1000)
174 
178 #define ENETPHY_EXTENDED_CFG_SIZE_MAX (128U)
179 
181 #define ENETPHY_FSM_TICK_PERIOD_MS (100U)
182 
184 #define ENETPHY_INVALID_PHYADDR (~0U)
185 
187 #define ENETPHY_TIMEOUT_WAIT_FOREVER (0xFFFFFFFFU)
188 
190 #define ENETPHY_TIMEOUT_NO_WAIT (0U)
191 
192 /* ========================================================================== */
193 /* Structures and Enums */
194 /* ========================================================================== */
195 
199 typedef enum EnetPhy_Magic_e
200 {
202  ENETPHY_MAGIC = 0xCADACADAU,
203 
206 } EnetPhy_Magic;
207 
211 typedef enum EnetPhy_Mii_e
212 {
215 
218 
221 
224 
227 
230 } EnetPhy_Mii;
231 
235 typedef enum EnetPhy_Speed_e
236 {
239 
242 
245 
248 } EnetPhy_Speed;
249 
253 typedef enum EnetPhy_Duplexity_e
254 {
257 
260 
264 
268 typedef struct EnetPhy_Version_s
269 {
271  uint32_t oui;
272 
274  uint32_t model;
275 
277  uint32_t revision;
279 
283 typedef enum EnetPhy_LinkStatus_e
284 {
287 
290 
293 
297 
301 typedef struct EnetPhy_LinkCfg_s
302 {
305 
309 
313 typedef struct EnetPhy_FsmTimeoutCfg_s
314 {
320 
326 
329 
335 
341 
347 
349  uint32_t mdixTicks;
351 
355 typedef struct EnetPhy_Cfg_s
356 {
358  uint32_t phyGroup;
359 
361  uint32_t phyAddr;
362 
364  uint32_t nwayCaps;
365 
367  bool mdixEn;
368 
373 
376 
379 
382 
385 
388 
391 
393  uint8_t extendedCfg[ENETPHY_EXTENDED_CFG_SIZE_MAX];
394 
396  uint32_t extendedCfgSize;
397 
398 } EnetPhy_Cfg;
399 
403 typedef struct EnetPhy_Mdio_s
404 {
417  int32_t (*isAlive)(uint32_t phyAddr,
418  bool *isAlive,
419  void *arg);
420 
433  int32_t (*isLinked)(uint32_t phyAddr,
434  bool *isLinked,
435  void *arg);
436 
450  int32_t (*readC22)(uint32_t group,
451  uint32_t phyAddr,
452  uint32_t reg,
453  uint16_t *val,
454  void *arg);
455 
469  int32_t (*writeC22)(uint32_t group,
470  uint32_t phyAddr,
471  uint32_t reg,
472  uint16_t val,
473  void *arg);
474 
489  int32_t (*readC45)(uint32_t group,
490  uint32_t phyAddr,
491  uint8_t mmd,
492  uint16_t reg,
493  uint16_t *val,
494  void *arg);
495 
510  int32_t (*writeC45)(uint32_t group,
511  uint32_t phyAddr,
512  uint8_t mmd,
513  uint16_t reg,
514  uint16_t val,
515  void *arg);
516 } EnetPhy_Mdio;
517 
522 
526 typedef struct EnetPhy_Drv_s *EnetPhyDrv_Handle;
527 
531 typedef enum EnetPhy_FsmState_e
532 {
535 
538 
541 
544 
547 
550 
553 
556 
559 
562 
566 
570 typedef struct EnetPhy_State_s
571 {
574 
577 
580 
583 
585  uint32_t timeout;
586 
588  uint32_t residenceTime;
589 
592 
595 
598 
601 
603  uint32_t linkCaps;
604 
606  uint32_t phyLinkCaps;
607 
610 
613 
616 } EnetPhy_State;
617 
621 typedef struct EnetPhy_Obj_s
622 {
625 
628 
631 
633  uint32_t macCaps;
634 
637 
640 
643 
645  uint32_t group;
646 
648  uint32_t addr;
649 
651  uint32_t reqLinkCaps;
652 
655 
658 
660  void *mdioArgs;
661 } EnetPhy_Obj;
662 
668 typedef struct EnetPhy_Obj_s *EnetPhy_Handle;
669 
670 /* ========================================================================== */
671 /* Global Variables Declarations */
672 /* ========================================================================== */
673 
674 /* None */
675 
676 /* ========================================================================== */
677 /* Function Declarations */
678 /* ========================================================================== */
679 
688 
699  const void *extendedCfg,
700  uint32_t extendedCfgSize);
701 
720  EnetPhy_Mii mii,
721  const EnetPhy_LinkCfg *linkCfg,
722  uint32_t macPortCaps,
723  EnetPhy_MdioHandle hMdio,
724  void *mdioArgs);
725 
734 
745 
758 
769 
783 
797  EnetPhy_LinkCfg *linkCfg);
798 
811  uint32_t reg,
812  uint16_t *val);
813 
826  uint32_t reg,
827  uint16_t val);
828 
842  uint32_t reg,
843  uint16_t mask,
844  uint16_t val);
845 
858  uint32_t reg,
859  uint16_t *val);
860 
873  uint32_t reg,
874  uint16_t val);
875 
889  uint32_t reg,
890  uint16_t mask,
891  uint16_t val);
892 
906  uint8_t mmd,
907  uint32_t reg,
908  uint16_t *val);
909 
923  uint8_t mmd,
924  uint32_t reg,
925  uint16_t val);
926 
941  uint8_t mmd,
942  uint32_t reg,
943  uint16_t mask,
944  uint16_t val);
945 
954 
955 /* ========================================================================== */
956 /* Deprecated Function Declarations */
957 /* ========================================================================== */
958 
959 /* None */
960 
961 /* ========================================================================== */
962 /* Static Function Definitions */
963 /* ========================================================================== */
964 
965 /* None */
966 
967 #ifdef __cplusplus
968 }
969 #endif
970 
971 #endif /* ENETPHY_H_ */
972 
EnetPhy_State::enableMdix
bool enableMdix
Definition: enetphy.h:615
EnetPhy_Obj::timeoutCfg
EnetPhy_FsmTimeoutCfg timeoutCfg
Definition: enetphy.h:639
EnetPhy_setExtendedCfg
void EnetPhy_setExtendedCfg(EnetPhy_Cfg *phyCfg, const void *extendedCfg, uint32_t extendedCfgSize)
Set PHY extended parameters.
EnetPhy_FsmTimeoutCfg::nwayStartStateTicks
uint32_t nwayStartStateTicks
NWAY_START state timeout (in ticks).
Definition: enetphy.h:334
EnetPhy_readExtReg
int32_t EnetPhy_readExtReg(EnetPhy_Handle hPhy, uint32_t reg, uint16_t *val)
Read PHY extended register.
EnetPhy_FsmTimeoutCfg::findingStateTicks
uint32_t findingStateTicks
FINDING state timeout (in ticks).
Definition: enetphy.h:319
EnetPhy_Cfg::extClkSource
bool extClkSource
Definition: enetphy.h:384
EnetPhy_Cfg::loopbackEn
bool loopbackEn
Definition: enetphy.h:378
EnetPhy_Obj::hMdio
EnetPhy_MdioHandle hMdio
Definition: enetphy.h:624
EnetPhy_Cfg::isIsolateStateReq
bool isIsolateStateReq
Definition: enetphy.h:375
EnetPhy_Obj::addr
uint32_t addr
Definition: enetphy.h:648
EnetPhy_rmwC45Reg
int32_t EnetPhy_rmwC45Reg(EnetPhy_Handle hPhy, uint8_t mmd, uint32_t reg, uint16_t mask, uint16_t val)
Read-modify-write PHY register using Clause-45 frame.
EnetPhy_Cfg::timeoutCfg
EnetPhy_FsmTimeoutCfg timeoutCfg
Definition: enetphy.h:390
ENETPHY_SPEED_10MBIT
@ ENETPHY_SPEED_10MBIT
Definition: enetphy.h:238
EnetPhy_State::residenceTime
uint32_t residenceTime
Definition: enetphy.h:588
ENETPHY_FSM_STATE_FOUND
@ ENETPHY_FSM_STATE_FOUND
FOUND state.
Definition: enetphy.h:546
EnetPhy_Cfg::phyAddr
uint32_t phyAddr
Definition: enetphy.h:361
ENETPHY_FSM_STATE_NWAY_WAIT
@ ENETPHY_FSM_STATE_NWAY_WAIT
NWAY_WAIT state (auto-negotiation path)
Definition: enetphy.h:552
EnetPhy_State::speed
EnetPhy_Speed speed
Definition: enetphy.h:579
EnetPhy_getLinkCfg
int32_t EnetPhy_getLinkCfg(EnetPhy_Handle hPhy, EnetPhy_LinkCfg *linkCfg)
Get link configuration.
EnetPhy_readC45Reg
int32_t EnetPhy_readC45Reg(EnetPhy_Handle hPhy, uint8_t mmd, uint32_t reg, uint16_t *val)
Read PHY register using Clause-45 frame.
EnetPhy_rmwExtReg
int32_t EnetPhy_rmwExtReg(EnetPhy_Handle hPhy, uint32_t reg, uint16_t mask, uint16_t val)
Read-modify-write PHY extended register.
EnetPhyDrv_Handle
struct EnetPhy_Drv_s * EnetPhyDrv_Handle
PHY specific driver handle.
Definition: enetphy.h:526
EnetPhy_printRegs
void EnetPhy_printRegs(EnetPhy_Handle hPhy)
Print all PHY registers.
ENETPHY_FSM_STATE_LINK_WAIT
@ ENETPHY_FSM_STATE_LINK_WAIT
LINK_WAIT state.
Definition: enetphy.h:555
EnetPhy_Mii
EnetPhy_Mii
MAC Media-Independent Interface (MII).
Definition: enetphy.h:212
EnetPhy_Obj::hDrv
EnetPhyDrv_Handle hDrv
Definition: enetphy.h:654
ENETPHY_MAGIC
@ ENETPHY_MAGIC
Definition: enetphy.h:202
ENETPHY_LINK_DOWN
@ ENETPHY_LINK_DOWN
Definition: enetphy.h:295
ENETPHY_FSM_STATE_ENABLE
@ ENETPHY_FSM_STATE_ENABLE
ENABLE state.
Definition: enetphy.h:543
EnetPhy_State::linkCaps
uint32_t linkCaps
Definition: enetphy.h:603
ENETPHY_MAC_MII_RMII
@ ENETPHY_MAC_MII_RMII
RMII interface.
Definition: enetphy.h:217
ENETPHY_MAC_MII_GMII
@ ENETPHY_MAC_MII_GMII
GMII interface.
Definition: enetphy.h:220
EnetPhy_Cfg::skipExtendedCfg
bool skipExtendedCfg
Definition: enetphy.h:387
ENETPHY_SPEED_AUTO
@ ENETPHY_SPEED_AUTO
Definition: enetphy.h:247
EnetPhy_Version::revision
uint32_t revision
Definition: enetphy.h:277
EnetPhy_LinkCfg::duplexity
EnetPhy_Duplexity duplexity
Definition: enetphy.h:307
EnetPhy_State::needsManualCfg
bool needsManualCfg
Definition: enetphy.h:597
EnetPhy_readReg
int32_t EnetPhy_readReg(EnetPhy_Handle hPhy, uint32_t reg, uint16_t *val)
Read PHY register.
EnetPhy_Cfg
PHY configuration parameters.
Definition: enetphy.h:356
EnetPhy_FsmState
EnetPhy_FsmState
PHY driver state-machine states.
Definition: enetphy.h:532
EnetPhy_getId
int32_t EnetPhy_getId(EnetPhy_Handle hPhy, EnetPhy_Version *version)
Get PHY id.
ENETPHY_MAC_MII_MII
@ ENETPHY_MAC_MII_MII
MII interface.
Definition: enetphy.h:214
EnetPhy_isAlive
bool EnetPhy_isAlive(EnetPhy_Handle hPhy)
Get PHY alive status.
EnetPhy_FsmTimeoutCfg::mdixTicks
uint32_t mdixTicks
Timeout if MDIX is enabled (in ticks).
Definition: enetphy.h:349
ENETPHY_DUPLEX_HALF
@ ENETPHY_DUPLEX_HALF
Definition: enetphy.h:256
EnetPhy_State::needsMdixSwitch
bool needsMdixSwitch
Definition: enetphy.h:612
EnetPhy_Version
PHY version (ID).
Definition: enetphy.h:269
EnetPhy_FsmTimeoutCfg::resetWaitStateTicks
uint32_t resetWaitStateTicks
RESET_WAIT state timeout (in ticks).
Definition: enetphy.h:325
ENETPHY_DUPLEX_FULL
@ ENETPHY_DUPLEX_FULL
Definition: enetphy.h:259
EnetPhy_Obj::state
EnetPhy_State state
Definition: enetphy.h:642
EnetPhy_close
void EnetPhy_close(EnetPhy_Handle hPhy)
Close the PHY driver.
EnetPhy_Obj::linkCfg
EnetPhy_LinkCfg linkCfg
Definition: enetphy.h:636
ENETPHY_SPEED_1GBIT
@ ENETPHY_SPEED_1GBIT
Definition: enetphy.h:244
EnetPhy_MdioHandle
EnetPhy_Mdio * EnetPhy_MdioHandle
MDIO driver handle.
Definition: enetphy.h:521
ENETPHY_FSM_STATE_LOOPBACK
@ ENETPHY_FSM_STATE_LOOPBACK
LOOPBACK state.
Definition: enetphy.h:561
EnetPhy_open
EnetPhy_Handle EnetPhy_open(const EnetPhy_Cfg *phyCfg, EnetPhy_Mii mii, const EnetPhy_LinkCfg *linkCfg, uint32_t macPortCaps, EnetPhy_MdioHandle hMdio, void *mdioArgs)
Open the PHY driver.
EnetPhy_LinkCfg::speed
EnetPhy_Speed speed
Definition: enetphy.h:304
EnetPhy_FsmTimeoutCfg
PHY State-Machine time-out values.
Definition: enetphy.h:314
EnetPhy_Handle
struct EnetPhy_Obj_s * EnetPhy_Handle
PHY driver object handle.
Definition: enetphy.h:668
EnetPhy_isLinked
bool EnetPhy_isLinked(EnetPhy_Handle hPhy)
Get link status.
ENETPHY_LOST_LINK
@ ENETPHY_LOST_LINK
Definition: enetphy.h:292
EnetPhy_writeC45Reg
int32_t EnetPhy_writeC45Reg(EnetPhy_Handle hPhy, uint8_t mmd, uint32_t reg, uint16_t val)
Write PHY register using Clause-45 frame.
ENETPHY_NO_MAGIC
@ ENETPHY_NO_MAGIC
Definition: enetphy.h:205
ENETPHY_GOT_LINK
@ ENETPHY_GOT_LINK
Definition: enetphy.h:286
EnetPhy_Obj::magic
EnetPhy_Magic magic
Definition: enetphy.h:657
EnetPhy_Obj::mdioArgs
void * mdioArgs
Definition: enetphy.h:660
EnetPhy_Version::model
uint32_t model
Definition: enetphy.h:274
ENETPHY_FSM_STATE_NWAY_START
@ ENETPHY_FSM_STATE_NWAY_START
NWAY_START state (auto-negotiation path)
Definition: enetphy.h:549
EnetPhy_writeReg
int32_t EnetPhy_writeReg(EnetPhy_Handle hPhy, uint32_t reg, uint16_t val)
Write PHY register.
ENETPHY_DUPLEX_AUTO
@ ENETPHY_DUPLEX_AUTO
Definition: enetphy.h:262
EnetPhy_Obj::mii
EnetPhy_Mii mii
Definition: enetphy.h:630
ENETPHY_LINK_UP
@ ENETPHY_LINK_UP
Definition: enetphy.h:289
EnetPhy_State
PHY driver FSM state.
Definition: enetphy.h:571
EnetPhy_FsmTimeoutCfg::nwayWaitStateTicks
uint32_t nwayWaitStateTicks
NWAY_WAIT state timeout (in ticks).
Definition: enetphy.h:340
EnetPhy_FsmTimeoutCfg::resetWaitStateResidenceTicks
uint32_t resetWaitStateResidenceTicks
RESET_WAIT state residence time (in ticks).
Definition: enetphy.h:328
ENETPHY_SPEED_100MBIT
@ ENETPHY_SPEED_100MBIT
Definition: enetphy.h:241
ENETPHY_FSM_STATE_FINDING
@ ENETPHY_FSM_STATE_FINDING
FINDING state.
Definition: enetphy.h:537
ENETPHY_MAC_MII_SGMII
@ ENETPHY_MAC_MII_SGMII
SGMII interface.
Definition: enetphy.h:226
EnetPhy_Cfg::mdixEn
bool mdixEn
Definition: enetphy.h:367
EnetPhy_Cfg::extendedCfgSize
uint32_t extendedCfgSize
Definition: enetphy.h:396
EnetPhy_Cfg::masterMode
bool masterMode
Definition: enetphy.h:381
ENETPHY_FSM_STATE_INIT
@ ENETPHY_FSM_STATE_INIT
INIT state.
Definition: enetphy.h:534
EnetPhy_State::isNwayCapable
bool isNwayCapable
Definition: enetphy.h:591
ENETPHY_EXTENDED_CFG_SIZE_MAX
#define ENETPHY_EXTENDED_CFG_SIZE_MAX
Max extended configuration size, arbitrarily chosen.
Definition: enetphy.h:178
EnetPhy_State::needsNwayCfg
bool needsNwayCfg
Definition: enetphy.h:600
ENETPHY_MAC_MII_QSGMII
@ ENETPHY_MAC_MII_QSGMII
QSGMII interface.
Definition: enetphy.h:229
EnetPhy_Version::oui
uint32_t oui
Definition: enetphy.h:271
EnetPhy_LinkCfg
Link speed and duplexity configuration.
Definition: enetphy.h:302
EnetPhy_initCfg
void EnetPhy_initCfg(EnetPhy_Cfg *phyCfg)
Initialize PHY config params.
EnetPhy_State::fsmState
EnetPhy_FsmState fsmState
Definition: enetphy.h:573
EnetPhy_State::duplexity
EnetPhy_Duplexity duplexity
Definition: enetphy.h:582
EnetPhy_State::fsmStateChanged
bool fsmStateChanged
Definition: enetphy.h:576
EnetPhy_Cfg::nwayCaps
uint32_t nwayCaps
Definition: enetphy.h:364
EnetPhy_writeExtReg
int32_t EnetPhy_writeExtReg(EnetPhy_Handle hPhy, uint32_t reg, uint16_t val)
Write PHY extended register.
EnetPhy_FsmTimeoutCfg::linkWaitStateTicks
uint32_t linkWaitStateTicks
LINK_WAIT state timeout (in ticks).
Definition: enetphy.h:346
EnetPhy_Duplexity
EnetPhy_Duplexity
MAC interface duplexity.
Definition: enetphy.h:254
ENETPHY_MAC_MII_RGMII
@ ENETPHY_MAC_MII_RGMII
RGMII interface.
Definition: enetphy.h:223
EnetPhy_rmwReg
int32_t EnetPhy_rmwReg(EnetPhy_Handle hPhy, uint32_t reg, uint16_t mask, uint16_t val)
Read-modify-write PHY register.
EnetPhy_State::loopbackEn
bool loopbackEn
Definition: enetphy.h:609
EnetPhy_State::enableNway
bool enableNway
Definition: enetphy.h:594
EnetPhy_Obj
PHY driver object.
Definition: enetphy.h:622
EnetPhy_Obj::group
uint32_t group
Definition: enetphy.h:645
EnetPhy_Obj::macCaps
uint32_t macCaps
Definition: enetphy.h:633
EnetPhy_State::phyLinkCaps
uint32_t phyLinkCaps
Definition: enetphy.h:606
EnetPhy_Obj::reqLinkCaps
uint32_t reqLinkCaps
Definition: enetphy.h:651
EnetPhy_Cfg::phyGroup
uint32_t phyGroup
Definition: enetphy.h:358
EnetPhy_tick
EnetPhy_LinkStatus EnetPhy_tick(EnetPhy_Handle hPhy)
Run PHY state machine.
EnetPhy_Speed
EnetPhy_Speed
MAC interface speed.
Definition: enetphy.h:236
EnetPhy_Cfg::isStrapped
bool isStrapped
Definition: enetphy.h:372
ENETPHY_FSM_STATE_ISOLATE
@ ENETPHY_FSM_STATE_ISOLATE
ISOLATE state.
Definition: enetphy.h:564
EnetPhy_Mdio
MDIO driver.
Definition: enetphy.h:404
ENETPHY_FSM_STATE_RESET_WAIT
@ ENETPHY_FSM_STATE_RESET_WAIT
RESET_WAIT state.
Definition: enetphy.h:540
EnetPhy_Obj::phyCfg
EnetPhy_Cfg phyCfg
Definition: enetphy.h:627
ENETPHY_FSM_STATE_LINKED
@ ENETPHY_FSM_STATE_LINKED
LINKED state.
Definition: enetphy.h:558
EnetPhy_Magic
EnetPhy_Magic
EnetPhy driver magic value, used to indicate if driver is open or not.
Definition: enetphy.h:200
version
uint16_t version
Definition: tisci_core.h:2
EnetPhy_State::timeout
uint32_t timeout
Definition: enetphy.h:585
EnetPhy_LinkStatus
EnetPhy_LinkStatus
PHY link status.
Definition: enetphy.h:284