DDR ECC Test MAIN ESM

Table of Contents

• Introduction
• Supported Combinations
  • AM243X-EVM
• Steps to Run the Example
• See Also
• Sample Output

Note

This example demostrates handling the ESM error in the Main domain R5. The error can also be routed to MCU ESM and error handled in the safety domain (M4 core)

Introduction

This example simulates a 1b and 2b ECC error for DDR and waits for interrupt via the MAIN ESM instance. If the interrupt is not received the test fails.

Supported Combinations

AM243X-EVM

Parameter	Value
CPU + OS	r5fss0-0 nortos
Toolchain	ti-arm-clang
Board	am243x-evm
Example folder	examples/drivers/ddr/ddr_ecc_test_main_esm/

Steps to Run the Example

• When using CCS projects to build, import the CCS project for the required combination and build it using the CCS project menu (see Using SDK with CCS Projects).
• When using makefiles to build, note the required combination and build using make command (see Using SDK with Makefiles)
• Launch a CCS debug session and run the executable, see CCS Launch, Load and Run

See Also

DDR

Sample Output

Shown below is a sample output when the application is run,

Waiting on Single bit Error Correction Interrupt...
1b ECC error detected and corrected
Waiting on Dual bit error detection Interrupt...
2b ECC error detected
All tests have passed!!