SOC

Table of Contents

• Features Supported
• SysConfig Features
• Features NOT Supported
• Important Usage Guidelines
• Example Usage
• API

The SOC driver provides API to configure SOC specific features like clocks.

Features Supported

• API to enable/disable a module clock
• API to set clock frequency for module
• Generic utility API like get CPU clock, get core name string, control module MMR lock/unlock API
• Address Translation APIs for all the R5F cores
• SOC Software Warm Reset/POR Reset APIs

SysConfig Features

• SOC driver is integrated with each of the drivers. User need not perform any explicit configuration for this driver

Features NOT Supported

NA

Important Usage Guidelines

• Most of these APIs are already integrated with SysConfig tool and the generated code does the required call to enable a module, set the required clock and so on. User need to use these APIs in their application only for exceptional scenarios.
• All MCU domain resets act as a main reset to the whole device. (MAIN and MCU domains)
• MAIN domain resets will only reset the MAIN domain.
• Please refer "Reset" chapter in techical reference manual for more details.

Example Usage

Include the below file to access the APIs

#include <drivers/soc.h>

Get Core Name String

    const char *coreName;
 
    coreName = SOC_getCoreName(CSL_CORE_ID_R5FSS0_0);
    DebugP_log("Core name is: %s\r\n", coreName);

Get CPU Clock Frequency

    uint64_t cpuClockRate;
 
    cpuClockRate = SOC_getSelfCpuClk();
    DebugP_log("CPU Clock Frequency: %u\r\n", cpuClockRate);

Set CPU Clock Frequency

    #include <drivers/sciclient.h> /* For the device and clock macros */
 
    uint32_t moduleId = TISCI_DEV_PRU_ICSSG0;
    uint32_t clkId = TISCI_DEV_PRU_ICSSG0_CORE_CLK;
    uint64_t clkRate = 300000000U;
 
    SOC_moduleSetClockFrequency(moduleId, clkId, clkRate);

Set CPU Clock Frequency with a specific parent clock

    #include <drivers/sciclient.h> /* For the device and clock macros */
 
    uint32_t moduleId = TISCI_DEV_PRU_ICSSG0;
    uint32_t clkId = TISCI_DEV_PRU_ICSSG0_CORE_CLK;
    uint32_t clkParentId = TISCI_DEV_PRU_ICSSG0_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK;
    uint64_t clkRate = 300000000U;
 
    SOC_moduleSetClockFrequencyWithParent(moduleId, clkId, clkParentId, clkRate);

API

APIs for SOC Specific Functions