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AM243x MCU+ SDK
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80 #define ENETPHY_IS_ADDR_VALID(addr) ((addr) <= 31U)
83 #define ENETPHY_BIT(n) (1U << (n))
86 #define ENETPHY_IS_BIT_SET(val, n) (((val) & ENETPHY_BIT(n)) != 0U)
89 #define ENETPHY_ARRAYSIZE(x) (sizeof(x) / sizeof(x[0]))
103 #define ENETPHY_SOK (CSL_PASS)
106 #define ENETPHY_EFAIL (CSL_EFAIL)
109 #define ENETPHY_EBADARGS (CSL_EBADARGS)
112 #define ENETPHY_EINVALIDPARAMS (CSL_EINVALID_PARAMS)
115 #define ENETPHY_ETIMEOUT (CSL_ETIMEOUT)
118 #define ENETPHY_EALLOC (CSL_EALLOC)
121 #define ENETPHY_EPERM (CSL_EALLOC - 4)
124 #define ENETPHY_ENOTSUPPORTED (CSL_EALLOC - 5)
138 #define ENETPHY_LINK_CAP_HD10 ENETPHY_BIT(1)
141 #define ENETPHY_LINK_CAP_FD10 ENETPHY_BIT(2)
144 #define ENETPHY_LINK_CAP_HD100 ENETPHY_BIT(3)
147 #define ENETPHY_LINK_CAP_FD100 ENETPHY_BIT(4)
150 #define ENETPHY_LINK_CAP_HD1000 ENETPHY_BIT(5)
153 #define ENETPHY_LINK_CAP_FD1000 ENETPHY_BIT(6)
156 #define ENETPHY_LINK_CAP_10 (ENETPHY_LINK_CAP_HD10 | \
157 ENETPHY_LINK_CAP_FD10)
160 #define ENETPHY_LINK_CAP_100 (ENETPHY_LINK_CAP_HD100 | \
161 ENETPHY_LINK_CAP_FD100)
164 #define ENETPHY_LINK_CAP_1000 (ENETPHY_LINK_CAP_HD1000 | \
165 ENETPHY_LINK_CAP_FD1000)
168 #define ENETPHY_LINK_CAP_ALL (ENETPHY_LINK_CAP_HD10 | \
169 ENETPHY_LINK_CAP_FD10 | \
170 ENETPHY_LINK_CAP_HD100 | \
171 ENETPHY_LINK_CAP_FD100 | \
172 ENETPHY_LINK_CAP_HD1000 | \
173 ENETPHY_LINK_CAP_FD1000)
178 #define ENETPHY_EXTENDED_CFG_SIZE_MAX (128U)
181 #define ENETPHY_FSM_TICK_PERIOD_MS (100U)
184 #define ENETPHY_INVALID_PHYADDR (~0U)
187 #define ENETPHY_TIMEOUT_WAIT_FOREVER (0xFFFFFFFFU)
190 #define ENETPHY_TIMEOUT_NO_WAIT (0U)
199 typedef enum EnetPhy_Magic_e
211 typedef enum EnetPhy_Mii_e
235 typedef enum EnetPhy_Speed_e
253 typedef enum EnetPhy_Duplexity_e
268 typedef struct EnetPhy_Version_s
283 typedef enum EnetPhy_LinkStatus_e
301 typedef struct EnetPhy_LinkCfg_s
313 typedef struct EnetPhy_FsmTimeoutCfg_s
355 typedef struct EnetPhy_Cfg_s
400 typedef struct EnetPhy_Mdio_s
414 int32_t (*isAlive)(uint32_t phyAddr,
430 int32_t (*isLinked)(uint32_t phyAddr,
447 int32_t (*readC22)(uint32_t group,
466 int32_t (*writeC22)(uint32_t group,
486 int32_t (*readC45)(uint32_t group,
507 int32_t (*writeC45)(uint32_t group,
528 typedef enum EnetPhy_FsmState_e
564 typedef struct EnetPhy_State_s
615 typedef struct EnetPhy_Obj_s
693 const void *extendedCfg,
694 uint32_t extendedCfgSize);
716 uint32_t macPortCaps,
bool enableMdix
Definition: enetphy.h:609
EnetPhy_FsmTimeoutCfg timeoutCfg
Definition: enetphy.h:633
void EnetPhy_setExtendedCfg(EnetPhy_Cfg *phyCfg, const void *extendedCfg, uint32_t extendedCfgSize)
Set PHY extended parameters.
uint32_t nwayStartStateTicks
NWAY_START state timeout (in ticks).
Definition: enetphy.h:334
int32_t EnetPhy_readExtReg(EnetPhy_Handle hPhy, uint32_t reg, uint16_t *val)
Read PHY extended register.
uint32_t findingStateTicks
FINDING state timeout (in ticks).
Definition: enetphy.h:319
bool extClkSource
Definition: enetphy.h:381
bool loopbackEn
Definition: enetphy.h:375
EnetPhy_MdioHandle hMdio
Definition: enetphy.h:618
uint32_t addr
Definition: enetphy.h:642
int32_t EnetPhy_rmwC45Reg(EnetPhy_Handle hPhy, uint8_t mmd, uint32_t reg, uint16_t mask, uint16_t val)
Read-modify-write PHY register using Clause-45 frame.
EnetPhy_FsmTimeoutCfg timeoutCfg
Definition: enetphy.h:387
@ ENETPHY_SPEED_10MBIT
Definition: enetphy.h:238
uint32_t residenceTime
Definition: enetphy.h:582
@ ENETPHY_FSM_STATE_FOUND
FOUND state.
Definition: enetphy.h:543
uint32_t phyAddr
Definition: enetphy.h:361
@ ENETPHY_FSM_STATE_NWAY_WAIT
NWAY_WAIT state (auto-negotiation path)
Definition: enetphy.h:549
EnetPhy_Speed speed
Definition: enetphy.h:573
int32_t EnetPhy_getLinkCfg(EnetPhy_Handle hPhy, EnetPhy_LinkCfg *linkCfg)
Get link configuration.
int32_t EnetPhy_readC45Reg(EnetPhy_Handle hPhy, uint8_t mmd, uint32_t reg, uint16_t *val)
Read PHY register using Clause-45 frame.
int32_t EnetPhy_rmwExtReg(EnetPhy_Handle hPhy, uint32_t reg, uint16_t mask, uint16_t val)
Read-modify-write PHY extended register.
struct EnetPhy_Drv_s * EnetPhyDrv_Handle
PHY specific driver handle.
Definition: enetphy.h:523
void EnetPhy_printRegs(EnetPhy_Handle hPhy)
Print all PHY registers.
@ ENETPHY_FSM_STATE_LINK_WAIT
LINK_WAIT state.
Definition: enetphy.h:552
EnetPhy_Mii
MAC Media-Independent Interface (MII).
Definition: enetphy.h:212
EnetPhyDrv_Handle hDrv
Definition: enetphy.h:648
@ ENETPHY_MAGIC
Definition: enetphy.h:202
@ ENETPHY_LINK_DOWN
Definition: enetphy.h:295
@ ENETPHY_FSM_STATE_ENABLE
ENABLE state.
Definition: enetphy.h:540
uint32_t linkCaps
Definition: enetphy.h:597
@ ENETPHY_MAC_MII_RMII
RMII interface.
Definition: enetphy.h:217
@ ENETPHY_MAC_MII_GMII
GMII interface.
Definition: enetphy.h:220
bool skipExtendedCfg
Definition: enetphy.h:384
@ ENETPHY_SPEED_AUTO
Definition: enetphy.h:247
uint32_t revision
Definition: enetphy.h:277
EnetPhy_Duplexity duplexity
Definition: enetphy.h:307
bool needsManualCfg
Definition: enetphy.h:591
int32_t EnetPhy_readReg(EnetPhy_Handle hPhy, uint32_t reg, uint16_t *val)
Read PHY register.
PHY configuration parameters.
Definition: enetphy.h:356
EnetPhy_FsmState
PHY driver state-machine states.
Definition: enetphy.h:529
int32_t EnetPhy_getId(EnetPhy_Handle hPhy, EnetPhy_Version *version)
Get PHY id.
@ ENETPHY_MAC_MII_MII
MII interface.
Definition: enetphy.h:214
bool EnetPhy_isAlive(EnetPhy_Handle hPhy)
Get PHY alive status.
uint32_t mdixTicks
Timeout if MDIX is enabled (in ticks).
Definition: enetphy.h:349
@ ENETPHY_DUPLEX_HALF
Definition: enetphy.h:256
bool needsMdixSwitch
Definition: enetphy.h:606
PHY version (ID).
Definition: enetphy.h:269
uint32_t resetWaitStateTicks
RESET_WAIT state timeout (in ticks).
Definition: enetphy.h:325
@ ENETPHY_DUPLEX_FULL
Definition: enetphy.h:259
EnetPhy_State state
Definition: enetphy.h:636
void EnetPhy_close(EnetPhy_Handle hPhy)
Close the PHY driver.
EnetPhy_LinkCfg linkCfg
Definition: enetphy.h:630
@ ENETPHY_SPEED_1GBIT
Definition: enetphy.h:244
EnetPhy_Mdio * EnetPhy_MdioHandle
MDIO driver handle.
Definition: enetphy.h:518
@ ENETPHY_FSM_STATE_LOOPBACK
LOOPBACK state.
Definition: enetphy.h:558
EnetPhy_Handle EnetPhy_open(const EnetPhy_Cfg *phyCfg, EnetPhy_Mii mii, const EnetPhy_LinkCfg *linkCfg, uint32_t macPortCaps, EnetPhy_MdioHandle hMdio, void *mdioArgs)
Open the PHY driver.
EnetPhy_Speed speed
Definition: enetphy.h:304
PHY State-Machine time-out values.
Definition: enetphy.h:314
struct EnetPhy_Obj_s * EnetPhy_Handle
PHY driver object handle.
Definition: enetphy.h:662
bool EnetPhy_isLinked(EnetPhy_Handle hPhy)
Get link status.
@ ENETPHY_LOST_LINK
Definition: enetphy.h:292
int32_t EnetPhy_writeC45Reg(EnetPhy_Handle hPhy, uint8_t mmd, uint32_t reg, uint16_t val)
Write PHY register using Clause-45 frame.
@ ENETPHY_NO_MAGIC
Definition: enetphy.h:205
@ ENETPHY_GOT_LINK
Definition: enetphy.h:286
EnetPhy_Magic magic
Definition: enetphy.h:651
void * mdioArgs
Definition: enetphy.h:654
uint32_t model
Definition: enetphy.h:274
@ ENETPHY_FSM_STATE_NWAY_START
NWAY_START state (auto-negotiation path)
Definition: enetphy.h:546
int32_t EnetPhy_writeReg(EnetPhy_Handle hPhy, uint32_t reg, uint16_t val)
Write PHY register.
@ ENETPHY_DUPLEX_AUTO
Definition: enetphy.h:262
EnetPhy_Mii mii
Definition: enetphy.h:624
@ ENETPHY_LINK_UP
Definition: enetphy.h:289
PHY driver FSM state.
Definition: enetphy.h:565
uint32_t nwayWaitStateTicks
NWAY_WAIT state timeout (in ticks).
Definition: enetphy.h:340
uint32_t resetWaitStateResidenceTicks
RESET_WAIT state residence time (in ticks).
Definition: enetphy.h:328
@ ENETPHY_SPEED_100MBIT
Definition: enetphy.h:241
@ ENETPHY_FSM_STATE_FINDING
FINDING state.
Definition: enetphy.h:534
@ ENETPHY_MAC_MII_SGMII
SGMII interface.
Definition: enetphy.h:226
bool mdixEn
Definition: enetphy.h:367
uint32_t extendedCfgSize
Definition: enetphy.h:393
bool masterMode
Definition: enetphy.h:378
@ ENETPHY_FSM_STATE_INIT
INIT state.
Definition: enetphy.h:531
bool isNwayCapable
Definition: enetphy.h:585
#define ENETPHY_EXTENDED_CFG_SIZE_MAX
Max extended configuration size, arbitrarily chosen.
Definition: enetphy.h:178
bool needsNwayCfg
Definition: enetphy.h:594
@ ENETPHY_MAC_MII_QSGMII
QSGMII interface.
Definition: enetphy.h:229
uint32_t oui
Definition: enetphy.h:271
Link speed and duplexity configuration.
Definition: enetphy.h:302
void EnetPhy_initCfg(EnetPhy_Cfg *phyCfg)
Initialize PHY config params.
EnetPhy_FsmState fsmState
Definition: enetphy.h:567
EnetPhy_Duplexity duplexity
Definition: enetphy.h:576
bool fsmStateChanged
Definition: enetphy.h:570
uint32_t nwayCaps
Definition: enetphy.h:364
int32_t EnetPhy_writeExtReg(EnetPhy_Handle hPhy, uint32_t reg, uint16_t val)
Write PHY extended register.
uint32_t linkWaitStateTicks
LINK_WAIT state timeout (in ticks).
Definition: enetphy.h:346
EnetPhy_Duplexity
MAC interface duplexity.
Definition: enetphy.h:254
@ ENETPHY_MAC_MII_RGMII
RGMII interface.
Definition: enetphy.h:223
int32_t EnetPhy_rmwReg(EnetPhy_Handle hPhy, uint32_t reg, uint16_t mask, uint16_t val)
Read-modify-write PHY register.
bool loopbackEn
Definition: enetphy.h:603
bool enableNway
Definition: enetphy.h:588
PHY driver object.
Definition: enetphy.h:616
uint32_t group
Definition: enetphy.h:639
uint32_t macCaps
Definition: enetphy.h:627
uint32_t phyLinkCaps
Definition: enetphy.h:600
uint32_t reqLinkCaps
Definition: enetphy.h:645
uint32_t phyGroup
Definition: enetphy.h:358
EnetPhy_LinkStatus EnetPhy_tick(EnetPhy_Handle hPhy)
Run PHY state machine.
EnetPhy_Speed
MAC interface speed.
Definition: enetphy.h:236
bool isStrapped
Definition: enetphy.h:372
MDIO driver.
Definition: enetphy.h:401
@ ENETPHY_FSM_STATE_RESET_WAIT
RESET_WAIT state.
Definition: enetphy.h:537
EnetPhy_Cfg phyCfg
Definition: enetphy.h:621
@ ENETPHY_FSM_STATE_LINKED
LINKED state.
Definition: enetphy.h:555
EnetPhy_Magic
EnetPhy driver magic value, used to indicate if driver is open or not.
Definition: enetphy.h:200
uint16_t version
Definition: tisci_core.h:2
uint32_t timeout
Definition: enetphy.h:579
EnetPhy_LinkStatus
PHY link status.
Definition: enetphy.h:284