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AM243x MCU+ SDK
08.06.00
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58 #define SOC_DOMAIN_ID_MAIN (0U)
59 #define SOC_DOMAIN_ID_MCU (1U)
68 #define SOC_PSC_DOMAIN_ID_MAIN (0U)
69 #define SOC_PSC_DOMAIN_ID_MCU (1U)
78 #define SOC_PSC_SYNCRESETDISABLE (0x0U)
79 #define SOC_PSC_SYNCRESET (0x1U)
80 #define SOC_PSC_DISABLE (0x2U)
81 #define SOC_PSC_ENABLE (0x3U)
89 #define SOC_PSC_DOMAIN_OFF (0x0U)
90 #define SOC_PSC_DOMAIN_ON (0x1U)
96 #define SOC_BOOTMODE_MMCSD (0X36C3)
101 #define SOC_FWL_OPEN_MAGIC_NUM (0XFEDCBA98u)
272 uint32_t debugIsolationEnable);
299 uint32_t *domainState, uint32_t *moduleState);
311 int32_t
SOC_setPSCState(uint32_t instNum, uint32_t domainNum, uint32_t moduleNum, uint32_t pscState);
This file contains prototypes for APIs contained as a part of SCICLIENT as well as the structures of ...
int32_t SOC_moduleSetClockFrequency(uint32_t moduleId, uint32_t clkId, uint64_t clkRate)
Set module clock to specified frequency.
void SOC_controlModuleUnlockMMR(uint32_t domainId, uint32_t partition)
Unlock control module partition to allow writes into control MMRs.
uint64_t SOC_virtToPhy(void *virtAddr)
SOC Virtual (CPU) to Physical address translation function.
void SOC_generateSwWarmResetMainDomainFromMcuDomain(void)
Generate SW WARM Reset Main Domain from Mcu Domain.
void SOC_generateSwPORResetMainDomainFromMcuDomain(void)
Generate SW POR Reset Main Domain from Mcu Domain.
void SOC_clearResetCauseMainMcuDomain(uint32_t resetCause)
Clears reason for Warm and Main/Mcu Domain Power On Resets. CTRLMMR_RST_SRC is just a mirror of CTRLM...
void SOC_setMCUResetIsolationDone(uint32_t value)
Set MCU reset isolation done flag.
void SOC_generateSwWarmResetMcuDomain(void)
Generate SW WARM Reset Mcu Domain.
void SOC_waitForFwlUnlock(void)
Wait for Firewall unlock from SBL. The function polls for a Software defined Magic number at the PSRA...
int32_t SOC_moduleGetClockFrequency(uint32_t moduleId, uint32_t clkId, uint64_t *clkRate)
Get module clock frequency.
uint32_t SOC_getWarmResetCauseMainDomain(void)
Get the reset reason source for Main Domain.
int32_t SOC_isHsDevice(void)
Check the device is HS or not.
void SOC_waitMainDomainReset(void)
Wait for main domain reset to complete.
void * SOC_phyToVirt(uint64_t phyAddr)
Physical to Virtual (CPU) address translation function.
Structure containing the CPU Info such as CPU ID and Cluster Group ID.
Definition: CpuIdP.h:57
uint32_t value
Definition: tisci_otp_revision.h:2
int32_t SOC_setPSCState(uint32_t instNum, uint32_t domainNum, uint32_t moduleNum, uint32_t pscState)
Set PSC (Power Sleep Controller) state.
uint64_t SOC_getSelfCpuClk(void)
Get the clock frequency in Hz of the CPU on which the driver is running.
int32_t SOC_enableResetIsolation(uint32_t main2McuIsolation, uint32_t mcu2MainIsolation, uint32_t debugIsolationEnable)
Enable reset isolation of MCU domain for safety applications.
void SOC_generateSwWarmResetMainDomain(void)
Generate SW Warm Reset Main Domain.
void SOC_generateSwPORResetMainDomain(void)
Generate SW POR Reset Main Domain.
void SOC_controlModuleLockMMR(uint32_t domainId, uint32_t partition)
Lock control module partition to prevent writes into control MMRs.
int32_t SOC_moduleClockEnable(uint32_t moduleId, uint32_t enable)
Enable clock to specified module.
void SOC_setDevStat(uint32_t bootMode)
Change boot mode by setting devstat register.
int32_t SOC_getPSCState(uint32_t instNum, uint32_t domainNum, uint32_t moduleNum, uint32_t *domainState, uint32_t *moduleState)
Get PSC (Power Sleep Controller) state.
const char * SOC_getCoreName(uint16_t coreId)
Convert a core ID to a user readable name.
uint32_t SOC_isR5FDualCoreMode(CSL_ArmR5CPUInfo *cpuInfo)
Return R5SS supporting single or dual core mode.
void SOC_setEpwmTbClk(uint32_t epwmInstance, uint32_t enable)
Enable or disable ePWM time base clock from Control MMR.
uint32_t SOC_getWarmResetCauseMcuDomain(void)
Get the reset reason source for Mcu Domain.
@ enable
Definition: iPtcpDrv.h:69