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AM243x MCU+ SDK
08.06.00
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Go to the documentation of this file.
34 #ifndef SDLR_ECC_RAM_H_
35 #define SDLR_ECC_RAM_H_
49 volatile uint8_t Resv_16[16];
64 #define SDL_ECC_RAM_WRAP_REV (0x00000010U)
65 #define SDL_ECC_RAM_CTRL (0x00000014U)
66 #define SDL_ECC_RAM_ERR_CTRL1 (0x00000018U)
67 #define SDL_ECC_RAM_ERR_CTRL2 (0x0000001CU)
68 #define SDL_ECC_RAM_ERR_STAT1 (0x00000020U)
69 #define SDL_ECC_RAM_ERR_STAT2 (0x00000024U)
70 #define SDL_ECC_RAM_ERR_STAT3 (0x00000028U)
79 #define SDL_ECC_RAM_WRAP_REV_SCHEME_MASK (0xC0000000U)
80 #define SDL_ECC_RAM_WRAP_REV_SCHEME_SHIFT (0x0000001EU)
81 #define SDL_ECC_RAM_WRAP_REV_SCHEME_MAX (0x00000003U)
83 #define SDL_ECC_RAM_WRAP_REV_BU_MASK (0x30000000U)
84 #define SDL_ECC_RAM_WRAP_REV_BU_SHIFT (0x0000001CU)
85 #define SDL_ECC_RAM_WRAP_REV_BU_MAX (0x00000003U)
87 #define SDL_ECC_RAM_WRAP_REV_MODULE_ID_MASK (0x0FFF0000U)
88 #define SDL_ECC_RAM_WRAP_REV_MODULE_ID_SHIFT (0x00000010U)
89 #define SDL_ECC_RAM_WRAP_REV_MODULE_ID_MAX (0x00000FFFU)
91 #define SDL_ECC_RAM_WRAP_REV_REVRTL_MASK (0x0000F800U)
92 #define SDL_ECC_RAM_WRAP_REV_REVRTL_SHIFT (0x0000000BU)
93 #define SDL_ECC_RAM_WRAP_REV_REVRTL_MAX (0x0000001FU)
95 #define SDL_ECC_RAM_WRAP_REV_REVMAJ_MASK (0x00000700U)
96 #define SDL_ECC_RAM_WRAP_REV_REVMAJ_SHIFT (0x00000008U)
97 #define SDL_ECC_RAM_WRAP_REV_REVMAJ_MAX (0x00000007U)
99 #define SDL_ECC_RAM_WRAP_REV_CUSTOM_MASK (0x000000C0U)
100 #define SDL_ECC_RAM_WRAP_REV_CUSTOM_SHIFT (0x00000006U)
101 #define SDL_ECC_RAM_WRAP_REV_CUSTOM_MAX (0x00000003U)
103 #define SDL_ECC_RAM_WRAP_REV_REVMIN_MASK (0x0000003FU)
104 #define SDL_ECC_RAM_WRAP_REV_REVMIN_SHIFT (0x00000000U)
105 #define SDL_ECC_RAM_WRAP_REV_REVMIN_MAX (0x0000003FU)
109 #define SDL_ECC_RAM_CTRL_ECC_ENABLE_MASK (0x00000001U)
110 #define SDL_ECC_RAM_CTRL_ECC_ENABLE_SHIFT (0x00000000U)
111 #define SDL_ECC_RAM_CTRL_ECC_ENABLE_MAX (0x00000001U)
113 #define SDL_ECC_RAM_CTRL_ECC_CHECK_MASK (0x00000002U)
114 #define SDL_ECC_RAM_CTRL_ECC_CHECK_SHIFT (0x00000001U)
115 #define SDL_ECC_RAM_CTRL_ECC_CHECK_MAX (0x00000001U)
117 #define SDL_ECC_RAM_CTRL_ENABLE_RMW_MASK (0x00000004U)
118 #define SDL_ECC_RAM_CTRL_ENABLE_RMW_SHIFT (0x00000002U)
119 #define SDL_ECC_RAM_CTRL_ENABLE_RMW_MAX (0x00000001U)
121 #define SDL_ECC_RAM_CTRL_FORCE_SEC_MASK (0x00000008U)
122 #define SDL_ECC_RAM_CTRL_FORCE_SEC_SHIFT (0x00000003U)
123 #define SDL_ECC_RAM_CTRL_FORCE_SEC_MAX (0x00000001U)
125 #define SDL_ECC_RAM_CTRL_FORCE_DED_MASK (0x00000010U)
126 #define SDL_ECC_RAM_CTRL_FORCE_DED_SHIFT (0x00000004U)
127 #define SDL_ECC_RAM_CTRL_FORCE_DED_MAX (0x00000001U)
129 #define SDL_ECC_RAM_CTRL_FORCE_N_ROW_MASK (0x00000020U)
130 #define SDL_ECC_RAM_CTRL_FORCE_N_ROW_SHIFT (0x00000005U)
131 #define SDL_ECC_RAM_CTRL_FORCE_N_ROW_MAX (0x00000001U)
133 #define SDL_ECC_RAM_CTRL_ERROR_ONCE_MASK (0x00000040U)
134 #define SDL_ECC_RAM_CTRL_ERROR_ONCE_SHIFT (0x00000006U)
135 #define SDL_ECC_RAM_CTRL_ERROR_ONCE_MAX (0x00000001U)
137 #define SDL_ECC_RAM_CTRL_CHECK_PARITY_MASK (0x00000080U)
138 #define SDL_ECC_RAM_CTRL_CHECK_PARITY_SHIFT (0x00000007U)
139 #define SDL_ECC_RAM_CTRL_CHECK_PARITY_MAX (0x00000001U)
141 #define SDL_ECC_RAM_CTRL_CHECK_SVBUS_TIMEOUT_MASK (0x00000100U)
142 #define SDL_ECC_RAM_CTRL_CHECK_SVBUS_TIMEOUT_SHIFT (0x00000008U)
143 #define SDL_ECC_RAM_CTRL_CHECK_SVBUS_TIMEOUT_MAX (0x00000001U)
147 #define SDL_ECC_RAM_ERR_CTRL1_ECC_ROW_MASK (0xFFFFFFFFU)
148 #define SDL_ECC_RAM_ERR_CTRL1_ECC_ROW_SHIFT (0x00000000U)
149 #define SDL_ECC_RAM_ERR_CTRL1_ECC_ROW_MAX (0xFFFFFFFFU)
153 #define SDL_ECC_RAM_ERR_CTRL2_ECC_BIT1_MASK (0x0000FFFFU)
154 #define SDL_ECC_RAM_ERR_CTRL2_ECC_BIT1_SHIFT (0x00000000U)
155 #define SDL_ECC_RAM_ERR_CTRL2_ECC_BIT1_MAX (0x0000FFFFU)
157 #define SDL_ECC_RAM_ERR_CTRL2_ECC_BIT2_MASK (0xFFFF0000U)
158 #define SDL_ECC_RAM_ERR_CTRL2_ECC_BIT2_SHIFT (0x00000010U)
159 #define SDL_ECC_RAM_ERR_CTRL2_ECC_BIT2_MAX (0x0000FFFFU)
163 #define SDL_ECC_RAM_ERR_STAT1_ECC_SEC_MASK (0x00000003U)
164 #define SDL_ECC_RAM_ERR_STAT1_ECC_SEC_SHIFT (0x00000000U)
165 #define SDL_ECC_RAM_ERR_STAT1_ECC_SEC_MAX (0x00000003U)
167 #define SDL_ECC_RAM_ERR_STAT1_ECC_DED_MASK (0x0000000CU)
168 #define SDL_ECC_RAM_ERR_STAT1_ECC_DED_SHIFT (0x00000002U)
169 #define SDL_ECC_RAM_ERR_STAT1_ECC_DED_MAX (0x00000003U)
171 #define SDL_ECC_RAM_ERR_STAT1_ECC_OTHER_MASK (0x00000010U)
172 #define SDL_ECC_RAM_ERR_STAT1_ECC_OTHER_SHIFT (0x00000004U)
173 #define SDL_ECC_RAM_ERR_STAT1_ECC_OTHER_MAX (0x00000001U)
175 #define SDL_ECC_RAM_ERR_STAT1_PARITY_ERR_MASK (0x00000060U)
176 #define SDL_ECC_RAM_ERR_STAT1_PARITY_ERR_SHIFT (0x00000005U)
177 #define SDL_ECC_RAM_ERR_STAT1_PARITY_ERR_MAX (0x00000003U)
179 #define SDL_ECC_RAM_ERR_STAT1_CTR_REG_ERR_MASK (0x00000080U)
180 #define SDL_ECC_RAM_ERR_STAT1_CTR_REG_ERR_SHIFT (0x00000007U)
181 #define SDL_ECC_RAM_ERR_STAT1_CTR_REG_ERR_MAX (0x00000001U)
183 #define SDL_ECC_RAM_ERR_STAT1_CLR_ECC_SEC_MASK (0x00000300U)
184 #define SDL_ECC_RAM_ERR_STAT1_CLR_ECC_SEC_SHIFT (0x00000008U)
185 #define SDL_ECC_RAM_ERR_STAT1_CLR_ECC_SEC_MAX (0x00000003U)
187 #define SDL_ECC_RAM_ERR_STAT1_CLR_ECC_DED_MASK (0x00000C00U)
188 #define SDL_ECC_RAM_ERR_STAT1_CLR_ECC_DED_SHIFT (0x0000000AU)
189 #define SDL_ECC_RAM_ERR_STAT1_CLR_ECC_DED_MAX (0x00000003U)
191 #define SDL_ECC_RAM_ERR_STAT1_CLR_ECC_OTHER_MASK (0x00001000U)
192 #define SDL_ECC_RAM_ERR_STAT1_CLR_ECC_OTHER_SHIFT (0x0000000CU)
193 #define SDL_ECC_RAM_ERR_STAT1_CLR_ECC_OTHER_MAX (0x00000001U)
195 #define SDL_ECC_RAM_ERR_STAT1_CLR_PARITY_ERR_MASK (0x00006000U)
196 #define SDL_ECC_RAM_ERR_STAT1_CLR_PARITY_ERR_SHIFT (0x0000000DU)
197 #define SDL_ECC_RAM_ERR_STAT1_CLR_PARITY_ERR_MAX (0x00000003U)
199 #define SDL_ECC_RAM_ERR_STAT1_CLR_CTRL_REG_ERR_MASK (0x00008000U)
200 #define SDL_ECC_RAM_ERR_STAT1_CLR_CTRL_REG_ERR_SHIFT (0x0000000FU)
201 #define SDL_ECC_RAM_ERR_STAT1_CLR_CTRL_REG_ERR_MAX (0x00000001U)
203 #define SDL_ECC_RAM_ERR_STAT1_ECC_BIT1_MASK (0xFFFF0000U)
204 #define SDL_ECC_RAM_ERR_STAT1_ECC_BIT1_SHIFT (0x00000010U)
205 #define SDL_ECC_RAM_ERR_STAT1_ECC_BIT1_MAX (0x0000FFFFU)
209 #define SDL_ECC_RAM_ERR_STAT2_ECC_ROW_MASK (0xFFFFFFFFU)
210 #define SDL_ECC_RAM_ERR_STAT2_ECC_ROW_SHIFT (0x00000000U)
211 #define SDL_ECC_RAM_ERR_STAT2_ECC_ROW_MAX (0xFFFFFFFFU)
215 #define SDL_ECC_RAM_ERR_STAT3_WB_PEND_MASK (0x00000001U)
216 #define SDL_ECC_RAM_ERR_STAT3_WB_PEND_SHIFT (0x00000000U)
217 #define SDL_ECC_RAM_ERR_STAT3_WB_PEND_MAX (0x00000001U)
219 #define SDL_ECC_RAM_ERR_STAT3_SVBUS_TIMEOUT_ERR_MASK (0x00000002U)
220 #define SDL_ECC_RAM_ERR_STAT3_SVBUS_TIMEOUT_ERR_SHIFT (0x00000001U)
221 #define SDL_ECC_RAM_ERR_STAT3_SVBUS_TIMEOUT_ERR_MAX (0x00000001U)
223 #define SDL_ECC_RAM_ERR_STAT3_CLR_SVBUS_TIMEOUT_ERR_MASK (0x00000200U)
224 #define SDL_ECC_RAM_ERR_STAT3_CLR_SVBUS_TIMEOUT_ERR_SHIFT (0x00000009U)
225 #define SDL_ECC_RAM_ERR_STAT3_CLR_SVBUS_TIMEOUT_ERR_MAX (0x00000001U)
volatile uint32_t ERR_STAT1
Definition: sdlr_ecc_ram.h:54
volatile uint32_t ERR_STAT2
Definition: sdlr_ecc_ram.h:55
Definition: sdlr_ecc_ram.h:48
volatile uint32_t WRAP_REV
Definition: sdlr_ecc_ram.h:50
volatile uint32_t ERR_STAT3
Definition: sdlr_ecc_ram.h:56
volatile uint32_t CTRL
Definition: sdlr_ecc_ram.h:51
volatile uint32_t ERR_CTRL1
Definition: sdlr_ecc_ram.h:52
This file contains the macro definations for Register layer.
volatile uint32_t ERR_CTRL2
Definition: sdlr_ecc_ram.h:53