50 #ifndef INCLUDE_SDL_ECC_SOC_H_
51 #define INCLUDE_SDL_ECC_SOC_H_
56 #include <sdl/include/sdl_types.h>
57 #if defined(SOC_AM64X)
58 #include <sdl/esm/soc/am64x/sdl_esm_core.h>
60 #if defined(SOC_AM243X)
61 #include <sdl/esm/soc/am243x/sdl_esm_core.h>
64 #include <sdl/include/am64x_am243x/sdlr_soc_ecc_aggr.h>
65 #include <sdl/include/am64x_am243x/sdlr_intr_esm0.h>
66 #include <sdl/include/am64x_am243x/sdlr_soc_baseaddress.h>
67 #include <sdl/include/am64x_am243x/sdlr_intr_mcu_esm0.h>
75 #define SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
76 #define SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RAM_IDS_TOTAL_ENTRIES (27U)
77 #define SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RAM_IDS_TOTAL_ENTRIES (27U)
78 #define SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RAM_IDS_TOTAL_ENTRIES (24U)
79 #define SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (9U)
80 #define SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (9U)
81 #define SDL_DMASS0_DMSS_AM64_ECCAGGR_RAM_IDS_TOTAL_ENTRIES (27U)
82 #define SDL_MSRAM_256K2_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
83 #define SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
84 #define SDL_ADC0_ADC12_CORE_FIFO_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (2U)
85 #define SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES (1U)
86 #define SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES (1U)
87 #define SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (8U)
88 #define SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (3U)
89 #define SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (4U)
90 #define SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (4U)
91 #define SDL_VTM0_K3VTM_N16FFC_ECCAGGR_RAM_IDS_TOTAL_ENTRIES (0U)
92 #define SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (12U)
93 #define SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_RAM_IDS_TOTAL_ENTRIES (4U)
94 #define SDL_USB0_USB3P0SS64_16FFC_USB3P0SS64_CORE_A_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
95 #define SDL_DMSC0_DMSC_LITE_RAM_IDS_TOTAL_ENTRIES (4U)
96 #define SDL_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
97 #define SDL_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
98 #define SDL_MSRAM_256K3_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
99 #define SDL_MSRAM_256K5_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
100 #define SDL_MSRAM_256K4_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
101 #define SDL_MSRAM_256K7_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
102 #define SDL_MSRAM_256K6_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
103 #define SDL_ECC_AGGR1_RAM_IDS_TOTAL_ENTRIES (1U)
104 #define SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
105 #define SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
106 #define SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES (1U)
107 #define SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES (1U)
108 #define SDL_MCU_M4FSS0_BLAZAR_ECC_RAM_IDS_TOTAL_ENTRIES (2U)
109 #define SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (29U)
110 #define SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (29U)
111 #define SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (29U)
112 #define SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (29U)
113 #define SDL_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES (3U)
114 #define SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_RAM_IDS_TOTAL_ENTRIES (4U)
115 #define SDL_ECC_Base_Address_TOTAL_ENTRIES (40U)
128 { SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_RAM_ID, 0x00000000u,
129 SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_RAM_SIZE, 4u,
130 SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_ROW_WIDTH, ((bool)
true) },
139 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_ID, 0u,
140 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_SIZE, 4u,
141 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
142 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_ID, 0u,
143 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_SIZE, 4u,
144 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
145 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_ID, 0u,
146 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_SIZE, 4u,
147 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
148 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_ID, 0u,
149 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_SIZE, 4u,
150 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
151 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_ID, 0u,
152 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_SIZE, 4u,
153 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
154 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_ID, 0u,
155 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_SIZE, 4u,
156 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
157 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
158 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
159 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
160 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
161 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
162 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
163 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
164 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
165 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
166 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
167 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
168 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
169 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID, 0u,
170 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_SIZE, 4u,
171 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
172 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID, 0u,
173 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_SIZE, 4u,
174 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
175 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_ID, 0u,
176 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_SIZE, 4u,
177 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
178 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_ID, 0u,
179 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_SIZE, 4u,
180 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
181 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
182 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
183 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
184 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
185 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
186 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
187 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
188 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
189 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
190 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
191 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
192 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
193 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_ID, 0u,
194 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_SIZE, 4u,
195 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
196 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
197 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
198 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
199 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
200 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
201 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
202 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
203 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
204 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
205 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
206 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
207 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
208 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID, 0u,
209 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_SIZE, 4u,
210 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
211 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID, 0u,
212 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_SIZE, 4u,
213 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
214 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID, 0u,
215 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_SIZE, 4u,
216 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
217 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID, 0u,
218 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_SIZE, 4u,
219 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
228 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_ID, 0u,
229 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_SIZE, 4u,
230 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
231 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_ID, 0u,
232 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_SIZE, 4u,
233 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
234 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_ID, 0u,
235 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_SIZE, 4u,
236 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
237 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_ID, 0u,
238 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_SIZE, 4u,
239 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
240 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_ID, 0u,
241 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_SIZE, 4u,
242 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
243 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_ID, 0u,
244 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_SIZE, 4u,
245 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
246 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
247 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
248 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
249 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
250 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
251 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
252 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
253 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
254 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
255 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
256 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
257 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
258 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID, 0u,
259 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_SIZE, 4u,
260 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
261 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID, 0u,
262 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_SIZE, 4u,
263 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
264 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_ID, 0u,
265 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_SIZE, 4u,
266 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
267 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_ID, 0u,
268 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_SIZE, 4u,
269 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
270 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
271 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
272 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
273 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
274 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
275 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
276 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
277 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
278 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
279 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
280 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
281 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
282 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_ID, 0u,
283 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_SIZE, 4u,
284 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
285 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
286 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
287 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
288 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
289 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
290 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
291 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
292 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
293 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
294 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
295 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
296 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
297 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID, 0u,
298 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_SIZE, 4u,
299 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
300 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID, 0u,
301 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_SIZE, 4u,
302 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
303 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID, 0u,
304 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_SIZE, 4u,
305 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
306 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID, 0u,
307 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_SIZE, 4u,
308 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
317 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID, 0u,
318 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_SIZE, 4u,
319 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
320 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID, 0u,
321 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_SIZE, 4u,
322 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
323 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID, 0u,
324 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_SIZE, 4u,
325 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
326 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID, 0u,
327 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_SIZE, 4u,
328 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
329 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_RAM_ID, 0u,
330 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_RAM_SIZE, 4u,
331 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
332 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_RAM_ID, 0u,
333 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_RAM_SIZE, 4u,
334 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
335 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_RAM_ID, 0u,
336 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_RAM_SIZE, 4u,
337 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
338 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_RAM_ID, 0u,
339 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_RAM_SIZE, 4u,
340 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
341 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_RAM_ID, 0u,
342 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_RAM_SIZE, 4u,
343 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
344 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_RAM_ID, 0u,
345 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_RAM_SIZE, 4u,
346 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
347 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_RAM_ID, 0u,
348 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_RAM_SIZE, 4u,
349 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
350 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_RAM_ID, 0u,
351 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_RAM_SIZE, 4u,
352 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
353 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_RAM_ID, 0u,
354 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_RAM_SIZE, 4u,
355 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
356 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_RAM_ID, 0u,
357 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_RAM_SIZE, 4u,
358 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
359 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_RAM_ID, 0u,
360 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_RAM_SIZE, 4u,
361 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
362 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_RAM_ID, 0u,
363 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_RAM_SIZE, 4u,
364 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
365 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_RAM_ID, 0u,
366 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_RAM_SIZE, 4u,
367 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
368 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_RAM_ID, 0u,
369 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_RAM_SIZE, 4u,
370 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
371 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_RAM_ID, 0u,
372 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_RAM_SIZE, 4u,
373 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
374 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_RAM_ID, 0u,
375 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_RAM_SIZE, 4u,
376 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
377 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_RAM_ID, 0u,
378 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_RAM_SIZE, 4u,
379 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
380 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_RAM_ID, 0u,
381 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_RAM_SIZE, 4u,
382 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
383 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_RAM_ID, 0u,
384 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_RAM_SIZE, 4u,
385 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
386 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_RAM_ID, 0u,
387 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_RAM_SIZE, 4u,
388 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_ROW_WIDTH, ((bool)
false) },
397 { SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_RAM_ID, 0u,
398 SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_RAM_SIZE, 4u,
399 SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_ROW_WIDTH, ((bool)
false) },
400 { SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_RAM_ID, 0u,
401 SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_RAM_SIZE, 4u,
402 SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_ROW_WIDTH, ((bool)
false) },
403 { SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_RAM_ID, 0u,
404 SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_RAM_SIZE, 4u,
405 SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_ROW_WIDTH, ((bool)
false) },
406 { SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_RAM_ID, 0u,
407 SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_RAM_SIZE, 4u,
408 SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_ROW_WIDTH, ((bool)
false) },
409 { SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_RAM_ID, 0u,
410 SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_RAM_SIZE, 4u,
411 SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_ROW_WIDTH, ((bool)
false) },
412 { SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU0_PDSP_IRAM_ECC_RAM_ID, 0u,
413 SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU0_PDSP_IRAM_ECC_RAM_SIZE, 4u,
414 SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU0_PDSP_IRAM_ECC_ROW_WIDTH, ((bool)
false) },
415 { SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU1_PDSP_IRAM_ECC_RAM_ID, 0u,
416 SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU1_PDSP_IRAM_ECC_RAM_SIZE, 4u,
417 SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU1_PDSP_IRAM_ECC_ROW_WIDTH, ((bool)
false) },
418 { SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX0_IRAM_ECC_RAM_ID, 0u,
419 SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX0_IRAM_ECC_RAM_SIZE, 4u,
420 SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX0_IRAM_ECC_ROW_WIDTH, ((bool)
false) },
421 { SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX1_IRAM_ECC_RAM_ID, 0u,
422 SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX1_IRAM_ECC_RAM_SIZE, 4u,
423 SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX1_IRAM_ECC_ROW_WIDTH, ((bool)
false) },
432 { SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_RAM_ID, 0u,
433 SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_RAM_SIZE, 4u,
434 SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_ROW_WIDTH, ((bool)
false) },
435 { SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_RAM_ID, 0u,
436 SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_RAM_SIZE, 4u,
437 SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_ROW_WIDTH, ((bool)
false) },
438 { SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_RAM_ID, 0u,
439 SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_RAM_SIZE, 4u,
440 SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_ROW_WIDTH, ((bool)
false) },
441 { SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_RAM_ID, 0u,
442 SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_RAM_SIZE, 4u,
443 SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_ROW_WIDTH, ((bool)
false) },
444 { SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_RAM_ID, 0u,
445 SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_RAM_SIZE, 4u,
446 SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_ROW_WIDTH, ((bool)
false) },
447 { SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU0_PDSP_IRAM_ECC_RAM_ID, 0u,
448 SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU0_PDSP_IRAM_ECC_RAM_SIZE, 4u,
449 SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU0_PDSP_IRAM_ECC_ROW_WIDTH, ((bool)
false) },
450 { SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU1_PDSP_IRAM_ECC_RAM_ID, 0u,
451 SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU1_PDSP_IRAM_ECC_RAM_SIZE, 4u,
452 SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU1_PDSP_IRAM_ECC_ROW_WIDTH, ((bool)
false) },
453 { SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX0_IRAM_ECC_RAM_ID, 0u,
454 SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX0_IRAM_ECC_RAM_SIZE, 4u,
455 SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX0_IRAM_ECC_ROW_WIDTH, ((bool)
false) },
456 { SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX1_IRAM_ECC_RAM_ID, 0u,
457 SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX1_IRAM_ECC_RAM_SIZE, 4u,
458 SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX1_IRAM_ECC_ROW_WIDTH, ((bool)
false) },
467 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_CFG_CONFIG_RAM_ID, 0u,
468 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_CFG_CONFIG_RAM_SIZE, 4u,
469 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_CFG_CONFIG_ROW_WIDTH, ((bool)
false) },
470 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_CFG_STATE_RAM_ID, 0u,
471 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_CFG_STATE_RAM_SIZE, 4u,
472 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_CFG_STATE_ROW_WIDTH, ((bool)
false) },
473 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_TPCFIFO_F0_RAM_ID, 0u,
474 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_TPCFIFO_F0_RAM_SIZE, 4u,
475 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_TPCFIFO_F0_ROW_WIDTH, ((bool)
false) },
476 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_TPCFIFO_F1_RAM_ID, 0u,
477 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_TPCFIFO_F1_RAM_SIZE, 4u,
478 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_TPCFIFO_F1_ROW_WIDTH, ((bool)
false) },
479 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_RPCFIFO_F0_RAM_ID, 0u,
480 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_RPCFIFO_F0_RAM_SIZE, 4u,
481 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_RPCFIFO_F0_ROW_WIDTH, ((bool)
false) },
482 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_RPCFIFO_F1_RAM_ID, 0u,
483 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_RPCFIFO_F1_RAM_SIZE, 4u,
484 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_RPCFIFO_F1_ROW_WIDTH, ((bool)
false) },
485 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_RPCFIFO_WC_RAM_ID, 0u,
486 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_RPCFIFO_WC_RAM_SIZE, 4u,
487 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_RPCFIFO_WC_ROW_WIDTH, ((bool)
false) },
488 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_STATS_STST0_RAM_ID, 0u,
489 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_STATS_STST0_RAM_SIZE, 4u,
490 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_STATS_STST0_ROW_WIDTH, ((bool)
false) },
491 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_STATS_STSR0_RAM_ID, 0u,
492 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_STATS_STSR0_RAM_SIZE, 4u,
493 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_STATS_STSR0_ROW_WIDTH, ((bool)
false) },
494 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_RINGOCC_CNTR_RAM_ID, 0u,
495 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_RINGOCC_CNTR_RAM_SIZE, 4u,
496 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_RINGOCC_CNTR_ROW_WIDTH, ((bool)
false) },
497 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_CFG_CONFIG_RAM_ID, 0u,
498 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_CFG_CONFIG_RAM_SIZE, 4u,
499 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_CFG_CONFIG_ROW_WIDTH, ((bool)
false) },
500 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_CFG_STATE_RAM_ID, 0u,
501 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_CFG_STATE_RAM_SIZE, 4u,
502 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_CFG_STATE_ROW_WIDTH, ((bool)
false) },
503 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_PCFIFO_DFIFO_F0_RAM_ID, 0u,
504 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_PCFIFO_DFIFO_F0_RAM_SIZE, 4u,
505 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_PCFIFO_DFIFO_F0_ROW_WIDTH, ((bool)
false) },
506 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_PCFIFO_DFIFO_F1_RAM_ID, 0u,
507 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_PCFIFO_DFIFO_F1_RAM_SIZE, 4u,
508 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_PCFIFO_DFIFO_F1_ROW_WIDTH, ((bool)
false) },
509 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_TPCFIFO_F0_RAM_ID, 0u,
510 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_TPCFIFO_F0_RAM_SIZE, 4u,
511 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_TPCFIFO_F0_ROW_WIDTH, ((bool)
false) },
512 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_TPCFIFO_F1_RAM_ID, 0u,
513 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_TPCFIFO_F1_RAM_SIZE, 4u,
514 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_TPCFIFO_F1_ROW_WIDTH, ((bool)
false) },
515 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_RPCFIFO_F0_RAM_ID, 0u,
516 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_RPCFIFO_F0_RAM_SIZE, 4u,
517 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_RPCFIFO_F0_ROW_WIDTH, ((bool)
false) },
518 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_RPCFIFO_F1_RAM_ID, 0u,
519 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_RPCFIFO_F1_RAM_SIZE, 4u,
520 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_RPCFIFO_F1_ROW_WIDTH, ((bool)
false) },
521 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_RPCFIFO_WC_RAM_ID, 0u,
522 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_RPCFIFO_WC_RAM_SIZE, 4u,
523 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_RPCFIFO_WC_ROW_WIDTH, ((bool)
false) },
524 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_STATS_STST0_RAM_ID, 0u,
525 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_STATS_STST0_RAM_SIZE, 4u,
526 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_STATS_STST0_ROW_WIDTH, ((bool)
false) },
527 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_STATS_STSR0_RAM_ID, 0u,
528 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_STATS_STSR0_RAM_SIZE, 4u,
529 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_STATS_STSR0_ROW_WIDTH, ((bool)
false) },
530 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_RINGOCC_CNTR_RAM_ID, 0u,
531 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_RINGOCC_CNTR_RAM_SIZE, 4u,
532 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_RINGOCC_CNTR_ROW_WIDTH, ((bool)
false) },
533 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_INTAGGR_STATREG_SR_SPRAM_184X128_SWW_SR_RAM_ID, 0u,
534 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_INTAGGR_STATREG_SR_SPRAM_184X128_SWW_SR_RAM_SIZE, 4u,
535 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_INTAGGR_STATREG_SR_SPRAM_184X128_SWW_SR_ROW_WIDTH, ((bool)
false) },
536 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_INTAGGR_COMMON_IM_TPRAM_2250X34_SWW_SR_RAM_ID, 0u,
537 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_INTAGGR_COMMON_IM_TPRAM_2250X34_SWW_SR_RAM_SIZE, 4u,
538 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_INTAGGR_COMMON_IM_TPRAM_2250X34_SWW_SR_ROW_WIDTH, ((bool)
false) },
539 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_IPCSS_RINGACC_STRAM_RAM_ID, 0u,
540 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_IPCSS_RINGACC_STRAM_RAM_SIZE, 4u,
541 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_IPCSS_RINGACC_STRAM_ROW_WIDTH, ((bool)
false) },
542 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_IPCSS_SEC_PROXY_BUF_STRAM_RAM_ID, 0u,
543 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_IPCSS_SEC_PROXY_BUF_STRAM_RAM_SIZE, 4u,
544 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_IPCSS_SEC_PROXY_BUF_STRAM_ROW_WIDTH, ((bool)
false) },
545 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_IPCSS_SEC_PROXY_BUF_BUFRAM_RAM_ID, 0u,
546 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_IPCSS_SEC_PROXY_BUF_BUFRAM_RAM_SIZE, 4u,
547 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_IPCSS_SEC_PROXY_BUF_BUFRAM_ROW_WIDTH, ((bool)
false) },
556 { SDL_MSRAM_256K2_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_ID, 0x70080000u,
557 SDL_MSRAM_256K2_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_SIZE, 4u,
558 SDL_MSRAM_256K2_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_ROW_WIDTH, ((bool)
true) },
567 { SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_RAM_ID, 0u,
568 SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_RAM_SIZE, 4u,
569 SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_ROW_WIDTH, ((bool)
false) },
578 { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_ALE_RAM_RAM_ID, 0u,
579 SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_ALE_RAM_RAM_SIZE, 4u,
580 SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_ALE_RAM_ROW_WIDTH, ((bool)
false) },
581 { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P0_RX_FIFO_RAM_ID, 0u,
582 SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P0_RX_FIFO_RAM_SIZE, 4u,
583 SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P0_RX_FIFO_ROW_WIDTH, ((bool)
false) },
584 { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P0_TX_FIFO_RAM_ID, 0u,
585 SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P0_TX_FIFO_RAM_SIZE, 4u,
586 SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P0_TX_FIFO_ROW_WIDTH, ((bool)
false) },
587 { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P1_RX_FIFO_RAM_ID, 0u,
588 SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P1_RX_FIFO_RAM_SIZE, 4u,
589 SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P1_RX_FIFO_ROW_WIDTH, ((bool)
false) },
590 { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P1_TX_FIFO_RAM_ID, 0u,
591 SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P1_TX_FIFO_RAM_SIZE, 4u,
592 SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P1_TX_FIFO_ROW_WIDTH, ((bool)
false) },
593 { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P2_RX_FIFO_RAM_ID, 0u,
594 SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P2_RX_FIFO_RAM_SIZE, 4u,
595 SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P2_RX_FIFO_ROW_WIDTH, ((bool)
false) },
596 { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P2_TX_FIFO_RAM_ID, 0u,
597 SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P2_TX_FIFO_RAM_SIZE, 4u,
598 SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P2_TX_FIFO_ROW_WIDTH, ((bool)
false) },
599 { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_EST_RAM_RAM_ID, 0u,
600 SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_EST_RAM_RAM_SIZE, 4u,
601 SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_EST_RAM_ROW_WIDTH, ((bool)
false) },
609 { SDL_ADC0_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_RAM_ID, 0u,
610 SDL_ADC0_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_RAM_SIZE, 4u,
611 SDL_ADC0_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_ROW_WIDTH, ((bool)
false) },
612 { SDL_ADC0_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_RAM_ID, 0u,
613 SDL_ADC0_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_RAM_SIZE, 4u,
614 SDL_ADC0_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_ROW_WIDTH, ((bool)
false) },
623 { SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_ID, 0u,
624 SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_SIZE, 4u,
625 SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_ROW_WIDTH, ((bool)
false) },
634 { SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_ID, 0u,
635 SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_SIZE, 4u,
636 SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_ROW_WIDTH, ((bool)
false) },
645 { SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_ICB_RAMECC_RAM_ID, 0u,
646 SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_ICB_RAMECC_RAM_SIZE, 4u,
647 SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_ICB_RAMECC_ROW_WIDTH, ((bool)
false) },
648 { SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_ITE_RAMECC_RAM_ID, 0u,
649 SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_ITE_RAMECC_RAM_SIZE, 4u,
650 SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_ITE_RAMECC_ROW_WIDTH, ((bool)
false) },
651 { SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_LPI_RAMECC_RAM_ID, 0u,
652 SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_LPI_RAMECC_RAM_SIZE, 4u,
653 SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_LPI_RAMECC_ROW_WIDTH, ((bool)
false) },
662 { SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXIMFIFO_RAM_ID, 0u,
663 SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXIMFIFO_RAM_SIZE, 4u,
664 SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXIMFIFO_ROW_WIDTH, ((bool)
false) },
665 { SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXISFIFO_RAM_ID, 0u,
666 SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXISFIFO_RAM_SIZE, 4u,
667 SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXISFIFO_ROW_WIDTH, ((bool)
false) },
668 { SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_DIBRAM_RAM_ID, 0u,
669 SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_DIBRAM_RAM_SIZE, 4u,
670 SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_DIBRAM_ROW_WIDTH, ((bool)
false) },
671 { SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID, 0u,
672 SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_SIZE, 4u,
673 SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ROW_WIDTH, ((bool)
false) },
682 { SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_PNPFIFO_RAM_ID, 0u,
683 SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_PNPFIFO_RAM_SIZE, 4u,
684 SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_PNPFIFO_ROW_WIDTH, ((bool)
false) },
685 { SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_RXCPLFIFO_RAM_ID, 0u,
686 SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_RXCPLFIFO_RAM_SIZE, 4u,
687 SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_RXCPLFIFO_ROW_WIDTH, ((bool)
false) },
688 { SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_RPLYBUF_RAM_ID, 0u,
689 SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_RPLYBUF_RAM_SIZE, 4u,
690 SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_RPLYBUF_ROW_WIDTH, ((bool)
false) },
691 { SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXISRODR_RAM_ID, 0u,
692 SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXISRODR_RAM_SIZE, 4u,
693 SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXISRODR_ROW_WIDTH, ((bool)
false) },
703 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
704 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_0_WIDTH },
705 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
706 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_1_WIDTH },
707 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
708 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_2_WIDTH },
709 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
710 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_3_WIDTH },
711 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
712 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_4_WIDTH },
713 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
714 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_5_WIDTH },
724 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
725 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_0_WIDTH },
726 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
727 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_1_WIDTH },
728 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
729 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_2_WIDTH },
730 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
731 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_3_WIDTH },
732 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
733 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_4_WIDTH },
734 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
735 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_5_WIDTH },
736 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
737 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_6_WIDTH },
738 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
739 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_7_WIDTH },
740 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
741 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_8_WIDTH },
742 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
743 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_9_WIDTH },
744 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
745 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_10_WIDTH },
746 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
747 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_11_WIDTH },
748 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
749 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_12_WIDTH },
750 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
751 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_13_WIDTH },
752 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
753 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_14_WIDTH },
754 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
755 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_15_WIDTH },
756 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
757 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_16_WIDTH },
758 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
759 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_17_WIDTH },
760 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
761 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_18_WIDTH },
762 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
763 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_19_WIDTH },
764 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
765 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_20_WIDTH },
766 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
767 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_21_WIDTH },
768 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
769 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_22_WIDTH },
770 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
771 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_23_WIDTH },
772 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
773 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_24_WIDTH },
774 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
775 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_25_WIDTH },
776 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
777 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_26_WIDTH },
778 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
779 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_27_WIDTH },
780 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
781 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_28_WIDTH },
782 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
783 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_29_WIDTH },
784 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
785 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_30_WIDTH },
786 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
787 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_31_WIDTH },
788 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
789 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_32_WIDTH },
790 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
791 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_33_WIDTH },
792 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
793 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_34_WIDTH },
794 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
795 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_35_WIDTH },
796 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
797 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_36_WIDTH },
798 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
799 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_37_WIDTH },
800 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
801 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_38_WIDTH },
802 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
803 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_39_WIDTH },
804 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
805 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_40_WIDTH },
806 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
807 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_41_WIDTH },
808 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
809 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_42_WIDTH },
810 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
811 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_43_WIDTH },
812 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
813 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_44_WIDTH },
814 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
815 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_45_WIDTH },
816 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
817 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_46_WIDTH },
818 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
819 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_47_WIDTH },
820 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
821 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_48_WIDTH },
822 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
823 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_49_WIDTH },
824 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
825 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_50_WIDTH },
826 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
827 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_51_WIDTH },
828 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
829 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_52_WIDTH },
830 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
831 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_53_WIDTH },
832 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
833 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_54_WIDTH },
834 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
835 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_55_WIDTH },
836 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
837 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_56_WIDTH },
838 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
839 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_57_WIDTH },
840 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
841 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_58_WIDTH },
842 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
843 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_59_WIDTH },
844 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
845 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_60_WIDTH },
846 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
847 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_61_WIDTH },
848 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
849 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_62_WIDTH },
850 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
851 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_63_WIDTH },
852 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
853 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_64_WIDTH },
854 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
855 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_65_WIDTH },
856 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
857 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_66_WIDTH },
858 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
859 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_67_WIDTH },
860 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
861 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_68_WIDTH },
862 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
863 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_69_WIDTH },
864 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
865 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_70_WIDTH },
866 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
867 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_71_WIDTH },
868 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
869 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_72_WIDTH },
870 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
871 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_73_WIDTH },
872 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
873 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_74_WIDTH },
874 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
875 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_75_WIDTH },
876 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
877 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_76_WIDTH },
878 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
879 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_77_WIDTH },
880 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
881 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_78_WIDTH },
882 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
883 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_79_WIDTH },
884 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
885 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_80_WIDTH },
886 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
887 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_81_WIDTH },
888 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
889 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_82_WIDTH },
890 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
891 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_83_WIDTH },
892 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
893 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_84_WIDTH },
894 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
895 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_85_WIDTH },
896 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
897 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_86_WIDTH },
898 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
899 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_87_WIDTH },
900 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
901 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_88_WIDTH },
902 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
903 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_89_WIDTH },
904 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
905 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_90_WIDTH },
906 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
907 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_91_WIDTH },
908 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
909 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_92_WIDTH },
910 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
911 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_93_WIDTH },
912 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
913 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_94_WIDTH },
914 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
915 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_95_WIDTH },
916 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
917 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_96_WIDTH },
918 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
919 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_97_WIDTH },
920 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
921 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_98_WIDTH },
922 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
923 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_99_WIDTH },
924 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
925 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_100_WIDTH },
926 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
927 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_101_WIDTH },
928 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
929 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_102_WIDTH },
930 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
931 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_103_WIDTH },
932 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
933 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_104_WIDTH },
934 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
935 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_105_WIDTH },
936 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
937 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_106_WIDTH },
938 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
939 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_107_WIDTH },
940 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
941 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_108_WIDTH },
942 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
943 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_109_WIDTH },
944 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
945 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_110_WIDTH },
946 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
947 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_111_WIDTH },
948 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
949 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_112_WIDTH },
950 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
951 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_113_WIDTH },
952 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
953 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_114_WIDTH },
954 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
955 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_115_WIDTH },
956 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
957 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_116_WIDTH },
958 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
959 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_117_WIDTH },
960 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
961 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_118_WIDTH },
962 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
963 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_119_WIDTH },
964 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
965 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_120_WIDTH },
966 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
967 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_121_WIDTH },
968 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
969 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_122_WIDTH },
970 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
971 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_123_WIDTH },
972 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
973 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_124_WIDTH },
974 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
975 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_125_WIDTH },
976 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
977 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_126_WIDTH },
978 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
979 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_127_WIDTH },
980 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
981 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_128_WIDTH },
982 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
983 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_129_WIDTH },
984 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
985 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_130_WIDTH },
986 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
987 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_131_WIDTH },
988 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
989 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_132_WIDTH },
990 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_133_CHECKER_TYPE,
991 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_133_WIDTH },
992 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_134_CHECKER_TYPE,
993 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_134_WIDTH },
994 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_135_CHECKER_TYPE,
995 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_135_WIDTH },
996 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_136_CHECKER_TYPE,
997 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_136_WIDTH },
998 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_137_CHECKER_TYPE,
999 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_137_WIDTH },
1000 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_138_CHECKER_TYPE,
1001 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_138_WIDTH },
1002 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_139_CHECKER_TYPE,
1003 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_139_WIDTH },
1004 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_140_CHECKER_TYPE,
1005 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_140_WIDTH },
1006 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_141_CHECKER_TYPE,
1007 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_141_WIDTH },
1008 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_142_CHECKER_TYPE,
1009 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_142_WIDTH },
1010 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_143_CHECKER_TYPE,
1011 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_143_WIDTH },
1012 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_144_CHECKER_TYPE,
1013 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_144_WIDTH },
1014 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_145_CHECKER_TYPE,
1015 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_145_WIDTH },
1016 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_146_CHECKER_TYPE,
1017 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_146_WIDTH },
1018 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_147_CHECKER_TYPE,
1019 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_147_WIDTH },
1020 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_148_CHECKER_TYPE,
1021 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_148_WIDTH },
1022 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_149_CHECKER_TYPE,
1023 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_149_WIDTH },
1024 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_150_CHECKER_TYPE,
1025 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_150_WIDTH },
1026 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_151_CHECKER_TYPE,
1027 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_151_WIDTH },
1028 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_152_CHECKER_TYPE,
1029 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_152_WIDTH },
1030 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_153_CHECKER_TYPE,
1031 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_153_WIDTH },
1032 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_154_CHECKER_TYPE,
1033 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_154_WIDTH },
1034 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_155_CHECKER_TYPE,
1035 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_155_WIDTH },
1036 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_156_CHECKER_TYPE,
1037 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_156_WIDTH },
1038 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_157_CHECKER_TYPE,
1039 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_157_WIDTH },
1040 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_158_CHECKER_TYPE,
1041 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_158_WIDTH },
1042 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_159_CHECKER_TYPE,
1043 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_159_WIDTH },
1044 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_160_CHECKER_TYPE,
1045 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_160_WIDTH },
1046 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_161_CHECKER_TYPE,
1047 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_161_WIDTH },
1048 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_162_CHECKER_TYPE,
1049 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_162_WIDTH },
1050 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_163_CHECKER_TYPE,
1051 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_163_WIDTH },
1052 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_164_CHECKER_TYPE,
1053 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_164_WIDTH },
1054 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_165_CHECKER_TYPE,
1055 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_165_WIDTH },
1056 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_166_CHECKER_TYPE,
1057 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_166_WIDTH },
1058 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_167_CHECKER_TYPE,
1059 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_167_WIDTH },
1060 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_168_CHECKER_TYPE,
1061 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_168_WIDTH },
1062 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_169_CHECKER_TYPE,
1063 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_169_WIDTH },
1064 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_170_CHECKER_TYPE,
1065 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_170_WIDTH },
1075 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
1076 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
1077 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
1078 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
1079 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
1080 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
1090 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
1091 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
1092 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
1093 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
1094 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
1095 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
1096 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
1097 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
1098 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
1099 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
1100 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
1101 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
1102 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
1103 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
1104 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
1105 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
1106 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
1107 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
1108 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
1109 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
1110 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
1111 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
1112 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
1113 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
1114 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
1115 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
1116 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
1117 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
1118 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
1119 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
1120 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
1121 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
1122 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
1123 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
1124 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
1125 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
1126 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
1127 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
1128 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
1129 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
1130 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
1131 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
1132 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
1133 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
1134 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
1135 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
1136 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
1137 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
1138 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
1139 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
1140 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
1141 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
1142 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
1143 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
1144 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
1145 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
1146 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
1147 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
1148 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
1149 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
1150 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
1151 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
1152 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
1153 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
1154 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
1155 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
1156 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
1157 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
1158 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
1159 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
1160 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
1161 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
1162 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
1163 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
1164 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
1165 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
1166 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
1167 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
1168 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
1169 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
1170 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
1171 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
1172 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
1173 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
1174 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
1175 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
1176 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
1177 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
1178 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
1179 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
1180 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
1181 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
1182 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
1183 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
1184 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
1185 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
1186 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
1187 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
1188 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
1189 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
1198 { SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKTRAM0_ECC_RAM_ID, 0u,
1199 SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKTRAM0_ECC_RAM_SIZE, 4u,
1200 SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKTRAM0_ECC_ROW_WIDTH, ((bool)
false) },
1201 { SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKTRAM1_ECC_RAM_ID, 0u,
1202 SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKTRAM1_ECC_RAM_SIZE, 4u,
1203 SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKTRAM1_ECC_ROW_WIDTH, ((bool)
false) },
1204 { SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKA_PROG_RAM_ECC_RAM_ID, 0u,
1205 SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKA_PROG_RAM_ECC_RAM_SIZE, 4u,
1206 SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKA_PROG_RAM_ECC_ROW_WIDTH, ((bool)
false) },
1207 { SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK01_ECC_RAM_ID, 0u,
1208 SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK01_ECC_RAM_SIZE, 4u,
1209 SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK01_ECC_ROW_WIDTH, ((bool)
false) },
1210 { SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK23_ECC_RAM_ID, 0u,
1211 SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK23_ECC_RAM_SIZE, 4u,
1212 SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK23_ECC_ROW_WIDTH, ((bool)
false) },
1213 { SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK4_ECC_RAM_ID, 0u,
1214 SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK4_ECC_RAM_SIZE, 4u,
1215 SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK4_ECC_ROW_WIDTH, ((bool)
false) },
1216 { SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK01_ECC_RAM_ID, 0u,
1217 SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK01_ECC_RAM_SIZE, 4u,
1218 SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK01_ECC_ROW_WIDTH, ((bool)
false) },
1219 { SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK23_ECC_RAM_ID, 0u,
1220 SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK23_ECC_RAM_SIZE, 4u,
1221 SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK23_ECC_ROW_WIDTH, ((bool)
false) },
1222 { SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK45_ECC_RAM_ID, 0u,
1223 SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK45_ECC_RAM_SIZE, 4u,
1224 SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK45_ECC_ROW_WIDTH, ((bool)
false) },
1225 { SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK67_ECC_RAM_ID, 0u,
1226 SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK67_ECC_RAM_SIZE, 4u,
1227 SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK67_ECC_ROW_WIDTH, ((bool)
false) },
1228 { SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK89_ECC_RAM_ID, 0u,
1229 SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK89_ECC_RAM_SIZE, 4u,
1230 SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK89_ECC_ROW_WIDTH, ((bool)
false) },
1231 { SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK10_ECC_RAM_ID, 0u,
1232 SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK10_ECC_RAM_SIZE, 4u,
1233 SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK10_ECC_ROW_WIDTH, ((bool)
false) },
1242 { SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_PDMA_AM64_MAIN1_PDMA_CORE_TF0_F0_TPRAM_60X128_SBW_SR_RAM_ID, 0u,
1243 SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_PDMA_AM64_MAIN1_PDMA_CORE_TF0_F0_TPRAM_60X128_SBW_SR_RAM_SIZE, 4u,
1244 SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_PDMA_AM64_MAIN1_PDMA_CORE_TF0_F0_TPRAM_60X128_SBW_SR_ROW_WIDTH, ((bool)
false) },
1245 { SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_PDMA_AM64_MAIN1_PDMA_CORE_TF0_F1_TPRAM_60X128_SBW_SR_RAM_ID, 0u,
1246 SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_PDMA_AM64_MAIN1_PDMA_CORE_TF0_F1_TPRAM_60X128_SBW_SR_RAM_SIZE, 4u,
1247 SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_PDMA_AM64_MAIN1_PDMA_CORE_TF0_F1_TPRAM_60X128_SBW_SR_ROW_WIDTH, ((bool)
false) },
1248 { SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_PDMA_AM64_MAIN1_PDMA_CORE_RF0_F0_TPRAM_68X144_SBW_SR_RAM_ID, 0u,
1249 SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_PDMA_AM64_MAIN1_PDMA_CORE_RF0_F0_TPRAM_68X144_SBW_SR_RAM_SIZE, 4u,
1250 SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_PDMA_AM64_MAIN1_PDMA_CORE_RF0_F0_TPRAM_68X144_SBW_SR_ROW_WIDTH, ((bool)
false) },
1251 { SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_PDMA_AM64_MAIN1_PDMA_CORE_RF0_F1_TPRAM_68X144_SBW_SR_RAM_ID, 0u,
1252 SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_PDMA_AM64_MAIN1_PDMA_CORE_RF0_F1_TPRAM_68X144_SBW_SR_RAM_SIZE, 4u,
1253 SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_PDMA_AM64_MAIN1_PDMA_CORE_RF0_F1_TPRAM_68X144_SBW_SR_ROW_WIDTH, ((bool)
false) },
1262 { SDL_USB0_USB3P0SS64_16FFC_USB3P0SS64_CORE_A_ECC_AGGR_USB3P0SS64_16FFC_USB3P0SS64_CORE_USB3P0_KSBUS_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID, 0u,
1263 SDL_USB0_USB3P0SS64_16FFC_USB3P0SS64_CORE_A_ECC_AGGR_USB3P0SS64_16FFC_USB3P0SS64_CORE_USB3P0_KSBUS_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_SIZE, 4u,
1264 SDL_USB0_USB3P0SS64_16FFC_USB3P0SS64_CORE_A_ECC_AGGR_USB3P0SS64_16FFC_USB3P0SS64_CORE_USB3P0_KSBUS_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ROW_WIDTH, ((bool)
false) },
1273 { SDL_DMSC0_DMSC_LITE_ISRAM1_RAMECC_RAM_ID, 0u,
1274 SDL_DMSC0_DMSC_LITE_ISRAM1_RAMECC_RAM_SIZE, 4u,
1275 SDL_DMSC0_DMSC_LITE_ISRAM1_RAMECC_ROW_WIDTH, ((bool)
false) },
1276 { SDL_DMSC0_DMSC_LITE_ISRAM0_RAMECC_RAM_ID, 0u,
1277 SDL_DMSC0_DMSC_LITE_ISRAM0_RAMECC_RAM_SIZE, 4u,
1278 SDL_DMSC0_DMSC_LITE_ISRAM0_RAMECC_ROW_WIDTH, ((bool)
false) },
1279 { SDL_DMSC0_DMSC_LITE_IM_RAMECC_RAM_ID, 0u,
1280 SDL_DMSC0_DMSC_LITE_IM_RAMECC_RAM_SIZE, 4u,
1281 SDL_DMSC0_DMSC_LITE_IM_RAMECC_ROW_WIDTH, ((bool)
false) },
1282 { SDL_DMSC0_DMSC_LITE_SR_RAMECC_RAM_ID, 0u,
1283 SDL_DMSC0_DMSC_LITE_SR_RAMECC_RAM_SIZE, 4u,
1284 SDL_DMSC0_DMSC_LITE_SR_RAMECC_ROW_WIDTH, ((bool)
false) },
1293 { SDL_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_ID, 0x70040000u,
1294 SDL_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_SIZE, 4u,
1295 SDL_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_ROW_WIDTH, ((bool)
true) },
1304 { SDL_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_ID, 0x70000000u,
1305 SDL_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_SIZE, 4u,
1306 SDL_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_ROW_WIDTH, ((bool)
true) },
1315 { SDL_MSRAM_256K3_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_ID, 0x700C0000u,
1316 SDL_MSRAM_256K3_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_SIZE, 4u,
1317 SDL_MSRAM_256K3_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_ROW_WIDTH, ((bool)
true) },
1326 { SDL_MSRAM_256K5_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_ID, 0x70140000u,
1327 SDL_MSRAM_256K5_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_SIZE, 4u,
1328 SDL_MSRAM_256K5_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_ROW_WIDTH, ((bool)
true) },
1337 { SDL_MSRAM_256K4_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_ID, 0x70100000u,
1338 SDL_MSRAM_256K4_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_SIZE, 4u,
1339 SDL_MSRAM_256K4_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_ROW_WIDTH, ((bool)
true) },
1348 { SDL_MSRAM_256K7_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_ID, 0x701C0000u,
1349 SDL_MSRAM_256K7_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_SIZE, 4u,
1350 SDL_MSRAM_256K7_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_ROW_WIDTH, ((bool)
true) },
1359 { SDL_MSRAM_256K6_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_ID, 0x70180000u,
1360 SDL_MSRAM_256K6_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_SIZE, 4u,
1361 SDL_MSRAM_256K6_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_ROW_WIDTH, ((bool)
true) },
1370 { SDL_ECC_AGGR1_IMAILBOX8_MAIN_0__RAMECC_RAM_ID, 0u,
1371 SDL_ECC_AGGR1_IMAILBOX8_MAIN_0__RAMECC_RAM_SIZE, 4u,
1372 SDL_ECC_AGGR1_IMAILBOX8_MAIN_0__RAMECC_ROW_WIDTH, ((bool)
false) },
1382 { SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
1383 SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_GROUP_0_WIDTH },
1384 { SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
1385 SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_GROUP_1_WIDTH },
1386 { SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
1387 SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_GROUP_2_WIDTH },
1388 { SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
1389 SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_GROUP_3_WIDTH },
1390 { SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
1391 SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_GROUP_4_WIDTH },
1392 { SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
1393 SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_GROUP_5_WIDTH },
1394 { SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
1395 SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_GROUP_6_WIDTH },
1396 { SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
1397 SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_GROUP_7_WIDTH },
1398 { SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
1399 SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_GROUP_8_WIDTH },
1400 { SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
1401 SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_GROUP_9_WIDTH },
1402 { SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
1403 SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_GROUP_10_WIDTH },
1404 { SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
1405 SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_GROUP_11_WIDTH },
1406 { SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
1407 SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_GROUP_12_WIDTH },
1417 { SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_0_CHECKER_TYPE,
1418 SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_0_WIDTH },
1419 { SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_1_CHECKER_TYPE,
1420 SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_1_WIDTH },
1421 { SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_2_CHECKER_TYPE,
1422 SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_2_WIDTH },
1423 { SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_3_CHECKER_TYPE,
1424 SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_3_WIDTH },
1425 { SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_4_CHECKER_TYPE,
1426 SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_4_WIDTH },
1427 { SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_5_CHECKER_TYPE,
1428 SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_5_WIDTH },
1429 { SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_6_CHECKER_TYPE,
1430 SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_6_WIDTH },
1431 { SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_7_CHECKER_TYPE,
1432 SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_7_WIDTH },
1433 { SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_8_CHECKER_TYPE,
1434 SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_8_WIDTH },
1435 { SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_9_CHECKER_TYPE,
1436 SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_9_WIDTH },
1437 { SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_10_CHECKER_TYPE,
1438 SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_10_WIDTH },
1448 { SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
1449 SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
1450 { SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
1451 SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
1452 { SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
1453 SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
1454 { SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
1455 SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
1465 { SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
1466 SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
1467 { SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
1468 SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
1469 { SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
1470 SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
1471 { SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
1472 SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
1473 { SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
1474 SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
1475 { SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
1476 SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
1477 { SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
1478 SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
1479 { SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
1480 SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
1481 { SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
1482 SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
1483 { SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
1484 SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
1485 { SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
1486 SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
1487 { SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
1488 SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
1489 { SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
1490 SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
1491 { SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
1492 SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
1493 { SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
1494 SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
1504 { SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_0_CHECKER_TYPE,
1505 SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_0_WIDTH },
1506 { SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_1_CHECKER_TYPE,
1507 SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_1_WIDTH },
1508 { SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_2_CHECKER_TYPE,
1509 SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_2_WIDTH },
1518 { SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x020718000u,
1519 SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
1520 SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)
true) },
1530 { SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
1531 SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
1540 { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x020708000u,
1541 SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
1542 SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)
true) },
1552 { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
1553 SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
1562 { SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_EMMC8SS_16FFC_SDHC_WRAP_TXMEM_RAM_ID, 0u,
1563 SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_EMMC8SS_16FFC_SDHC_WRAP_TXMEM_RAM_SIZE, 4u,
1564 SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_EMMC8SS_16FFC_SDHC_WRAP_TXMEM_ROW_WIDTH, ((bool)
false) },
1573 { SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_EMMC8SS_16FFC_SDHC_WRAP_RXMEM_RAM_ID, 0u,
1574 SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_EMMC8SS_16FFC_SDHC_WRAP_RXMEM_RAM_SIZE, 4u,
1575 SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_EMMC8SS_16FFC_SDHC_WRAP_RXMEM_ROW_WIDTH, ((bool)
false) },
1578 #if defined (M4F_CORE)
1585 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_ECC_RAM_ID, 0x00000000u,
1586 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_ECC_RAM_SIZE, 4u,
1587 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_ECC_ROW_WIDTH, ((bool)
true) },
1588 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_ECC_RAM_ID, 0x00030000u,
1589 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_ECC_RAM_SIZE, 4u,
1590 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_ECC_ROW_WIDTH, ((bool)
true) },
1599 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_ECC_RAM_ID, 0x05000000u,
1600 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_ECC_RAM_SIZE, 4u,
1601 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_ECC_ROW_WIDTH, ((bool)
true) },
1602 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_ECC_RAM_ID, 0x05040000u,
1603 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_ECC_RAM_SIZE, 4u,
1604 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_ECC_ROW_WIDTH, ((bool)
true) },
1615 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
1616 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_0_WIDTH },
1617 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
1618 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_1_WIDTH },
1619 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
1620 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_2_WIDTH },
1621 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
1622 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_3_WIDTH },
1623 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
1624 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_4_WIDTH },
1625 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
1626 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_5_WIDTH },
1627 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
1628 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_6_WIDTH },
1629 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
1630 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_7_WIDTH },
1631 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
1632 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_8_WIDTH },
1633 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
1634 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_9_WIDTH },
1635 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
1636 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_10_WIDTH },
1637 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
1638 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_11_WIDTH },
1639 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
1640 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_12_WIDTH },
1641 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
1642 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_13_WIDTH },
1643 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
1644 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_14_WIDTH },
1645 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
1646 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_15_WIDTH },
1647 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
1648 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_16_WIDTH },
1649 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
1650 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_17_WIDTH },
1651 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
1652 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_GROUP_18_WIDTH },
1662 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
1663 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_0_WIDTH },
1664 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
1665 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_1_WIDTH },
1666 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
1667 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_2_WIDTH },
1668 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
1669 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_3_WIDTH },
1670 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
1671 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_4_WIDTH },
1672 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
1673 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_5_WIDTH },
1674 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
1675 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_6_WIDTH },
1676 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
1677 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_7_WIDTH },
1678 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
1679 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_8_WIDTH },
1680 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
1681 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_9_WIDTH },
1682 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
1683 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_10_WIDTH },
1684 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
1685 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_11_WIDTH },
1686 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
1687 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_12_WIDTH },
1688 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
1689 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_13_WIDTH },
1690 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
1691 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_14_WIDTH },
1692 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
1693 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_15_WIDTH },
1694 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
1695 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_16_WIDTH },
1696 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
1697 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_17_WIDTH },
1698 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
1699 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_GROUP_18_WIDTH },
1709 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
1710 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_0_WIDTH },
1711 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
1712 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_1_WIDTH },
1713 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
1714 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_2_WIDTH },
1715 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
1716 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_3_WIDTH },
1717 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
1718 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_4_WIDTH },
1719 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
1720 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_5_WIDTH },
1721 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
1722 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_6_WIDTH },
1723 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
1724 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_7_WIDTH },
1725 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
1726 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_8_WIDTH },
1727 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
1728 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_9_WIDTH },
1729 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
1730 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_10_WIDTH },
1731 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
1732 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_11_WIDTH },
1733 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
1734 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_12_WIDTH },
1735 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
1736 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_13_WIDTH },
1737 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
1738 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_14_WIDTH },
1739 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
1740 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_15_WIDTH },
1741 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
1742 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_16_WIDTH },
1743 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
1744 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_17_WIDTH },
1745 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
1746 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_18_WIDTH },
1747 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
1748 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_19_WIDTH },
1749 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
1750 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_20_WIDTH },
1751 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
1752 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_21_WIDTH },
1753 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
1754 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_22_WIDTH },
1755 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
1756 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_23_WIDTH },
1757 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
1758 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_24_WIDTH },
1759 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
1760 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_25_WIDTH },
1761 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
1762 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_26_WIDTH },
1763 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
1764 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_27_WIDTH },
1765 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
1766 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_28_WIDTH },
1767 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
1768 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_29_WIDTH },
1769 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
1770 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_30_WIDTH },
1771 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
1772 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_31_WIDTH },
1773 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
1774 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_32_WIDTH },
1775 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
1776 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_33_WIDTH },
1777 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
1778 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_34_WIDTH },
1779 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
1780 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_35_WIDTH },
1781 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
1782 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_36_WIDTH },
1783 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
1784 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_37_WIDTH },
1785 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
1786 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_38_WIDTH },
1787 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
1788 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_39_WIDTH },
1789 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
1790 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_40_WIDTH },
1791 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
1792 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_41_WIDTH },
1793 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
1794 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_GROUP_42_WIDTH },
1804 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
1805 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_0_WIDTH },
1806 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
1807 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_1_WIDTH },
1808 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
1809 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_2_WIDTH },
1810 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
1811 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_3_WIDTH },
1812 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
1813 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_4_WIDTH },
1814 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
1815 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_5_WIDTH },
1816 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
1817 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_6_WIDTH },
1818 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
1819 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_7_WIDTH },
1820 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
1821 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_8_WIDTH },
1822 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
1823 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_9_WIDTH },
1824 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
1825 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_10_WIDTH },
1835 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
1836 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_0_WIDTH },
1837 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
1838 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_1_WIDTH },
1839 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
1840 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_2_WIDTH },
1841 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
1842 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_3_WIDTH },
1843 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
1844 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_4_WIDTH },
1845 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
1846 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_5_WIDTH },
1847 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
1848 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_6_WIDTH },
1849 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
1850 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_7_WIDTH },
1851 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
1852 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_8_WIDTH },
1853 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
1854 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_9_WIDTH },
1855 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
1856 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_10_WIDTH },
1866 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
1867 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
1868 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
1869 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
1870 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
1871 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
1872 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
1873 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
1874 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
1875 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
1876 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
1877 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
1878 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
1879 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
1880 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
1881 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
1882 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
1883 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
1884 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
1885 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
1886 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
1887 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
1888 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
1889 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
1890 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
1891 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
1892 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
1893 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
1894 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
1895 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
1896 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
1897 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
1898 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
1899 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
1900 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
1901 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
1902 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
1903 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
1904 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
1905 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
1906 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
1907 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
1908 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
1909 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
1910 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
1911 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
1912 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
1913 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
1914 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
1915 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
1916 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
1917 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
1918 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
1919 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
1920 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
1921 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
1922 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
1923 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
1924 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
1925 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
1926 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
1927 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
1928 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
1929 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
1930 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
1931 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
1932 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
1933 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
1934 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
1935 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
1936 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
1937 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
1938 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
1939 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
1940 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
1941 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
1942 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
1943 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
1944 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
1945 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
1946 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
1947 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
1948 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
1949 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
1950 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
1951 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
1952 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
1953 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
1954 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
1955 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
1956 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
1957 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
1958 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
1959 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
1960 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
1961 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
1962 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
1963 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
1964 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
1965 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
1966 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
1967 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
1968 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
1969 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
1970 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
1971 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
1972 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
1973 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
1974 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
1975 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
1976 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
1977 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
1978 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
1979 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
1980 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
1981 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
1982 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
1983 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
1984 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
1985 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
1986 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
1987 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
1988 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
1989 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
1990 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
1991 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
1992 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
1993 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
1994 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
1995 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
1996 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
1997 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
1998 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
1999 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
2000 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
2001 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
2002 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
2003 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
2004 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_69_CHECKER_TYPE,
2005 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
2006 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_70_CHECKER_TYPE,
2007 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_70_WIDTH },
2008 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_71_CHECKER_TYPE,
2009 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_71_WIDTH },
2010 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_72_CHECKER_TYPE,
2011 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_72_WIDTH },
2012 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_73_CHECKER_TYPE,
2013 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_73_WIDTH },
2014 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_74_CHECKER_TYPE,
2015 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_74_WIDTH },
2016 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_75_CHECKER_TYPE,
2017 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_75_WIDTH },
2018 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_76_CHECKER_TYPE,
2019 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_76_WIDTH },
2020 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_77_CHECKER_TYPE,
2021 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_77_WIDTH },
2022 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_78_CHECKER_TYPE,
2023 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_78_WIDTH },
2024 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_79_CHECKER_TYPE,
2025 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_79_WIDTH },
2026 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_80_CHECKER_TYPE,
2027 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_80_WIDTH },
2028 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_81_CHECKER_TYPE,
2029 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_81_WIDTH },
2030 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_82_CHECKER_TYPE,
2031 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_82_WIDTH },
2032 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_83_CHECKER_TYPE,
2033 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_83_WIDTH },
2034 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_84_CHECKER_TYPE,
2035 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_84_WIDTH },
2036 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_85_CHECKER_TYPE,
2037 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_85_WIDTH },
2038 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_86_CHECKER_TYPE,
2039 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_86_WIDTH },
2040 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_87_CHECKER_TYPE,
2041 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_87_WIDTH },
2042 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_88_CHECKER_TYPE,
2043 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_88_WIDTH },
2044 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_89_CHECKER_TYPE,
2045 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_89_WIDTH },
2046 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_90_CHECKER_TYPE,
2047 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_90_WIDTH },
2048 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_91_CHECKER_TYPE,
2049 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_91_WIDTH },
2050 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_92_CHECKER_TYPE,
2051 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_92_WIDTH },
2052 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_93_CHECKER_TYPE,
2053 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_93_WIDTH },
2054 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_94_CHECKER_TYPE,
2055 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_94_WIDTH },
2056 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_95_CHECKER_TYPE,
2057 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_95_WIDTH },
2058 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_96_CHECKER_TYPE,
2059 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_96_WIDTH },
2060 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_97_CHECKER_TYPE,
2061 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_97_WIDTH },
2062 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_98_CHECKER_TYPE,
2063 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_98_WIDTH },
2064 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_99_CHECKER_TYPE,
2065 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_99_WIDTH },
2066 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_100_CHECKER_TYPE,
2067 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_100_WIDTH },
2068 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_101_CHECKER_TYPE,
2069 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_101_WIDTH },
2070 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_102_CHECKER_TYPE,
2071 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_102_WIDTH },
2072 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_103_CHECKER_TYPE,
2073 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_103_WIDTH },
2074 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_104_CHECKER_TYPE,
2075 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_104_WIDTH },
2076 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_105_CHECKER_TYPE,
2077 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_105_WIDTH },
2078 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_106_CHECKER_TYPE,
2079 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_106_WIDTH },
2080 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_107_CHECKER_TYPE,
2081 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_107_WIDTH },
2082 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_108_CHECKER_TYPE,
2083 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_108_WIDTH },
2084 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_109_CHECKER_TYPE,
2085 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_109_WIDTH },
2086 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_110_CHECKER_TYPE,
2087 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_110_WIDTH },
2088 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_111_CHECKER_TYPE,
2089 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_GROUP_111_WIDTH },
2099 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_0_CHECKER_TYPE,
2100 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_0_WIDTH },
2101 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_1_CHECKER_TYPE,
2102 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_1_WIDTH },
2103 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_2_CHECKER_TYPE,
2104 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_2_WIDTH },
2105 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_3_CHECKER_TYPE,
2106 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_3_WIDTH },
2107 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_4_CHECKER_TYPE,
2108 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_4_WIDTH },
2109 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_5_CHECKER_TYPE,
2110 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_5_WIDTH },
2111 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_6_CHECKER_TYPE,
2112 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_6_WIDTH },
2113 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_7_CHECKER_TYPE,
2114 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_7_WIDTH },
2115 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_8_CHECKER_TYPE,
2116 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_8_WIDTH },
2117 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_9_CHECKER_TYPE,
2118 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_9_WIDTH },
2119 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_10_CHECKER_TYPE,
2120 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_10_WIDTH },
2121 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_11_CHECKER_TYPE,
2122 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_11_WIDTH },
2123 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_12_CHECKER_TYPE,
2124 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_12_WIDTH },
2125 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_13_CHECKER_TYPE,
2126 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_13_WIDTH },
2127 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_14_CHECKER_TYPE,
2128 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_14_WIDTH },
2129 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_15_CHECKER_TYPE,
2130 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_15_WIDTH },
2131 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_16_CHECKER_TYPE,
2132 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_16_WIDTH },
2133 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_17_CHECKER_TYPE,
2134 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_17_WIDTH },
2135 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_18_CHECKER_TYPE,
2136 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_18_WIDTH },
2137 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_19_CHECKER_TYPE,
2138 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_19_WIDTH },
2139 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_20_CHECKER_TYPE,
2140 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_20_WIDTH },
2141 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_21_CHECKER_TYPE,
2142 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_21_WIDTH },
2152 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
2153 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_0_WIDTH },
2154 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
2155 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_1_WIDTH },
2156 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
2157 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_2_WIDTH },
2158 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
2159 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_3_WIDTH },
2160 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
2161 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_4_WIDTH },
2162 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
2163 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_5_WIDTH },
2164 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
2165 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_6_WIDTH },
2166 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
2167 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_7_WIDTH },
2168 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
2169 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_8_WIDTH },
2170 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
2171 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_9_WIDTH },
2172 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
2173 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_10_WIDTH },
2174 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
2175 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_11_WIDTH },
2176 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
2177 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_12_WIDTH },
2178 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
2179 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_13_WIDTH },
2180 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
2181 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_14_WIDTH },
2182 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
2183 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_15_WIDTH },
2184 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
2185 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_16_WIDTH },
2186 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
2187 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_17_WIDTH },
2188 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
2189 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_18_WIDTH },
2190 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
2191 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_19_WIDTH },
2192 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
2193 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_20_WIDTH },
2194 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
2195 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_21_WIDTH },
2196 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
2197 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_22_WIDTH },
2198 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
2199 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_23_WIDTH },
2200 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
2201 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_24_WIDTH },
2202 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
2203 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_25_WIDTH },
2204 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
2205 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_26_WIDTH },
2206 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
2207 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_GROUP_27_WIDTH },
2217 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
2218 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_0_WIDTH },
2219 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
2220 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_1_WIDTH },
2221 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
2222 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_2_WIDTH },
2223 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
2224 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_3_WIDTH },
2225 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
2226 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_4_WIDTH },
2227 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
2228 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_5_WIDTH },
2229 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
2230 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_6_WIDTH },
2231 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
2232 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_7_WIDTH },
2233 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
2234 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_8_WIDTH },
2235 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
2236 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_9_WIDTH },
2237 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
2238 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_10_WIDTH },
2239 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
2240 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_11_WIDTH },
2241 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
2242 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_12_WIDTH },
2243 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
2244 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_13_WIDTH },
2245 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
2246 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_14_WIDTH },
2247 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
2248 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_GROUP_15_WIDTH },
2258 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
2259 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_0_WIDTH },
2260 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
2261 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_1_WIDTH },
2262 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
2263 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_2_WIDTH },
2264 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
2265 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_3_WIDTH },
2266 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
2267 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_4_WIDTH },
2268 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
2269 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_5_WIDTH },
2270 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
2271 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_6_WIDTH },
2272 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
2273 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_7_WIDTH },
2274 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
2275 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_8_WIDTH },
2276 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
2277 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_9_WIDTH },
2278 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
2279 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_10_WIDTH },
2280 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
2281 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_11_WIDTH },
2282 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
2283 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_12_WIDTH },
2284 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
2285 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_13_WIDTH },
2286 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
2287 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_14_WIDTH },
2288 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
2289 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_GROUP_15_WIDTH },
2299 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
2300 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_0_WIDTH },
2301 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
2302 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_1_WIDTH },
2303 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
2304 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_2_WIDTH },
2305 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
2306 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_3_WIDTH },
2307 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
2308 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_4_WIDTH },
2309 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
2310 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_5_WIDTH },
2311 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
2312 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_6_WIDTH },
2313 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
2314 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_7_WIDTH },
2315 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
2316 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_8_WIDTH },
2317 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
2318 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_9_WIDTH },
2319 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
2320 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_10_WIDTH },
2321 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
2322 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_11_WIDTH },
2323 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
2324 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_12_WIDTH },
2325 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
2326 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_13_WIDTH },
2327 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
2328 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_14_WIDTH },
2329 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
2330 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_GROUP_15_WIDTH },
2340 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_GROUP_0_CHECKER_TYPE,
2341 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_GROUP_0_WIDTH },
2342 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_GROUP_1_CHECKER_TYPE,
2343 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_GROUP_1_WIDTH },
2344 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_GROUP_2_CHECKER_TYPE,
2345 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_GROUP_2_WIDTH },
2346 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_GROUP_3_CHECKER_TYPE,
2347 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_GROUP_3_WIDTH },
2348 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_GROUP_4_CHECKER_TYPE,
2349 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_GROUP_4_WIDTH },
2350 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_GROUP_5_CHECKER_TYPE,
2351 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_GROUP_5_WIDTH },
2360 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID, 0u,
2361 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_SIZE, 4u,
2362 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_ROW_WIDTH, ((bool)
false) },
2363 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID, 0u,
2364 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_SIZE, 4u,
2365 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_ROW_WIDTH, ((bool)
false) },
2366 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID, 0u,
2367 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_SIZE, 4u,
2368 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_ROW_WIDTH, ((bool)
false) },
2369 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID, 0u,
2370 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_SIZE, 4u,
2371 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_ROW_WIDTH, ((bool)
false) },
2372 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID, 0u,
2373 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_SIZE, 4u,
2374 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_ROW_WIDTH, ((bool)
false) },
2375 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID, 0u,
2376 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_SIZE, 4u,
2377 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_ROW_WIDTH, ((bool)
false) },
2378 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID, 0u,
2379 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_SIZE, 4u,
2380 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_ROW_WIDTH, ((bool)
false) },
2381 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID, 0u,
2382 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_SIZE, 4u,
2383 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_ROW_WIDTH, ((bool)
false) },
2384 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID, 0u,
2385 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_SIZE, 4u,
2386 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_ROW_WIDTH, ((bool)
false) },
2387 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID, 0u,
2388 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_SIZE, 4u,
2389 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_ROW_WIDTH, ((bool)
false) },
2390 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID, 0u,
2391 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_SIZE, 4u,
2392 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_ROW_WIDTH, ((bool)
false) },
2393 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID, 0u,
2394 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_SIZE, 4u,
2395 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_ROW_WIDTH, ((bool)
false) },
2396 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID, 0u,
2397 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_SIZE, 4u,
2398 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_ROW_WIDTH, ((bool)
false) },
2399 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID, 0u,
2400 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_SIZE, 4u,
2401 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_ROW_WIDTH, ((bool)
false) },
2402 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID, 0u,
2403 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_SIZE, 4u,
2404 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_ROW_WIDTH, ((bool)
false) },
2405 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID, 0u,
2406 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_SIZE, 4u,
2407 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_ROW_WIDTH, ((bool)
false) },
2408 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID, 0u,
2409 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_SIZE, 4u,
2410 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_ROW_WIDTH, ((bool)
false) },
2411 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID, 0u,
2412 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_SIZE, 4u,
2413 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_ROW_WIDTH, ((bool)
false) },
2414 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID, 0u,
2415 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_SIZE, 4u,
2416 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_ROW_WIDTH, ((bool)
false) },
2417 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID, 0u,
2418 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_SIZE, 4u,
2419 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_ROW_WIDTH, ((bool)
false) },
2420 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID, 0u,
2421 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_SIZE, 4u,
2422 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_ROW_WIDTH, ((bool)
false) },
2423 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_ATCM0_BANK0_RAM_ID, 0u,
2424 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_ATCM0_BANK0_RAM_SIZE, 4u,
2425 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_ATCM0_BANK0_ROW_WIDTH, ((bool)
false) },
2426 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_ATCM0_BANK1_RAM_ID, 0u,
2427 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_ATCM0_BANK1_RAM_SIZE, 4u,
2428 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_ATCM0_BANK1_ROW_WIDTH, ((bool)
false) },
2429 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B0TCM0_BANK0_RAM_ID, 0u,
2430 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B0TCM0_BANK0_RAM_SIZE, 4u,
2431 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B0TCM0_BANK0_ROW_WIDTH, ((bool)
false) },
2432 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B0TCM0_BANK1_RAM_ID, 0u,
2433 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B0TCM0_BANK1_RAM_SIZE, 4u,
2434 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B0TCM0_BANK1_ROW_WIDTH, ((bool)
false) },
2435 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B1TCM0_BANK0_RAM_ID, 0u,
2436 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B1TCM0_BANK0_RAM_SIZE, 4u,
2437 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B1TCM0_BANK0_ROW_WIDTH, ((bool)
false) },
2438 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B1TCM0_BANK1_RAM_ID, 0u,
2439 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B1TCM0_BANK1_RAM_SIZE, 4u,
2440 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B1TCM0_BANK1_ROW_WIDTH, ((bool)
false) },
2441 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID, 0u,
2442 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_SIZE, 4u,
2443 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ROW_WIDTH, ((bool)
false) },
2444 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_MEM_MST_RAMECC_RAM_ID, 0u,
2445 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_MEM_MST_RAMECC_RAM_SIZE, 4u,
2446 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_MEM_MST_RAMECC_ROW_WIDTH, ((bool)
false) },
2455 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_ITAG_RAM0_RAM_ID, 0u,
2456 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_ITAG_RAM0_RAM_SIZE, 4u,
2457 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_ITAG_RAM0_ROW_WIDTH, ((bool)
false) },
2458 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_ITAG_RAM1_RAM_ID, 0u,
2459 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_ITAG_RAM1_RAM_SIZE, 4u,
2460 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_ITAG_RAM1_ROW_WIDTH, ((bool)
false) },
2461 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_ITAG_RAM2_RAM_ID, 0u,
2462 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_ITAG_RAM2_RAM_SIZE, 4u,
2463 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_ITAG_RAM2_ROW_WIDTH, ((bool)
false) },
2464 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_ITAG_RAM3_RAM_ID, 0u,
2465 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_ITAG_RAM3_RAM_SIZE, 4u,
2466 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_ITAG_RAM3_ROW_WIDTH, ((bool)
false) },
2467 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_IDATA_BANK0_RAM_ID, 0u,
2468 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_IDATA_BANK0_RAM_SIZE, 4u,
2469 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_IDATA_BANK0_ROW_WIDTH, ((bool)
false) },
2470 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_IDATA_BANK1_RAM_ID, 0u,
2471 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_IDATA_BANK1_RAM_SIZE, 4u,
2472 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_IDATA_BANK1_ROW_WIDTH, ((bool)
false) },
2473 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_IDATA_BANK2_RAM_ID, 0u,
2474 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_IDATA_BANK2_RAM_SIZE, 4u,
2475 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_IDATA_BANK2_ROW_WIDTH, ((bool)
false) },
2476 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_IDATA_BANK3_RAM_ID, 0u,
2477 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_IDATA_BANK3_RAM_SIZE, 4u,
2478 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_IDATA_BANK3_ROW_WIDTH, ((bool)
false) },
2479 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DTAG_RAM0_RAM_ID, 0u,
2480 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DTAG_RAM0_RAM_SIZE, 4u,
2481 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DTAG_RAM0_ROW_WIDTH, ((bool)
false) },
2482 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DTAG_RAM1_RAM_ID, 0u,
2483 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DTAG_RAM1_RAM_SIZE, 4u,
2484 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DTAG_RAM1_ROW_WIDTH, ((bool)
false) },
2485 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DTAG_RAM2_RAM_ID, 0u,
2486 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DTAG_RAM2_RAM_SIZE, 4u,
2487 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DTAG_RAM2_ROW_WIDTH, ((bool)
false) },
2488 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DTAG_RAM3_RAM_ID, 0u,
2489 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DTAG_RAM3_RAM_SIZE, 4u,
2490 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DTAG_RAM3_ROW_WIDTH, ((bool)
false) },
2491 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDIRTY_RAM_RAM_ID, 0u,
2492 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDIRTY_RAM_RAM_SIZE, 4u,
2493 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDIRTY_RAM_ROW_WIDTH, ((bool)
false) },
2494 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM0_RAM_ID, 0u,
2495 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM0_RAM_SIZE, 4u,
2496 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM0_ROW_WIDTH, ((bool)
false) },
2497 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM1_RAM_ID, 0u,
2498 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM1_RAM_SIZE, 4u,
2499 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM1_ROW_WIDTH, ((bool)
false) },
2500 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM2_RAM_ID, 0u,
2501 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM2_RAM_SIZE, 4u,
2502 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM2_ROW_WIDTH, ((bool)
false) },
2503 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM3_RAM_ID, 0u,
2504 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM3_RAM_SIZE, 4u,
2505 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM3_ROW_WIDTH, ((bool)
false) },
2506 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM4_RAM_ID, 0u,
2507 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM4_RAM_SIZE, 4u,
2508 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM4_ROW_WIDTH, ((bool)
false) },
2509 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM5_RAM_ID, 0u,
2510 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM5_RAM_SIZE, 4u,
2511 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM5_ROW_WIDTH, ((bool)
false) },
2512 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM6_RAM_ID, 0u,
2513 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM6_RAM_SIZE, 4u,
2514 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM6_ROW_WIDTH, ((bool)
false) },
2515 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM7_RAM_ID, 0u,
2516 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM7_RAM_SIZE, 4u,
2517 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM7_ROW_WIDTH, ((bool)
false) },
2518 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_ATCM1_BANK0_RAM_ID, 0u,
2519 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_ATCM1_BANK0_RAM_SIZE, 4u,
2520 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_ATCM1_BANK0_ROW_WIDTH, ((bool)
false) },
2521 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_ATCM1_BANK1_RAM_ID, 0u,
2522 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_ATCM1_BANK1_RAM_SIZE, 4u,
2523 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_ATCM1_BANK1_ROW_WIDTH, ((bool)
false) },
2524 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_B0TCM1_BANK0_RAM_ID, 0u,
2525 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_B0TCM1_BANK0_RAM_SIZE, 4u,
2526 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_B0TCM1_BANK0_ROW_WIDTH, ((bool)
false) },
2527 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_B0TCM1_BANK1_RAM_ID, 0u,
2528 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_B0TCM1_BANK1_RAM_SIZE, 4u,
2529 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_B0TCM1_BANK1_ROW_WIDTH, ((bool)
false) },
2530 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_B1TCM1_BANK0_RAM_ID, 0u,
2531 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_B1TCM1_BANK0_RAM_SIZE, 4u,
2532 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_B1TCM1_BANK0_ROW_WIDTH, ((bool)
false) },
2533 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_B1TCM1_BANK1_RAM_ID, 0u,
2534 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_B1TCM1_BANK1_RAM_SIZE, 4u,
2535 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_B1TCM1_BANK1_ROW_WIDTH, ((bool)
false) },
2536 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_KS_VIM_RAMECC_RAM_ID, 0u,
2537 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_KS_VIM_RAMECC_RAM_SIZE, 4u,
2538 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_KS_VIM_RAMECC_ROW_WIDTH, ((bool)
false) },
2539 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_AXI2VBUSM_MEM_MST_RAMECC_RAM_ID, 0u,
2540 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_AXI2VBUSM_MEM_MST_RAMECC_RAM_SIZE, 4u,
2541 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_AXI2VBUSM_MEM_MST_RAMECC_ROW_WIDTH, ((bool)
false) },
2550 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID, 0u,
2551 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_SIZE, 4u,
2552 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_ROW_WIDTH, ((bool)
false) },
2553 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID, 0u,
2554 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_SIZE, 4u,
2555 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_ROW_WIDTH, ((bool)
false) },
2556 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID, 0u,
2557 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_SIZE, 4u,
2558 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_ROW_WIDTH, ((bool)
false) },
2559 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID, 0u,
2560 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_SIZE, 4u,
2561 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_ROW_WIDTH, ((bool)
false) },
2562 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID, 0u,
2563 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_SIZE, 4u,
2564 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_ROW_WIDTH, ((bool)
false) },
2565 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID, 0u,
2566 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_SIZE, 4u,
2567 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_ROW_WIDTH, ((bool)
false) },
2568 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID, 0u,
2569 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_SIZE, 4u,
2570 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_ROW_WIDTH, ((bool)
false) },
2571 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID, 0u,
2572 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_SIZE, 4u,
2573 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_ROW_WIDTH, ((bool)
false) },
2574 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID, 0u,
2575 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_SIZE, 4u,
2576 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_ROW_WIDTH, ((bool)
false) },
2577 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID, 0u,
2578 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_SIZE, 4u,
2579 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_ROW_WIDTH, ((bool)
false) },
2580 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID, 0u,
2581 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_SIZE, 4u,
2582 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_ROW_WIDTH, ((bool)
false) },
2583 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID, 0u,
2584 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_SIZE, 4u,
2585 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_ROW_WIDTH, ((bool)
false) },
2586 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID, 0u,
2587 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_SIZE, 4u,
2588 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_ROW_WIDTH, ((bool)
false) },
2589 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID, 0u,
2590 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_SIZE, 4u,
2591 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_ROW_WIDTH, ((bool)
false) },
2592 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID, 0u,
2593 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_SIZE, 4u,
2594 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_ROW_WIDTH, ((bool)
false) },
2595 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID, 0u,
2596 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_SIZE, 4u,
2597 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_ROW_WIDTH, ((bool)
false) },
2598 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID, 0u,
2599 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_SIZE, 4u,
2600 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_ROW_WIDTH, ((bool)
false) },
2601 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID, 0u,
2602 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_SIZE, 4u,
2603 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_ROW_WIDTH, ((bool)
false) },
2604 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID, 0u,
2605 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_SIZE, 4u,
2606 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_ROW_WIDTH, ((bool)
false) },
2607 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID, 0u,
2608 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_SIZE, 4u,
2609 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_ROW_WIDTH, ((bool)
false) },
2610 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID, 0u,
2611 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_SIZE, 4u,
2612 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_ROW_WIDTH, ((bool)
false) },
2613 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_ATCM0_BANK0_RAM_ID, 0u,
2614 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_ATCM0_BANK0_RAM_SIZE, 8u,
2615 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_ATCM0_BANK0_ROW_WIDTH, ((bool)
true) },
2616 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_ATCM0_BANK1_RAM_ID, 0u,
2617 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_ATCM0_BANK1_RAM_SIZE, 4u,
2618 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_ATCM0_BANK1_ROW_WIDTH, ((bool)
false) },
2619 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B0TCM0_BANK0_RAM_ID, 0x41010000u,
2620 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B0TCM0_BANK0_RAM_SIZE, 4u,
2621 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B0TCM0_BANK0_ROW_WIDTH, ((bool)
false) },
2622 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B0TCM0_BANK1_RAM_ID, 0x41010000u,
2623 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B0TCM0_BANK1_RAM_SIZE, 4u,
2624 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B0TCM0_BANK1_ROW_WIDTH, ((bool)
false) },
2625 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B1TCM0_BANK0_RAM_ID, 0x41010000u,
2626 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B1TCM0_BANK0_RAM_SIZE, 4u,
2627 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B1TCM0_BANK0_ROW_WIDTH, ((bool)
false) },
2628 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B1TCM0_BANK1_RAM_ID, 0x41010000u,
2629 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B1TCM0_BANK1_RAM_SIZE, 4u,
2630 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B1TCM0_BANK1_ROW_WIDTH, ((bool)
false) },
2631 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID, 0u,
2632 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_SIZE, 4u,
2633 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ROW_WIDTH, ((bool)
false) },
2634 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_MEM_MST_RAMECC_RAM_ID, 0u,
2635 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_MEM_MST_RAMECC_RAM_SIZE, 4u,
2636 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_MEM_MST_RAMECC_ROW_WIDTH, ((bool)
false) },
2645 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_ITAG_RAM0_RAM_ID, 0u,
2646 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_ITAG_RAM0_RAM_SIZE, 4u,
2647 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_ITAG_RAM0_ROW_WIDTH, ((bool)
false) },
2648 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_ITAG_RAM1_RAM_ID, 0u,
2649 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_ITAG_RAM1_RAM_SIZE, 4u,
2650 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_ITAG_RAM1_ROW_WIDTH, ((bool)
false) },
2651 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_ITAG_RAM2_RAM_ID, 0u,
2652 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_ITAG_RAM2_RAM_SIZE, 4u,
2653 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_ITAG_RAM2_ROW_WIDTH, ((bool)
false) },
2654 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_ITAG_RAM3_RAM_ID, 0u,
2655 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_ITAG_RAM3_RAM_SIZE, 4u,
2656 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_ITAG_RAM3_ROW_WIDTH, ((bool)
false) },
2657 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_IDATA_BANK0_RAM_ID, 0u,
2658 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_IDATA_BANK0_RAM_SIZE, 4u,
2659 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_IDATA_BANK0_ROW_WIDTH, ((bool)
false) },
2660 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_IDATA_BANK1_RAM_ID, 0u,
2661 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_IDATA_BANK1_RAM_SIZE, 4u,
2662 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_IDATA_BANK1_ROW_WIDTH, ((bool)
false) },
2663 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_IDATA_BANK2_RAM_ID, 0u,
2664 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_IDATA_BANK2_RAM_SIZE, 4u,
2665 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_IDATA_BANK2_ROW_WIDTH, ((bool)
false) },
2666 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_IDATA_BANK3_RAM_ID, 0u,
2667 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_IDATA_BANK3_RAM_SIZE, 4u,
2668 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_IDATA_BANK3_ROW_WIDTH, ((bool)
false) },
2669 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DTAG_RAM0_RAM_ID, 0u,
2670 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DTAG_RAM0_RAM_SIZE, 4u,
2671 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DTAG_RAM0_ROW_WIDTH, ((bool)
false) },
2672 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DTAG_RAM1_RAM_ID, 0u,
2673 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DTAG_RAM1_RAM_SIZE, 4u,
2674 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DTAG_RAM1_ROW_WIDTH, ((bool)
false) },
2675 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DTAG_RAM2_RAM_ID, 0u,
2676 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DTAG_RAM2_RAM_SIZE, 4u,
2677 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DTAG_RAM2_ROW_WIDTH, ((bool)
false) },
2678 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DTAG_RAM3_RAM_ID, 0u,
2679 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DTAG_RAM3_RAM_SIZE, 4u,
2680 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DTAG_RAM3_ROW_WIDTH, ((bool)
false) },
2681 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDIRTY_RAM_RAM_ID, 0u,
2682 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDIRTY_RAM_RAM_SIZE, 4u,
2683 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDIRTY_RAM_ROW_WIDTH, ((bool)
false) },
2684 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM0_RAM_ID, 0u,
2685 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM0_RAM_SIZE, 4u,
2686 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM0_ROW_WIDTH, ((bool)
false) },
2687 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM1_RAM_ID, 0u,
2688 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM1_RAM_SIZE, 4u,
2689 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM1_ROW_WIDTH, ((bool)
false) },
2690 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM2_RAM_ID, 0u,
2691 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM2_RAM_SIZE, 4u,
2692 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM2_ROW_WIDTH, ((bool)
false) },
2693 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM3_RAM_ID, 0u,
2694 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM3_RAM_SIZE, 4u,
2695 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM3_ROW_WIDTH, ((bool)
false) },
2696 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM4_RAM_ID, 0u,
2697 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM4_RAM_SIZE, 4u,
2698 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM4_ROW_WIDTH, ((bool)
false) },
2699 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM5_RAM_ID, 0u,
2700 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM5_RAM_SIZE, 4u,
2701 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM5_ROW_WIDTH, ((bool)
false) },
2702 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM6_RAM_ID, 0u,
2703 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM6_RAM_SIZE, 4u,
2704 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM6_ROW_WIDTH, ((bool)
false) },
2705 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM7_RAM_ID, 0u,
2706 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM7_RAM_SIZE, 4u,
2707 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM7_ROW_WIDTH, ((bool)
false) },
2708 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_ATCM1_BANK0_RAM_ID, 0u,
2709 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_ATCM1_BANK0_RAM_SIZE, 4u,
2710 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_ATCM1_BANK0_ROW_WIDTH, ((bool)
false) },
2711 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_ATCM1_BANK1_RAM_ID, 0u,
2712 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_ATCM1_BANK1_RAM_SIZE, 4u,
2713 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_ATCM1_BANK1_ROW_WIDTH, ((bool)
false) },
2714 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_B0TCM1_BANK0_RAM_ID, 0u,
2715 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_B0TCM1_BANK0_RAM_SIZE, 4u,
2716 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_B0TCM1_BANK0_ROW_WIDTH, ((bool)
false) },
2717 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_B0TCM1_BANK1_RAM_ID, 0u,
2718 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_B0TCM1_BANK1_RAM_SIZE, 4u,
2719 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_B0TCM1_BANK1_ROW_WIDTH, ((bool)
false) },
2720 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_B1TCM1_BANK0_RAM_ID, 0u,
2721 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_B1TCM1_BANK0_RAM_SIZE, 4u,
2722 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_B1TCM1_BANK0_ROW_WIDTH, ((bool)
false) },
2723 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_B1TCM1_BANK1_RAM_ID, 0u,
2724 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_B1TCM1_BANK1_RAM_SIZE, 4u,
2725 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_B1TCM1_BANK1_ROW_WIDTH, ((bool)
false) },
2726 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_KS_VIM_RAMECC_RAM_ID, 0u,
2727 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_KS_VIM_RAMECC_RAM_SIZE, 4u,
2728 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_KS_VIM_RAMECC_ROW_WIDTH, ((bool)
false) },
2729 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_AXI2VBUSM_MEM_MST_RAMECC_RAM_ID, 0u,
2730 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_AXI2VBUSM_MEM_MST_RAMECC_RAM_SIZE, 4u,
2731 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_AXI2VBUSM_MEM_MST_RAMECC_ROW_WIDTH, ((bool)
false) },
2740 { SDL_ECC_AGGR0_ITIMER_MGR1024_MAIN_0__TIMER_FSM_RAMECC_RAM_ID, 0u,
2741 SDL_ECC_AGGR0_ITIMER_MGR1024_MAIN_0__TIMER_FSM_RAMECC_RAM_SIZE, 4u,
2742 SDL_ECC_AGGR0_ITIMER_MGR1024_MAIN_0__TIMER_FSM_RAMECC_ROW_WIDTH, ((bool)
false) },
2743 { SDL_ECC_AGGR0_ITIMER_MGR1024_MAIN_0__REPROG_FSM_RAMECC_RAM_ID, 0u,
2744 SDL_ECC_AGGR0_ITIMER_MGR1024_MAIN_0__REPROG_FSM_RAMECC_RAM_SIZE, 4u,
2745 SDL_ECC_AGGR0_ITIMER_MGR1024_MAIN_0__REPROG_FSM_RAMECC_ROW_WIDTH, ((bool)
false) },
2746 { SDL_ECC_AGGR0_ITIMER_MGR1024_MAIN_0__EFIFO_RAMECC_RAM_ID, 0u,
2747 SDL_ECC_AGGR0_ITIMER_MGR1024_MAIN_0__EFIFO_RAMECC_RAM_SIZE, 4u,
2748 SDL_ECC_AGGR0_ITIMER_MGR1024_MAIN_0__EFIFO_RAMECC_ROW_WIDTH, ((bool)
false) },
2757 { SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_PDMA_AM64_MAIN0_PDMA_CORE_TF0_F0_TPRAM_72X128_SBW_SR_RAM_ID, 0u,
2758 SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_PDMA_AM64_MAIN0_PDMA_CORE_TF0_F0_TPRAM_72X128_SBW_SR_RAM_SIZE, 4u,
2759 SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_PDMA_AM64_MAIN0_PDMA_CORE_TF0_F0_TPRAM_72X128_SBW_SR_ROW_WIDTH, ((bool)
false) },
2760 { SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_PDMA_AM64_MAIN0_PDMA_CORE_TF0_F1_TPRAM_72X128_SBW_SR_RAM_ID, 0u,
2761 SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_PDMA_AM64_MAIN0_PDMA_CORE_TF0_F1_TPRAM_72X128_SBW_SR_RAM_SIZE, 4u,
2762 SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_PDMA_AM64_MAIN0_PDMA_CORE_TF0_F1_TPRAM_72X128_SBW_SR_ROW_WIDTH, ((bool)
false) },
2763 { SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_PDMA_AM64_MAIN0_PDMA_CORE_RF0_F0_TPRAM_72X144_SBW_SR_RAM_ID, 0u,
2764 SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_PDMA_AM64_MAIN0_PDMA_CORE_RF0_F0_TPRAM_72X144_SBW_SR_RAM_SIZE, 4u,
2765 SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_PDMA_AM64_MAIN0_PDMA_CORE_RF0_F0_TPRAM_72X144_SBW_SR_ROW_WIDTH, ((bool)
false) },
2766 { SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_PDMA_AM64_MAIN0_PDMA_CORE_RF0_F1_TPRAM_72X144_SBW_SR_RAM_ID, 0u,
2767 SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_PDMA_AM64_MAIN0_PDMA_CORE_RF0_F1_TPRAM_72X144_SBW_SR_RAM_SIZE, 4u,
2768 SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_PDMA_AM64_MAIN0_PDMA_CORE_RF0_F1_TPRAM_72X144_SBW_SR_ROW_WIDTH, ((bool)
false) },
2777 { SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_RAM_ID,
2778 SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_INJECT_TYPE,
2779 SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_ECC_TYPE,
2790 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_ID,
2791 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_INJECT_TYPE,
2792 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ECC_TYPE,
2795 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_ID,
2796 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_INJECT_TYPE,
2797 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ECC_TYPE,
2800 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_ID,
2801 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_INJECT_TYPE,
2802 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ECC_TYPE,
2805 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_ID,
2806 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_INJECT_TYPE,
2807 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ECC_TYPE,
2810 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_ID,
2811 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_INJECT_TYPE,
2812 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ECC_TYPE,
2815 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_ID,
2816 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_INJECT_TYPE,
2817 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ECC_TYPE,
2820 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
2821 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
2822 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
2825 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
2826 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
2827 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
2830 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
2831 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
2832 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
2835 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
2836 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
2837 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
2840 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID,
2841 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_INJECT_TYPE,
2842 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ECC_TYPE,
2845 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID,
2846 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_INJECT_TYPE,
2847 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ECC_TYPE,
2850 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_ID,
2851 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_INJECT_TYPE,
2852 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ECC_TYPE,
2855 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_ID,
2856 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_INJECT_TYPE,
2857 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ECC_TYPE,
2860 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
2861 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
2862 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
2865 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
2866 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
2867 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
2870 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
2871 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
2872 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
2875 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
2876 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
2877 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
2880 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_ID,
2881 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_INJECT_TYPE,
2882 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ECC_TYPE,
2885 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
2886 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
2887 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
2890 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
2891 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
2892 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
2895 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
2896 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
2897 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
2900 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
2901 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
2902 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
2905 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID,
2906 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_INJECT_TYPE,
2907 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ECC_TYPE,
2910 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID,
2911 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_INJECT_TYPE,
2912 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ECC_TYPE,
2915 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID,
2916 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_INJECT_TYPE,
2917 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ECC_TYPE,
2920 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID,
2921 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_INJECT_TYPE,
2922 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ECC_TYPE,
2933 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_RAM_ID,
2934 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_INJECT_TYPE,
2935 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ECC_TYPE,
2938 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_RAM_ID,
2939 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_INJECT_TYPE,
2940 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ECC_TYPE,
2943 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_RAM_ID,
2944 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_INJECT_TYPE,
2945 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ECC_TYPE,
2948 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_RAM_ID,
2949 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_INJECT_TYPE,
2950 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ECC_TYPE,
2953 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_RAM_ID,
2954 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_INJECT_TYPE,
2955 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ECC_TYPE,
2958 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_RAM_ID,
2959 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_INJECT_TYPE,
2960 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ECC_TYPE,
2963 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
2964 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
2965 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
2968 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
2969 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
2970 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
2973 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
2974 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
2975 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
2978 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
2979 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
2980 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
2983 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID,
2984 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_INJECT_TYPE,
2985 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ECC_TYPE,
2988 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID,
2989 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_INJECT_TYPE,
2990 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ECC_TYPE,
2993 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_RAM_ID,
2994 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_INJECT_TYPE,
2995 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ECC_TYPE,
2998 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_RAM_ID,
2999 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_INJECT_TYPE,
3000 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ECC_TYPE,
3003 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
3004 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
3005 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
3008 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
3009 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
3010 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
3013 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
3014 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
3015 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
3018 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
3019 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
3020 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
3023 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_RAM_ID,
3024 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_INJECT_TYPE,
3025 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ECC_TYPE,
3028 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
3029 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
3030 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
3033 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
3034 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
3035 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
3038 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
3039 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
3040 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
3043 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
3044 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
3045 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
3048 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID,
3049 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_INJECT_TYPE,
3050 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ECC_TYPE,
3053 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID,
3054 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_INJECT_TYPE,
3055 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ECC_TYPE,
3058 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID,
3059 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_INJECT_TYPE,
3060 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ECC_TYPE,
3063 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID,
3064 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_INJECT_TYPE,
3065 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ECC_TYPE,
3076 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_RAM_ID,
3077 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_INJECT_TYPE,
3078 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ECC_TYPE,
3081 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_RAM_ID,
3082 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_INJECT_TYPE,
3083 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ECC_TYPE,
3086 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_RAM_ID,
3087 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_INJECT_TYPE,
3088 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ECC_TYPE,
3091 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_RAM_ID,
3092 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_INJECT_TYPE,
3093 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ECC_TYPE,
3096 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_RAM_ID,
3097 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_INJECT_TYPE,
3098 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_ECC_TYPE,
3101 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_RAM_ID,
3102 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_INJECT_TYPE,
3103 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_ECC_TYPE,
3106 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_RAM_ID,
3107 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_INJECT_TYPE,
3108 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_ECC_TYPE,
3111 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_RAM_ID,
3112 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_INJECT_TYPE,
3113 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_ECC_TYPE,
3116 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_RAM_ID,
3117 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_INJECT_TYPE,
3118 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_ECC_TYPE,
3121 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_RAM_ID,
3122 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_INJECT_TYPE,
3123 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_ECC_TYPE,
3126 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_RAM_ID,
3127 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_INJECT_TYPE,
3128 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_ECC_TYPE,
3131 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_RAM_ID,
3132 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_INJECT_TYPE,
3133 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_ECC_TYPE,
3136 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_RAM_ID,
3137 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_INJECT_TYPE,
3138 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_ECC_TYPE,
3141 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_RAM_ID,
3142 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_INJECT_TYPE,
3143 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_ECC_TYPE,
3146 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_RAM_ID,
3147 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_INJECT_TYPE,
3148 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_ECC_TYPE,
3151 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_RAM_ID,
3152 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_INJECT_TYPE,
3153 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_ECC_TYPE,
3156 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_RAM_ID,
3157 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_INJECT_TYPE,
3158 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_ECC_TYPE,
3161 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_RAM_ID,
3162 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_INJECT_TYPE,
3163 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_ECC_TYPE,
3166 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_RAM_ID,
3167 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_INJECT_TYPE,
3168 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_ECC_TYPE,
3171 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_RAM_ID,
3172 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_INJECT_TYPE,
3173 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_ECC_TYPE,
3176 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_RAM_ID,
3177 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_INJECT_TYPE,
3178 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_ECC_TYPE,
3181 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_RAM_ID,
3182 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_INJECT_TYPE,
3183 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_ECC_TYPE,
3186 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_RAM_ID,
3187 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_INJECT_TYPE,
3188 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_ECC_TYPE,
3191 { SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_RAM_ID,
3192 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_INJECT_TYPE,
3193 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_ECC_TYPE,
3204 { SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_RAM_ID,
3205 SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_INJECT_TYPE,
3206 SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_ECC_TYPE,
3209 { SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_RAM_ID,
3210 SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_INJECT_TYPE,
3211 SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_ECC_TYPE,
3214 { SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_RAM_ID,
3215 SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_INJECT_TYPE,
3216 SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_ECC_TYPE,
3219 { SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_RAM_ID,
3220 SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_INJECT_TYPE,
3221 SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_ECC_TYPE,
3224 { SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_RAM_ID,
3225 SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_INJECT_TYPE,
3226 SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_ECC_TYPE,
3229 { SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU0_PDSP_IRAM_ECC_RAM_ID,
3230 SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU0_PDSP_IRAM_ECC_INJECT_TYPE,
3231 SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU0_PDSP_IRAM_ECC_ECC_TYPE,
3234 { SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU1_PDSP_IRAM_ECC_RAM_ID,
3235 SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU1_PDSP_IRAM_ECC_INJECT_TYPE,
3236 SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU1_PDSP_IRAM_ECC_ECC_TYPE,
3239 { SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX0_IRAM_ECC_RAM_ID,
3240 SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX0_IRAM_ECC_INJECT_TYPE,
3241 SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX0_IRAM_ECC_ECC_TYPE,
3244 { SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX1_IRAM_ECC_RAM_ID,
3245 SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX1_IRAM_ECC_INJECT_TYPE,
3246 SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX1_IRAM_ECC_ECC_TYPE,
3257 { SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_RAM_ID,
3258 SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_INJECT_TYPE,
3259 SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_ECC_TYPE,
3262 { SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_RAM_ID,
3263 SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_INJECT_TYPE,
3264 SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_ECC_TYPE,
3267 { SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_RAM_ID,
3268 SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_INJECT_TYPE,
3269 SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_ECC_TYPE,
3272 { SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_RAM_ID,
3273 SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_INJECT_TYPE,
3274 SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_ECC_TYPE,
3277 { SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_RAM_ID,
3278 SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_INJECT_TYPE,
3279 SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_ECC_TYPE,
3282 { SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU0_PDSP_IRAM_ECC_RAM_ID,
3283 SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU0_PDSP_IRAM_ECC_INJECT_TYPE,
3284 SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU0_PDSP_IRAM_ECC_ECC_TYPE,
3287 { SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU1_PDSP_IRAM_ECC_RAM_ID,
3288 SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU1_PDSP_IRAM_ECC_INJECT_TYPE,
3289 SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU1_PDSP_IRAM_ECC_ECC_TYPE,
3292 { SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX0_IRAM_ECC_RAM_ID,
3293 SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX0_IRAM_ECC_INJECT_TYPE,
3294 SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX0_IRAM_ECC_ECC_TYPE,
3297 { SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX1_IRAM_ECC_RAM_ID,
3298 SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX1_IRAM_ECC_INJECT_TYPE,
3299 SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX1_IRAM_ECC_ECC_TYPE,
3310 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_CFG_CONFIG_RAM_ID,
3311 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_CFG_CONFIG_INJECT_TYPE,
3312 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_CFG_CONFIG_ECC_TYPE,
3315 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_CFG_STATE_RAM_ID,
3316 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_CFG_STATE_INJECT_TYPE,
3317 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_CFG_STATE_ECC_TYPE,
3320 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_TPCFIFO_F0_RAM_ID,
3321 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_TPCFIFO_F0_INJECT_TYPE,
3322 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_TPCFIFO_F0_ECC_TYPE,
3325 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_TPCFIFO_F1_RAM_ID,
3326 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_TPCFIFO_F1_INJECT_TYPE,
3327 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_TPCFIFO_F1_ECC_TYPE,
3330 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_RPCFIFO_F0_RAM_ID,
3331 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_RPCFIFO_F0_INJECT_TYPE,
3332 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_RPCFIFO_F0_ECC_TYPE,
3335 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_RPCFIFO_F1_RAM_ID,
3336 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_RPCFIFO_F1_INJECT_TYPE,
3337 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_RPCFIFO_F1_ECC_TYPE,
3340 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_RPCFIFO_WC_RAM_ID,
3341 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_RPCFIFO_WC_INJECT_TYPE,
3342 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_RPCFIFO_WC_ECC_TYPE,
3345 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_STATS_STST0_RAM_ID,
3346 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_STATS_STST0_INJECT_TYPE,
3347 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_STATS_STST0_ECC_TYPE,
3350 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_STATS_STSR0_RAM_ID,
3351 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_STATS_STSR0_INJECT_TYPE,
3352 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_STATS_STSR0_ECC_TYPE,
3355 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_RINGOCC_CNTR_RAM_ID,
3356 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_RINGOCC_CNTR_INJECT_TYPE,
3357 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_PKTDMA_RINGOCC_CNTR_ECC_TYPE,
3360 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_CFG_CONFIG_RAM_ID,
3361 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_CFG_CONFIG_INJECT_TYPE,
3362 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_CFG_CONFIG_ECC_TYPE,
3365 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_CFG_STATE_RAM_ID,
3366 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_CFG_STATE_INJECT_TYPE,
3367 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_CFG_STATE_ECC_TYPE,
3370 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_PCFIFO_DFIFO_F0_RAM_ID,
3371 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_PCFIFO_DFIFO_F0_INJECT_TYPE,
3372 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_PCFIFO_DFIFO_F0_ECC_TYPE,
3375 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_PCFIFO_DFIFO_F1_RAM_ID,
3376 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_PCFIFO_DFIFO_F1_INJECT_TYPE,
3377 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_PCFIFO_DFIFO_F1_ECC_TYPE,
3380 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_TPCFIFO_F0_RAM_ID,
3381 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_TPCFIFO_F0_INJECT_TYPE,
3382 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_TPCFIFO_F0_ECC_TYPE,
3385 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_TPCFIFO_F1_RAM_ID,
3386 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_TPCFIFO_F1_INJECT_TYPE,
3387 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_TPCFIFO_F1_ECC_TYPE,
3390 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_RPCFIFO_F0_RAM_ID,
3391 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_RPCFIFO_F0_INJECT_TYPE,
3392 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_RPCFIFO_F0_ECC_TYPE,
3395 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_RPCFIFO_F1_RAM_ID,
3396 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_RPCFIFO_F1_INJECT_TYPE,
3397 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_RPCFIFO_F1_ECC_TYPE,
3400 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_RPCFIFO_WC_RAM_ID,
3401 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_RPCFIFO_WC_INJECT_TYPE,
3402 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_RPCFIFO_WC_ECC_TYPE,
3405 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_STATS_STST0_RAM_ID,
3406 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_STATS_STST0_INJECT_TYPE,
3407 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_STATS_STST0_ECC_TYPE,
3410 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_STATS_STSR0_RAM_ID,
3411 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_STATS_STSR0_INJECT_TYPE,
3412 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_STATS_STSR0_ECC_TYPE,
3415 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_RINGOCC_CNTR_RAM_ID,
3416 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_RINGOCC_CNTR_INJECT_TYPE,
3417 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_BCDMA_RINGOCC_CNTR_ECC_TYPE,
3420 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_INTAGGR_STATREG_SR_SPRAM_184X128_SWW_SR_RAM_ID,
3421 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_INTAGGR_STATREG_SR_SPRAM_184X128_SWW_SR_INJECT_TYPE,
3422 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_INTAGGR_STATREG_SR_SPRAM_184X128_SWW_SR_ECC_TYPE,
3425 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_INTAGGR_COMMON_IM_TPRAM_2250X34_SWW_SR_RAM_ID,
3426 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_INTAGGR_COMMON_IM_TPRAM_2250X34_SWW_SR_INJECT_TYPE,
3427 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_INTAGGR_COMMON_IM_TPRAM_2250X34_SWW_SR_ECC_TYPE,
3430 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_IPCSS_RINGACC_STRAM_RAM_ID,
3431 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_IPCSS_RINGACC_STRAM_INJECT_TYPE,
3432 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_IPCSS_RINGACC_STRAM_ECC_TYPE,
3435 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_IPCSS_SEC_PROXY_BUF_STRAM_RAM_ID,
3436 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_IPCSS_SEC_PROXY_BUF_STRAM_INJECT_TYPE,
3437 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_IPCSS_SEC_PROXY_BUF_STRAM_ECC_TYPE,
3440 { SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_IPCSS_SEC_PROXY_BUF_BUFRAM_RAM_ID,
3441 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_IPCSS_SEC_PROXY_BUF_BUFRAM_INJECT_TYPE,
3442 SDL_DMASS0_DMSS_AM64_ECCAGGR_DMSS_AM64_IPCSS_SEC_PROXY_BUF_BUFRAM_ECC_TYPE,
3453 { SDL_MSRAM_256K2_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_ID,
3454 SDL_MSRAM_256K2_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_INJECT_TYPE,
3455 SDL_MSRAM_256K2_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_ECC_TYPE,
3466 { SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_RAM_ID,
3467 SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_INJECT_TYPE,
3468 SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_ECC_TYPE,
3479 { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_ALE_RAM_RAM_ID,
3480 SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_ALE_RAM_INJECT_TYPE,
3481 SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_ALE_RAM_ECC_TYPE,
3484 { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P0_RX_FIFO_RAM_ID,
3485 SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P0_RX_FIFO_INJECT_TYPE,
3486 SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P0_RX_FIFO_ECC_TYPE,
3489 { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P0_TX_FIFO_RAM_ID,
3490 SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P0_TX_FIFO_INJECT_TYPE,
3491 SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P0_TX_FIFO_ECC_TYPE,
3494 { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P1_RX_FIFO_RAM_ID,
3495 SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P1_RX_FIFO_INJECT_TYPE,
3496 SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P1_RX_FIFO_ECC_TYPE,
3499 { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P1_TX_FIFO_RAM_ID,
3500 SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P1_TX_FIFO_INJECT_TYPE,
3501 SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P1_TX_FIFO_ECC_TYPE,
3504 { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P2_RX_FIFO_RAM_ID,
3505 SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P2_RX_FIFO_INJECT_TYPE,
3506 SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P2_RX_FIFO_ECC_TYPE,
3509 { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P2_TX_FIFO_RAM_ID,
3510 SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P2_TX_FIFO_INJECT_TYPE,
3511 SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P2_TX_FIFO_ECC_TYPE,
3574 { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_EST_RAM_RAM_ID,
3575 SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_EST_RAM_INJECT_TYPE,
3576 SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_EST_RAM_ECC_TYPE,
3587 { SDL_ADC0_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_RAM_ID,
3588 SDL_ADC0_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_INJECT_TYPE,
3589 SDL_ADC0_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_ECC_TYPE,
3592 { SDL_ADC0_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_RAM_ID,
3593 SDL_ADC0_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_INJECT_TYPE,
3594 SDL_ADC0_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_ECC_TYPE,
3605 { SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_ID,
3606 SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_INJECT_TYPE,
3607 SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_ECC_TYPE,
3618 { SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_ID,
3619 SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_INJECT_TYPE,
3620 SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_ECC_TYPE,
3631 { SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_ICB_RAMECC_RAM_ID,
3632 SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_ICB_RAMECC_INJECT_TYPE,
3633 SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_ICB_RAMECC_ECC_TYPE,
3636 { SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_ITE_RAMECC_RAM_ID,
3637 SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_ITE_RAMECC_INJECT_TYPE,
3638 SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_ITE_RAMECC_ECC_TYPE,
3641 { SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_LPI_RAMECC_RAM_ID,
3642 SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_LPI_RAMECC_INJECT_TYPE,
3643 SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_LPI_RAMECC_ECC_TYPE,
3654 { SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXIMFIFO_RAM_ID,
3655 SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXIMFIFO_INJECT_TYPE,
3656 SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXIMFIFO_ECC_TYPE,
3659 { SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXISFIFO_RAM_ID,
3660 SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXISFIFO_INJECT_TYPE,
3661 SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXISFIFO_ECC_TYPE,
3664 { SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_DIBRAM_RAM_ID,
3665 SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_DIBRAM_INJECT_TYPE,
3666 SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_DIBRAM_ECC_TYPE,
3669 { SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID,
3670 SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_INJECT_TYPE,
3671 SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ECC_TYPE,
3682 { SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_PNPFIFO_RAM_ID,
3683 SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_PNPFIFO_INJECT_TYPE,
3684 SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_PNPFIFO_ECC_TYPE,
3687 { SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_RXCPLFIFO_RAM_ID,
3688 SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_RXCPLFIFO_INJECT_TYPE,
3689 SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_RXCPLFIFO_ECC_TYPE,
3692 { SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_RPLYBUF_RAM_ID,
3693 SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_RPLYBUF_INJECT_TYPE,
3694 SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_RPLYBUF_ECC_TYPE,
3697 { SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXISRODR_RAM_ID,
3698 SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXISRODR_INJECT_TYPE,
3699 SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXISRODR_ECC_TYPE,
3710 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_RAM_ID,
3711 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_INJECT_TYPE,
3712 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_ECC_TYPE,
3713 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_MAX_NUM_CHECKERS,
3715 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_RAM_ID,
3716 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_INJECT_TYPE,
3717 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_ECC_TYPE,
3718 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_MAX_NUM_CHECKERS,
3720 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_RAM_ID,
3721 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_INJECT_TYPE,
3722 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_ECC_TYPE,
3723 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS,
3725 { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_RAM_ID,
3726 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_INJECT_TYPE,
3727 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_ECC_TYPE,
3728 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
3738 { SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKTRAM0_ECC_RAM_ID,
3739 SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKTRAM0_ECC_INJECT_TYPE,
3740 SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKTRAM0_ECC_ECC_TYPE,
3743 { SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKTRAM1_ECC_RAM_ID,
3744 SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKTRAM1_ECC_INJECT_TYPE,
3745 SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKTRAM1_ECC_ECC_TYPE,
3748 { SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKA_PROG_RAM_ECC_RAM_ID,
3749 SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKA_PROG_RAM_ECC_INJECT_TYPE,
3750 SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKA_PROG_RAM_ECC_ECC_TYPE,
3753 { SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK01_ECC_RAM_ID,
3754 SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK01_ECC_INJECT_TYPE,
3755 SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK01_ECC_ECC_TYPE,
3758 { SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK23_ECC_RAM_ID,
3759 SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK23_ECC_INJECT_TYPE,
3760 SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK23_ECC_ECC_TYPE,
3763 { SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK4_ECC_RAM_ID,
3764 SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK4_ECC_INJECT_TYPE,
3765 SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK4_ECC_ECC_TYPE,
3768 { SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK01_ECC_RAM_ID,
3769 SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK01_ECC_INJECT_TYPE,
3770 SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK01_ECC_ECC_TYPE,
3773 { SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK23_ECC_RAM_ID,
3774 SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK23_ECC_INJECT_TYPE,
3775 SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK23_ECC_ECC_TYPE,
3778 { SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK45_ECC_RAM_ID,
3779 SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK45_ECC_INJECT_TYPE,
3780 SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK45_ECC_ECC_TYPE,
3783 { SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK67_ECC_RAM_ID,
3784 SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK67_ECC_INJECT_TYPE,
3785 SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK67_ECC_ECC_TYPE,
3788 { SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK89_ECC_RAM_ID,
3789 SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK89_ECC_INJECT_TYPE,
3790 SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK89_ECC_ECC_TYPE,
3793 { SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK10_ECC_RAM_ID,
3794 SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK10_ECC_INJECT_TYPE,
3795 SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK10_ECC_ECC_TYPE,
3806 { SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_PDMA_AM64_MAIN1_PDMA_CORE_TF0_F0_TPRAM_60X128_SBW_SR_RAM_ID,
3807 SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_PDMA_AM64_MAIN1_PDMA_CORE_TF0_F0_TPRAM_60X128_SBW_SR_INJECT_TYPE,
3808 SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_PDMA_AM64_MAIN1_PDMA_CORE_TF0_F0_TPRAM_60X128_SBW_SR_ECC_TYPE,
3811 { SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_PDMA_AM64_MAIN1_PDMA_CORE_TF0_F1_TPRAM_60X128_SBW_SR_RAM_ID,
3812 SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_PDMA_AM64_MAIN1_PDMA_CORE_TF0_F1_TPRAM_60X128_SBW_SR_INJECT_TYPE,
3813 SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_PDMA_AM64_MAIN1_PDMA_CORE_TF0_F1_TPRAM_60X128_SBW_SR_ECC_TYPE,
3816 { SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_PDMA_AM64_MAIN1_PDMA_CORE_RF0_F0_TPRAM_68X144_SBW_SR_RAM_ID,
3817 SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_PDMA_AM64_MAIN1_PDMA_CORE_RF0_F0_TPRAM_68X144_SBW_SR_INJECT_TYPE,
3818 SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_PDMA_AM64_MAIN1_PDMA_CORE_RF0_F0_TPRAM_68X144_SBW_SR_ECC_TYPE,
3821 { SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_PDMA_AM64_MAIN1_PDMA_CORE_RF0_F1_TPRAM_68X144_SBW_SR_RAM_ID,
3822 SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_PDMA_AM64_MAIN1_PDMA_CORE_RF0_F1_TPRAM_68X144_SBW_SR_INJECT_TYPE,
3823 SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_PDMA_AM64_MAIN1_PDMA_CORE_RF0_F1_TPRAM_68X144_SBW_SR_ECC_TYPE,
3834 { SDL_USB0_USB3P0SS64_16FFC_USB3P0SS64_CORE_A_ECC_AGGR_USB3P0SS64_16FFC_USB3P0SS64_CORE_USB3P0_KSBUS_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID,
3835 SDL_USB0_USB3P0SS64_16FFC_USB3P0SS64_CORE_A_ECC_AGGR_USB3P0SS64_16FFC_USB3P0SS64_CORE_USB3P0_KSBUS_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_INJECT_TYPE,
3836 SDL_USB0_USB3P0SS64_16FFC_USB3P0SS64_CORE_A_ECC_AGGR_USB3P0SS64_16FFC_USB3P0SS64_CORE_USB3P0_KSBUS_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ECC_TYPE,
3847 { SDL_DMSC0_DMSC_LITE_ISRAM1_RAMECC_RAM_ID,
3848 SDL_DMSC0_DMSC_LITE_ISRAM1_RAMECC_INJECT_TYPE,
3849 SDL_DMSC0_DMSC_LITE_ISRAM1_RAMECC_ECC_TYPE,
3852 { SDL_DMSC0_DMSC_LITE_ISRAM0_RAMECC_RAM_ID,
3853 SDL_DMSC0_DMSC_LITE_ISRAM0_RAMECC_INJECT_TYPE,
3854 SDL_DMSC0_DMSC_LITE_ISRAM0_RAMECC_ECC_TYPE,
3857 { SDL_DMSC0_DMSC_LITE_IM_RAMECC_RAM_ID,
3858 SDL_DMSC0_DMSC_LITE_IM_RAMECC_INJECT_TYPE,
3859 SDL_DMSC0_DMSC_LITE_IM_RAMECC_ECC_TYPE,
3862 { SDL_DMSC0_DMSC_LITE_SR_RAMECC_RAM_ID,
3863 SDL_DMSC0_DMSC_LITE_SR_RAMECC_INJECT_TYPE,
3864 SDL_DMSC0_DMSC_LITE_SR_RAMECC_ECC_TYPE,
3875 { SDL_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_ID,
3876 SDL_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_INJECT_TYPE,
3877 SDL_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_ECC_TYPE,
3888 { SDL_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_ID,
3889 SDL_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_INJECT_TYPE,
3890 SDL_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_ECC_TYPE,
3901 { SDL_MSRAM_256K3_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_ID,
3902 SDL_MSRAM_256K3_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_INJECT_TYPE,
3903 SDL_MSRAM_256K3_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_ECC_TYPE,
3914 { SDL_MSRAM_256K5_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_ID,
3915 SDL_MSRAM_256K5_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_INJECT_TYPE,
3916 SDL_MSRAM_256K5_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_ECC_TYPE,
3927 { SDL_MSRAM_256K4_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_ID,
3928 SDL_MSRAM_256K4_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_INJECT_TYPE,
3929 SDL_MSRAM_256K4_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_ECC_TYPE,
3940 { SDL_MSRAM_256K7_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_ID,
3941 SDL_MSRAM_256K7_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_INJECT_TYPE,
3942 SDL_MSRAM_256K7_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_ECC_TYPE,
3953 { SDL_MSRAM_256K6_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_ID,
3954 SDL_MSRAM_256K6_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_INJECT_TYPE,
3955 SDL_MSRAM_256K6_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_ECC_TYPE,
3966 { SDL_ECC_AGGR1_IMAILBOX8_MAIN_0__RAMECC_RAM_ID,
3967 SDL_ECC_AGGR1_IMAILBOX8_MAIN_0__RAMECC_INJECT_TYPE,
3968 SDL_ECC_AGGR1_IMAILBOX8_MAIN_0__RAMECC_ECC_TYPE,
3971 { SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_RAM_ID,
3972 SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_INJECT_TYPE,
3973 SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_ECC_TYPE,
3974 SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
3976 { SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_RAM_ID,
3977 SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_INJECT_TYPE,
3978 SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ECC_TYPE,
3979 SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS,
3981 { SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_RAM_ID,
3982 SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_INJECT_TYPE,
3983 SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_ECC_TYPE,
3984 SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
3986 { SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_RAM_ID,
3987 SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_INJECT_TYPE,
3988 SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_ECC_TYPE,
3989 SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
3991 { SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_RAM_ID,
3992 SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_INJECT_TYPE,
3993 SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ECC_TYPE,
3994 SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS,
4004 { SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
4005 SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
4006 SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
4009 { SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
4010 SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
4011 SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
4012 SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
4022 { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
4023 SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
4024 SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
4027 { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
4028 SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
4029 SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
4030 SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
4040 { SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_EMMC8SS_16FFC_SDHC_WRAP_TXMEM_RAM_ID,
4041 SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_EMMC8SS_16FFC_SDHC_WRAP_TXMEM_INJECT_TYPE,
4042 SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_EMMC8SS_16FFC_SDHC_WRAP_TXMEM_ECC_TYPE,
4053 { SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_EMMC8SS_16FFC_SDHC_WRAP_RXMEM_RAM_ID,
4054 SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_EMMC8SS_16FFC_SDHC_WRAP_RXMEM_INJECT_TYPE,
4055 SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_EMMC8SS_16FFC_SDHC_WRAP_RXMEM_ECC_TYPE,
4066 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_ECC_RAM_ID,
4067 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_ECC_INJECT_TYPE,
4068 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_ECC_ECC_TYPE,
4071 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_ECC_RAM_ID,
4072 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_ECC_INJECT_TYPE,
4073 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_ECC_ECC_TYPE,
4076 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_RAM_ID,
4077 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_INJECT_TYPE,
4078 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_ECC_TYPE,
4079 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_MAX_NUM_CHECKERS,
4081 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_RAM_ID,
4082 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_INJECT_TYPE,
4083 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_ECC_TYPE,
4084 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_MAX_NUM_CHECKERS,
4086 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_RAM_ID,
4087 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_INJECT_TYPE,
4088 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_ECC_TYPE,
4089 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_MAX_NUM_CHECKERS,
4091 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_RAM_ID,
4092 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_INJECT_TYPE,
4093 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_ECC_TYPE,
4094 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
4096 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_RAM_ID,
4097 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_INJECT_TYPE,
4098 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_ECC_TYPE,
4099 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
4101 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_RAM_ID,
4102 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
4103 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
4104 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
4106 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_RAM_ID,
4107 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_INJECT_TYPE,
4108 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_ECC_TYPE,
4109 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_MAX_NUM_CHECKERS,
4111 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_RAM_ID,
4112 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_INJECT_TYPE,
4113 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_ECC_TYPE,
4114 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_MAX_NUM_CHECKERS,
4116 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_RAM_ID,
4117 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_INJECT_TYPE,
4118 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_ECC_TYPE,
4119 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_MAX_NUM_CHECKERS,
4121 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_RAM_ID,
4122 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_INJECT_TYPE,
4123 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_ECC_TYPE,
4124 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_MAX_NUM_CHECKERS,
4126 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_RAM_ID,
4127 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_INJECT_TYPE,
4128 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_ECC_TYPE,
4129 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_MAX_NUM_CHECKERS,
4131 { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_RAM_ID,
4132 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_INJECT_TYPE,
4133 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_ECC_TYPE,
4134 SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_MAX_NUM_CHECKERS,
4144 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID,
4145 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_INJECT_TYPE,
4146 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_ECC_TYPE,
4149 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID,
4150 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_INJECT_TYPE,
4151 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_ECC_TYPE,
4154 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID,
4155 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_INJECT_TYPE,
4156 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_ECC_TYPE,
4159 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID,
4160 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_INJECT_TYPE,
4161 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_ECC_TYPE,
4164 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID,
4165 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_INJECT_TYPE,
4166 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_ECC_TYPE,
4169 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID,
4170 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_INJECT_TYPE,
4171 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_ECC_TYPE,
4174 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID,
4175 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_INJECT_TYPE,
4176 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_ECC_TYPE,
4179 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID,
4180 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_INJECT_TYPE,
4181 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_ECC_TYPE,
4184 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID,
4185 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_INJECT_TYPE,
4186 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_ECC_TYPE,
4189 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID,
4190 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_INJECT_TYPE,
4191 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_ECC_TYPE,
4194 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID,
4195 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_INJECT_TYPE,
4196 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_ECC_TYPE,
4199 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID,
4200 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_INJECT_TYPE,
4201 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_ECC_TYPE,
4204 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID,
4205 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_INJECT_TYPE,
4206 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_ECC_TYPE,
4209 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID,
4210 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_INJECT_TYPE,
4211 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_ECC_TYPE,
4214 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID,
4215 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_INJECT_TYPE,
4216 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_ECC_TYPE,
4219 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID,
4220 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_INJECT_TYPE,
4221 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_ECC_TYPE,
4224 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID,
4225 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_INJECT_TYPE,
4226 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_ECC_TYPE,
4229 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID,
4230 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_INJECT_TYPE,
4231 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_ECC_TYPE,
4234 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID,
4235 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_INJECT_TYPE,
4236 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_ECC_TYPE,
4239 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID,
4240 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_INJECT_TYPE,
4241 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_ECC_TYPE,
4244 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID,
4245 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_INJECT_TYPE,
4246 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_ECC_TYPE,
4249 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_ATCM0_BANK0_RAM_ID,
4250 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_ATCM0_BANK0_INJECT_TYPE,
4251 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_ATCM0_BANK0_ECC_TYPE,
4254 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_ATCM0_BANK1_RAM_ID,
4255 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_ATCM0_BANK1_INJECT_TYPE,
4256 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_ATCM0_BANK1_ECC_TYPE,
4259 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B0TCM0_BANK0_RAM_ID,
4260 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B0TCM0_BANK0_INJECT_TYPE,
4261 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B0TCM0_BANK0_ECC_TYPE,
4264 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B0TCM0_BANK1_RAM_ID,
4265 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B0TCM0_BANK1_INJECT_TYPE,
4266 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B0TCM0_BANK1_ECC_TYPE,
4269 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B1TCM0_BANK0_RAM_ID,
4270 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B1TCM0_BANK0_INJECT_TYPE,
4271 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B1TCM0_BANK0_ECC_TYPE,
4274 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B1TCM0_BANK1_RAM_ID,
4275 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B1TCM0_BANK1_INJECT_TYPE,
4276 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B1TCM0_BANK1_ECC_TYPE,
4279 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID,
4280 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_INJECT_TYPE,
4281 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ECC_TYPE,
4284 { SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_MEM_MST_RAMECC_RAM_ID,
4285 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_MEM_MST_RAMECC_INJECT_TYPE,
4286 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_MEM_MST_RAMECC_ECC_TYPE,
4297 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_ITAG_RAM0_RAM_ID,
4298 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_ITAG_RAM0_INJECT_TYPE,
4299 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_ITAG_RAM0_ECC_TYPE,
4302 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_ITAG_RAM1_RAM_ID,
4303 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_ITAG_RAM1_INJECT_TYPE,
4304 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_ITAG_RAM1_ECC_TYPE,
4307 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_ITAG_RAM2_RAM_ID,
4308 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_ITAG_RAM2_INJECT_TYPE,
4309 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_ITAG_RAM2_ECC_TYPE,
4312 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_ITAG_RAM3_RAM_ID,
4313 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_ITAG_RAM3_INJECT_TYPE,
4314 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_ITAG_RAM3_ECC_TYPE,
4317 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_IDATA_BANK0_RAM_ID,
4318 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_IDATA_BANK0_INJECT_TYPE,
4319 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_IDATA_BANK0_ECC_TYPE,
4322 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_IDATA_BANK1_RAM_ID,
4323 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_IDATA_BANK1_INJECT_TYPE,
4324 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_IDATA_BANK1_ECC_TYPE,
4327 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_IDATA_BANK2_RAM_ID,
4328 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_IDATA_BANK2_INJECT_TYPE,
4329 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_IDATA_BANK2_ECC_TYPE,
4332 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_IDATA_BANK3_RAM_ID,
4333 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_IDATA_BANK3_INJECT_TYPE,
4334 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_IDATA_BANK3_ECC_TYPE,
4337 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DTAG_RAM0_RAM_ID,
4338 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DTAG_RAM0_INJECT_TYPE,
4339 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DTAG_RAM0_ECC_TYPE,
4342 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DTAG_RAM1_RAM_ID,
4343 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DTAG_RAM1_INJECT_TYPE,
4344 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DTAG_RAM1_ECC_TYPE,
4347 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DTAG_RAM2_RAM_ID,
4348 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DTAG_RAM2_INJECT_TYPE,
4349 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DTAG_RAM2_ECC_TYPE,
4352 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DTAG_RAM3_RAM_ID,
4353 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DTAG_RAM3_INJECT_TYPE,
4354 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DTAG_RAM3_ECC_TYPE,
4357 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDIRTY_RAM_RAM_ID,
4358 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDIRTY_RAM_INJECT_TYPE,
4359 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDIRTY_RAM_ECC_TYPE,
4362 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM0_RAM_ID,
4363 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM0_INJECT_TYPE,
4364 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM0_ECC_TYPE,
4367 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM1_RAM_ID,
4368 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM1_INJECT_TYPE,
4369 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM1_ECC_TYPE,
4372 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM2_RAM_ID,
4373 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM2_INJECT_TYPE,
4374 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM2_ECC_TYPE,
4377 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM3_RAM_ID,
4378 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM3_INJECT_TYPE,
4379 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM3_ECC_TYPE,
4382 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM4_RAM_ID,
4383 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM4_INJECT_TYPE,
4384 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM4_ECC_TYPE,
4387 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM5_RAM_ID,
4388 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM5_INJECT_TYPE,
4389 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM5_ECC_TYPE,
4392 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM6_RAM_ID,
4393 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM6_INJECT_TYPE,
4394 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM6_ECC_TYPE,
4397 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM7_RAM_ID,
4398 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM7_INJECT_TYPE,
4399 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM7_ECC_TYPE,
4402 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_ATCM1_BANK0_RAM_ID,
4403 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_ATCM1_BANK0_INJECT_TYPE,
4404 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_ATCM1_BANK0_ECC_TYPE,
4407 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_ATCM1_BANK1_RAM_ID,
4408 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_ATCM1_BANK1_INJECT_TYPE,
4409 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_ATCM1_BANK1_ECC_TYPE,
4412 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_B0TCM1_BANK0_RAM_ID,
4413 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_B0TCM1_BANK0_INJECT_TYPE,
4414 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_B0TCM1_BANK0_ECC_TYPE,
4417 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_B0TCM1_BANK1_RAM_ID,
4418 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_B0TCM1_BANK1_INJECT_TYPE,
4419 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_B0TCM1_BANK1_ECC_TYPE,
4422 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_B1TCM1_BANK0_RAM_ID,
4423 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_B1TCM1_BANK0_INJECT_TYPE,
4424 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_B1TCM1_BANK0_ECC_TYPE,
4427 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_B1TCM1_BANK1_RAM_ID,
4428 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_B1TCM1_BANK1_INJECT_TYPE,
4429 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_B1TCM1_BANK1_ECC_TYPE,
4432 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_KS_VIM_RAMECC_RAM_ID,
4433 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_KS_VIM_RAMECC_INJECT_TYPE,
4434 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_KS_VIM_RAMECC_ECC_TYPE,
4437 { SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_AXI2VBUSM_MEM_MST_RAMECC_RAM_ID,
4438 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_AXI2VBUSM_MEM_MST_RAMECC_INJECT_TYPE,
4439 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_AXI2VBUSM_MEM_MST_RAMECC_ECC_TYPE,
4450 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID,
4451 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_INJECT_TYPE,
4452 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_ECC_TYPE,
4455 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID,
4456 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_INJECT_TYPE,
4457 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_ECC_TYPE,
4460 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID,
4461 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_INJECT_TYPE,
4462 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_ECC_TYPE,
4465 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID,
4466 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_INJECT_TYPE,
4467 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_ECC_TYPE,
4470 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID,
4471 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_INJECT_TYPE,
4472 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_ECC_TYPE,
4475 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID,
4476 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_INJECT_TYPE,
4477 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_ECC_TYPE,
4480 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID,
4481 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_INJECT_TYPE,
4482 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_ECC_TYPE,
4485 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID,
4486 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_INJECT_TYPE,
4487 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_ECC_TYPE,
4490 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID,
4491 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_INJECT_TYPE,
4492 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_ECC_TYPE,
4495 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID,
4496 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_INJECT_TYPE,
4497 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_ECC_TYPE,
4500 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID,
4501 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_INJECT_TYPE,
4502 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_ECC_TYPE,
4505 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID,
4506 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_INJECT_TYPE,
4507 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_ECC_TYPE,
4510 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID,
4511 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_INJECT_TYPE,
4512 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_ECC_TYPE,
4515 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID,
4516 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_INJECT_TYPE,
4517 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_ECC_TYPE,
4520 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID,
4521 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_INJECT_TYPE,
4522 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_ECC_TYPE,
4525 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID,
4526 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_INJECT_TYPE,
4527 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_ECC_TYPE,
4530 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID,
4531 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_INJECT_TYPE,
4532 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_ECC_TYPE,
4535 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID,
4536 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_INJECT_TYPE,
4537 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_ECC_TYPE,
4540 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID,
4541 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_INJECT_TYPE,
4542 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_ECC_TYPE,
4545 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID,
4546 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_INJECT_TYPE,
4547 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_ECC_TYPE,
4550 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID,
4551 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_INJECT_TYPE,
4552 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_ECC_TYPE,
4555 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_ATCM0_BANK0_RAM_ID,
4556 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_ATCM0_BANK0_INJECT_TYPE,
4557 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_ATCM0_BANK0_ECC_TYPE,
4560 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_ATCM0_BANK1_RAM_ID,
4561 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_ATCM0_BANK1_INJECT_TYPE,
4562 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_ATCM0_BANK1_ECC_TYPE,
4565 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B0TCM0_BANK0_RAM_ID,
4566 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B0TCM0_BANK0_INJECT_TYPE,
4567 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B0TCM0_BANK0_ECC_TYPE,
4570 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B0TCM0_BANK1_RAM_ID,
4571 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B0TCM0_BANK1_INJECT_TYPE,
4572 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B0TCM0_BANK1_ECC_TYPE,
4575 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B1TCM0_BANK0_RAM_ID,
4576 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B1TCM0_BANK0_INJECT_TYPE,
4577 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B1TCM0_BANK0_ECC_TYPE,
4580 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B1TCM0_BANK1_RAM_ID,
4581 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B1TCM0_BANK1_INJECT_TYPE,
4582 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B1TCM0_BANK1_ECC_TYPE,
4585 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID,
4586 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_INJECT_TYPE,
4587 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ECC_TYPE,
4590 { SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_MEM_MST_RAMECC_RAM_ID,
4591 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_MEM_MST_RAMECC_INJECT_TYPE,
4592 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_MEM_MST_RAMECC_ECC_TYPE,
4603 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_ITAG_RAM0_RAM_ID,
4604 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_ITAG_RAM0_INJECT_TYPE,
4605 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_ITAG_RAM0_ECC_TYPE,
4608 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_ITAG_RAM1_RAM_ID,
4609 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_ITAG_RAM1_INJECT_TYPE,
4610 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_ITAG_RAM1_ECC_TYPE,
4613 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_ITAG_RAM2_RAM_ID,
4614 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_ITAG_RAM2_INJECT_TYPE,
4615 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_ITAG_RAM2_ECC_TYPE,
4618 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_ITAG_RAM3_RAM_ID,
4619 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_ITAG_RAM3_INJECT_TYPE,
4620 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_ITAG_RAM3_ECC_TYPE,
4623 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_IDATA_BANK0_RAM_ID,
4624 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_IDATA_BANK0_INJECT_TYPE,
4625 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_IDATA_BANK0_ECC_TYPE,
4628 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_IDATA_BANK1_RAM_ID,
4629 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_IDATA_BANK1_INJECT_TYPE,
4630 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_IDATA_BANK1_ECC_TYPE,
4633 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_IDATA_BANK2_RAM_ID,
4634 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_IDATA_BANK2_INJECT_TYPE,
4635 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_IDATA_BANK2_ECC_TYPE,
4638 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_IDATA_BANK3_RAM_ID,
4639 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_IDATA_BANK3_INJECT_TYPE,
4640 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_IDATA_BANK3_ECC_TYPE,
4643 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DTAG_RAM0_RAM_ID,
4644 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DTAG_RAM0_INJECT_TYPE,
4645 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DTAG_RAM0_ECC_TYPE,
4648 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DTAG_RAM1_RAM_ID,
4649 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DTAG_RAM1_INJECT_TYPE,
4650 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DTAG_RAM1_ECC_TYPE,
4653 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DTAG_RAM2_RAM_ID,
4654 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DTAG_RAM2_INJECT_TYPE,
4655 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DTAG_RAM2_ECC_TYPE,
4658 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DTAG_RAM3_RAM_ID,
4659 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DTAG_RAM3_INJECT_TYPE,
4660 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DTAG_RAM3_ECC_TYPE,
4663 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDIRTY_RAM_RAM_ID,
4664 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDIRTY_RAM_INJECT_TYPE,
4665 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDIRTY_RAM_ECC_TYPE,
4668 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM0_RAM_ID,
4669 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM0_INJECT_TYPE,
4670 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM0_ECC_TYPE,
4673 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM1_RAM_ID,
4674 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM1_INJECT_TYPE,
4675 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM1_ECC_TYPE,
4678 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM2_RAM_ID,
4679 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM2_INJECT_TYPE,
4680 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM2_ECC_TYPE,
4683 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM3_RAM_ID,
4684 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM3_INJECT_TYPE,
4685 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM3_ECC_TYPE,
4688 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM4_RAM_ID,
4689 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM4_INJECT_TYPE,
4690 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM4_ECC_TYPE,
4693 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM5_RAM_ID,
4694 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM5_INJECT_TYPE,
4695 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM5_ECC_TYPE,
4698 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM6_RAM_ID,
4699 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM6_INJECT_TYPE,
4700 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM6_ECC_TYPE,
4703 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM7_RAM_ID,
4704 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM7_INJECT_TYPE,
4705 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_DDATA_RAM7_ECC_TYPE,
4708 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_ATCM1_BANK0_RAM_ID,
4709 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_ATCM1_BANK0_INJECT_TYPE,
4710 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_ATCM1_BANK0_ECC_TYPE,
4713 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_ATCM1_BANK1_RAM_ID,
4714 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_ATCM1_BANK1_INJECT_TYPE,
4715 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_ATCM1_BANK1_ECC_TYPE,
4718 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_B0TCM1_BANK0_RAM_ID,
4719 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_B0TCM1_BANK0_INJECT_TYPE,
4720 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_B0TCM1_BANK0_ECC_TYPE,
4723 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_B0TCM1_BANK1_RAM_ID,
4724 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_B0TCM1_BANK1_INJECT_TYPE,
4725 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_B0TCM1_BANK1_ECC_TYPE,
4728 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_B1TCM1_BANK0_RAM_ID,
4729 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_B1TCM1_BANK0_INJECT_TYPE,
4730 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_B1TCM1_BANK0_ECC_TYPE,
4733 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_B1TCM1_BANK1_RAM_ID,
4734 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_B1TCM1_BANK1_INJECT_TYPE,
4735 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_PULSAR_LITE_B1TCM1_BANK1_ECC_TYPE,
4738 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_KS_VIM_RAMECC_RAM_ID,
4739 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_KS_VIM_RAMECC_INJECT_TYPE,
4740 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_KS_VIM_RAMECC_ECC_TYPE,
4743 { SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_AXI2VBUSM_MEM_MST_RAMECC_RAM_ID,
4744 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_AXI2VBUSM_MEM_MST_RAMECC_INJECT_TYPE,
4745 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_CPU1_AXI2VBUSM_MEM_MST_RAMECC_ECC_TYPE,
4756 { SDL_ECC_AGGR0_ITIMER_MGR1024_MAIN_0__TIMER_FSM_RAMECC_RAM_ID,
4757 SDL_ECC_AGGR0_ITIMER_MGR1024_MAIN_0__TIMER_FSM_RAMECC_INJECT_TYPE,
4758 SDL_ECC_AGGR0_ITIMER_MGR1024_MAIN_0__TIMER_FSM_RAMECC_ECC_TYPE,
4761 { SDL_ECC_AGGR0_ITIMER_MGR1024_MAIN_0__REPROG_FSM_RAMECC_RAM_ID,
4762 SDL_ECC_AGGR0_ITIMER_MGR1024_MAIN_0__REPROG_FSM_RAMECC_INJECT_TYPE,
4763 SDL_ECC_AGGR0_ITIMER_MGR1024_MAIN_0__REPROG_FSM_RAMECC_ECC_TYPE,
4766 { SDL_ECC_AGGR0_ITIMER_MGR1024_MAIN_0__EFIFO_RAMECC_RAM_ID,
4767 SDL_ECC_AGGR0_ITIMER_MGR1024_MAIN_0__EFIFO_RAMECC_INJECT_TYPE,
4768 SDL_ECC_AGGR0_ITIMER_MGR1024_MAIN_0__EFIFO_RAMECC_ECC_TYPE,
4779 { SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_PDMA_AM64_MAIN0_PDMA_CORE_TF0_F0_TPRAM_72X128_SBW_SR_RAM_ID,
4780 SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_PDMA_AM64_MAIN0_PDMA_CORE_TF0_F0_TPRAM_72X128_SBW_SR_INJECT_TYPE,
4781 SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_PDMA_AM64_MAIN0_PDMA_CORE_TF0_F0_TPRAM_72X128_SBW_SR_ECC_TYPE,
4784 { SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_PDMA_AM64_MAIN0_PDMA_CORE_TF0_F1_TPRAM_72X128_SBW_SR_RAM_ID,
4785 SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_PDMA_AM64_MAIN0_PDMA_CORE_TF0_F1_TPRAM_72X128_SBW_SR_INJECT_TYPE,
4786 SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_PDMA_AM64_MAIN0_PDMA_CORE_TF0_F1_TPRAM_72X128_SBW_SR_ECC_TYPE,
4789 { SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_PDMA_AM64_MAIN0_PDMA_CORE_RF0_F0_TPRAM_72X144_SBW_SR_RAM_ID,
4790 SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_PDMA_AM64_MAIN0_PDMA_CORE_RF0_F0_TPRAM_72X144_SBW_SR_INJECT_TYPE,
4791 SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_PDMA_AM64_MAIN0_PDMA_CORE_RF0_F0_TPRAM_72X144_SBW_SR_ECC_TYPE,
4794 { SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_PDMA_AM64_MAIN0_PDMA_CORE_RF0_F1_TPRAM_72X144_SBW_SR_RAM_ID,
4795 SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_PDMA_AM64_MAIN0_PDMA_CORE_RF0_F1_TPRAM_72X144_SBW_SR_INJECT_TYPE,
4796 SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_PDMA_AM64_MAIN0_PDMA_CORE_RF0_F1_TPRAM_72X144_SBW_SR_ECC_TYPE,
4805 #if defined(SOC_AM64X)
4845 ((
SDL_ecc_aggrRegs *)((uintptr_t)SDL_COMPUTE_CLUSTER0_CORE0_ECC_AGGR_BASE)),
4847 ((
SDL_ecc_aggrRegs *)((uintptr_t)SDL_COMPUTE_CLUSTER0_CORE1_ECC_AGGR_BASE)),
4853 #if defined(SOC_AM243X)
4903 #if defined(SOC_AM64X)
4909 SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_NUM_RAMS,
4913 SDL_ESM_INST_MAIN_ESM0,
4914 SDLR_ESM0_ESM_LVL_EVENT_PSRAMECC0_ECC_CORR_LEVEL_0,
4915 SDLR_ESM0_ESM_LVL_EVENT_PSRAMECC0_ECC_UNCORR_LEVEL_0
4919 SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_NUM_RAMS,
4923 SDL_ESM_INST_MAIN_ESM0,
4924 SDLR_ESM0_ESM_LVL_EVENT_MMCSD1_EMMCSDSS_RXMEM_CORR_ERR_LVL_0,
4925 SDLR_ESM0_ESM_LVL_EVENT_MMCSD1_EMMCSDSS_RXMEM_UNCORR_ERR_LVL_0
4929 SDL_ADC0_ADC12_CORE_FIFO_RAM_ECC_AGGR_NUM_RAMS,
4933 SDL_ESM_INST_MAIN_ESM0,
4934 SDLR_ESM0_ESM_LVL_EVENT_ADC0_ECC_CORRECTED_ERR_LEVEL_0,
4935 SDLR_ESM0_ESM_LVL_EVENT_ADC0_ECC_UNCORRECTED_ERR_LEVEL_0
4940 SDL_ECC_AGGR1_NUM_RAMS,
4944 SDL_ESM_INST_MAIN_ESM0,
4945 SDLR_ESM0_ESM_LVL_EVENT_ECC_AGGR1_CORR_LEVEL_0,
4946 SDLR_ESM0_ESM_LVL_EVENT_ECC_AGGR1_UNCORR_LEVEL_0
4951 SDL_ECC_AGGR0_NUM_RAMS,
4955 SDL_ESM_INST_MAIN_ESM0,
4956 SDLR_ESM0_ESM_LVL_EVENT_ECC_AGGR0_CORR_LEVEL_0,
4957 SDLR_ESM0_ESM_LVL_EVENT_ECC_AGGR0_UNCORR_LEVEL_0
4962 SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_NUM_RAMS,
4966 SDL_ESM_INST_MAIN_ESM0,
4967 SDLR_ESM0_ESM_LVL_EVENT_SA2_UL0_SA_UL_ECC_CORR_LEVEL_0,
4968 SDLR_ESM0_ESM_LVL_EVENT_SA2_UL0_SA_UL_ECC_UNCORR_LEVEL_0
4973 SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
4977 SDL_ESM_INST_MAIN_ESM0,
4978 SDLR_ESM0_ESM_LVL_EVENT_MCAN0_MCANSS_ECC_CORR_LVL_INT_0,
4979 SDLR_ESM0_ESM_LVL_EVENT_MCAN0_MCANSS_ECC_UNCORR_LVL_INT_0
4984 SDL_DMASS0_DMSS_AM64_ECCAGGR_NUM_RAMS,
4988 SDL_ESM_INST_MAIN_ESM0,
4989 SDLR_ESM0_ESM_LVL_EVENT_DMASS0_ECC_AGGR_0_ECC_CORRECTED_ERR_LEVEL_0,
4990 SDLR_ESM0_ESM_LVL_EVENT_DMASS0_ECC_AGGR_0_ECC_UNCORRECTED_ERR_LEVEL_0
4995 SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_NUM_RAMS,
4999 SDL_ESM_INST_MAIN_ESM0,
5000 SDLR_ESM0_ESM_LVL_EVENT_MMCSD1_EMMCSDSS_TXMEM_CORR_ERR_LVL_0,
5001 SDLR_ESM0_ESM_LVL_EVENT_MMCSD1_EMMCSDSS_TXMEM_UNCORR_ERR_LVL_0
5005 SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
5009 SDL_ESM_INST_MAIN_ESM0,
5010 SDLR_ESM0_ESM_LVL_EVENT_MCAN1_MCANSS_ECC_CORR_LVL_INT_0,
5011 SDLR_ESM0_ESM_LVL_EVENT_MCAN1_MCANSS_ECC_UNCORR_LVL_INT_0
5015 SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_NUM_RAMS,
5019 SDL_ESM_INST_MAIN_ESM0,
5020 SDLR_ESM0_ESM_LVL_EVENT_PRU_ICSSG1_PR1_ECC_SEC_ERR_PEND_0,
5021 SDLR_ESM0_ESM_LVL_EVENT_PRU_ICSSG1_PR1_ECC_DED_ERR_PEND_0
5025 SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_NUM_RAMS,
5029 SDL_ESM_INST_MAIN_ESM0,
5030 SDLR_ESM0_ESM_LVL_EVENT_PRU_ICSSG0_PR1_ECC_SEC_ERR_PEND_0,
5031 SDLR_ESM0_ESM_LVL_EVENT_PRU_ICSSG0_PR1_ECC_DED_ERR_PEND_0
5035 SDL_MSRAM_256K2_MSRAM32KX64E_ECC_AGGR_NUM_RAMS,
5039 SDL_ESM_INST_MAIN_ESM0,
5040 SDLR_ESM0_ESM_LVL_EVENT_MSRAM_256K2_ECC_CORR_LEVEL_0,
5041 SDLR_ESM0_ESM_LVL_EVENT_MSRAM_256K2_ECC_UNCORR_LEVEL_0
5045 SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_NUM_RAMS,
5049 SDL_ESM_INST_MAIN_ESM0,
5050 SDLR_ESM0_ESM_LVL_EVENT_FSS0_OSPI_0_OSPI_ECC_CORR_LVL_INTR_0,
5051 SDLR_ESM0_ESM_LVL_EVENT_FSS0_OSPI_0_OSPI_ECC_UNCORR_LVL_INTR_0
5055 SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_NUM_RAMS,
5059 SDL_ESM_INST_MAIN_ESM0,
5060 SDLR_ESM0_ESM_LVL_EVENT_CPSW0_ECC_SEC_PEND_0,
5061 SDLR_ESM0_ESM_LVL_EVENT_CPSW0_ECC_DED_PEND_0
5065 SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_NUM_RAMS,
5069 SDL_ESM_INST_MAIN_ESM0,
5070 SDLR_ESM0_ESM_LVL_EVENT_GICSS0_ECC_AGGR_CORR_LEVEL_0,
5071 SDLR_ESM0_ESM_LVL_EVENT_GICSS0_ECC_AGGR_UNCORR_LEVEL_0
5076 SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_NUM_RAMS,
5080 SDL_ESM_INST_MAIN_ESM0,
5081 SDLR_ESM0_ESM_LVL_EVENT_PCIE0_PCIE_ECC0_CORR_LEVEL_0,
5082 SDLR_ESM0_ESM_LVL_EVENT_PCIE0_PCIE_ECC0_UNCORR_LEVEL_0
5087 SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_NUM_RAMS,
5091 SDL_ESM_INST_MAIN_ESM0,
5098 SDL_USB0_USB3P0SS64_16FFC_USB3P0SS64_CORE_A_ECC_AGGR_NUM_RAMS,
5102 SDL_ESM_INST_MAIN_ESM0,
5103 SDLR_ESM0_ESM_LVL_EVENT_USB0_A_ECC_AGGR_CORRECTED_ERR_LEVEL_0,
5104 SDLR_ESM0_ESM_LVL_EVENT_USB0_A_ECC_AGGR_UNCORRECTED_ERR_LEVEL_0
5109 SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_NUM_RAMS,
5113 SDL_ESM_INST_MAIN_ESM0,
5114 SDLR_ESM0_ESM_LVL_EVENT_PDMA1_ECC_SEC_PEND_0,
5115 SDLR_ESM0_ESM_LVL_EVENT_PDMA1_ECC_DED_PEND_0
5120 SDL_DMSC0_DMSC_LITE_NUM_RAMS,
5124 SDL_ESM_INST_MAIN_ESM0,
5125 SDLR_ESM0_ESM_LVL_EVENT_DMSC0_ECC_AGGR_0_ECC_CORRECTED_ERR_LEVEL_0,
5126 SDLR_ESM0_ESM_LVL_EVENT_DMSC0_ECC_AGGR_0_ECC_UNCORRECTED_ERR_LEVEL_0
5131 SDL_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_NUM_RAMS,
5135 SDL_ESM_INST_MAIN_ESM0,
5136 SDLR_ESM0_ESM_LVL_EVENT_MSRAM_256K1_ECC_CORR_LEVEL_0,
5137 SDLR_ESM0_ESM_LVL_EVENT_MSRAM_256K1_ECC_UNCORR_LEVEL_0
5141 SDL_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_NUM_RAMS,
5145 SDL_ESM_INST_MAIN_ESM0,
5146 SDLR_ESM0_ESM_LVL_EVENT_MSRAM_256K0_ECC_CORR_LEVEL_0,
5147 SDLR_ESM0_ESM_LVL_EVENT_MSRAM_256K0_ECC_UNCORR_LEVEL_0
5151 SDL_MSRAM_256K3_MSRAM32KX64E_ECC_AGGR_NUM_RAMS,
5155 SDL_ESM_INST_MAIN_ESM0,
5156 SDLR_ESM0_ESM_LVL_EVENT_MSRAM_256K3_ECC_CORR_LEVEL_0,
5157 SDLR_ESM0_ESM_LVL_EVENT_MSRAM_256K3_ECC_UNCORR_LEVEL_0
5161 SDL_MSRAM_256K5_MSRAM32KX64E_ECC_AGGR_NUM_RAMS,
5165 SDL_ESM_INST_MAIN_ESM0,
5166 SDLR_ESM0_ESM_LVL_EVENT_MSRAM_256K5_ECC_CORR_LEVEL_0,
5167 SDLR_ESM0_ESM_LVL_EVENT_MSRAM_256K5_ECC_UNCORR_LEVEL_0
5171 SDL_MSRAM_256K4_MSRAM32KX64E_ECC_AGGR_NUM_RAMS,
5175 SDL_ESM_INST_MAIN_ESM0,
5176 SDLR_ESM0_ESM_LVL_EVENT_MSRAM_256K4_ECC_CORR_LEVEL_0,
5177 SDLR_ESM0_ESM_LVL_EVENT_MSRAM_256K4_ECC_UNCORR_LEVEL_0
5181 SDL_MSRAM_256K7_MSRAM32KX64E_ECC_AGGR_NUM_RAMS,
5185 SDL_ESM_INST_MAIN_ESM0,
5186 SDLR_ESM0_ESM_LVL_EVENT_MSRAM_256K7_ECC_CORR_LEVEL_0,
5187 SDLR_ESM0_ESM_LVL_EVENT_MSRAM_256K7_ECC_UNCORR_LEVEL_0
5191 SDL_MSRAM_256K6_MSRAM32KX64E_ECC_AGGR_NUM_RAMS,
5195 SDL_ESM_INST_MAIN_ESM0,
5196 SDLR_ESM0_ESM_LVL_EVENT_MSRAM_256K6_ECC_CORR_LEVEL_0,
5197 SDLR_ESM0_ESM_LVL_EVENT_MSRAM_256K6_ECC_UNCORR_LEVEL_0
5201 SDL_MCU_M4FSS0_BLAZAR_ECC_NUM_RAMS,
5205 SDL_ESM_INST_MCU_ESM0,
5206 SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_M4FSS0_ECC_AGGR_0_ECC_CORRECTED_ERR_LEVEL_0,
5207 SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_M4FSS0_ECC_AGGR_0_ECC_UNCORRECTED_ERR_LEVEL_0
5211 SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_NUM_RAMS,
5215 SDL_ESM_INST_MAIN_ESM0,
5216 SDLR_ESM0_ESM_LVL_EVENT_PDMA0_ECC_SEC_PEND_0,
5217 SDLR_ESM0_ESM_LVL_EVENT_PDMA0_ECC_DED_PEND_0
5222 SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_NUM_RAMS,
5226 SDL_ESM_INST_MAIN_ESM0,
5227 SDLR_ESM0_ESM_LVL_EVENT_MMCSD0_EMMCSS_RXMEM_CORR_ERR_LVL_0,
5228 SDLR_ESM0_ESM_LVL_EVENT_MMCSD0_EMMCSS_RXMEM_UNCORR_ERR_LVL_0
5232 SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_NUM_RAMS,
5236 SDL_ESM_INST_MAIN_ESM0,
5237 SDLR_ESM0_ESM_LVL_EVENT_MMCSD0_EMMCSS_TXMEM_CORR_ERR_LVL_0,
5238 SDLR_ESM0_ESM_LVL_EVENT_MMCSD0_EMMCSS_TXMEM_UNCORR_ERR_LVL_0
5242 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_NUM_RAMS,
5246 SDL_ESM_INST_MAIN_ESM0,
5247 SDLR_ESM0_ESM_LVL_EVENT_VTM0_CORR_LEVEL_0,
5248 SDLR_ESM0_ESM_LVL_EVENT_VTM0_UNCORR_LEVEL_0
5252 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_NUM_RAMS,
5256 SDL_ESM_INST_MAIN_ESM0,
5257 SDLR_ESM0_ESM_LVL_EVENT_R5FSS1_CORE0_ECC_CORRECTED_LEVEL_0,
5258 SDLR_ESM0_ESM_LVL_EVENT_R5FSS1_CORE0_ECC_UNCORRECTED_LEVEL_0
5262 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_NUM_RAMS,
5266 SDL_ESM_INST_MAIN_ESM0,
5267 SDLR_ESM0_ESM_LVL_EVENT_R5FSS1_CORE1_ECC_CORRECTED_LEVEL_0,
5268 SDLR_ESM0_ESM_LVL_EVENT_R5FSS1_CORE1_ECC_UNCORRECTED_LEVEL_0
5272 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_NUM_RAMS,
5276 SDL_ESM_INST_MAIN_ESM0,
5277 SDLR_ESM0_ESM_LVL_EVENT_R5FSS0_CORE0_ECC_CORRECTED_LEVEL_0,
5278 SDLR_ESM0_ESM_LVL_EVENT_R5FSS0_CORE0_ECC_UNCORRECTED_LEVEL_0
5282 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_NUM_RAMS,
5286 SDL_ESM_INST_MAIN_ESM0,
5287 SDLR_ESM0_ESM_LVL_EVENT_R5FSS0_CORE1_ECC_CORRECTED_LEVEL_0,
5288 SDLR_ESM0_ESM_LVL_EVENT_R5FSS0_CORE1_ECC_UNCORRECTED_LEVEL_0
5292 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_NUM_RAMS,
5296 SDL_ESM_INST_MAIN_ESM0,
5297 SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR0_CORRECTED_ERR_LEVEL_0,
5298 SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR0_UNCORRECTED_ERR_LEVEL_0
5302 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_NUM_RAMS,
5306 SDL_ESM_INST_MAIN_ESM0,
5307 SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR_COREPAC_CORRECTED_ERR_LEVEL_0,
5308 SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR_COREPAC_UNCORRECTED_ERR_LEVEL_0
5312 SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_NUM_RAMS,
5316 SDL_ESM_INST_MAIN_ESM0,
5317 SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR1_CORRECTED_ERR_LEVEL_0,
5318 SDLR_ESM0_ESM_LVL_EVENT_A53SS0_ECC_ECCAGGR1_UNCORRECTED_ERR_LEVEL_0
5323 #if defined(SOC_AM243X)
5329 SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_NUM_RAMS,
5333 SDL_ESM_INST_MAIN_ESM0,
5334 SDLR_ESM0_ESM_LVL_EVENT_PSRAMECC0_ECC_CORR_LEVEL_0,
5335 SDLR_ESM0_ESM_LVL_EVENT_PSRAMECC0_ECC_UNCORR_LEVEL_0
5339 SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_NUM_RAMS,
5343 SDL_ESM_INST_MAIN_ESM0,
5344 SDLR_ESM0_ESM_LVL_EVENT_MMCSD1_EMMCSDSS_RXMEM_CORR_ERR_LVL_0,
5345 SDLR_ESM0_ESM_LVL_EVENT_MMCSD1_EMMCSDSS_RXMEM_UNCORR_ERR_LVL_0
5349 SDL_ADC0_ADC12_CORE_FIFO_RAM_ECC_AGGR_NUM_RAMS,
5353 SDL_ESM_INST_MAIN_ESM0,
5354 SDLR_ESM0_ESM_LVL_EVENT_ADC0_ECC_CORRECTED_ERR_LEVEL_0,
5355 SDLR_ESM0_ESM_LVL_EVENT_ADC0_ECC_UNCORRECTED_ERR_LEVEL_0
5360 SDL_ECC_AGGR1_NUM_RAMS,
5364 SDL_ESM_INST_MAIN_ESM0,
5365 SDLR_ESM0_ESM_LVL_EVENT_ECC_AGGR1_CORR_LEVEL_0,
5366 SDLR_ESM0_ESM_LVL_EVENT_ECC_AGGR1_UNCORR_LEVEL_0
5371 SDL_ECC_AGGR0_NUM_RAMS,
5375 SDL_ESM_INST_MAIN_ESM0,
5376 SDLR_ESM0_ESM_LVL_EVENT_ECC_AGGR0_CORR_LEVEL_0,
5377 SDLR_ESM0_ESM_LVL_EVENT_ECC_AGGR0_UNCORR_LEVEL_0
5382 SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_NUM_RAMS,
5386 SDL_ESM_INST_MAIN_ESM0,
5387 SDLR_ESM0_ESM_LVL_EVENT_SA2_UL0_SA_UL_ECC_CORR_LEVEL_0,
5388 SDLR_ESM0_ESM_LVL_EVENT_SA2_UL0_SA_UL_ECC_UNCORR_LEVEL_0
5393 SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
5397 SDL_ESM_INST_MAIN_ESM0,
5398 SDLR_ESM0_ESM_LVL_EVENT_MCAN0_MCANSS_ECC_CORR_LVL_INT_0,
5399 SDLR_ESM0_ESM_LVL_EVENT_MCAN0_MCANSS_ECC_UNCORR_LVL_INT_0
5404 SDL_DMASS0_DMSS_AM64_ECCAGGR_NUM_RAMS,
5408 SDL_ESM_INST_MAIN_ESM0,
5409 SDLR_ESM0_ESM_LVL_EVENT_DMASS0_ECC_AGGR_0_ECC_CORRECTED_ERR_LEVEL_0,
5410 SDLR_ESM0_ESM_LVL_EVENT_DMASS0_ECC_AGGR_0_ECC_UNCORRECTED_ERR_LEVEL_0
5415 SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_NUM_RAMS,
5419 SDL_ESM_INST_MAIN_ESM0,
5420 SDLR_ESM0_ESM_LVL_EVENT_MMCSD1_EMMCSDSS_TXMEM_CORR_ERR_LVL_0,
5421 SDLR_ESM0_ESM_LVL_EVENT_MMCSD1_EMMCSDSS_TXMEM_UNCORR_ERR_LVL_0
5425 SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
5429 SDL_ESM_INST_MAIN_ESM0,
5430 SDLR_ESM0_ESM_LVL_EVENT_MCAN1_MCANSS_ECC_CORR_LVL_INT_0,
5431 SDLR_ESM0_ESM_LVL_EVENT_MCAN1_MCANSS_ECC_UNCORR_LVL_INT_0
5435 SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_NUM_RAMS,
5439 SDL_ESM_INST_MAIN_ESM0,
5440 SDLR_ESM0_ESM_LVL_EVENT_PRU_ICSSG1_PR1_ECC_SEC_ERR_PEND_0,
5441 SDLR_ESM0_ESM_LVL_EVENT_PRU_ICSSG1_PR1_ECC_DED_ERR_PEND_0
5445 SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_NUM_RAMS,
5449 SDL_ESM_INST_MAIN_ESM0,
5450 SDLR_ESM0_ESM_LVL_EVENT_PRU_ICSSG0_PR1_ECC_SEC_ERR_PEND_0,
5451 SDLR_ESM0_ESM_LVL_EVENT_PRU_ICSSG0_PR1_ECC_DED_ERR_PEND_0
5455 SDL_MSRAM_256K2_MSRAM32KX64E_ECC_AGGR_NUM_RAMS,
5459 SDL_ESM_INST_MAIN_ESM0,
5460 SDLR_ESM0_ESM_LVL_EVENT_MSRAM_256K2_ECC_CORR_LEVEL_0,
5461 SDLR_ESM0_ESM_LVL_EVENT_MSRAM_256K2_ECC_UNCORR_LEVEL_0
5465 SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_NUM_RAMS,
5469 SDL_ESM_INST_MAIN_ESM0,
5470 SDLR_ESM0_ESM_LVL_EVENT_FSS0_OSPI_0_OSPI_ECC_CORR_LVL_INTR_0,
5471 SDLR_ESM0_ESM_LVL_EVENT_FSS0_OSPI_0_OSPI_ECC_UNCORR_LVL_INTR_0
5475 SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_NUM_RAMS,
5479 SDL_ESM_INST_MAIN_ESM0,
5480 SDLR_ESM0_ESM_LVL_EVENT_CPSW0_ECC_SEC_PEND_0,
5481 SDLR_ESM0_ESM_LVL_EVENT_CPSW0_ECC_DED_PEND_0
5485 SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_NUM_RAMS,
5489 SDL_ESM_INST_MAIN_ESM0,
5490 SDLR_ESM0_ESM_LVL_EVENT_GICSS0_ECC_AGGR_CORR_LEVEL_0,
5491 SDLR_ESM0_ESM_LVL_EVENT_GICSS0_ECC_AGGR_UNCORR_LEVEL_0
5496 SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_NUM_RAMS,
5500 SDL_ESM_INST_MAIN_ESM0,
5501 SDLR_ESM0_ESM_LVL_EVENT_PCIE0_PCIE_ECC0_CORR_LEVEL_0,
5502 SDLR_ESM0_ESM_LVL_EVENT_PCIE0_PCIE_ECC0_UNCORR_LEVEL_0
5507 SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_NUM_RAMS,
5511 SDL_ESM_INST_MAIN_ESM0,
5518 SDL_USB0_USB3P0SS64_16FFC_USB3P0SS64_CORE_A_ECC_AGGR_NUM_RAMS,
5522 SDL_ESM_INST_MAIN_ESM0,
5523 SDLR_ESM0_ESM_LVL_EVENT_USB0_A_ECC_AGGR_CORRECTED_ERR_LEVEL_0,
5524 SDLR_ESM0_ESM_LVL_EVENT_USB0_A_ECC_AGGR_UNCORRECTED_ERR_LEVEL_0
5529 SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_NUM_RAMS,
5533 SDL_ESM_INST_MAIN_ESM0,
5534 SDLR_ESM0_ESM_LVL_EVENT_PDMA1_ECC_SEC_PEND_0,
5535 SDLR_ESM0_ESM_LVL_EVENT_PDMA1_ECC_DED_PEND_0
5540 SDL_DMSC0_DMSC_LITE_NUM_RAMS,
5544 SDL_ESM_INST_MAIN_ESM0,
5545 SDLR_ESM0_ESM_LVL_EVENT_DMSC0_ECC_AGGR_0_ECC_CORRECTED_ERR_LEVEL_0,
5546 SDLR_ESM0_ESM_LVL_EVENT_DMSC0_ECC_AGGR_0_ECC_UNCORRECTED_ERR_LEVEL_0
5551 SDL_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_NUM_RAMS,
5555 SDL_ESM_INST_MAIN_ESM0,
5556 SDLR_ESM0_ESM_LVL_EVENT_MSRAM_256K1_ECC_CORR_LEVEL_0,
5557 SDLR_ESM0_ESM_LVL_EVENT_MSRAM_256K1_ECC_UNCORR_LEVEL_0
5561 SDL_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_NUM_RAMS,
5565 SDL_ESM_INST_MAIN_ESM0,
5566 SDLR_ESM0_ESM_LVL_EVENT_MSRAM_256K0_ECC_CORR_LEVEL_0,
5567 SDLR_ESM0_ESM_LVL_EVENT_MSRAM_256K0_ECC_UNCORR_LEVEL_0
5571 SDL_MSRAM_256K3_MSRAM32KX64E_ECC_AGGR_NUM_RAMS,
5575 SDL_ESM_INST_MAIN_ESM0,
5576 SDLR_ESM0_ESM_LVL_EVENT_MSRAM_256K3_ECC_CORR_LEVEL_0,
5577 SDLR_ESM0_ESM_LVL_EVENT_MSRAM_256K3_ECC_UNCORR_LEVEL_0
5581 SDL_MSRAM_256K5_MSRAM32KX64E_ECC_AGGR_NUM_RAMS,
5585 SDL_ESM_INST_MAIN_ESM0,
5586 SDLR_ESM0_ESM_LVL_EVENT_MSRAM_256K5_ECC_CORR_LEVEL_0,
5587 SDLR_ESM0_ESM_LVL_EVENT_MSRAM_256K5_ECC_UNCORR_LEVEL_0
5591 SDL_MSRAM_256K4_MSRAM32KX64E_ECC_AGGR_NUM_RAMS,
5595 SDL_ESM_INST_MAIN_ESM0,
5596 SDLR_ESM0_ESM_LVL_EVENT_MSRAM_256K4_ECC_CORR_LEVEL_0,
5597 SDLR_ESM0_ESM_LVL_EVENT_MSRAM_256K4_ECC_UNCORR_LEVEL_0
5601 SDL_MSRAM_256K7_MSRAM32KX64E_ECC_AGGR_NUM_RAMS,
5605 SDL_ESM_INST_MAIN_ESM0,
5606 SDLR_ESM0_ESM_LVL_EVENT_MSRAM_256K7_ECC_CORR_LEVEL_0,
5607 SDLR_ESM0_ESM_LVL_EVENT_MSRAM_256K7_ECC_UNCORR_LEVEL_0
5611 SDL_MSRAM_256K6_MSRAM32KX64E_ECC_AGGR_NUM_RAMS,
5615 SDL_ESM_INST_MAIN_ESM0,
5616 SDLR_ESM0_ESM_LVL_EVENT_MSRAM_256K6_ECC_CORR_LEVEL_0,
5617 SDLR_ESM0_ESM_LVL_EVENT_MSRAM_256K6_ECC_UNCORR_LEVEL_0
5621 SDL_MCU_M4FSS0_BLAZAR_ECC_NUM_RAMS,
5625 SDL_ESM_INST_MCU_ESM0,
5626 SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_M4FSS0_ECC_AGGR_0_ECC_CORRECTED_ERR_LEVEL_0,
5627 SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_M4FSS0_ECC_AGGR_0_ECC_UNCORRECTED_ERR_LEVEL_0
5631 SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_NUM_RAMS,
5635 SDL_ESM_INST_MAIN_ESM0,
5636 SDLR_ESM0_ESM_LVL_EVENT_PDMA0_ECC_SEC_PEND_0,
5637 SDLR_ESM0_ESM_LVL_EVENT_PDMA0_ECC_DED_PEND_0
5642 SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_NUM_RAMS,
5646 SDL_ESM_INST_MAIN_ESM0,
5647 SDLR_ESM0_ESM_LVL_EVENT_MMCSD0_EMMCSS_RXMEM_CORR_ERR_LVL_0,
5648 SDLR_ESM0_ESM_LVL_EVENT_MMCSD0_EMMCSS_RXMEM_UNCORR_ERR_LVL_0
5652 SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_NUM_RAMS,
5656 SDL_ESM_INST_MAIN_ESM0,
5657 SDLR_ESM0_ESM_LVL_EVENT_MMCSD0_EMMCSS_TXMEM_CORR_ERR_LVL_0,
5658 SDLR_ESM0_ESM_LVL_EVENT_MMCSD0_EMMCSS_TXMEM_UNCORR_ERR_LVL_0
5662 SDL_VTM0_K3VTM_N16FFC_ECCAGGR_NUM_RAMS,
5666 SDL_ESM_INST_MAIN_ESM0,
5667 SDLR_ESM0_ESM_LVL_EVENT_VTM0_CORR_LEVEL_0,
5668 SDLR_ESM0_ESM_LVL_EVENT_VTM0_UNCORR_LEVEL_0
5672 SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_NUM_RAMS,
5676 SDL_ESM_INST_MAIN_ESM0,
5677 SDLR_ESM0_ESM_LVL_EVENT_R5FSS1_CORE0_ECC_CORRECTED_LEVEL_0,
5678 SDLR_ESM0_ESM_LVL_EVENT_R5FSS1_CORE0_ECC_UNCORRECTED_LEVEL_0
5682 SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_NUM_RAMS,
5686 SDL_ESM_INST_MAIN_ESM0,
5687 SDLR_ESM0_ESM_LVL_EVENT_R5FSS1_CORE1_ECC_CORRECTED_LEVEL_0,
5688 SDLR_ESM0_ESM_LVL_EVENT_R5FSS1_CORE1_ECC_UNCORRECTED_LEVEL_0
5692 SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_NUM_RAMS,
5696 SDL_ESM_INST_MAIN_ESM0,
5697 SDLR_ESM0_ESM_LVL_EVENT_R5FSS0_CORE0_ECC_CORRECTED_LEVEL_0,
5698 SDLR_ESM0_ESM_LVL_EVENT_R5FSS0_CORE0_ECC_UNCORRECTED_LEVEL_0
5702 SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_NUM_RAMS,
5706 SDL_ESM_INST_MAIN_ESM0,
5707 SDLR_ESM0_ESM_LVL_EVENT_R5FSS0_CORE1_ECC_CORRECTED_LEVEL_0,
5708 SDLR_ESM0_ESM_LVL_EVENT_R5FSS0_CORE1_ECC_UNCORRECTED_LEVEL_0