|
AM243x MCU+ SDK
08.06.00
|
|
Go to the documentation of this file.
61 #include <drivers/hw_include/csl_types.h>
62 #include <drivers/hw_include/cslr_mcspi.h>
63 #include <drivers/hw_include/cslr.h>
65 #if defined (DMA_VERSION_MCSPI_UDMA)
69 #if defined (DMA_VERSION_MCSPI_EDMA)
70 #include <drivers/mcspi/v0/dma/edma/mcspi_dma_edma.h>
93 #define MCSPI_CHANNEL_0 (0U)
94 #define MCSPI_CHANNEL_1 (1U)
95 #define MCSPI_CHANNEL_2 (2U)
96 #define MCSPI_CHANNEL_3 (3U)
107 #define MCSPI_OPER_MODE_POLLED (0U)
108 #define MCSPI_OPER_MODE_INTERRUPT (1U)
109 #define MCSPI_OPER_MODE_DMA (2U)
113 #define MCSPI_MAX_NUM_CHANNELS (4U)
123 #define MCSPI_TRANSFER_COMPLETED (0U)
124 #define MCSPI_TRANSFER_STARTED (1U)
125 #define MCSPI_TRANSFER_CANCELLED (2U)
126 #define MCSPI_TRANSFER_FAILED (3U)
127 #define MCSPI_TRANSFER_CSN_DEASSERT (4U)
128 #define MCSPI_TRANSFER_TIMEOUT (5U)
150 #define MCSPI_TRANSFER_MODE_BLOCKING (0U)
155 #define MCSPI_TRANSFER_MODE_CALLBACK (1U)
174 #define MCSPI_MS_MODE_CONTROLLER (CSL_MCSPI_MODULCTRL_MS_MASTER)
176 #define MCSPI_MS_MODE_PERIPHERAL (CSL_MCSPI_MODULCTRL_MS_SLAVE)
193 #define MCSPI_FF_POL0_PHA0 (0U)
194 #define MCSPI_FF_POL0_PHA1 (1U)
195 #define MCSPI_FF_POL1_PHA0 (2U)
196 #define MCSPI_FF_POL1_PHA1 (3U)
208 #define MCSPI_CS_POL_HIGH (CSL_MCSPI_CH0CONF_EPOL_ACTIVEHIGH)
210 #define MCSPI_CS_POL_LOW (CSL_MCSPI_CH0CONF_EPOL_ACTIVELOW)
219 #define MCSPI_TR_MODE_TX_RX (CSL_MCSPI_CH0CONF_TRM_TRANSRECEI)
220 #define MCSPI_TR_MODE_RX_ONLY (CSL_MCSPI_CH0CONF_TRM_RECEIVONLY)
221 #define MCSPI_TR_MODE_TX_ONLY (CSL_MCSPI_CH0CONF_TRM_TRANSONLY)
231 #define MCSPI_IS_D0 (CSL_MCSPI_CH0CONF_IS_LINE0)
233 #define MCSPI_IS_D1 (CSL_MCSPI_CH0CONF_IS_LINE1)
243 #define MCSPI_DPE_ENABLE (CSL_MCSPI_CH0CONF_DPE0_ENABLED)
245 #define MCSPI_DPE_DISABLE (CSL_MCSPI_CH0CONF_DPE0_DISABLED)
254 #define MCSPI_SLV_CS_SELECT_0 (CSL_MCSPI_CH0CONF_SPIENSLV_SPIEN0)
255 #define MCSPI_SLV_CS_SELECT_1 (CSL_MCSPI_CH0CONF_SPIENSLV_SPIEN1)
256 #define MCSPI_SLV_CS_SELECT_2 (CSL_MCSPI_CH0CONF_SPIENSLV_SPIEN2)
257 #define MCSPI_SLV_CS_SELECT_3 (CSL_MCSPI_CH0CONF_SPIENSLV_SPIEN3)
267 #define MCSPI_SB_POL_HIGH (CSL_MCSPI_CH0CONF_SBPOL_HIGHLEVEL)
269 #define MCSPI_SB_POL_LOW (CSL_MCSPI_CH0CONF_SBPOL_LOWLEVEL)
281 #define MCSPI_TCS0_0_CLK (CSL_MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY)
283 #define MCSPI_TCS0_1_CLK (CSL_MCSPI_CH0CONF_TCS0_ONECYCLEDLY)
285 #define MCSPI_TCS0_2_CLK (CSL_MCSPI_CH0CONF_TCS0_TWOCYCLEDLY)
287 #define MCSPI_TCS0_3_CLK (CSL_MCSPI_CH0CONF_TCS0_THREECYCLEDLY)
300 #define MCSPI_CH_MODE_SINGLE (CSL_MCSPI_MODULCTRL_SINGLE_SINGLE)
302 #define MCSPI_CH_MODE_MULTI (CSL_MCSPI_MODULCTRL_SINGLE_MULTI)
315 #define MCSPI_PINMODE_3PIN (CSL_MCSPI_MODULCTRL_PIN34_3PINMODE)
316 #define MCSPI_PINMODE_4PIN (CSL_MCSPI_MODULCTRL_PIN34_4PINMODE)
328 #define MCSPI_INITDLY_0 (CSL_MCSPI_MODULCTRL_INITDLY_NODELAY)
330 #define MCSPI_INITDLY_4 (CSL_MCSPI_MODULCTRL_INITDLY_4CLKDLY)
332 #define MCSPI_INITDLY_8 (CSL_MCSPI_MODULCTRL_INITDLY_8CLKDLY)
334 #define MCSPI_INITDLY_16 (CSL_MCSPI_MODULCTRL_INITDLY_16CLKDLY)
336 #define MCSPI_INITDLY_32 (CSL_MCSPI_MODULCTRL_INITDLY_32CLKDLY)
854 #define MCSPI_FIFO_LENGTH (64U)
858 #define MCSPI_RX_FIFO_ENABLE ((uint32_t) CSL_MCSPI_CH0CONF_FFER_FFENABLED \
860 CSL_MCSPI_CH0CONF_FFER_SHIFT)
865 #define MCSPI_RX_FIFO_DISABLE ((uint32_t) CSL_MCSPI_CH0CONF_FFER_FFDISABLED \
866 << CSL_MCSPI_CH0CONF_FFER_SHIFT)
871 #define MCSPI_TX_FIFO_ENABLE ((uint32_t) CSL_MCSPI_CH0CONF_FFEW_FFENABLED \
872 << CSL_MCSPI_CH0CONF_FFEW_SHIFT)
877 #define MCSPI_TX_FIFO_DISABLE ((uint32_t) CSL_MCSPI_CH0CONF_FFEW_FFDISABLED \
878 << CSL_MCSPI_CH0CONF_FFEW_SHIFT)
883 #define MCSPI_REG_OFFSET (0x14U)
885 #define MCSPI_CHCONF(x) ((uint32_t) CSL_MCSPI_CH0CONF + \
886 (uint32_t) ((uint32_t) MCSPI_REG_OFFSET * \
889 #define MCSPI_CHSTAT(x) ((uint32_t) CSL_MCSPI_CH0STAT + \
890 (uint32_t) ((uint32_t) MCSPI_REG_OFFSET * \
893 #define MCSPI_CHCTRL(x) ((uint32_t) CSL_MCSPI_CH0CTRL + \
894 (uint32_t) ((uint32_t) MCSPI_REG_OFFSET * \
897 #define MCSPI_CHTX(x) ((uint32_t) CSL_MCSPI_TX0 + \
898 (uint32_t) ((uint32_t) MCSPI_REG_OFFSET * \
901 #define MCSPI_CHRX(x) ((uint32_t) CSL_MCSPI_RX0 + \
902 (uint32_t) ((uint32_t) MCSPI_REG_OFFSET * \
905 #define MCSPI_CLKD_MASK (0x0FU)
908 #define MCSPI_IRQSTATUS_CLEAR_ALL (CSL_MCSPI_IRQSTATUS_EOW_MASK | \
909 CSL_MCSPI_IRQSTATUS_WKS_MASK | \
910 CSL_MCSPI_IRQSTATUS_RX3_FULL_MASK | \
911 CSL_MCSPI_IRQSTATUS_TX3_UNDERFLOW_MASK | \
912 CSL_MCSPI_IRQSTATUS_TX3_EMPTY_MASK | \
913 CSL_MCSPI_IRQSTATUS_RX2_FULL_MASK | \
914 CSL_MCSPI_IRQSTATUS_TX2_UNDERFLOW_MASK | \
915 CSL_MCSPI_IRQSTATUS_TX2_EMPTY_MASK | \
916 CSL_MCSPI_IRQSTATUS_RX1_FULL_MASK | \
917 CSL_MCSPI_IRQSTATUS_TX1_UNDERFLOW_MASK | \
918 CSL_MCSPI_IRQSTATUS_TX1_EMPTY_MASK | \
919 CSL_MCSPI_IRQSTATUS_RX0_OVERFLOW_MASK | \
920 CSL_MCSPI_IRQSTATUS_RX0_FULL_MASK | \
921 CSL_MCSPI_IRQSTATUS_TX0_UNDERFLOW_MASK | \
922 CSL_MCSPI_IRQSTATUS_TX0_EMPTY_MASK)
950 uint32_t numWordsRxTx);
1027 static inline uint32_t
MCSPI_readChConf(uint32_t baseAddr, uint32_t chNum);
1081 uint32_t enableFlag);
1103 uint32_t enableFlag);
1140 uint32_t dataWidth);
1147 uint32_t bufWidthShift = 0U;
1153 else if(dataSize <= 16U)
1162 return bufWidthShift;
1198 CSL_REG32_WR(baseAddr +
MCSPI_CHTX(chNum), txData);
1203 uint32_t enableFlag)
1209 enableFlag >> CSL_MCSPI_CH0CONF_FFEW_SHIFT);
1214 uint32_t enableFlag)
1220 enableFlag >> CSL_MCSPI_CH0CONF_FFER_SHIFT);
1226 return (CSL_REG32_RD(baseAddr +
MCSPI_CHRX(chNum)));
1235 CSL_FINS(regVal, MCSPI_CH0CONF_WL, (dataWidth - 1U));
Definition: mcspi_dma_udma.h:50
#define MCSPI_IS_D1
Data line 1 (SPIDAT[1]) selected for reception.
Definition: mcspi/v0/mcspi.h:233
#define MCSPI_CHRX(x)
Base address of McSPI_CHRX(x)
Definition: mcspi/v0/mcspi.h:901
int32_t MCSPI_dmaChConfig(MCSPI_Handle handle, const MCSPI_ChConfig *chCfg, const MCSPI_DmaChConfig *dmaChCfg)
Function to configure a DMA of a channel.
void MCSPI_close(MCSPI_Handle handle)
Function to close a MCSPI peripheral specified by the MCSPI handle.
MCSPI instance attributes - used during init time.
Definition: mcspi/v0/mcspi.h:488
uint32_t transferTimeout
Definition: mcspi/v0/mcspi.h:424
static uint32_t MCSPI_readRxDataReg(uint32_t baseAddr, uint32_t chNum)
This API will return the data present in the MCSPI_RX register.
Definition: mcspi/v0/mcspi.h:1223
MCSPI channel object.
Definition: mcspi/v0/mcspi.h:526
uint32_t count
Definition: mcspi/v0/mcspi.h:373
static void MCSPI_writeTxDataReg(uint32_t baseAddr, uint32_t txData, uint32_t chNum)
This API will put the data on to the McSPI Channel transmit register.
Definition: mcspi/v0/mcspi.h:1193
uint32_t txFifoTrigLvl
Definition: mcspi/v0/mcspi.h:480
static uint32_t MCSPI_readChCtrlReg(uint32_t baseAddr, uint32_t chNum)
This API returns Channel control register value.
Definition: mcspi/v0/mcspi.h:1171
uint32_t rxFifoTrigLvl
Definition: mcspi/v0/mcspi.h:482
void(* MCSPI_CallbackFxn)(MCSPI_Handle handle, MCSPI_Transaction *transaction)
The definition of a callback function used by the SPI driver when used in MCSPI_TRANSFER_MODE_CALLBAC...
Definition: mcspi/v0/mcspi.h:407
uint32_t operMode
Definition: mcspi/v0/mcspi.h:502
uint32_t status
Definition: mcspi/v0/mcspi.h:396
Data structure used with MCSPI_transfer()
Definition: mcspi/v0/mcspi.h:352
uint32_t initDelay
Definition: mcspi/v0/mcspi.h:514
uint32_t effTxFifoDepth
Definition: mcspi/v0/mcspi.h:564
static void MCSPI_enableRxFIFO(uint32_t baseAddr, uint32_t chNum, uint32_t enableFlag)
This API will enable/disable the Rx FIFOs of McSPI peripheral.
Definition: mcspi/v0/mcspi.h:1212
static uint32_t MCSPI_readChStatusReg(uint32_t baseAddr, uint32_t chNum)
This API will return the status of the McSPI channel currently in use.
Definition: mcspi/v0/mcspi.h:1165
MCSPI_ChConfig chCfg
Definition: mcspi/v0/mcspi.h:530
uint32_t intrMask
Definition: mcspi/v0/mcspi.h:568
static uint32_t MCSPI_readChConf(uint32_t baseAddr, uint32_t chNum)
This API returns Channel Config register value.
Definition: mcspi/v0/mcspi.h:1182
#define MCSPI_CS_POL_LOW
SPIEN (CS) is held low during the ACTIVE state.
Definition: mcspi/v0/mcspi.h:210
uint16_t index
Definition: tisci_rm_proxy.h:3
int32_t MCSPI_reConfigFifo(MCSPI_Handle handle, uint32_t chNum, uint32_t numWordsRxTx)
Function to re-configure Effective FIFO Words.
uint32_t chConfRegVal
Definition: mcspi/v0/mcspi.h:572
static uint32_t MCSPI_getBufWidthShift(uint32_t dataSize)
This API will return the buffer width in bytes based on dataSize.
Definition: mcspi/v0/mcspi.h:1145
uint32_t transferMode
Definition: mcspi/v0/mcspi.h:422
#define MCSPI_MS_MODE_CONTROLLER
The module generates the clock and CS.
Definition: mcspi/v0/mcspi.h:174
#define MCSPI_DPE_DISABLE
No transmission on Data Line.
Definition: mcspi/v0/mcspi.h:245
MCSPI driver object.
Definition: mcspi/v0/mcspi.h:583
uint32_t MCSPI_getBaseAddr(MCSPI_Handle handle)
Function to get base address of MCSPI instance of a particular handle.
#define MCSPI_SB_POL_LOW
Start-bit polarity is held to 0 during MCSPI transfer.
Definition: mcspi/v0/mcspi.h:269
uint32_t bitRate
Definition: mcspi/v0/mcspi.h:453
void MCSPI_deinit(void)
This function de-initializes the MCSPI module.
MCSPI_Handle handle
Definition: mcspi/v0/mcspi.h:587
#define MCSPI_MAX_NUM_CHANNELS
Max number of channels/Chip Select (CS) supported.
Definition: mcspi/v0/mcspi.h:113
MCSPI Parameters.
Definition: mcspi/v0/mcspi.h:421
#define SystemP_WAIT_FOREVER
Value to use when needing a timeout of infinity or wait forver until resource is available.
Definition: SystemP.h:83
uint32_t csDisable
Definition: mcspi/v0/mcspi.h:356
uint32_t chCtrlRegVal
Definition: mcspi/v0/mcspi.h:574
void * MCSPI_Handle
A handle that is returned from a MCSPI_open() call.
Definition: mcspi/v0/mcspi.h:82
uint32_t trMode
Definition: mcspi/v0/mcspi.h:457
MCSPI_Object * object
Definition: mcspi/v0/mcspi.h:630
uint32_t inputClkFreq
Definition: mcspi/v0/mcspi.h:494
void MCSPI_init(void)
This function initializes the MCSPI module.
#define MCSPI_TRANSFER_MODE_BLOCKING
MCSPI_transfer() blocks execution. This mode can only be used when called within a Task context
Definition: mcspi/v0/mcspi.h:150
uint32_t isOpen
Definition: mcspi/v0/mcspi.h:536
HwiP_Object hwiObj
Definition: mcspi/v0/mcspi.h:608
SemaphoreP_Object transferSemObj
Definition: mcspi/v0/mcspi.h:604
uint32_t baseAddr
Definition: mcspi/v0/mcspi.h:492
uint32_t curRxWords
Definition: mcspi/v0/mcspi.h:550
#define MCSPI_CHSTAT(x)
Base address of McSPI_CHSTAT(x)
Definition: mcspi/v0/mcspi.h:889
uint32_t csPolarity
Definition: mcspi/v0/mcspi.h:455
static void MCSPI_setDataWidth(uint32_t baseAddr, uint32_t chNum, uint32_t dataWidth)
This API will set the data width in the channel config register.
Definition: mcspi/v0/mcspi.h:1229
uint32_t startBitPolarity
Definition: mcspi/v0/mcspi.h:471
#define MCSPI_SLV_CS_SELECT_0
Definition: mcspi/v0/mcspi.h:254
static void MCSPI_writeChCtrlReg(uint32_t baseAddr, uint32_t chNum, uint32_t regVal)
This API sets Channel control register value.
Definition: mcspi/v0/mcspi.h:1176
uint32_t chMode
Definition: mcspi/v0/mcspi.h:510
int32_t MCSPI_transfer(MCSPI_Handle handle, MCSPI_Transaction *transaction)
Function to perform MCSPI transactions.
uint32_t intrNum
Definition: mcspi/v0/mcspi.h:500
int32_t MCSPI_transferCancel(MCSPI_Handle handle)
Function to cancel MCSPI transactions on channel of a SPI peripheral specified by the MCSPI handle.
uint32_t msMode
Definition: mcspi/v0/mcspi.h:428
const uint8_t * curTxBufPtr
Definition: mcspi/v0/mcspi.h:542
static void MCSPI_Transaction_init(MCSPI_Transaction *trans)
Function to initialize the MCSPI_Transaction struct to its defaults.
Definition: mcspi/v0/mcspi.h:835
uint32_t csDisable
Definition: mcspi/v0/mcspi.h:538
void * args
Definition: mcspi/v0/mcspi.h:394
uint32_t dataWidthBitMask
Definition: mcspi/v0/mcspi.h:562
uint32_t pinMode
Definition: mcspi/v0/mcspi.h:512
#define MCSPI_CHTX(x)
Base address of McSPI_CHTX(x)
Definition: mcspi/v0/mcspi.h:897
uint32_t startBitEnable
Definition: mcspi/v0/mcspi.h:468
#define MCSPI_TCS0_0_CLK
0.5 clock cycles delay
Definition: mcspi/v0/mcspi.h:281
void * txBuf
Definition: mcspi/v0/mcspi.h:376
void * rxBuf
Definition: mcspi/v0/mcspi.h:387
uint32_t systRegVal
Definition: mcspi/v0/mcspi.h:576
uint32_t effRxFifoDepth
Definition: mcspi/v0/mcspi.h:566
uint32_t dataSize
Definition: mcspi/v0/mcspi.h:362
static void MCSPI_ChConfig_init(MCSPI_ChConfig *chConfig)
Function to initialize the MCSPI_ChConfig struct to its defaults.
Definition: mcspi/v0/mcspi.h:813
uint32_t curTxWords
Definition: mcspi/v0/mcspi.h:546
uint32_t slvCsSelect
Definition: mcspi/v0/mcspi.h:465
int32_t MCSPI_chConfig(MCSPI_Handle handle, const MCSPI_ChConfig *chCfg)
Function to configure a MCSPI channel.
uint8_t intrPriority
Definition: mcspi/v0/mcspi.h:504
static void MCSPI_enableTxFIFO(uint32_t baseAddr, uint32_t chNum, uint32_t enableFlag)
This API will enable/disable the Tx FIFOs of McSPI peripheral.
Definition: mcspi/v0/mcspi.h:1201
void * mcspiDmaHandle
Definition: mcspi/v0/mcspi.h:613
uint8_t bufWidthShift
Definition: mcspi/v0/mcspi.h:556
MCSPI global configuration array.
Definition: mcspi/v0/mcspi.h:627
void * transferSem
Definition: mcspi/v0/mcspi.h:601
MCSPI_Transaction * currTransaction
Definition: mcspi/v0/mcspi.h:611
#define MCSPI_CHCONF(x)
Base address of McSPI_CHCONF(x)
Definition: mcspi/v0/mcspi.h:885
uint8_t * curRxBufPtr
Definition: mcspi/v0/mcspi.h:544
#define MCSPI_FF_POL0_PHA0
Definition: mcspi/v0/mcspi.h:193
Opaque Hwi object used with the Hwi APIs.
Definition: HwiP.h:91
MCSPI_OpenParams openPrms
Definition: mcspi/v0/mcspi.h:589
uint32_t defaultTxData
Definition: mcspi/v0/mcspi.h:477
static void MCSPI_OpenParams_init(MCSPI_OpenParams *openPrms)
Function to initialize the MCSPI_OpenParams struct to its defaults.
Definition: mcspi/v0/mcspi.h:802
uint32_t dpe1
Definition: mcspi/v0/mcspi.h:463
uint32_t gMcspiConfigNum
Externally defined driver configuration array size.
uint32_t csEnable
Definition: mcspi/v0/mcspi.h:540
Opaque semaphore object used with the semaphore APIs.
Definition: SemaphoreP.h:59
MCSPI_DmaChConfig dmaChCfg
Definition: mcspi/v0/mcspi.h:570
int32_t mcspiDmaIndex
Definition: mcspi/v0/mcspi.h:430
#define MCSPI_TRANSFER_COMPLETED
Definition: mcspi/v0/mcspi.h:123
uint32_t channel
Definition: mcspi/v0/mcspi.h:353
#define MCSPI_TR_MODE_TX_RX
Definition: mcspi/v0/mcspi.h:219
uint32_t inputSelect
Definition: mcspi/v0/mcspi.h:459
uint32_t isOpen
Definition: mcspi/v0/mcspi.h:599
uint32_t dpe0
Definition: mcspi/v0/mcspi.h:461
static void MCSPI_writeChConfReg(uint32_t baseAddr, uint32_t chNum, uint32_t regVal)
This API sets Channel Config register value.
Definition: mcspi/v0/mcspi.h:1187
MCSPI_Handle MCSPI_open(uint32_t index, const MCSPI_OpenParams *openPrms)
This function opens a given MCSPI peripheral.
MCSPI configuration parameters for the channel.
Definition: mcspi/v0/mcspi.h:448
MCSPI_Config gMcspiConfig[]
Externally defined driver configuration array.
MCSPI_CallbackFxn transferCallbackFxn
Definition: mcspi/v0/mcspi.h:426
uint32_t baseAddr
Definition: mcspi/v0/mcspi.h:591
const MCSPI_Attrs * attrs
Definition: mcspi/v0/mcspi.h:628
#define MCSPI_CHCTRL(x)
Base address of McSPI_CHCTRL(x)
Definition: mcspi/v0/mcspi.h:893
#define MCSPI_CHANNEL_0
Definition: mcspi/v0/mcspi.h:93
uint32_t frameFormat
Definition: mcspi/v0/mcspi.h:451
uint32_t csIdleTime
Definition: mcspi/v0/mcspi.h:474
#define MCSPI_DPE_ENABLE
Data line selected for transmission.
Definition: mcspi/v0/mcspi.h:243
uint32_t chNum
Definition: mcspi/v0/mcspi.h:449
void * hwiHandle
Definition: mcspi/v0/mcspi.h:606