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AM243x MCU+ SDK
08.06.00
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Go to the documentation of this file.
40 #ifndef SDL_ECC_AGGR_H
41 #define SDL_ECC_AGGR_H
108 #define SDL_ECC_AGGR_INTR_SRC_NONE ((uint32_t) 0U)
110 #define SDL_ECC_AGGR_INTR_SRC_SINGLE_BIT ((uint32_t) 1U)
112 #define SDL_ECC_AGGR_INTR_SRC_DOUBLE_BIT ((uint32_t) 2U)
114 #define SDL_ECC_ADDR_ERROR_TYPE_SUCCESSIVE_SINGLE_BITS ((uint32_t) 3U)
116 #define SDL_ECC_AGGR_INTR_SRC_INVALID ((uint32_t) 4U)
123 #define SDL_ECC_AGGR_SELECT_ERR_CTRL1 (0U)
125 #define SDL_ECC_AGGR_SELECT_ERR_CTRL2 (1U)
127 #define SDL_ECC_AGGR_MAX_NUM_RAM_ERR_CTRL (2U)
135 #define SDL_ECC_AGGR_SELECT_ERR_STAT1 (0U)
137 #define SDL_ECC_AGGR_SELECT_ERR_STAT2 (1U)
139 #define SDL_ECC_AGGR_SELECT_ERR_STAT3 (2U)
141 #define SDL_ECC_AGGR_MAX_NUM_RAM_ERR_STAT (3U)
149 #define SDL_ECC_AGGR_NUM_ENABLE_REGISTERS (8U)
158 #define SDL_ECC_AGGR_VALID_TIMEOUT_ERR (1U)
160 #define SDL_ECC_AGGR_VALID_PARITY_ERR (2U)
171 #define SDL_ECC_AGGR_INJECT_PATTERN_ZERO ((uint32_t) 0U)
173 #define SDL_ECC_AGGR_INJECT_PATTERN_F ((uint32_t) 1U)
175 #define SDL_ECC_AGGR_INJECT_PATTERN_A ((uint32_t) 2U)
177 #define SDL_ECC_AGGR_INJECT_PATTERN_5 ((uint32_t) 3U)
179 #define SDL_ECC_EGGR_INJECT_PATTERN_MAX (SDL_ECC_AGGR_INJECT_PATTERN_A)
189 #define SDL_ECC_AGGR_ERROR_SUBTYPE_NORMAL ((uint32_t) 0U)
191 #define SDL_ECC_AGGR_ERROR_SUBTYPE_INJECT ((uint32_t) 1U)
int32_t SDL_ecc_aggrWriteEccRamErrStatReg(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, uint32_t instSelect, uint32_t val)
int32_t SDL_ecc_aggrAckIntr(SDL_ecc_aggrRegs *pEccAggrRegs, SDL_Ecc_AggrIntrSrc intrSrc)
int32_t SDL_ecc_aggrDisableIntr(const SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, SDL_Ecc_AggrIntrSrc intrSrc)
int32_t SDL_ecc_aggrWriteEccRamReg(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, uint32_t regOffset, uint32_t val)
uint32_t timeOutCnt
Definition: V1/sdl_ip_ecc.h:280
int32_t SDL_ecc_aggrSetEccRamNIntrPending(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, SDL_Ecc_AggrIntrSrc intrSrc, uint32_t numEvents)
uint32_t singleBitErrorCount
Definition: V1/sdl_ip_ecc.h:248
uint32_t REV
Definition: V1/sdl_ip_ecc.h:298
This structure contains error status information returned by the SDL_ecc_aggrGetEccRamGetErrorStatus ...
Definition: V1/sdl_ip_ecc.h:232
uint32_t SDL_Ecc_AggrEDCErrorSubType
This enumerator defines the types of possible EDC errors.
Definition: V1/sdl_ip_ecc.h:187
int32_t SDL_ecc_aggrIsIntrPending(const SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, SDL_Ecc_AggrIntrSrc intrSrc, bool *pIsPend)
uint32_t ECC_CTRL
Definition: V1/sdl_ip_ecc.h:300
int32_t SDL_ecc_aggrClrEccRamNIntrPending(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, SDL_Ecc_AggrIntrSrc intrSrc, uint32_t numEvents)
Definition: V1/sdlr_ecc.h:53
SDL_Ecc_AggrIntrSrc intrSrc
Definition: V1/sdl_ip_ecc.h:211
bool bNextRow
Definition: V1/sdl_ip_ecc.h:221
bool intrEnableTimeoutErr
Definition: V1/sdl_ip_ecc.h:261
int32_t SDL_ecc_aggrDisableIntrs(const SDL_ecc_aggrRegs *pEccAggrRegs, SDL_Ecc_AggrIntrSrc intrSrc)
int32_t SDL_ecc_aggrForceEccRamError(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, const SDL_Ecc_AggrErrorInfo *pEccForceError)
int32_t SDL_ecc_aggrReadStaticRegs(SDL_ecc_aggrRegs *pEccAggrRegs, SDL_ECC_staticRegs *pEccAggrStaticRegs)
int32_t SDL_ecc_aggrClrEccRamIntrPending(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, SDL_Ecc_AggrIntrSrc intrSrc)
uint32_t eccBit1
Definition: V1/sdl_ip_ecc.h:215
int32_t SDL_ecc_aggrIntrEnableCtrl(SDL_ecc_aggrRegs *pEccAggrRegs, const SDL_ecc_aggrEnableCtrl *pEnableCtrl)
bool intrStatusSetTimeoutErr
Definition: V1/sdl_ip_ecc.h:276
int32_t SDL_ecc_aggrReadEccRamErrStatReg(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, uint32_t instSelect, uint32_t *pRegVal)
int32_t SDL_ecc_aggrEnableAllIntrs(const SDL_ecc_aggrRegs *pEccAggrRegs)
This structure contains error forcing information used by the SDL_ecc_aggrForceEccRamError function.
Definition: V1/sdl_ip_ecc.h:209
int32_t SDL_ecc_aggrWriteEccRamErrCtrlReg(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, uint32_t instSelect, uint32_t val)
uint32_t parityCnt
Definition: V1/sdl_ip_ecc.h:282
uint32_t ECC_ERR_CTRL1
Definition: V1/sdl_ip_ecc.h:302
uint32_t ECC_ERR_CTRL2
Definition: V1/sdl_ip_ecc.h:304
uint8_t SDL_ecc_aggrValid
This defines the valid ecc aggr error configuration.
Definition: V1/sdl_ip_ecc.h:157
int32_t SDL_ecc_aggrReadEccRamErrCtrlReg(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, uint32_t instSelect, uint32_t *pRegVal)
bool controlRegErr
Definition: V1/sdl_ip_ecc.h:234
bool intrStatusSetParityErr
Definition: V1/sdl_ip_ecc.h:278
This structure contains the static register group for Ecc aggregator used by the SDL_ecc_aggrReadStat...
Definition: V1/sdl_ip_ecc.h:296
int32_t SDL_ecc_aggrReadEccRamCtrlReg(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, uint32_t *pRegVal)
int32_t SDL_ecc_aggrIntrStatusCtrl(SDL_ecc_aggrRegs *pEccAggrRegs, const SDL_ecc_aggrStatusCtrl *pStatusCtrl)
uint32_t eccBit1
Definition: V1/sdl_ip_ecc.h:246
int32_t SDL_ecc_aggrReadEccRamReg(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, uint32_t regOffset, uint32_t *pRegVal)
uint32_t eccBit2
Definition: V1/sdl_ip_ecc.h:217
bool intrEnableParityErr
Definition: V1/sdl_ip_ecc.h:263
uint32_t eccRow
Definition: V1/sdl_ip_ecc.h:244
int32_t SDL_ecc_aggrEnableIntrs(const SDL_ecc_aggrRegs *pEccAggrRegs, SDL_Ecc_AggrIntrSrc intrSrc)
bool bOneShotMode
Definition: V1/sdl_ip_ecc.h:219
uint32_t parityErrorCount
Definition: V1/sdl_ip_ecc.h:242
bool writebackPend
Definition: V1/sdl_ip_ecc.h:240
int32_t SDL_ecc_aggrDisableAllIntrs(const SDL_ecc_aggrRegs *pEccAggrRegs)
SDL_ecc_aggrValid validCfg
Definition: V1/sdl_ip_ecc.h:265
uint32_t SDL_Ecc_AggrIntrSrc
This enumerator defines the types of possible ECC errors.
Definition: V1/sdl_ip_ecc.h:106
uint32_t SDL_Ecc_injectPattern
This enumerator defines the types of ECC patterns.
Definition: V1/sdl_ip_ecc.h:169
bool sVBUSTimeoutErr
Definition: V1/sdl_ip_ecc.h:238
int32_t SDL_ecc_aggrVerifyConfigEccRam(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, bool bEnable, bool bEccCheck, bool bEnableRMW)
int32_t SDL_ecc_aggrGetNumRams(const SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t *pNumRams)
int32_t SDL_ecc_aggrWriteEccRamCtrlReg(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, uint32_t val)
uint32_t doubleBitErrorCount
Definition: V1/sdl_ip_ecc.h:250
This structure contains the ECC aggr status config.
Definition: V1/sdl_ip_ecc.h:274
bool successiveSingleBitErr
Definition: V1/sdl_ip_ecc.h:236
This structure contains the ECC aggr enable error config.
Definition: V1/sdl_ip_ecc.h:259
int32_t SDL_ecc_aggrEnableAllIntr(const SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId)
#define SDL_ECC_AGGR_NUM_ENABLE_REGISTERS
This defines the number of enable registers.
Definition: V1/sdl_ip_ecc.h:149
int32_t SDL_ecc_aggrGetEccRamErrorStatus(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, SDL_Ecc_AggrEccRamErrorStatusInfo *pEccErrorStatus)
int32_t SDL_ecc_aggrIsAnyIntrPending(const SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, bool *pIsPend)
int32_t SDL_ecc_aggrEnableIntr(const SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, SDL_Ecc_AggrIntrSrc intrSrc)
int32_t SDL_ecc_aggrIntrGetStatus(const SDL_ecc_aggrRegs *pEccAggrRegs, SDL_ecc_aggrStatusCtrl *pStatusCtrl)
int32_t SDL_ecc_aggrGetRevision(const SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t *pRev)
int32_t SDL_ecc_aggrDisableAllIntr(const SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId)
int32_t SDL_ecc_aggrIsEccRamIntrPending(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, SDL_Ecc_AggrIntrSrc intrSrc, bool *pIsPend)
int32_t SDL_ecc_aggrSetEccRamIntrPending(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, SDL_Ecc_AggrIntrSrc intrSrc)
SDL_ecc_aggrValid validCfg
Definition: V1/sdl_ip_ecc.h:284
uint32_t eccRow
Definition: V1/sdl_ip_ecc.h:213
int32_t SDL_ecc_aggrConfigEccRam(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, bool bEnable, bool bEccCheck, bool bEnableRMW)
int32_t SDL_ecc_aggrReadEccRamWrapRevReg(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, uint32_t *pRegVal)