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AM243x MCU+ SDK
08.04.00
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54 #ifndef TISCI_PROCBOOT_H_
55 #define TISCI_PROCBOOT_H_
167 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_ARMV8_DBG_EN (0x00000001U)
169 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_ARMV8_DBG_NIDEN (0x00000002U)
171 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_ARMV8_DBG_SPIDEN (0x00000004U)
173 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_ARMV8_DBG_SPNIDEN (0x00000008U)
175 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_ARMV8_AARCH32 (0x00000100U)
180 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_DBG_EN (0x00000001U)
182 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_DBG_NIDEN (0x00000002U)
184 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_LOCKSTEP (0x00000100U)
186 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_TEINIT (0x00000200U)
188 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_NMFI_EN (0x00000400U)
190 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE (0x00000800U)
192 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_BTCM_EN (0x00001000U)
194 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_ATCM_EN (0x00002000U)
196 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_MEM_INIT_DIS (0x00004000U)
199 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_SINGLE_CORE (0x00008000U)
205 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2PL_MASK (0x0000000FU)
207 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2PL_SHIFT (0x00000000U)
209 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2PL_1 (0x00000001U)
211 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2PL_2 (0x00000002U)
213 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2PL_3 (0x00000003U)
215 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2PL_4 (0x00000004U)
217 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2PL_5 (0x00000005U)
221 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2AL_MASK (0x000000F0U)
223 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2AL_SHIFT (0x00000004U)
225 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2AL_2 (0x00000020U)
227 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2AL_3 (0x00000030U)
229 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2AL_4 (0x00000040U)
231 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2AL_5 (0x00000050U)
241 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C6X_SSCLKMV_MASK (0x00000007U)
243 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C6X_SSCLKMV_SHIFT (0x00000000U)
245 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C6X_SSCLKMV_DIV2 (0x00000001U)
247 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C6X_SSCLKMV_DIV3 (0x00000002U)
249 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C6X_SSCLKMV_DIV4 (0x00000003U)
254 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_M4F_DBG_EN (0x00000001U)
256 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_M4F_DBG_NIDEN (0x00000002U)
297 #define TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_ARMV8_ACINACTM (0x00000001U)
299 #define TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_ARMV8_AINACTS (0x00000002U)
301 #define TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_ARMV8_L2FLUSHREQ (0x00000100U)
306 #define TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_CORE_HALT (0x00000001U)
308 #define TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_LPSC (0x00000002U)
310 #define TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_RESET (0x00000004U)
395 #define TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_ARMV8_WFE (0x00000001U)
397 #define TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_ARMV8_WFI (0x00000002U)
399 #define TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_ARMV8_L2F_DONE (0x00000010U)
401 #define TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_ARMV8_STANDBYWFIL2 (0x00000020U)
406 #define TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_R5_WFE (0x00000001U)
408 #define TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_R5_WFI (0x00000002U)
410 #define TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_R5_CLK_GATED (0x00000004U)
412 #define TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_R5_LOCKSTEP_PERMITTED (0x00000100U)
414 #define TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_R5_SINGLECORE_ONLY (0x00000200U)
419 #define TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_C7X_WFE (0x00000001U)
421 #define TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_C7X_WFI (0x00000002U)
426 #define TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_M4F_WFI (0x00000002U)
struct tisci_header hdr
Definition: tisci_procboot.h:95
uint32_t bootvector_hi
Definition: tisci_procboot.h:272
Processor Status Wait.
Definition: tisci_procboot.h:485
Release physical processor control response.
Definition: tisci_procboot.h:125
Processor Status Wait Response.
Definition: tisci_procboot.h:509
uint8_t delay_before_iteration_loop_start_us
Definition: tisci_procboot.h:491
struct tisci_header hdr
Definition: tisci_procboot.h:448
struct tisci_header hdr
Definition: tisci_procboot.h:126
uint8_t processor_id
Definition: tisci_procboot.h:142
Response to authenticate and start image request.
Definition: tisci_procboot.h:374
uint8_t processor_id
Definition: tisci_procboot.h:487
uint32_t status_flags_1_set_any_wait
Definition: tisci_procboot.h:493
uint32_t control_flags_1_set
Definition: tisci_procboot.h:324
Release physical processor control request.
Definition: tisci_procboot.h:107
struct tisci_msg_proc_request_req __attribute__((__packed__))
struct tisci_header hdr
Definition: tisci_procboot.h:486
uint32_t bootvector_hi
Definition: tisci_procboot.h:451
uint32_t config_flags_1
Definition: tisci_procboot.h:452
struct tisci_header hdr
Definition: tisci_procboot.h:352
uint8_t processor_id
Definition: tisci_procboot.h:323
uint8_t processor_id
Definition: tisci_procboot.h:109
uint32_t bootvector_lo
Definition: tisci_procboot.h:271
Processor Status request.
Definition: tisci_procboot.h:387
uint32_t control_flags_1
Definition: tisci_procboot.h:453
uint32_t image_address_hi
Definition: tisci_procboot.h:377
Response to optional processor specific message for sequence control.
Definition: tisci_procboot.h:341
uint32_t certificate_address_hi
Definition: tisci_procboot.h:354
uint32_t config_flags_1_clear
Definition: tisci_procboot.h:274
struct tisci_header hdr
Definition: tisci_procboot.h:76
uint32_t status_flags_1
Definition: tisci_procboot.h:454
uint8_t host_id
Definition: tisci_procboot.h:143
uint8_t processor_id
Definition: tisci_procboot.h:449
uint8_t processor_id
Definition: tisci_procboot.h:389
struct tisci_header hdr
Definition: tisci_procboot.h:141
Processor Status Response.
Definition: tisci_procboot.h:447
uint32_t bootvector_lo
Definition: tisci_procboot.h:450
Request for physical processor control response.
Definition: tisci_procboot.h:94
This file contains:
Definition: tisci_procboot.h:75
Processor Boot Configuration.
Definition: tisci_procboot.h:268
uint32_t status_flags_1_set_all_wait
Definition: tisci_procboot.h:492
Request to handover control of a processor to another host if permitted.
Definition: tisci_procboot.h:140
uint32_t config_flags_1_set
Definition: tisci_procboot.h:273
uint8_t processor_id
Definition: tisci_procboot.h:77
uint32_t certificate_address_lo
Definition: tisci_procboot.h:353
Optional processor specific message for sequence control.
Definition: tisci_procboot.h:321
struct tisci_header hdr
Definition: tisci_procboot.h:375
Response to handover of control of a processor to another host if permitted.
Definition: tisci_procboot.h:160
uint32_t status_flags_1_clr_all_wait
Definition: tisci_procboot.h:494
Authenticate and start image.
Definition: tisci_procboot.h:351
uint32_t image_size
Definition: tisci_procboot.h:378
uint32_t control_flags_1_clear
Definition: tisci_procboot.h:325
Response to Processor Boot Configuration message.
Definition: tisci_procboot.h:290
struct tisci_header hdr
Definition: tisci_procboot.h:291
struct tisci_header hdr
Definition: tisci_procboot.h:161
struct tisci_header hdr
Definition: tisci_procboot.h:388
struct tisci_header hdr
Definition: tisci_procboot.h:322
uint32_t status_flags_1_clr_any_wait
Definition: tisci_procboot.h:495
struct tisci_header hdr
Definition: tisci_procboot.h:108
uint8_t processor_id
Definition: tisci_procboot.h:270
uint32_t image_address_lo
Definition: tisci_procboot.h:376
uint8_t delay_per_iteration_us
Definition: tisci_procboot.h:490
uint8_t num_wait_iterations
Definition: tisci_procboot.h:488
struct tisci_header hdr
Definition: tisci_procboot.h:510
struct tisci_header hdr
Definition: tisci_procboot.h:342
struct tisci_header hdr
Definition: tisci_procboot.h:269
uint8_t num_match_iterations
Definition: tisci_procboot.h:489